JP5277877B2 - Manufacturing method of optical waveguide element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress abnormal growth due to oxidation of an end surface of an exposed core layer by suppressing the oxidation of the end surface in selective growth and eliminating the need to use a halogen-based gas before the selective growth. <P>SOLUTION: On a semiconductor substrate, a first core layer 20 is formed of a compound semiconductor containing no Al. A first core layer in a second region A2 in contact with a first region A1 as a portion of a waveguide to be formed on the semiconductor substrate with respect to a wave guiding direction is removed to expose the end surface of the first core layer at a border between the first region and the second region. In the second region where the first core layer is removed, a second core layer 30 is formed of a compound semiconductor containing Al. The first core layer in a third region A3 disposed on the opposite side from the second region about the first region as a reference and coming into contact with the first region is removed to expose the end surface of the first core layer at a border between the first region and third region. In the third region where the first core layer is removed, a third core layer 35 is formed of a compound semiconductor containing Al. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a method for manufacturing an optical waveguide element in which two types of core layers made of a compound semiconductor containing aluminum (Al) are combined, and the optical waveguide element.

  In optical fiber communication, an optical element that operates stably even when the ambient temperature changes is desired. In such an optical element, temperature adjustment is not necessary, so that power consumption can be reduced. Usually, an InP substrate is used for an optical element in a 1.3 μm band and a 1.55 μm band, which are general wavelength bands for optical fiber communication, and an InGaAsP-based compound semiconductor is used for an active layer. In order to ensure stable operation at a high temperature, it is effective to use an AlGaInAs compound semiconductor having a large conduction band offset.

  By integrating a plurality of functional elements on a single semiconductor substrate, the optical element can be reduced in size.

  When a plurality of functional elements using an AlGaInAs-based material for the core layer are formed on one semiconductor substrate, it is necessary to bond at least two core layers by a butt joint structure. By patterning the first core layer to expose the end face, and selectively growing the second core layer so as to contact the end face of the first core layer, two core layers joined by a butt joint structure are formed. can do.

  When the end face of the first core layer is exposed, Al in the first core layer is oxidized. When the end surface of the first core layer is oxidized when the second core layer is selectively grown, abnormal growth occurs and a large number of defects are generated. During the operation of the optical element, the deterioration of the crystal proceeds starting from the defective portion, resulting in a decrease in the reliability of the optical element.

  Immediately before performing the selective growth of the second core layer, abnormal growth can be suppressed by removing the oxide by exposing the end face of the first core layer to a halogen-based gas (Patent Document 1).

Japanese Patent Laid-Open No. 2005-150181

  If a halogen-based gas is introduced immediately before the selective growth, the exposed surface layer portion of the InP buffer layer and the cladding layer is also etched at the same time. For this reason, it is difficult to stably control the shape of the butt joint structure. In addition, when a halogen-based gas is introduced into the gas piping or reaction chamber of the film forming apparatus, the deposits attached to the inner wall are easily peeled off. The peeled deposit may adhere to the regrowth surface.

An optical waveguide device manufacturing method for solving the above problems is as follows.
Forming a first core layer made of a compound semiconductor not containing Al as a group III element on a semiconductor substrate;
The first core layer in the second region in contact with the first region which is a part of the waveguide direction to be formed on the semiconductor substrate is removed, and the first region and the second region are removed. Exposing an end face of the first core layer at a boundary with a region;
Forming a second core layer made of a compound semiconductor containing Al as a group III element in the second region from which the first core layer has been removed;
The first core layer in the third region that is disposed on the opposite side of the second region with respect to the first region and is in contact with the first region is removed, and the first region Exposing the end face of the first core layer at the boundary with the third region;
Said first core layer has been removed the third region, and chromatic and forming a third core layer comprising a compound semiconductor containing Al as a group III element,
When the first core layer in the second region is removed, the first core is formed in a part of the third region that is in contact with the boundary between the first region and the third region. Leaving a layer and removing the first core layer in a region away from the first region;
In the step of forming the second core layer, the second core layer is formed also in a region where the first core layer is removed in the third region,
In the step of removing the first core layer in the third region, the second core layer in the third region is also removed.

  When the second core layer is formed, the end face of the first core layer is exposed. Even when the third core layer is formed, the end face of the first core layer is exposed, and the end face of the second core layer is not exposed. Since the first core layer does not contain Al, oxidation of the end face of the exposed core layer can be suppressed. Thereby, the abnormal growth resulting from the oxidation of the end face can be suppressed.

  Since it is not necessary to use a halogen-based gas before the growth of the second core layer and the third core layer, it is possible to suppress the occurrence of excessive etching.

  Embodiments will be described below with reference to the drawings.

  With reference to FIGS. 1A to 1V, a method of manufacturing an optical waveguide device according to Example 1 will be described. As an example, metal organic vapor phase epitaxy (MOVPE) can be employed for the growth of the group III-V compound semiconductor described below. Trimethylindium can be used as the In material, triethylgallium as the Ga material, trimethylaluminum as the Al material, arsine as the As material, and phosphine as the P material. Monosilane can be used as a raw material for Si which is a doping element, and diethyl zinc can be used as a Zn raw material. Hydrogen gas is used as the carrier gas. The growth pressure is about 670 Pa (about 50 Torr).

As shown in FIG. 1A, a buffer layer 11 made of n-type InP and having a thickness of 300 nm is formed on a semiconductor substrate 10 made of n-type InP and having a (001) plane as a main surface at a growth temperature of 630 ° C. . A 50 nm thick diffraction grating forming layer 12 made of n-type InGaAsP having a transition wavelength of 1.15 μm is formed on the buffer layer 11. A 10 nm thick diffraction grating cap layer 13 made of n-type InP is formed on the diffraction grating forming layer 12. The carrier concentration of the buffer layer 11, the diffraction grating formation layer 12, and the diffraction grating cap layer 13 is, for example, 5.0 × 10 ¹⁷ cm ⁻³ .

  As shown in FIG. 1B, the diffraction grating 14 is formed by patterning the diffraction grating cap layer 13 and the diffraction grating forming layer 12. The diffraction grating 14 has periodicity in the [110] direction, the period is 200 nm, and the duty ratio is 50%. For example, electron beam exposure is used to form the diffraction grating 14.

As shown in FIG. 1C, a gap of the diffraction grating 14 is filled with n-type InP, and a spacer layer 15 made of n-type InP and having a thickness of 50 nm is continuously formed. The carrier concentration of the spacer layer 15 is 5.0 × 10 ¹⁷ cm ⁻³ . A first core layer 20 having a thickness of 335 nm and made of InGaAsP having a transition wavelength of 1.15 μm is formed on the spacer layer 15. The first core layer 20 functions as a core layer of the distributed reflection region DR1. A first upper clad layer 21 made of p-type InP and having a thickness of 150 nm is formed on the first core layer 20. The Zn carrier concentration of the first upper cladding layer 21 is set to 5.0 × 10 ¹⁷ cm ⁻³ .

  As shown in FIG. 1Dx, a first first mask pattern 22 made of silicon oxide and having a thickness of 300 nm is formed on the first upper cladding layer 21. The first first mask pattern 22 is formed by a silicon oxide film forming process by low pressure vapor deposition (LPCVD) and a patterning process using a photolithography technique. FIG. 1Dy shows a plan view of the first first mask pattern 22. A cross-sectional view taken along one-dot chain line 1D-1D in FIG. 1Dy corresponds to FIG. 1Dx.

  The surface of the semiconductor substrate 10 is divided into a plurality of unit regions 23 by lattice-shaped cleavage lines. Each unit region 23 corresponds to one optical waveguide element. The unit areas 23 are arranged in a matrix in the [110] direction and the [1-10] direction. The [110] direction corresponds to the light guiding direction. In each unit region 23, first to third regions A1 to A3 arranged in the waveguide direction are defined. The second region A2 is in contact with one edge of the first region A1 and reaches the edge of the unit region 23. The third region A3 is disposed on the opposite side of the second region A2 with respect to the first region A1, and reaches the other edge of the unit region 23.

  In two unit regions 23 adjacent to each other in the waveguide direction, the arrangement order of the first to third regions is reversed. That is, the second region A2 of one unit region 23 is continuous with the second region A2 of the unit region 23 adjacent in the waveguide direction. Further, the third region A3 of one unit region 23 is continuous with the third region A3 of the unit region 23 adjacent in the waveguide direction. In the two unit regions 23 adjacent in the direction orthogonal to the waveguide direction ([1-10] direction), the arrangement order of the first to third regions A1 to A3 is the same.

  The length of each unit region 23 in the waveguide direction is 200 μm. The lengths in the waveguide direction of the first region A1, the second region A2, and the third region A3 are 50 μm, 100 μm, and 50 μm, respectively. In a later step, a distributed feedback (DFB) laser element is formed in the second region A2, and a distributed reflection waveguide is formed in the first region A1 and the third region A3.

  One mesa stripe region 25 constituting a waveguide is defined for a plurality of unit regions 23 arranged in a line in the waveguide direction. The mesa stripe region 25 is disposed approximately at the center of the unit region 23 with respect to the direction orthogonal to the waveguide direction. Regarding the waveguide direction, each unit region 23 reaches from one edge to the other edge.

  The first mask pattern 22 includes a main part 22A and a sub part 22B. The main portion 22A includes the mesa stripe region 25 along the mesa stripe region 25 in the first region A1 and the third region A3. The sub part 22B extends in a direction orthogonal to the waveguide direction along the boundary line between the first region A1 and the second region A2. The width of the main part 22A is 15 μm, and the width of the sub part 22B is 5 μm. The first mask pattern 22 straddling the plurality of unit regions 23 has a ladder-like planar shape. Due to the ladder shape, the first mask pattern 22 does not include a corner protruding outward.

  As shown in FIG. 1E, the first upper cladding layer 21 and the first core layer 20 are etched using the first mask pattern 22 as an etching mask. Diluted hydrochloric acid is used for etching the first upper cladding layer 21, and a mixed solution of diluted hydrochloric acid and hydrogen peroxide is used for etching the first core layer 20. The spacer layer 15 is exposed in a region not covered with the first mask pattern 22, for example, the second region A2. The end surface of the first core layer 20 is exposed at the first end E1 corresponding to the boundary between the first region A1 and the second region A2. Since the first core layer 20 does not contain Al, the exposed end face is hardly oxidized.

  As shown in FIG. 1F, the first mask pattern 22 is used as a selective growth mask, and the second core layer 30 and the second upper cladding layer 31 are formed on the exposed spacer layer 15. Selectively grow in this order. Since the first mask pattern 22 does not include an outwardly protruding corner, covering growth from the edge of the first mask pattern 22 toward the inside of the first mask pattern 22 is suppressed.

  The second core layer 30 has a laminated structure in which a lower separation confinement hetero (lower SCH) layer, a multiple quantum well layer, and an upper separation confinement hetero (upper SCH) layer are laminated from the substrate side. The lower SCH layer and the upper SCH layer are made of AlGaInAs having a transition wavelength of 1.0 μm, and each has a thickness of 50 nm. The multiple quantum well layer includes barrier layers and well layers alternately stacked for 15 periods. Each of the barrier layers is made of AlGaInAs having a transition wavelength of 1.05 μm and has a thickness of 10 nm, and each of the well layers is made of AlGaInAs having a transition wavelength of 1.45 μm and has a thickness of 5 nm. The second core layer 30 becomes an active layer of a distributed feedback (DFB) laser element, and the emission wavelength is 1.3 μm. The composition and thickness of the second upper cladding layer 31 are the same as the composition and thickness of the first upper cladding layer 21.

Hereinafter, the procedure of selective growth will be described. First, the semiconductor substrate 10 shown in FIG. 1E is loaded into a MOVPE growth furnace, and the substrate is heated to 630 ° C. in a PH ₃ atmosphere. Subsequently, PH ₃ is replaced with AsH ₃ , and a group III element source gas is introduced. Since the end face of the first core layer 20 is not oxidized, abnormal growth during selective growth is suppressed. After forming the second upper cladding layer 31, the substrate temperature is lowered and the substrate is taken out from the growth furnace.

  As shown in FIG. 1G, after the selective growth, the first mask pattern 22 is removed using hydrofluoric acid. The first upper cladding layer 21 covered with the first mask pattern 22 is exposed.

  As shown in FIG. 1Hx, a second mask pattern 33 made of silicon oxide is formed on the first and second upper cladding layers 21 and 31. FIG. 1Hy shows a plan view of the second mask pattern 33. A cross-sectional view taken along one-dot chain line 1H-1H in FIG. 1Hy corresponds to FIG. 1Hx. The first mask pattern 22 formed in the process shown in FIG. 1Dy is indicated by a broken line.

  The second mask pattern 33 is disposed along the mesa stripe region 25 in the first region A1 and the second region A2, and includes the mesa stripe region 25. The width of the second mask pattern 33 is slightly wider than the width of the main portion 22A of the first mask pattern 22 shown in FIG. 1Dy. For example, the width of the second mask pattern 33 is 25 μm. The first mask pattern 22 has a continuous planar shape from one of the two unit regions 23 adjacent to each other with the second regions A2 in contact with each other, and the length thereof is 300 μm.

  As shown in FIG. 1I, using the second mask pattern 33 as an etching mask, the first upper cladding layer 21 and the first core layer 20 are dry-etched using an inductively coupled plasma (ICP) etching apparatus. The etching is stopped before the bottom surface of the etched region reaches the bottom surface of the first core layer 20. At this time, the second core layer 30 and the second upper clad layer 31 in the region not covered with the second mask pattern 33 shown in FIG.

  As shown in FIG. 1J, the first core layer 20 is wet-etched to the bottom surface using the second mask pattern 33 as an etching mask. As the etchant, a mixed solution of dilute hydrochloric acid and hydrogen peroxide is used. At this time, the second core layer 30 in the region not covered with the second mask pattern 33 shown in FIG.

  By applying wet etching, the etching can be stopped with good reproducibility when the spacer layer 15 is exposed. That is, depth control can be easily performed.

  When wet etching is employed, the etching rate of the first core layer 20 containing InGaAsP is slower than the etching rate of the second core layer 30 containing AlGaInAs. If the first core layer 20 is etched only by wet etching without performing dry etching, side etching from the [−110] direction of the third core layer 30 is likely to occur. For this reason, there is a possibility that side etching of the third core layer 30 proceeds excessively and the third core layer 30 in the mesa stripe region 25 is removed before the etching of the first core layer 20 is completed. .

  If the first core layer 20 and the third core layer 30 are removed halfway in the thickness direction by dry etching, the wet etching time can be shortened. For this reason, it is possible to prevent the third core layer 30 from being side-etched excessively.

  The end face of the first core layer 20 is exposed at the boundary between the first region A1 and the third region A3. The end surface of the second core layer 30 containing Al that is orthogonal to the waveguide direction is not exposed. Thus, it can be set as the structure which the end surface of the 2nd core layer 30 containing Al is not exposed. Note that the end face of the second core layer 30 is exposed at the edge parallel to the waveguide direction of the second mask pattern 33 shown in FIG. 1Hy. However, since this portion is finally removed, even if abnormal growth occurs during selective growth, the influence on the device characteristics is small.

  As shown in FIG. 1K, the third core layer 35 is selectively grown on the exposed spacer layer 15 using the second mask pattern 33 as a selective growth mask. Further thereon, a third upper cladding layer 36 is selectively grown. The basic growth procedure is the same as the growth procedure of the second core layer 30 and the second upper cladding layer 31 shown in FIG. 1F. The third core layer 35 is made of AlGaInAs having a transition wavelength of 1.12 μm and has a thickness of 335 nm. The composition and thickness of the third upper cladding layer 36 are the same as the composition and thickness of the first upper cladding layer 21. Since the exposed end surface of the first core layer 21 is not easily oxidized, the occurrence of abnormal growth on the end surface can be suppressed.

  As shown in FIG. 1L, after the selective growth, the second mask pattern 33 is removed using hydrofluoric acid.

As shown in FIG. 1M, an upper cladding layer 40 made of p-type InP and having a thickness of 1.5 μm is formed on the first to third upper cladding layers 21, 31, and 36. The Zn carrier concentration in the upper cladding layer 40 is 1.0 × 10 ¹⁸ cm ⁻³ . A contact layer 41 made of p-type InGaAs and having a thickness of 0.5 μm is formed on the upper cladding layer 40. The Zn carrier concentration of the contact layer 41 is 1.0 × 10 ¹⁹ cm ⁻³ .

  As shown in FIG. 1Nx, a mesa mask pattern 45 made of silicon oxide is formed on the contact layer 41. FIG. 1Nx shows a cross section orthogonal to the waveguide direction. FIG. 1Ny shows a plan view of the mesa mask pattern 45. FIG. The second mask pattern 33 formed in the process of FIG. 1H is indicated by a broken line. A cross-sectional view taken along one-dot chain line 1N-1N in FIG. 1Ny corresponds to FIG. 1Nx. The mesa mask pattern 45 coincides with the mesa stripe region 25 and has a width of 1.5 μm.

  In the cross section shown in FIG. 1Nx (the cross section of the second region A2), the second core layer 30 and the second upper clad layer 31 are disposed immediately below the mesa mask pattern 45. The widths of the second core layer 30 and the second upper cladding layer 31 are wider than the width of the mesa mask pattern 45. A third core layer 35 is disposed on both sides of the second core layer 30, and a third upper cladding layer 36 is disposed on both sides of the second upper cladding layer 31.

  In the cross section of the first region A1, the first core layer 20 and the first upper cladding layer 21 are disposed immediately below the mesa mask pattern 45.

  As shown in FIG. 1O, etching is performed from the contact layer 41 to the surface layer portion of the semiconductor substrate 10 using the mesa mask pattern 45 as an etching mask. This etching is performed using an ICP etching apparatus. As a result, a stripe mesa structure 47 having the same planar shape as the mesa mask pattern 45 is formed.

  As shown in FIG. 1P, a buried layer 48 made of Fe-doped high resistance InP is selectively grown on both sides of the stripe mesa structure 47 using the mesa mask pattern 45 as a mask for selective growth. The thickness of the buried layer 48 is controlled so that the upper surface of the buried layer 48 is at the same height as the upper surface of the contact layer 41. After the buried layer 48 is formed, the mesa mask pattern 45 is removed.

  As shown in FIG. 1Qx, a contact mask pattern 50 made of silicon oxide is formed on the contact layer 41. FIG. 1Qy shows a plan view of the contact mask pattern 50. FIG. A cross-sectional view taken along one-dot chain line 1Q-1Q in FIG. 1Qy corresponds to FIG. 1Qx. The contact mask pattern 50 covers the second region A2.

  As shown in FIG. 1R, the contact layer 41 is etched using a mixed liquid of hydrofluoric acid and nitric acid using the contact mask pattern 50 as an etching mask. The upper cladding layer 40 is exposed in a region not covered with the contact mask pattern 50.

  As shown in FIG. 1S, the contact mask pattern 50 is removed.

  As shown in FIG. 1T, the upper electrode 51 is formed on the contact layer 41 remaining in the second region A2, and the lower electrode 52 is formed on the back surface of the semiconductor substrate 10. The upper electrode 51 has a three-layer structure of Au / Zn / Au, and the lower electrode 52 has a two-layer structure of AuGe / Au.

  As shown in FIG. 1U, the substrate is cleaved along the (110) plane perpendicular to the waveguide direction and divided into chip arrays.

  As shown in FIG. 1V, non-reflective films 54 and 55 are formed on the cleaved surfaces on both sides of the chip array. Then, it is divided into chips by cleaving along the (1-10) plane parallel to the waveguide direction. The second region A2 functions as a distributed feedback semiconductor laser element, and the first region A1 and the second region A3 function as distributed reflection regions. The first core layer 20 in the first region A1 and the second core layer 30 in the second region A2 are joined together by a butt joint structure, and the first core layer 20 in the first region A1 and the third core layer 30 The third core layer 35 in the region A3 is joined by a butt joint structure. Laser light is emitted from the end of the second region A2 to the outside.

  In the first embodiment, as described above, the second core layer 30 containing Al and the third core layer 35 are coupled via the first core layer 20 not containing Al. Further, oxidation of the end face of the core layer during selective growth can be prevented, and abnormal growth can be suppressed.

  FIG. 2Ay shows a plan view of the first mask pattern 22 used in the second embodiment. FIG. 2Ax is a cross-sectional view taken along one-dot chain line 2A-2A in FIG. 2Ay. The main portion 22A of the first mask pattern 22 used in Example 1 covers the entire area in the first region A1 and the third region A3 in the mesa stripe region 25 as shown in FIG. 1Dy. It was. The main portion 22A of the first mask pattern 22 used in the second embodiment covers the entire area in the first area A1 in the mesa stripe area 25, but the first area A1 in the third area A3. Cover only the part that touches. Of the mesa stripe region 25 in the third region A3, the first mask pattern 22 is not disposed in a region away from the first region A1.

  A sub part 22B extends from both ends of the main part 22A in a direction orthogonal to the waveguide direction. The boundary between the first region A1 and the third region A3 is located inside the sub part 22B.

  2Ax corresponds to the cross-sectional view shown in FIG. In Example 1, in the mesa stripe region 25, the second core layer 30 grew only in the first region A1. In Example 2, as shown in FIG. 2Ax, the second core layer 30 grows also in the third region A3.

  FIG. 2By shows a plan view of the second mask pattern 33 used in the second embodiment. FIG. 2Bx shows a cross-sectional view taken along one-dot chain line 2B-2B in FIG. 2By. The first mask pattern 22 formed in the process shown in FIG. 2Ay is indicated by a broken line. The shape and arrangement of the second mask pattern 33 are the same as the shape and arrangement of the second mask pattern 33 used in Example 1 shown in FIGS. 1Hx and 12Hy. That is, the second mask pattern 33 is wider than the mesa stripe region 25 and includes the mesa stripe region 25 in the first region A1 and the second region A2.

  The first and second upper clad layers 21 and 31 and the first and second core layers 20 and 30 are etched using the second mask pattern 33 as an etching mask. The structure after the etching is the same as the structure in the middle of the manufacturing method according to Example 1 shown in FIG. 1J. The subsequent steps are the same as those in the first embodiment.

  The area of the first mask pattern 22 used in the second embodiment is smaller than the area of the first mask pattern 22 used in the first embodiment. For this reason, when the second core layer 30 shown in FIG. 2Ax is selectively grown, compositional deviation and film thickness deviation due to the selective growth effect can be suppressed. In particular, when the composition and film thickness of the multiple quantum well structure deviate from the target values, the shift of the transition wavelength becomes larger than when the composition and film thickness of the bulk structure film deviate from the target values. For this reason, the first mask pattern 22 used for the selective growth of the second core layer 30 having the multiple quantum well structure rather than the second mask pattern 33 used for the selective growth of the third core layer 35 having the bulk structure. It is effective to make this smaller.

  In the second embodiment, as compared with the first embodiment, the gain reduction of the distributed feedback (DFB) semiconductor laser element having the second core layer 30 as an active layer is suppressed, and the influence of reflection at the butt joint portion is reduced. Can do.

  With reference to FIGS. 3A to 3Y, a method of manufacturing an optical waveguide device according to Example 3 will be described. For forming the III-V compound semiconductor layer, MOVPE is used as in the case of Example 1. As shown in FIG. 3Y, the optical waveguide device manufactured by the method according to the third embodiment includes a DFB semiconductor laser unit DFB, a passive unit PS, an electron absorption modulation unit EA, a passive unit PS, and a semiconductor optical amplification unit SOA arranged in a line. including. With respect to the waveguide direction, a region where the electron absorption modulation unit EA and the passive units PS on both sides thereof are arranged is defined as a first region A1, and a region where the DFB semiconductor laser unit is arranged is a second region A2. And the region where the semiconductor optical amplifier SOA is arranged is defined as a third region A3. Moreover, the area | region where the electronic absorption modulation part EA is arrange | positioned among 1st area | region A1 is defined as 4th area | region A4.

  As shown in FIG. 3A, a buffer layer 11, a diffraction grating formation layer 12, and a diffraction grating cap layer 13 are formed on the semiconductor substrate 10. The structure of these layers is the same as that shown in FIG.

  As shown in FIG. 3B, the diffraction grating 14 is formed in the second region A2 by patterning the diffraction grating forming layer 12 and the diffraction grating cap layer 13. The diffraction grating 14 has periodicity in the waveguide direction ([110] direction), the period is 200 nm, and the duty ratio is 50%. A diffraction grating is not formed in the first region A1 and the third region A3.

  As shown in FIG. 3C, the diffraction grating 14 is embedded with a spacer layer 15. The spacer layer 15 has the same composition and film thickness as the spacer layer 15 of Example 1 shown in FIG. 1C. A first core layer 20 made of InGaAsP having a transition wavelength of 1.12 μm is formed on the spacer layer 15. The first core layer 20 eventually becomes the core layer of the passive part PS. A first upper clad layer 21 is formed on the first core layer 20. The first upper clad layer 21 has the same composition and film thickness as the first upper clad layer 21 of Example 1 shown in FIG. 1C.

  As shown in FIG. 3Dx, a first mask pattern 22 made of silicon oxide is formed on the first upper cladding layer 21. FIG. 3Dy shows a plan view of the first mask pattern 22. A cross-sectional view taken along one-dot chain line 3D-3D in FIG. 3Dy corresponds to FIG. 3Dx. As in the case of the first embodiment, the unit region 23 and the mesa stripe region 25 are defined on the surface of the semiconductor substrate 10. Each of the unit areas 23 is partitioned into a first area A1, a second area A2, and a third area A3. The second region A2, the first region A1, and the third region A3 are arranged in this order in the waveguide direction. The dimensions in the waveguide direction of the second region A2, the first region A1, and the third region A3 are 300 μm, 400 μm, and 300 μm, respectively.

  The first mask pattern 22 is disposed along the mesa stripe region 25 in the first region A1 and the second region A2, and includes the mesa stripe region 25. The width of the first mask pattern 22 is, for example, 15 μm. The first mask pattern 22 used in the third embodiment does not have a portion corresponding to the sub-portion 22B of the first mask pattern 22 used in the first embodiment.

  As shown in FIG. 3E, the first upper cladding layer 21 and the first core layer 20 are etched using the first mask pattern 22 as an etching mask. The spacer layer 15 is exposed in the third region A3. Although the end face of the first core layer 20 is exposed, the exposed end face is hardly oxidized because the first core layer 20 does not contain Al.

  As shown in FIG. 3F, the second core layer 30 is selectively grown on the spacer layer 15 using the first mask pattern 22 as a mask for selective growth, and then the second upper cladding layer 31 is formed thereon. Select to grow. Since the exposed end surface of the first core layer 20 is not easily oxidized, abnormal growth during selective growth is suppressed. The second core layer 30 is made of AlGaInAs having a transition wavelength of 1.3 μm and has a thickness of 335 nm. The second upper clad layer 31 has the same composition and film thickness as the first upper clad layer 21. The second core layer 30 becomes the core layer of the semiconductor optical amplifier SOA.

  As shown in FIG. 3G, the first mask pattern 22 is removed using hydrofluoric acid.

  As shown in FIG. 3Hx, a second mask pattern 33 made of silicon oxide is formed on the first and second upper cladding layers 21 and 31. FIG. 3H shows a plan view of the second mask pattern 33. A cross-sectional view taken along one-dot chain line 3H-3H in FIG. 3Hy corresponds to FIG. 3Hx. The second mask pattern 33 is disposed along the mesa stripe region 25 in the first region A1 and the third region A3 and includes the mesa stripe region 25. The width of the second mask pattern 33 is, for example, 25 μm.

  As shown in FIG. 3I, the first upper cladding layer 21 and the first core layer 20 are etched using the second mask pattern 33 as an etching mask. At this time, the second upper cladding layer 31 and the second core layer 30 are also removed simultaneously in the regions on both sides of the mesa stripe region 25 shown in FIG. The spacer layer 15 is exposed in a region not covered with the second mask pattern 33. Although the end face of the first core layer 20 is exposed, the exposed end face is hardly oxidized.

  As shown in FIG. 3J, the third core layer 35 is selectively grown on the exposed spacer layer 15 using the second mask pattern 33 as a selective growth mask. Further thereon, a third upper cladding layer 36 is selectively grown. Since the exposed end face of the first core layer 20 is not easily oxidized, abnormal growth during selective growth is suppressed. The laminated structure of the third core layer 35 is the same as the laminated structure of the second core layer 30 of Example 1 shown in FIG. 1F. The composition and thickness of the third upper cladding layer 36 are the same as the composition and thickness of the first upper cladding layer 21.

  As shown in FIG. 3K, the second mask pattern 33 is removed using hydrofluoric acid.

  As shown in FIG. 3Lx, a third mask pattern 60 made of silicon oxide is formed on the first to third upper clad layers 21, 31 and 36. The third mask pattern 60 is disposed along the mesa stripe region 25 and includes the mesa stripe region 25 in a portion other than the fourth region A4 defined inside the first region A1. The mesa stripe region 25 in the fourth region A4 is not covered with the third mask pattern 60. The width of the third mask pattern 60 is, for example, 35 μm. The length of the fourth region A4 in the waveguide direction is 300 μm, and is 50 μm away from both the second region A2 and the third region A3.

  As shown in FIG. 3M, the first upper cladding layer 21 and the first core layer 20 are etched using the third mask pattern 60 as an etching mask. Although the end face of the first core layer 20 is exposed, since the first core layer 20 does not contain Al, the exposed end face is hardly oxidized. At this time, the second and third upper clad layers 31 and 36 and the second and third core layers 30 and 35 in the region not covered with the third mask pattern 60 shown in FIG. .

  As shown in FIG. 3N, a fourth core layer 65 is selectively grown on the spacer layer 15 using the third mask pattern 60 as a mask for selective growth. Further, a fourth upper cladding layer 66 is selectively grown on the fourth core layer 65.

  The fourth core layer 65 has a structure in which a lower SCH layer, a multiple quantum well layer, and an upper SCH layer are stacked in this order. The upper SCH layer and the lower SCH layer are made of AlGaInAs having a transition wavelength of 1.0 μm and have a thickness of 50 nm. The multiple quantum well layer includes a barrier layer having a thickness of 5 nm made of AlGaInAs having a transition wavelength of 1.05 μm and a well layer having a thickness of 10 nm made of AlGaInAs having a transition wavelength of 1.30 μm. The number of repetitions of alternate lamination is, for example, 15 times. The fourth core layer 65 becomes a core layer of the electron absorption modulation unit EA. The composition and thickness of the fourth upper cladding layer 66 are the same as the composition and thickness of the first upper cladding layer 21.

  As shown in FIG. 3O, the third mask pattern 60 is removed using hydrofluoric acid.

  As shown in FIG. 3P, the upper clad layer 40 is formed on the first to fourth upper clad layers 21, 31, 36, 66, and the contact layer 41 is formed thereon. The composition and film thickness of the upper cladding layer 40 and the contact layer 41 are equal to the composition and film thickness of the upper cladding layer 40 and the contact layer 41 of Example 1 shown in FIG. 1M.

  As shown in FIG. 3Qx, a mesa mask pattern 45 is formed on the contact layer 41. FIG. 3Qy shows a plan view of the mesa mask pattern 45. FIG. A cross-sectional view taken along one-dot chain line 3Q-3Q in FIG. 3Qy corresponds to FIG. 3Qx. That is, FIG. 3Qx shows a cross section perpendicular to the waveguide direction. The mesa mask pattern 45 coincides with the mesa stripe region 25. The width of the mesa mask pattern 45 is 1.5 μm.

  In the cross section shown in FIG. 3Qx (the cross section of the second region A2), the third core layer 35 and the third upper clad layer 36 are disposed immediately below the mesa mask pattern 45. The widths of the third core layer 35 and the third upper clad layer 36 are larger than the width of the mesa mask pattern 45. A fourth core layer 65 is disposed on both sides of the third core layer 35, and a fourth upper cladding layer 66 is disposed on both sides of the third upper cladding layer 36.

  As shown in FIG. 3R, etching is performed from the contact layer 41 to the surface layer portion of the semiconductor substrate 10 using the mesa mask pattern 45 as an etching mask. As a result, the stripe mesa structure 47 including the first to fourth core layers 20, 30, 35, 65 is formed.

  As shown in FIG. 3S, the buried layer 48 is selectively grown on both sides of the stripe mesa structure 47 using the mesa mask pattern 45 as a mask for selective growth. The composition of the buried layer 48 is the same as that of the buried layer 48 of Example 1 shown in FIG. 1P. The thickness of the buried layer 48 is controlled so that the upper surface thereof is the same height as the upper surface of the contact layer 41. After the formation of the buried layer 48, the mesa mask pattern 45 is removed using hydrofluoric acid.

  As shown in FIG. 3Tx, a contact mask pattern 50 made of silicon oxide is formed on the contact layer 41. FIG. 3Ty shows a plan view of the contact mask pattern 50. A cross-sectional view taken along one-dot chain line 3T-3T in FIG. 3Ty corresponds to FIG. 3Tx. The contact mask pattern 50 covers the second to fourth regions A2 to A4.

  As shown in FIG. 3U, the contact layer 41 is etched with a mixed solution of hydrofluoric acid and nitric acid using the contact mask pattern 50 as an etching mask.

  As shown in FIG. 3V, the contact mask pattern 50 is removed. The contact layer 41 is exposed in the second to fourth regions A2 to A4.

  As shown in FIG. 3W, the upper electrode 51 is formed on the contact layer 41, and the lower electrode 52 is formed on the back surface of the semiconductor substrate 10.

  As shown in FIG. 3X, the semiconductor substrate 10 is cleaved along a boundary line of the unit region 23 perpendicular to the waveguide direction.

  As shown in FIG. 3Y, non-reflective films 54 and 55 are formed on the cleavage plane. Thereby, an optical element array having a length in the waveguide direction of 1000 μm is formed. The optical element array is divided into optical elements by cleaving along the boundary line of the unit region 23 parallel to the waveguide direction.

  Also in the third embodiment, when the second to fourth core layers 30, 35, and 65 are selectively grown, the exposed end surface orthogonal to the waveguide direction is always formed of the first core layer 20 that does not contain Al. . The end surface of the core layer containing Al is not exposed. For this reason, it is possible to suppress oxidation of the end face and to suppress abnormal growth during selective growth.

  As shown in FIG. 3Dy, the first mask pattern 22 used in the third embodiment does not have a portion corresponding to the sub-portion 22B (FIG. 1Dy) of the first mask pattern 22 used in the first embodiment. Also in the third embodiment, as shown in FIG. 4, the first mask pattern 22 having a planar shape in which the sub-portion 22B is continuous may be used for the main portion 22A. Conversely, in the first embodiment, the first mask pattern 22 that does not have the sub-portion 22B may be used.

  5Ax and 5Ay are a cross-sectional view and a plan view of the optical waveguide device manufacturing method according to the fourth embodiment in the middle of manufacturing. A cross-sectional view taken along one-dot chain line 5A-5A in FIG. 5Ay corresponds to FIG. 5Ax.

  In Example 3, the second core layer 30 formed by the first selective growth shown in FIG. 3F was the active layer of the semiconductor optical amplifier SOA. In Example 4, the first core layer 30 formed by the first selective growth becomes an active layer of the DFB laser element.

  The first mask pattern 22 used during the first selective growth includes a main part 22A and a sub part 22B. The main portion 22A is in the first region A1 between the second region A2 and the fourth region A4, and in the first region A1 between the third region A3 and the fourth region A4. Has been placed.

  One end of the main portion 22A disposed near the second region A2 coincides with the boundary between the first region A1 and the second region A2. The other end enters the fourth area A4 rather than the edge of the fourth area A4. One end portion of the main portion 22A arranged near the third region A3 enters the third region A3 from the boundary between the first region A1 and the third region A3, and the other end portion. Has entered the fourth region A4 rather than the edge of the fourth region A4. The sub portion 22B extends from the end portion of the main portion 22A in a direction orthogonal to the waveguide direction.

  During the first selective growth, the end face of the first core layer 20 is exposed as in the case of the third embodiment. Since the first core layer 20 does not contain Al, it is difficult to be oxidized. For this reason, abnormal growth at the time of selective growth can be suppressed. Further, the main portion 22A of the first mask pattern 22 used in Example 3 of FIG. 3Dy was arranged in the fourth region A4. On the other hand, the main portion 22A of the first mask pattern 22 used in the fourth embodiment is only disposed in the very vicinity of the edge of the fourth region A4, and is disposed inside the fourth region A4. It has not been. In the fourth embodiment, the region where the second core layer 30 should be selectively grown is wider than that in the third embodiment. For this reason, composition deviation and film thickness deviation of the second core layer 30 in the vicinity of the first mask pattern 22 can be suppressed.

  FIG. 5Bx shows a cross-sectional view after the second selective growth. FIG. 5By shows a plan view of the second mask pattern 33 used as a mask during the second selective growth. A cross-sectional view taken along one-dot chain line 5B-5B in FIG. 5By corresponds to FIG. 5Bx. Note that. A region where the first mask pattern 22 is disposed is indicated by a broken line. The second mask pattern 33 includes the mesa stripe region 25 in the first region A1 and the second region A2. The second mask pattern 33 is not formed on the mesa stripe region 25 in the third region A3.

  The first mask pattern 22 has entered the third region A3 rather than the boundary between the first region A1 and the third region A3. One end of the second mask pattern 33 coincides with the boundary between the first region A1 and the third region A3. For this reason, during the second selective growth, the end face of the first core layer 20 is exposed at the boundary between the first region A1 and the third region A3. Since the first core layer 20 is not easily oxidized, abnormal growth during selective growth can be suppressed.

  FIG. 5Cx shows a cross-sectional view after the third selective growth. FIG. 5Cy shows a plan view of a third mask pattern 60 used as a mask during the third selective growth. A cross-sectional view taken along one-dot chain line 5C-5C in FIG. 5C corresponds to FIG. 5Cx. A region where the second mask pattern 33 is formed is indicated by a broken line. At the time of the third selective growth, the first core layer 20 is exposed at both ends of the fourth region A4, but the end faces orthogonal to the waveguide direction of the second and third core layers 30 and 35 containing Al. Is not exposed. For this reason, abnormal growth during selective growth can be suppressed.

  In the first to fourth embodiments, the Al-containing core layer is applied to the active layer of the DFB laser element, the waveguide layer in the distributed reflection region, the active layer of the semiconductor optical amplifier, the active layer of the electroabsorption modulator, and the like. However, it can also be applied to the active layer and waveguide layer of other optical elements. In general, the present invention can be applied to a case where two or more types of waveguide layers containing Al are integrated on a single substrate. In this case, two or more kinds of waveguide layers containing Al are coupled through a waveguide layer not containing Al. At the time of selective growth, only the end face of the waveguide layer not containing Al is exposed, and the end face of the waveguide layer containing Al is not exposed.

  In Example 1 and Example 2, two selective growths are performed to form two types of waveguide layers containing Al. In Examples 3 and 4, selective growth is performed three times to include Al. Three types of waveguide layers were formed. It is also possible to increase the number of times of selective growth and perform selective growth four or more times to form four or more types of waveguide layers containing Al.

  In the first to fourth embodiments, the semiconductor substrate 10 and each layer on the substrate side of the core layer are n-type and each layer above the core layer is p-type, but the conductivity type may be reversed. Further, as a material of the first core layer 20 not containing Al, a III-V group compound semiconductor other than InGaAsP may be used. For example, a GaInNAs mixed crystal, an InGaAsSb mixed crystal, a TlInGaAs mixed crystal, an InGaAsBi mixed crystal, or the like can be used. Moreover, you may use III-V group compound semiconductors other than AlGaInAs for the 2nd-4th core layers 30, 35, and 65 containing Al. For example, an AlGaInAsP-based mixed crystal, an AlGaInNAs-based mixed crystal, an AlInGaAsSb-based mixed crystal, a TlAlInGaAs-based mixed crystal, an AlInGaAsBi-based mixed crystal, or the like can be used.

  In Examples 1 to 4, a semi-insulating buried hetero (SI-BH) structure is adopted as the buried structure of the stripe mesa structure, but a semi-insulating planar buried hetero (SI-PBH) is used. It is also possible to adopt a structure or a PN junction buried hetero (PN-BH) structure. Further, it is possible to form a so-called high mesa waveguide without forming a buried layer made of a semiconductor. Furthermore, it is also possible to use a ridge-type waveguide in which the core layer is not patterned in a mesa shape.

  In addition to the multiple quantum well structure and the bulk structure, a quantum wire structure, a quantum dot structure, and a combination thereof can be applied to the core layer.

  Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

FIGS. 1A to 1C are cross-sectional views of an element in a manufacturing stage of an optical waveguide element manufacturing method according to Example 1. FIGS. (1Dx) and (1Dy) are respectively a cross-sectional view and a plan view of the device in the middle of the manufacturing process of the optical waveguide device manufacturing method according to the first embodiment. (1E) to (1G) are cross-sectional views of the element in the middle of manufacturing of the optical waveguide element manufacturing method according to the first embodiment. (1Hx) and (1Hy) are a cross-sectional view and a plan view of the device in the middle of manufacturing of the method of manufacturing an optical waveguide device according to Example 1, respectively. (1I) to (1J) are cross-sectional views of the element in the course of manufacturing the optical waveguide element manufacturing method according to the first embodiment. (1K) to (1L) are cross-sectional views of the element in the course of manufacturing the optical waveguide element manufacturing method according to the first embodiment. (1M) is a cross-sectional view of an element in the course of manufacturing the optical waveguide element manufacturing method according to Example 1. FIG. (1Nx) and (1Ny) are respectively a cross-sectional view and a plan view of the device in the middle of the manufacturing process of the optical waveguide device manufacturing method according to the first embodiment. (1O) to (1P) are cross-sectional views of the element in the course of manufacturing the optical waveguide element manufacturing method according to the first embodiment. (1Qx) and (1Qy) are respectively a cross-sectional view and a plan view of the device in the middle of the manufacturing process of the optical waveguide device manufacturing method according to the first embodiment. (1R) to (1S) are cross-sectional views of the element in the middle of manufacturing of the optical waveguide element manufacturing method according to the first embodiment. (1T) to (1U) are cross-sectional views of the element in the middle of manufacturing of the optical waveguide element manufacturing method according to the first embodiment. (1V) is sectional drawing of the element manufactured with the manufacturing method of the optical waveguide element by Example 1. FIG. (2Ay) and (2Ax) are a plan view and a cross-sectional view of the element in the middle of manufacturing of the optical waveguide element manufacturing method according to Example 2, respectively. (2By) and (2Bx) are respectively a plan view and a cross-sectional view of the element in the middle of manufacturing of the optical waveguide element manufacturing method according to the second embodiment. (3A) to (3C) are cross-sectional views of the element in the middle of manufacturing of the optical waveguide element manufacturing method according to Example 3. (3Dx) and (3Dy) are respectively a cross-sectional view and a plan view of the device in the middle of the manufacturing process of the optical waveguide device manufacturing method according to the third embodiment. (3E) to (3G) are cross-sectional views of the element in the middle of manufacturing of the optical waveguide element manufacturing method according to Example 3. (3Hx) and (3Hy) are a cross-sectional view and a plan view of the device in the middle of manufacturing of the method of manufacturing an optical waveguide device according to Example 3, respectively. (3I) to (3K) are cross-sectional views of the element in the middle of manufacturing of the optical waveguide element manufacturing method according to the third embodiment. (3Lx) and (3Ly) are a cross-sectional view and a plan view of the device in the middle of manufacturing of the method of manufacturing an optical waveguide device according to Example 3, respectively. (3M) to (3O) are cross-sectional views of the element in the middle of manufacturing of the optical waveguide element manufacturing method according to Example 3. (3P) is a cross-sectional view of an element in the course of manufacturing the method of manufacturing an optical waveguide element according to Example 3. FIG. (3Qx) and (3Qy) are a cross-sectional view and a plan view of the device in the middle of manufacturing of the method of manufacturing an optical waveguide device according to Example 3, respectively. (3R) to (3S) are cross-sectional views of the element in the middle of manufacturing of the optical waveguide element manufacturing method according to Example 3. (3Tx) and (3Ty) are a cross-sectional view and a plan view of the device in the middle of manufacturing of the optical waveguide device manufacturing method according to Example 3, respectively. (3U) to (3V) are cross-sectional views of the element in the middle of manufacturing of the optical waveguide element manufacturing method according to the third embodiment. (3W) to (3X) are cross-sectional views of the element in the course of manufacturing the optical waveguide element manufacturing method according to the third embodiment. (3Y) is a cross-sectional view of an element manufactured by the method for manufacturing an optical waveguide element according to Example 3. 10 is a plan view of a first mask pattern used in a method according to a modification of Example 3. FIG. (5Ax) and (5Ay) are a cross-sectional view and a plan view of the device in the middle of manufacturing of the method of manufacturing an optical waveguide device according to Example 4, respectively. (5Bx) and (5By) are a cross-sectional view and a plan view of the device in the middle of manufacturing of the method of manufacturing an optical waveguide device according to Example 4, respectively. (5Cx) and (5Cy) are a cross-sectional view and a plan view of the device in the middle of manufacturing of the method of manufacturing an optical waveguide device according to Example 4, respectively.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor substrate 11 Buffer layer 12 Diffraction grating formation layer 13 Diffraction grating cap layer 14 Diffraction grating 15 Spacer layer 20 First core layer 21 First upper clad layer 22 First mask pattern 23 Unit area 25 Mesa stripe area 30 First Second core layer 31 Second upper clad layer 33 Second mask pattern 35 Third core layer 36 Third upper clad layer 40 Fourth upper clad layer 41 Contact layer 45 Mesa mask pattern 47 Stripe mesa structure 48 buried layer 50 contact mask pattern 51 upper electrode 52 lower electrodes 54, 55 non-reflective film 60 third mask pattern 65 fourth core layer 66 fourth upper cladding layers A1 to A4 first to fourth regions

Claims (4)

Forming a first core layer made of a compound semiconductor not containing Al as a group III element on a semiconductor substrate;
The first core layer in the second region in contact with the first region which is a part of the waveguide direction to be formed on the semiconductor substrate is removed, and the first region and the second region are removed. Exposing an end face of the first core layer at a boundary with a region;
Forming a second core layer made of a compound semiconductor containing Al as a group III element in the second region from which the first core layer has been removed;
The first core layer in the third region that is disposed on the opposite side of the second region with respect to the first region and is in contact with the first region is removed, and the first region Exposing the end face of the first core layer at the boundary with the third region;
Said first core layer has been removed the third region, and chromatic and forming a third core layer comprising a compound semiconductor containing Al as a group III element,
When the first core layer in the second region is removed, the first core is formed in a part of the third region that is in contact with the boundary between the first region and the third region. Leaving a layer and removing the first core layer in a region away from the first region;
In the step of forming the second core layer, the second core layer is formed also in a region where the first core layer is removed in the third region,
The method of manufacturing an optical waveguide device , wherein in the step of removing the first core layer in the third region, the second core layer in the third region is also removed .   The optical waveguide according to claim 1, further comprising a step of forming a mesa structure that is long in the waveguide direction by patterning the first to third core layers after forming the third core layer. A method for manufacturing a waveguide element. After forming the third core layer and before forming the mesa structure,
Removing the first core layer in the fourth region away from both the edge on the second region side and the edge on the third region side in the first region; Exposing the end face of the first core layer at both ends of the region of 4;
Forming a fourth core layer made of a compound semiconductor containing Al as a group III element in the fourth region,
The method for manufacturing an optical waveguide element according to claim 1, wherein in the step of forming the mesa structure, the fourth core layer is also patterned. Removing the first core layer in the third region,
Removing the first core layer partway through dry etching;
The method for manufacturing an optical waveguide element according to claim 1, further comprising a step of removing the first core layer to a bottom surface thereof by wet etching.

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