JP6154040B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine such as a ball and ball game machine (pachinko machine) and a revolving type game machine (slot machine).

  In Patent Document 1, an interrupt is generated when a power-off signal is received, data necessary for recovery of the control state is saved in the interrupt process, and the storage destination address of the saved data is stored. A gaming machine that executes a data saving process is described.

  Patent Document 2 describes a gaming machine that executes a power interruption detection process based on a power interruption detection signal by polling after prohibiting the occurrence of a timer interrupt in the main routine.

Japanese Patent No. 3768419 JP 2007-50109 A

In the gaming machine to obtain the abnormal signal, such as in Patent Document 1 of the power disconnection signal and Patent Document 2 power failure detection signal, the game medium detection signal and the error signal and the same input output by detection of the game medium A connection may be made to enter a port. In such a gaming machine, when a game medium detection signal is erroneously input to the input port due to noise or the like due to power interruption, the game medium detection signal may be erroneously detected .

Therefore, the present invention provides a game machine connected so that an abnormal signal and a game medium detection signal are input to the same input port of the control device, and erroneous detection of the game medium detection signal due to noise caused by power interruption. The purpose is to prevent .

In order to achieve the above object, the gaming machine according to the first aspect of the present invention includes a game medium detecting means, a control device, and an abnormality detecting means. When the game medium is detected, the game medium detection means outputs a game medium detection signal. The control device executes a predetermined process based on the detection of the game medium by the game medium detection means .

The abnormality detection means detects an abnormal state occurring in the gaming machine and outputs an abnormal signal indicating that an abnormality has occurred. The control device is connected so that the game medium detection signal output from the game medium detection means and the abnormality signal output from the abnormality detection means are input to the same input port, and the game medium input to the same input port. a process of determining whether it has detected the input of the processing and the abnormality signal to the same input port to acquire a detection signal, and executable within a single input processing. The control device includes a series of processes that execute the input process, the predetermined process based on the game medium detection signal acquired in the input process, and the input process and other processes other than the predetermined process at predetermined time intervals. Is executable. When the control device detects the input of the abnormal signal in the input process, the control device can execute the other process without interrupting the series of processes, and when the game medium detection signal is acquired in the input process. Even so, the predetermined processing based on the game medium detection signal is not executed.

According to a second aspect of the present invention, there is provided the gaming machine according to the first aspect, wherein the control device executes an interrupt process including the series of processes every predetermined time, and inputs an abnormal signal in the input process. If detected, a detection flag indicating that a game medium detection signal has been acquired in the input process is not generated regardless of whether or not a game medium detection signal has been acquired in the input process.

In the above configuration, in the interrupt process, the process of obtaining the game medium detection signal input to the same input port and the process of determining whether or not the input of the abnormal signal to the same input port is detected as one input with the executable in the processing, when an abnormality is detected signal at the input processing does not perform the predetermined processing based on the game medium detection signal even when the acquired game media detection signal in the input process Therefore, even if a game medium detection signal is erroneously input to the control device due to noise or the like due to power interruption, the game medium is not erroneously detected based on the erroneous input and a predetermined process is not executed. Therefore, it is possible to prevent the predetermined processing from being executed improperly due to noise or the like due to power interruption.

According to the present invention, in a gaming machine connected so that an abnormal signal and a game medium detection signal are input to the same input port of the control device, an erroneous detection of the game medium detection signal due to noise or the like due to power interruption Can be prevented .

1 is an external perspective view of a pachinko machine according to an embodiment of the present invention. It is the perspective view which open | released the glass door and front board of the pachinko machine of FIG. It is a rear view of the pachinko machine of FIG. It is an enlarged front view of the integrated display unit of the pachinko machine of FIG. It is a block diagram which shows the electrical structure of the pachinko machine of FIG. FIG. 6 is a diagram for explaining interrupt processing executed by the main control device of FIG. 5, (a) shows the contents of each interrupt processing, and (b) shows an interrupt of a power-off save processing due to power interruption during timer interrupt processing. This is shown schematically. It is a flowchart which shows the CPU initialization process which the main controller of FIG. 5 performs. It is a flowchart which shows the CPU initialization process which the main controller of FIG. 5 performs. It is a flowchart which shows the main loop which the main controller of FIG. 5 performs. It is a flowchart which shows the serial communication reception interruption process which the main controller of FIG. 5 performs. It is a flowchart which shows the timer interruption process which the main control apparatus of FIG. 5 performs. It is a flowchart which shows the detail of the port input process of FIG. It is a flowchart which shows the saving process at the time of the power-off which the main control apparatus of FIG. 5 performs. FIG. 6 is a diagram for explaining interrupt processing executed by the payout control device of FIG. 5, in which (a) shows the contents of each interrupt processing, and (b) shows an interruption of power-off saving processing due to power interruption during timer interrupt processing. This is shown schematically. It is a flowchart which shows the CPU initialization process which the payout control apparatus of FIG. 5 performs. It is a flowchart which shows the main loop which the payout control apparatus of FIG. 5 performs. It is a flowchart which shows the serial communication reception interruption process which the payout control apparatus of FIG. 5 performs. It is a flowchart which shows the timer interruption process which the payout control apparatus of FIG. 5 performs. It is a flowchart which shows the detail of the port input process of FIG. It is a flowchart which shows the saving process at the time of the power-off which the payout control apparatus of FIG. 5 performs.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  A pachinko gaming machine (hereinafter abbreviated as “pachinko machine”) P shown in FIG. 1 uses a game ball as a game medium. A player borrows a game ball from a game hall operator and uses the pachinko machine P. Play a game. In the game of the pachinko machine P, each of the game balls is a medium having a game value, and the privilege (benefits) enjoyed by the player as a result of the game is, for example, a game ball acquired by the player Based on the number of games, it can be converted into a game value. Hereinafter, the configuration of the gaming machine will be described with reference to FIGS. Further, the present invention can also be applied to other gaming machines such as a revolving type gaming machine (slot machine) in which medals are used as game media and medals are paid out as a bonus of game results.

[Overall configuration of gaming machine]
As shown in FIGS. 1 to 3, the pachinko machine P includes a machine frame (outer frame) 1, an inner frame door (front frame) 2, a glass door 3, and a game board 5. The machine frame 1 is a vertically long wooden frame, and is fastened and fixed to an island facility (not shown) in the game hall. The inner frame door 2 is attached to the machine frame 1 so as to be freely opened and closed, and the glass door 3 is attached to the inner frame door 2 so as to be freely opened and closed.

  The game board 5 is accommodated inside the inner frame door 2 and is detachably fixed to the inner frame door 2. A vertically oval opening window 6 is formed at the center of the glass door 3, and a transparent glass plate 7 covering the front of the game board 5 is attached to the opening window 6. The front surface (board surface) of the game board 5 includes a game area 8 that a player can visually recognize from the front through the opening window 6, and when the glass door 3 is closed, the inner surface (rear face) of the glass plate 7 and the game area 8. A space in which a game ball can flow down is formed.

  A cylinder lock 9 is provided on an edge of one side (right side in FIG. 1) of the inner frame door 2. When the inner frame door 2 and the glass door 3 are closed with respect to the machine frame 1 and the cylinder lock 9 is locked, the opening of the inner frame door 2 and the glass door 3 with respect to the machine frame 1 is prohibited.

  The glass door 3 integrally has a front board 4 at a lower portion thereof, and the front board 4 is provided with an upper plate 10 and a lower plate 11 protruding forward. The upper plate 10 is disposed on the upper portion of the front board 4, and the lower plate 11 is disposed below the upper plate 10. The upper plate 10 stores game balls (rented balls) rented to players and game balls (prize balls) acquired by winning a prize, and the lower plate 11 further pays out when the upper plate 10 is full. Played game balls are stored. The pachinko machine P of the present embodiment is a so-called CR machine (a model connected to the CR unit 50 (shown in FIG. 5)), and the game balls borrowed by the player are placed on the upper plate 10 separately from the prize balls. To be paid out.

  On the upper surface of the front board 4, a lending operation unit 15 and an effect button 23 are provided. The lending operation unit 15 includes a ball lending switch 12, a return switch 13, a frequency display device 14, and a ball lending display device 24, and the player has a balance in the CR unit 50 (shown in FIG. 5) that is not zero and appropriate. When a valuable medium (such as a magnetic recording medium or a storage IC built-in medium) is inserted, the remaining frequency of the inserted valuable medium is displayed on the ball lending display device 24 and a ball lending lamp ( (Not shown) lights up. When the player operates the ball lending switch 12 in such a state, a number of game balls (for example, 125 pieces) corresponding to a predetermined frequency unit (for example, 5 degrees corresponding to 500 yen) are lent out. The display device 24 displays that the lending process is in progress, and the balance frequency of the valuable medium decreases according to the lending of game balls. In the present embodiment, a CR machine is used as an example, but the pachinko machine P may be a model other than the CR machine (a model not connected to the CR unit 50). The effect button 23 receives an operation from the player regarding the effect.

  On the front surface of the front board 4, an upper dish ball removing operation unit 16 and a lower dish ball removing operation unit 17 are provided. When the upper tray ball removal operation section 16 is operated, the game balls in the upper tray 10 flow down to the lower dish 11, and when the lower dish ball removal operation section 17 is operated, the game balls in the lower dish 11 fall downward. Then discharged. The game ball discharged from the lower plate 11 is received by, for example, a ball receiving box (not shown).

  A launch handle 18 is rotatably supported at the lower right portion of the front board 4, and a launch device 19 is attached to the lower portion of the inner frame door 2. The game balls on the upper plate 1 are supplied one by one to the launching device 19, and when the player rotates the launching handle 18, the launching device 19 (launching motor 86 (shown in FIG. 5)) is activated to enter the game area 8. A game ball is launched. The game area 8 is partitioned and formed in a substantially circular shape by the guide rail 20 and the game ball regulating rail 21, and the game ball launched from the launching device 19 slides along the rails 20, 21 and moves upward to the game area 8. And then flow down by being guided and guided by game nails and windmills.

  Speakers 22 are respectively attached to the upper part of the glass door 3 and the lower part of the inner frame door 2, and a plurality of frame lamps 25 are attached to the front surface of the glass door 3. The speaker 22 emits various sound effects related to the game. The frame lamp 25 performs an effect by, for example, light emission (lighting or blinking, change in luminance gradation, change in color tone, etc.) of the built-in LED.

[Configuration of the board]
In the game area 8, there are an integrated display unit 30, an effect display device (image display) 31, a through chucker 32, an electric tulip (ordinary electric accessory) 33, a stage 34, a first start winning opening (first special figure start) (Winning port) 35, second starting winning port (second special drawing starting winning port) 36, general winning port 37, out port 38, attacker device (special electric accessory) 39, a plurality of panel lamps 60, game nails (illustrated) (Not shown), a windmill (not shown), and the like are provided. The first start winning opening 35 and the second starting winning opening 36 are arranged with an interval in the vertical direction. The panel lamp 60 performs an effect by, for example, the light emission of a built-in LED (lighting and blinking, change in luminance gradation, change in color tone, etc.).

  The integrated display unit 30 is arranged in the lower right part of the game board 3 so as not to enter the field of view of the player who is viewing the effect display device 31 at the same time. As shown in FIG. 4, the integrated display unit 30 includes a first special symbol display device (first special symbol display device) 40, a second special symbol display device (second special symbol display device) 41, and a general-purpose display. A device (normal symbol display device) 42 and a state display device 43 are provided, and these display devices 40 to 43 are attached to the game board 5 in a state of being mounted on one integrated display board 48.

  The first special symbol display device 40 changes the first special symbol (number or pattern) based on the result of the electronic lottery related to the first special symbol, which is performed when the game ball is won at the first start winning opening 35. It is to stop display after it has been made. The second special symbol display device 41 changes the second special symbol (number or pattern) based on the result of the electronic lottery related to the second special symbol, which is performed in response to the winning of the game ball in the second start winning port 36. It is to stop display after it has been made. The first special symbol display device 40 and the second special symbol display device 41 of the present embodiment stop-display the first special symbol and the second special symbol after fluctuation by the 7-segment LED. In the present embodiment, since the game based on the winning at the second start winning opening 36 is executed in preference to the game based on the winning at the first starting winning opening 35, the first special symbol and the first Two special symbols will not change at the same time.

  The normal symbol display device 42 stops and displays the result of the electronic lottery related to the normal symbol, which is performed when the game ball of the through chucker 32 passes, after changing the normal symbol (number or pattern). The normal symbol display device 42 of the present embodiment stops and displays the normal symbol after the fluctuation by the 7-segment LED.

  The state display device 43 includes a round number display unit 44, a first special figure reservation number display unit 45, a second special figure reservation number display unit 46, and a general figure reservation number display unit 47. The round number display unit 44 is composed of four lamps (LEDs), and displays how many rounds the current jackpot continues depending on the combination of turning off, turning on, or blinking of the lamps. The first special figure hold number display unit 45 wins a game ball in the first start winning opening 35, and a random number determined per first special figure (a jackpot determined random number) acquired in accordance with the winning is the first special figure hold When stored as a random number in the first special figure reservation random number storage area (not shown) of the RAM 75, the stored number is displayed as the current reservation number. The second special figure reservation number display unit 46 receives a game ball in the second start winning opening 36, and the second special figure determined random number (a jackpot determined random number) acquired in accordance with the winning is the second special figure reserved When stored as a random number in the second special figure reserved random number storage area (not shown) of the RAM 75, the stored number is displayed as the current reserved number. The figure holding number display unit 47 stores the figure holding random number stored in the RAM 75 as a figure holding random number as a figure holding random number obtained as a figure holding random number obtained in response to the passing of the game ball through the through chucker 32. When stored in an area (not shown), the current number of holds is displayed. Each of the number-of-holding display units 45, 46, and 47 is composed of lamps (LEDs), and “0” to “4” (upper limit on the number of stored ball random numbers) depending on the combination of turning off, turning on, or blinking the lamps. ) To display the number of holds.

  As shown in FIG. 2, the effect display device 31 has a liquid crystal image display, and is provided at a substantially central portion of the game board 3, and game balls to the first start winning opening 35 and the second starting winning opening 36. A predetermined effect image is displayed on the basis of the result of the electronic lottery concerning the special symbol performed in response to the winning of the prize. The effect image includes a dummy symbol (effect symbol) that fluctuates in synchronization with the first special symbol and the second special symbol that are variably displayed on the first special symbol display device 40 and the second special symbol display device 41, A display of the number of retained random numbers per special figure and a display of the number of retained random numbers determined per second special figure are included.

  The electric tulip 33 includes a pair of blade members 49 and an electric tulip driving device 51 (shown in FIG. 5). The pair of blade members 49 are rotatable about an axis orthogonal to the game board 3 and are disposed on the left and right sides of the entrance of the second start winning opening 36. When a solenoid (not shown) of the electric tulip driving device 51 is energized, the pair of blade members rotate away from each other, the electric tulip 33 opens, and the entrance of the second start winning prize port 36 is expanded. . In a state where the electric tulip 33 is closed (normal state), a game ball cannot be won in the second start winning opening 36, and winning in the second starting winning opening 36 is restricted when the electric tulip 33 is opened.

  The stage 34 is a structure in which the game ball stays temporarily while rolling, and is disposed below the effect display device 31. A first start winning opening 35 is arranged directly below the center of the stage 34, and a game ball that has dropped from the central portion of the stage 34 is guided to the first starting winning opening 35 with a high probability.

  As a result of an electronic lottery concerning a special symbol that is performed when a game ball wins at the first start winning opening 35 and the second starting winning opening 36, the attacker device 39 becomes a jackpot game per special figure (big hit). Is a device that is opened a predetermined number of times (in this embodiment, 2 rounds or 15 rounds). The attacker device 39 includes a horizontally long rectangular prize-winning opening 52, a horizontally long plate-like lid member 53, and an attacker driving device 54 (shown in FIG. 5). The lower part of the lid member 53 is supported to be openable and closable in the front-rear direction about a horizontal axis. When a solenoid (not shown) of the attacker drive device 54 is energized, the upper part of the lid member 53 tilts forward and downward. The attacker device 39 is opened to expose the big prize opening 52, and a large amount of game balls are guided to the upper surface (back side) of the lid member 53 and can win the big prize opening 52. In the state where the attacker device 39 is closed (normal state), the lid member 54 closes the big prize opening 54, so that the prize winning to the big prize opening 52 is limited when the attacker device 39 is opened.

  When a game ball is won in each winning opening (first starting winning opening 35, second starting winning opening 36, general winning opening 37, large winning opening 52), a predetermined number of gaming balls are paid out to the player as winning balls. The winning game balls are collected from the winning openings 35, 36, 37, 52 to the back side of the game board 5. In addition, game balls that have not won any of the winning openings 35, 36, 37, 52 are finally collected from the out opening 38 to the back side of the game board 5. The collected game balls are discharged out of the frame from the back side of the pachinko machine P through an out passage assembly (not shown), and further join a supply route (not shown) of the island facility.

  Inside the through chucker 32, the first start winning opening 35, the second starting winning opening 36, the general winning opening 37, and the big winning opening 52, sensors for detecting the passage of game balls (passing through the gate shown in FIG. 5). A ball detecting sensor 55, a first special figure starting ball detecting sensor 56, a second special figure starting ball detecting sensor 57, a big winning ball detecting sensor 58 and a general winning ball detecting sensor 59) are provided. Each time these sensors 55, 56, 57, 58, 59 detect the passing of a game ball, they transmit a detection signal to the main control device 70 (shown in FIG. 5). The first special figure starting ball detection sensor 56, the second special figure starting ball detection sensor 57, the big winning ball detection sensor 58 and the general winning ball detection sensor 59 receive a prize for the game ball launched into the game area 8. It functions as a winning detection means for detecting. In the following description, among these detection signals, the detection signals transmitted by the sensors 56, 57, 58, 59 are referred to as winning ball detection signals, and the detection signals transmitted from the sensor 55 are referred to as ball passing detection signals. , There is a case to distinguish the two.

[Configuration of the back side]
As shown in FIG. 3, on the back side of the pachinko machine P, a power supply device 61, a main control board unit 62, a payout control board unit 63, a sub control board unit 64, an external information terminal board 65, a power cord (power plug) 66, a ground wire (ground terminal) 67, various electronic devices (including a control computer not shown) and the like constituting the power supply system and control system of the pachinko machine P are installed.

  The external information terminal board 65 is an interface for connecting the pachinko machine P to an external electronic device (for example, a hall computer 68 (shown in FIG. 5), a data display device, etc.). Various external information signals (for example, prize ball information, door opening information, symbol determination number information, jackpot information, start port information, etc.) representing the maintenance state and the like are transmitted from the external information terminal board 65 to an external electronic device.

  The power cord 66 is connected to a power supply device (for example, AC 24 V) installed in the island facility of the amusement hall, and secures a power source (electric power) necessary for the operation of the pachinko machine P. The ground wire 67 is connected to a ground terminal installed in the island facility, and grounds the pachinko machine P.

[Configuration related to control]
Next, a configuration related to the control of the pachinko machine P will be described. FIG. 5 is a block diagram showing various electronic devices equipped in the pachinko machine P.

  The pachinko machine P includes a main control device 70, a payout control device 71, and a sub control device 72. The main control device 70 is the center of the control operation, has a function of mainly controlling the execution of game processing in the pachinko machine P, and is built in the main control board unit 62. The payout control device 71 has a function of mainly controlling payout and launch of game balls, and is built in the payout control board unit 63. The sub-control device 72 mainly has a function of controlling effects and is built in the sub-control board unit 64. The main control device 70 and the payout control device 71 are a communication line through which a command is transmitted in one direction from the main control device 70 to the payout control device 71, and one direction from the payout control device 71 to the main control device 70. Are connected by a communication line through which commands are transmitted.

(Power supply device 61)
The power supply device 61 is supplied with external power (for example, 24V AC power) from the island facility through the power cord 66, and a plurality of constant voltage DC power sources or coarse rectified DC power sources that use this AC power source in the pachinko machine P. The power is converted into power and supplied to the main controller 70, the payout controller 71, the sub controller 72, and the like. The power supply device 61 includes a backup power supply (not shown) such as a power supply circuit and a capacitor, and a power cut notification signal (when a power cut occurs) when the supply of power from an external power supply is interrupted (when a power cut occurs). A power-off detection circuit (power-off signal generating means) 96 for generating a power-off signal is provided. The power supply device 61 transmits a power-off notice signal to the main control device 70 and the payout control device 71 and supplies backup power when a power-off occurs. Note that the power-off detection circuit 96 may be provided other than the power supply device 61 (for example, the main control device 70 or the payout control device 71).

  The RWM clear switch 69 is a switch operated to clear past game information stored in the main control device 70 and the payout control device 71. The RWM clear switch 69 is provided in the power supply device 61 and is operated by the RWM clear switch 69. Then, an RWM clear signal is transmitted to the main controller 70 and the payout controller 71.

(Main controller 70)
The main controller 70 is equipped with a circuit board (main control board) on which a main control CPU 73 that is a central processing unit (central instruction processing unit) is mounted. The main control CPU 73 includes a CPU core and various registers (general purpose). Register, flag register, index register, refresh register, interrupt register, instruction register, etc.), stack pointer, program counter, instruction recorder (all not shown), etc., and LSI together with semiconductor memory such as ROM 74 and RAM (RWM) 75 It is configured as. Each register holds an operation result, an address of an instruction to be read next, an execution state, and the like. The main controller 70 is equipped with a hard random number generation circuit 76 and a sampling circuit (not shown). The hardware random number generation circuit 76 generates hardware random numbers (for example, 0 to 65535 in decimal notation), and the generated random numbers are input to the main control CPU 73 through the sampling circuit. The hardware random number is used as a determined random number per first special figure and a determined random number per second special figure for jackpot determination, or a determined random number per universal figure for hit (per common figure) determination. The main controller 70 is equipped with peripheral ICs such as a clock (frequency generating circuit unit) 77, an input / output (I / O) port, a counter / timer circuit (CTC), etc., which are circuit boards together with the main control CPU 73. Implemented above.

  The RAM 75 has a work area (not shown) including a storage area for various flags. When an interrupt occurs or when a subroutine or function is called, data being processed, a return address, and the like are stored in a stack area (a save area) of the work area. ) Is temporarily evacuated. The main control CPU 73 functions as a power-off detection unit and an execution control unit by executing processing according to the game control program stored in the ROM 74.

  The winning detection signals of the ball detection sensors 56 to 59 are input to the main control CPU 73 via an input / output driver (not shown). In this embodiment, the winning detection signals from the first special figure starting ball detection sensor 56 and the second special figure starting ball detection sensor 57 are directly transmitted to the main control device 70, and the gate passing ball detection sensor 55, Winning detection signals from the winning ball detection sensor 58 and the general winning ball detection sensor 59 are transmitted to the main controller 70 via a relay terminal board (not shown).

  Each display of the first special figure display device 40, the second special figure display device 41, the universal figure display device 42, and the status display device 43 is controlled by a control signal from the main control CPU 73. The main control CPU 73 outputs control signals for the display devices 40 to 43 in accordance with the progress of the game, and controls the lighting state of each LED.

  The driving of the electric tulip driving device 51 and the attacker driving device 54 is controlled by a control signal from the main control CPU 73. The solenoids of the drive devices 51 and 54 are operated (excited) based on a control signal from the main control CPU 73 to open / close (activate) the electric tulip 33 and the attacker device 39.

  A glass door opening switch 78 and an inner frame door opening switch 79 are installed on the inner frame door 2. When the glass door 3 is opened from the inner frame door 2, a contact signal from the glass door opening switch 78 is input to the main control device 70 via the dispensing control device 71. When the inner frame door 2 is opened from the machine frame 1, a contact signal from the inner frame door opening switch 79 is input to the main control device 70 via the payout control device 71. The main control CPU 73 that has received the contact signals from the switches 78 and 79 transmits a control signal instructing execution of these notification processes to the sub-control device 72 in order to notify the opening of the door by sound, LED, liquid crystal or the like. To do. Also, the dispensing control device 71 that has received the contact signal from the switches 78 and 79 outputs an external information signal indicating that the door is open.

  The pachinko machine P is provided with an error detection sensor 98 that detects magnetism, radio waves, and the like. The error detection sensor 98 transmits an error detection signal to the main controller 70 when it detects magnetism, radio waves, and the like. Receiving the error detection signal, the main control CPU 73 executes predetermined error processing and outputs an external information signal indicating error detection.

(Discharge control device 71)
The payout control device 71 is equipped with a circuit board (payout control board) on which a payout control CPU 80 is mounted. The payout control CPU 80 also includes a CPU core (not shown), like the main control CPU 73, and includes a ROM 81 and a RAM 82. It is configured as an LSI together with a semiconductor memory. The payout control CPU 80 controls the game ball payout operation based on the prize ball instruction command (payout command transmission signal) received from the main control CPU 73, and causes the specified number of game balls to be paid out. The main control CPU 73 generates and outputs a prize ball information signal as an external information signal separately from the prize ball instruction command. Specifically, the main control CPU 73 generates and outputs a prize ball information signal as an external information signal every time the designated number reaches a predetermined number (for example, 10). The payout control CPU 80 also generates and outputs a prize ball information signal as an external information signal every time the total number of payouts reaches a predetermined number (for example, 10).

  The game balls replenished from the ball supply path (not shown) of the game hall are stored in a prize ball tank (not shown), and flow down a prize ball bowl (not shown) and introduced into a prize ball case (not shown). , And supplied to the upper plate 10 from the prize ball case.

  The prize ball case is provided with a payout motor (for example, a stepping motor) 83, and the payout control device 71 (payout control board unit 63) is provided with a drive circuit (not shown) of the payout motor 83. The payout control device 71 rotates the payout motor 83 to pay out the game ball from the prize ball case. One game ball is paid out by one pay-out operation (a predetermined amount of rotational drive) of the pay-out motor 83, and the paid-out game ball flows down to the front board 4 through a pay-out passage (not shown). To do.

  A payout counting switch 84 is installed on the downstream side of the payout motor 83, and when a prize ball is actually paid out by driving the payout motor 83, a payout count signal (payout detection signal) from the payout count switch 84 is sent out to the payout control device 71. Sent to. The payout count signal is transmitted every time a payout of one game ball is detected, and the payout control CPU 80 detects the actual payout number and the out of ball state based on the received payout count signal, and pays out the game ball. Manage.

  When an appropriate valuable medium whose balance is not zero is inserted into the CR unit 50, the CR unit 50 sends a lending device READY signal indicating that lending is being performed (the ball lending is possible), While transmitting to the payout control device 71 via the relay substrate 91, the lending permission LED signal and the frequency display LED signal are transmitted to the ball rental display device 24 and the frequency display device 14 via the relay substrate 91. The ball lending display device 24 that has received the ball lending LED signal turns on the ball lending available lamp, and the frequency display device 14 that has received the frequency display LED signal displays the balance frequency of the valuable medium. When the ball lending switch 12 is operated in this state, the operation signal (lending switch signal) is transmitted to the CR unit 50 via the relay board 91, and the CR unit 50 that has received the lending switch signal receives the valuable medium. A balance subtraction process is executed, and a terminal terminal lending request completion confirmation signal is transmitted to the dispensing control device 71 via the relay board 91. The terminal terminal lending request completion confirmation signal is a signal that requests lending of the game balls for the basic unit (25 pieces). For example, one operation of the ball lending switch 12 makes a lending request for 5 times (125 pieces). When the setting is made on the CR unit 50 side so as to correspond, when the ball lending switch 12 is operated once, the terminal terminal lending request completion confirmation signal is repeatedly transmitted five times.

  The RAM 82 (payout remaining number storage means) of the payout control device 71 is provided with a remaining payout number storage area for storing the remaining payout number of game balls. The payout remaining number storage area stores a prize ball memory area for storing the number of game balls scheduled to be paid out as a prize ball (the number of remaining prize balls), and a loan for storing the number of game balls scheduled to be paid out as a loan (number of remaining loans) It is divided into memory areas. When the payout control CPU 80 receives the prize ball instruction command from the main control CPU 73, the payout control CPU 80 adds the number of prize balls remaining by the number of prize balls indicated by the received prize ball instruction command, and receives a terminal terminal lending request completion confirmation signal from the CR unit 50. When received, the remaining number of loans is added by the basic unit. In the game ball payout operation, each time the payout control CPU 80 receives a payout count signal from the payout count SW84, the payout control CPU 80 subtracts one of the remaining prize balls or the remaining number of loans, and the remaining number of prize balls and the remaining number of loans. The payout operation is continued until both of them become zero. Note that the payout control CPU 80 of the present embodiment executes the payout of the remaining number of loans with priority over the remaining number of winning balls. That is, when the remaining loan amount is not zero, the remaining loan amount is preferentially subtracted until the remaining loan amount becomes zero, and only when the remaining loan amount is zero, the remaining prize ball is subtracted, The payout ends when the remaining number of prize balls reaches zero. If a process (successful ball payout process) is set to continuously execute a single prize ball payout up to a predetermined unit number (for example, 25) as an upper limit, continuous prize ball payout is set. Even if the remaining loan amount increases from zero during the process, the process (prize ball payout) is continued without interruption until the ongoing continuous ball payout process is completed. Then, after one consecutive prize ball payout process is completed, if the remaining number of prize balls is not zero even if the remaining number of prize balls has not yet reached zero, the remaining number of outstanding balls is more than the remaining number of prize balls. Priority is given to paying out. The payout control CPU 80 sends a stand READY signal indicating this when the payout operation is executable, and a stand terminal lending completion signal indicating this when the lending for the basic unit is completed, via the relay board 91. To each.

  A tray full tank switch 85 is installed in the supply path of game balls to the upper plate 10 (shown in FIG. 1), and when the lower plate 11 (shown in FIG. 1) is full of game balls, the plate full tank switch 85 is turned on. It becomes ON, and a full tank detection signal is transmitted to the payout control device 71. The payout control CPU 80 that has received the full tank detection signal temporarily holds the prize ball operation according to the prize ball instruction command received from the main control CPU 73, and stores the unpaid prize ball remaining number in the RAM 82. The RAM 82 can be backed up even when the power is cut off, so that even if a power outage (including momentary power outage) occurs during the game, the information on the number of remaining unpaid prize balls will not be lost. .

  The firing device 19 (shown in FIG. 2) is provided with a firing motor 86 and a ball feed solenoid 87, and the firing handle 18 (shown in FIG. 1) has a firing volume 88, a touch sensor 89, a firing stop switch 90, Is provided. The ball feed solenoid 87 sends game balls that have flowed down from the upper plate 10 (shown in FIG. 1) one by one to the launch position, and the launch motor 86 launches the game balls sent to the launch position. In addition, the launch interval of game balls is, for example, about 0.6 seconds (within 100 per minute).

  The firing volume 88 transmits a firing force instruction signal proportional to the rotational operation amount (stroke) of the firing handle 18 (shown in FIG. 1) to the dispensing control device 71. The touch sensor 89 detects that the player's body is touching the firing handle 18 from the change in capacitance, and transmits the detection signal to the payout control device 71. The firing stop switch 90 transmits a firing stop signal (contact signal) to the payout control device 71 when operated by the player.

  When the player rotates the firing handle 18, a firing force instruction signal corresponding to the amount of rotational operation is transmitted from the firing volume 88 to the payout control device 71. The payout control CPU 80 controls driving of the firing motor 86 based on the received firing force instruction signal. Thereby, the launch strength of the game ball is adjusted according to the operation amount of the player. However, the payout control CPU 80 stops driving the firing motor 86 when the detection signal from the touch sensor 89 is off (low level) and when the firing stop signal is input from the firing stop switch 90. In addition, the payout control CPU 80 stops the driving of the firing motor 86 when the CR unit 50 is not connected to the pachinko machine P.

  On the substrate of the payout control device 71, a state LED (not shown) is provided. The status LED is a power LED that emits light when power is supplied from the power supply, a pan full LED that emits light when the pan is full, a communication error LED that emits light when a communication error occurs, a door open LED that emits light when the door is open, and a payout operation failure It includes a payout operation failure LED that emits light, and a CR unconnected LED that emits light when not connected to the CR unit 50. The emission control of the status LED is executed by the payout control CPU 80 based on reception of a corresponding signal (command).

(Sub-control device 72)
The sub-control device 72 is equipped with a circuit board (composite sub-control board) on which an effect control CPU 92 is mounted. The effect control CPU 92 also includes a CPU core (not shown), like the main control CPU 73, and includes a ROM 93, The semiconductor memory such as the RAM 94 is configured as an LSI. The sub-control device 72 is equipped with an input / output driver and various peripheral ICs (both not shown).

  The ROM 93 of the sub-control device 72 stores an effect control program related to effect control, and the effect control CPU 92 follows an effect command transmitted from the main control CPU 73 in accordance with the stored effect control program. The effect control by the effect display device 31, the various lamps 25 and 60, the sound generator 97 and the movable accessory is executed. The effect display device 31 includes an image processor, a liquid crystal, and the like, and the sound generation device 97 includes a sound processor, a speaker 22, and the like. The production control includes image display control of the production display device 31, light emission control of the various lamps 25 and 60, sound generation control from the speaker 22, and drive control of the movable accessory drive device 95. Note that the image processor and the sound processor may be provided in the sub-control board unit 64.

(Output to the outside)
Various external information signals generated in the main control device 70 and the payout control device 71 are output from the external information terminal board 65 to the outside. The signals output from the external information terminal board 65 are totaled, for example, by a hall computer 68 in a game hall.

[Description of input port of main controller 70]
A plurality of ports (including three input ports of input port 0, input port 1, and input port 2 in this embodiment) are set as input / output ports of main controller 70. The input port 0 includes a switch abnormality signal (a disconnection signal of the detection sensors 55 to 59 mounted on the game board 5), a door opening signal (contact signals from the door opening switches 78 and 79), and an error detection signal (error detection sensor 98). ), A payout command permission signal (a signal from the payout control device 71), and an RWM clear signal (a signal from the power supply device 61). A winning ball detection signal from the big winning ball detection sensor 58 and the general winning ball detection sensor 59 is assigned to the input port 1. The input port 2 has a winning ball detection signal from the first special figure starting ball detection sensor 56, a winning ball detection signal from the second special figure starting ball detection sensor 57, and a ball passage detection signal from the gate passing ball detection sensor 55. , And a power-off notice signal from the power supply device 61 is assigned. Each input port is provided with a 1-bit reception storage area whose state is switched at the time of reception of each signal (switched at 1/0), and input confirmation of each signal is performed by bit check of the corresponding reception storage area. . The input port 2 functions as a power-off signal receiving unit that receives a power-off notice signal when a power-off occurs, and the state of the corresponding reception storage area is switched while the power-off notice signal is input to the input port 2. .

[Control processing executed by main controller 70]
Next, the control process executed by the main control CPU 73 of the main control device 70 according to the game control program stored in the ROM 74 will be described. The control processing executed by the main control CPU 73 includes CPU initialization processing as a main routine, main loop, serial communication reception interrupt processing, timer interrupt processing (main interrupt processing), and power-off saving processing. Control the execution of these processes.

  As shown in FIG. 6A, the interrupt generation factor of the serial communication reception interrupt process is established by reception of the main command, and the occurrence factor of the timer interrupt process is established every predetermined period (4 ms in this embodiment). The cause of the interruption of the saving process when the power is cut off is established by the occurrence of the INT interruption due to the reception of the power cut notice signal. The serial communication reception interrupt process, the timer interrupt process, and the power-off save process are set so that the interrupt priority becomes higher in this order. The serial communication reception interrupt process and the power-off save process prohibit multiple interrupts, and the timer interrupt process allows multiple interrupts.

  That is, in the main controller 70, as shown in FIG. 6B, the main routine is repeatedly executed as the basic process, and the timer interrupt process is activated at predetermined intervals to interrupt the main loop. When a main command is received during execution of the main routine or timer interrupt processing, serial communication reception interrupt processing is activated and interrupts the main loop or timer interrupt processing (not shown). If a power-off notice signal is received during execution of the main routine (serial communication reception interrupt processing and timer interrupt processing are not being executed and the main command has not been received), the power-off save processing is activated and the main routine is entered. interrupt. Further, when the power interruption notice signal is received during the execution of the timer interruption process, the power interruption interruption process is started after the timer interruption process is completed and the process returns to the main loop. However, the serial communication reception interrupt processing and main interrupt processing are not activated during the power-off save process, and if an interrupt factor is established during the power-off save process, the power-off save process is performed. The corresponding interrupt processing is started after waiting for the end of. Note that the interrupt process is started on condition that the interrupt destination process (the process currently being executed) is in the interrupt enabled state.

  In addition, the main interrupt process is a process of acquiring and storing the contents of the input port 1 and the input port 2 (steps S123 and S126 in FIG. 12) and whether the game ball has won based on the information acquired by the port input process. A winning determination process (a process for generating an on-edge detection flag for the input port 1 (step S125 in FIG. 12), a process for generating an on-edge detection flag for the input port 2 (step S128 in FIG. 12)), and a jackpot A jackpot determination process (switch management process in FIG. 11 (step S69) and a special game management process) in which an electronic winning lottery for determining whether or not to generate a gaming state is executed according to the determination result in the winning determination process (Step S70)) and a payout control management process (FIG. 11) for generating a payout command transmission signal according to the determination result in the winning determination process Step including S74 as), the output process of transmitting a payout command transmit signal produced at the payout control management process to the payout controller 71 (step S79 in FIG. 11). While the main CPU 73 prohibits interruption of the power-off saving process during execution of the timer interruption process, the main CPU 73 receives a power-off notice signal before executing the winning determination process in the timer interruption process being executed (step in FIG. 12). In S124: Yes, step S127: Yes, the winning determination process is not executed.

(CPU initialization process)
When power is turned on to the pachinko machine P, the main control CPU 73 starts a CPU initialization process. A stable game operation of the pachinko machine P is guaranteed by the CPU initialization process.

  7 and 8 are flowcharts showing a CPU initialization process executed by the main control CPU 73.

  When the CPU initialization process is started, the top address (address initial value) of the stack area is set in the stack pointer (step S1), and the vector type interrupt mode (interrupt mode mode 2) is set (step S2). As a result, the main control CPU 73 can refer to an arbitrary address (however, the least significant bit is 0) as an interrupt vector and execute a specified interrupt handler.

  Next, an interrupt vector table is set (step S3), a built-in register is set (step S4), the contents of the input port 0 are read twice (step S5), the result of the input port 0 is logically converted, and the RAM 75 Retreat to the retreat area (step S6).

  Next, a reset standby process is executed. In this process, a certain waiting time (for example, about several thousand ms) is secured at the start of reset (for example, power-on), and the power-off notice signal for the input port 2 is checked during that time. In this embodiment, a loop counter for 2 seconds is set as waiting for the start of sub-control (step S7), and the input port of the power-off notice signal is bit-checked while decrementing the value of the loop counter (step S8). If a power-off notice signal is input before 2 seconds elapse (before the loop counter reaches 0) (step S9: Yes), the process returns to the beginning of the reset standby process (step S7). This process is continued until two seconds elapse without inputting the power-off notice signal (Step S9: Yes → Step S7, or Step S9: No → Step S10: No → Step S8), and the power-off notice signal is inputted. If 2 seconds elapse without (step S9: No-> step S10: Yes), this process is terminated. Thereby, for example, transmission of a control signal from the main control device 70 to the sub control device 72 before the start of the start processing of the sub control device 72 can be prevented. Further, it is possible to protect the system when the operation of turning on and off the main power switch (not shown) is repeatedly performed within a short time (about 1 to 2 seconds).

  Next, access to the work area of the RAM 75 is permitted (step S11). Specifically, the RAM protect setting value in the work area is reset. As a result, the access to the work area of the RAM 75 is permitted thereafter.

  Next, the result of the input port 0 saved in step S6 is restored (step S12), the RWM clear signal of the restored input port 0 is referred to, and the bit of the RWM clear signal is turned on (RWM clear switch 69). Is determined) (step S13).

  When the RWM clear switch 69 is not operated (step S13: No), it is determined whether or not the backup validity determination value (backup validity determination flag) is stored in the RAM 75. Specifically, the data in the backup judgment storage area of the RAM 75 is compared with the backup validity judgment value (step S14), and if they match (when the backup validity judgment flag is set), the power is turned off. It is determined that it is a CPU initialization process after the time saving process has been properly completed (step S15: No), and when there is a mismatch (when the backup validity determination flag is not set), the saving process at the time of power-off is performed. It is determined that the CPU initialization process is not properly completed (step S15: Yes).

  If it is a CPU initialization process after the power-off saving process is properly completed (step S15: No), a sum check is performed on the backup information in the RAM 75. Specifically, the checksum value is calculated for the work area of the RAM 75 (the user work area including the use prohibition area and the stack area) excluding the backup determination storage area and the sum check buffer (step S16). It is determined whether or not the checksum value is a normal value (step S17). Specifically, the checksum value calculated in step S16 is compared with the checksum value saved in the power-off saving process (step S108), which will be described later, and if they match, it is determined to be a normal value. If they are different, it is determined that the values are not normal.

  If the checksum value is a normal value (step S17: Yes), a return process (step S18 to step S20) is executed.

  In the return process, after resetting the power return clear area (for example, the backup determination storage area) (step S18), the effect control return process (step S19) and the payout control return process (step S20) are executed.

  In the effect control return process (step S19), the sub-control device 72 is instructed to return to the sub-control device 72 (for example, model designation command, special symbol probability state designation command, working memory number command, number-of-times counter remaining command, special game) Send a status specification command. Receiving this, the sub control device 72 performs the effect state (for example, internal probability state, effect symbol display mode, working memory count effect display mode, sound output content, various lamps, etc. that were being executed at the previous power-off. Light emission state).

  In the payout control return process (step S20), a payout command for power supply return is transmitted to the payout control device 71. Receiving this, the payout control device 71 restores the previous power-off state and cancels the payout prohibition state.

  On the other hand, if the RWM clear switch 69 has been operated (step S13: Yes), if it is not a CPU initialization process after the power-off saving process is properly completed (step S15: Yes), or the checksum value is If it is not a normal value (step S16: No), an initialization process (steps S21 to S24) is executed.

  In the initialization process, all storage areas other than the use-prohibited area of the RAM 75 are cleared (step S21). As a result, the work area and stack area of the RAM 75 are all initialized.

  Next, the RAM 75 is initialized by setting an initial value at the time of clear activation in the RAM 75 (step S22), and an effect control initialization process (step S23) and a payout control initialization process (step S24) are executed.

  In the effect control initialization process (step S23), a subcommand for RWM clear designation is transmitted to the sub-control device 72. Receiving this, the sub-control device 72 initializes the effect control state. In the payout control initialization process (step S24), a payout command for RWM clear is transmitted to the payout control device 71. Receiving this, the payout control device 71 initializes the payout control state and cancels the payout prohibition state.

  When the payout control return process (step S20) or the payout control initialization process (step S24) ends, the subcommand after power-on is transmitted to the effect control device 73 (step S25), and the contents of the input port 1 are acquired. (Step S26) The contents of the input port 2 are acquired (Step S27), the random number latch register is cleared (Step S28), the main command permission signal is set (Step S29), and the timer interrupt counter is set (Step S29). In step S30, the interrupt daisy chain is reset (step S31), and the process proceeds to the main loop. By resetting the interrupt daisy chain (step S31), when the determination of step S113 (see FIG. 13) in the power-off saving process, which will be described later, shifts to the CPU initialization process in Yes, the RETI when exiting from the interrupt process Since the processing is not performed, even if the interrupt is permitted in step S45 (see FIG. 9) in the main loop to be described later, it is prevented that the processing does not shift to each interrupt processing.

(Main loop)
FIG. 9 is a flowchart showing a main loop executed by the main control CPU 73.

  In the main loop, after interrupts are prohibited (step S41), initial value random number update processing (step S42), main command analysis processing (step S43), subcommand transmission processing (step S44) are executed, and interrupts are permitted. (Step S45), Other random number update processing (Step S46) is executed, and the process returns to Step S41. Therefore, a period during which interruption of the power-off saving process is allowed for the main loop is during the execution of the other random number update process (step S46).

  In the initial value random number update process (step S42), the initial value update random number for winning symbol random numbers is updated. The initial value update random number for the winning symbol random number is a software random number for determining the initial value and the end value of the winning symbol random number. The winning symbol random number is a software random number used for the lottery of the winning type. Note that the reason why step S42 is executed in a state where interrupts are prohibited (step S41) is the same as the timer interrupt process (step S67 in FIG. 11), and therefore overlap (conflict) with this is prevented. Because. In addition, the winning determination random number (normal winning winning random number) and the big winning determining random number (special winning winning random number) of the present embodiment are hardware random numbers generated by the hard random number generation circuit 76, and the update cycle thereof is a timer. Since it is faster (for example, several μs) than the interrupt cycle (for example, several ms), it is not necessary to update the initial value of the jackpot decision random number.

  The main command analysis process (step S43) is a process for analyzing commands received from the payout control device 71 (including payout commands for specifying various error occurrences and payout commands for specifying error cancellation). In the subcommand transmission process (step S44), a subcommand (a subcommand necessary for presentation control) to be transmitted after the initial setting is transmitted to the presentation control device 72. In other random number update processing (step S46), for example, reach group determination random numbers, reach mode determination random numbers, fluctuation pattern random numbers, and the like are updated. The reach group decision random number is a software random number used for the lottery of the special symbol variation pattern reach group, and the reach mode decision random number is a software random number used for the lottery of the special symbol variation pattern reach mode. Is a software random number used for drawing a special symbol variation pattern.

(Serial communication reception interrupt processing)
FIG. 10 is a flowchart showing serial communication reception interrupt processing executed by the main control CPU 73. When the main control CPU 73 receives a main command (for example, various payout commands input from the payout control device 71) while interrupting the main loop or permitting interrupt of the timer interrupt process, the main control CPU 73 gives priority to the received main command. Interrupt the serial communication reception interrupt process to process.

  As shown in FIG. 10, in the serial communication reception interrupt process, the value of the AF register is saved in the save area of the RAM 75 (step S51), and the contents of the status register of channel A (CHA) are loaded (step S52). It is checked whether or not there is data in the FIFO (step S53), the received value is obtained from the CHA data register (step S54), and it is determined whether or not there is data in the receiving FIFO (step S55). If there is no data (step S55: Yes), the value of the AF register saved in step S51 is restored (step S57), the interrupt is permitted (step S58), and the serial communication reception interrupt process is terminated. On the other hand, if there is data in the reception FIFO (step S55: No), the reception data is stored in the main command buffer (step S56), the value of the AF register saved in step S51 is restored (step S57), and an interrupt is issued. After permitting (step S58), the serial communication reception interrupt process is terminated. Upon completion of the serial communication reception interrupt process, the process returns to the main loop (program address indicated by the stack pointer).

(Timer interrupt processing)
FIG. 11 is a flowchart showing timer interrupt processing executed by the main control CPU 73. In the main control CPU 73, the counter / timer circuit generates an interrupt request signal every predetermined period, and based on the generation of the interrupt request signal, interrupts the timer interrupt processing in the main loop that is permitted to interrupt.

  As shown in FIG. 11, in the timer interrupt process, all register values used during execution of the main loop are saved in the save area of the RAM 75 (step S61). Another value can be written into the register after saving the value during the timer interrupt processing.

  Next, the interrupt flag is initialized (step S62), the interrupt is permitted (step S63), the dynamic port output process is executed (step S64), and the port input process is executed (step S65). With the initialization of the interrupt flag (step S62), the interrupt flag is set every 4 ms, and the timer interrupt process is periodically executed every 4 ms.

  In the port input process (step S65), as shown in FIG. 12, the on-edge detection flag is cleared (step S121), the contents of the input port 0 are acquired and stored (step S122), and the contents of the input port 1 are acquired and stored. After saving (step S123), it is determined whether or not a power-off notice signal is received (step S124). Specifically, the input port of the power-off notice signal is bit-checked to determine whether or not the power-off notice signal is input.

  When the power-off notice signal is not received (step S124: No), the on-edge detection flag of the input port 1 is generated (step 125), and when the power-off notice signal is received (step S124: Yes). In this case, the on-edge detection flag for the input port 1 is not generated. The detection of the winning of the game ball to the big winning opening 52 and the general winning opening 37 is performed by changing the reception storage area (1 bit) corresponding to the big winning ball detecting sensor 58 and the general winning ball detecting sensor 59 to the reception state. For example, when the reception storage area corresponding to the general winning ball detection sensor 59 has been switched to the reception state, the corresponding on-edge detection flag must be received as a power-off notice signal. If the power-off notice signal is received, it is not set to ON and is kept off.

  Next, as with the input port 1, after acquiring and saving the contents of the input port 2 (step S126), it is determined whether or not a power-off notice signal has been received (step S127).

  When the power-off notice signal has not been received (step S127: No), the on-edge detection flag of the input port 2 is generated (step 128), this processing is terminated, and the power-off notice signal is received. In the case (step S127: Yes), this process ends without generating the on-edge detection flag of the input port 2. Receiving storage areas corresponding to the first special figure start ball detection sensor 56 and the second special figure start ball detection sensor 57, respectively, for detecting the winning of the game ball to the first start winning opening 35 and the second start winning opening 36. For example, when the reception storage area corresponding to the second special figure starting ball detection sensor 57 is switched to the reception state, the corresponding on-edge is detected. The detection flag is set to ON if the power-off notice signal is not received, and is kept off without being set to ON if the power-off notice signal is received. The detection of the passage of the game ball to the through chucker 32 is performed by detecting the change (rise) of the reception storage area (1 bit) corresponding to the gate passing ball detection sensor 55 to the reception state. If the reception storage area corresponding to the ball detection sensor 55 has been switched to the reception state, the corresponding on-edge detection flag is set to ON if the power-off notice signal has not been received, and the power-off notice signal has been received. Keep it off without setting it on.

  Thus, in the port input process, the passage detection signal from the gate passage ball detection sensor 55, the first special figure start ball detection sensor 56, the second special figure start ball detection sensor 57, the big winning ball detection sensor 58, and The input state (ON / OFF) of the winning detection signal from the general winning ball detection sensor 59 is read. If it is not when the power is cut off, it detects the passing or winning of the game ball by detecting the change of the receiving storage area to the receiving state, and if the passing or winning is detected, the corresponding on-edge detection flag is set to ON. Then, this process is terminated. On the other hand, when the power is cut off, the process is terminated without detecting the passing of a game ball or winning. When this process ends, the timer update process (step S66) and the initial value random number update process (step S67) in FIG. 11 are executed.

  In the timer update process (step S66), the count value of the counter / timer circuit is updated to the initial value, and the cycle count is restarted. In the initial value random number update process (step S67), the same process as the initial value random number update process (step S42 in FIG. 9) of the main loop is executed.

  Next, a winning symbol random number update process is executed (step S68). In the winning symbol random number update process, the value of the counter for generating the winning symbol random number for jackpot symbol lottery is updated. The counter value is incremented in the counter area of the RAM 75 and loops within a specified range.

  Next, switch management processing is executed (step S69). In the switch management process, a game ball won in the first start winning opening 35 detected in the port input process (step S65), a game ball win in the second start winning opening 36, and a game ball in the through chucker 32 is obtained. The hard random number used for each success / failure determination process is acquired based on the passage of.

  Specifically, when the winning of the game ball to the first start winning opening 35 is detected (when the corresponding on-edge flag is on), the first special figure reserved random number storage area stored in the RAM 75 is stored. It is determined whether or not the number of one special figure reserved random number is less than the upper limit number (4). If the number does not reach the upper limit number, a determined random number per first special figure is obtained and used as the first special figure reserved random number. Store in the first special figure reserved random number storage area. On the other hand, when the number of first special figure reservation random numbers has reached the upper limit, the determined random number per first special figure is not acquired.

  Similarly, when the winning of the game ball to the second start winning opening 36 is detected (when the corresponding on-edge flag is on), the second special figure stored in the second special figure holding random number storage area of the RAM 75 is detected. It is determined whether or not the number of figure-holding random numbers is less than the upper limit number (4). If the number does not reach the upper-limit number, a determined random number per second special figure is obtained and the second special figure holding random number is second. Store in the special figure holding random number storage area. On the other hand, when the number of second special figure reservation random numbers has reached the upper limit number, the determined random number per second special figure is not acquired.

  When the passage of the game ball to the through chucker 32 is detected (when the corresponding on-edge flag is turned on), the number of general-purpose reserved random numbers stored in the general-purpose reserved random number storage area of the RAM 75 is the upper limit number (4 If the maximum number is not reached, a determined random number per map is acquired and stored as a general reserved random number in the general reserved random number storage area. On the other hand, when the number of ordinary-pending random numbers has reached the upper limit, no determined random number is acquired per ordinary figure.

  In addition, when acquiring a determined random number per first special figure or a determined random number per second special figure, a soft random number used as a symbol display random number is acquired. The symbol display random number is made up of a plurality of independent random numbers (per symbol random number, reach group determination random number, reach mode determination random number, and variation pattern random number). 4) is stored in the RAM 75. Even when the passing of the game ball to the through chucker 32 is detected (in the case of a normal symbol), the symbol display random number is acquired and stored in the same manner as in the case of the special symbol. Compared to the simplified.

  In this way, the random number determined per first special figure or the random number determined per second special figure and the corresponding random number for symbol display (per random symbol random number, reach group determined random number, reach mode determined random number, and variation pattern random number) are acquired. The timing is when a game ball is won in the first start winning opening 35 or the second start winning opening 36 (when the game ball is detected by the first special figure start detection sensor 56 or the second special figure start detection sensor 56). Yes, the timing for acquiring the determined random number per symbol and the corresponding symbol display random number is when the game ball passes through the through chucker 32 (when the game ball is detected by the gate passing ball detection sensor 55).

  Next, special game management processing is executed (step S70). In the special game management process, the internal lottery (special symbol determination process) related to the first special symbol or the second special symbol, and the display mode of symbol variation and stop by the first special symbol display device 40 and the second special symbol display device 41 (Design and variation pattern determination process) is executed.

  In the special symbol determination process, the first special figure reservation random number stored first in the first special figure reservation random number storage area or the second special figure reservation random number stored first in the second special figure reservation random number storage area The first special figure success / failure determination table is set in advance as to whether or not the read special figure holding random number (the determined random number per first special figure or the determined random number per second special figure) is a win. Alternatively, it is determined with reference to the second special figure determination table (special drawing lottery). The first special figure reserved random number is erased from the first special figure reserved random number storage area by being read out as a determined random number per first special figure, and the second special figure reserved random number is read out as a determined random number per second special figure. As a result, it is erased from the second special figure reservation random number storage area. When both the first special figure reservation random number and the second special figure reservation random number are stored, the second special figure reservation random number may be preferentially read and the storage area (the first special figure or the second special figure may be stored). Regardless of whether or not it is a special figure, the stored ball random number stored first may be read.

  In the symbol and variation pattern determination process, the special symbol stop symbol and variation pattern (variation pattern command) correspond to the read random number determined per the first special symbol or the determined random number per second special symbol and the random number for determination per collision. The variation pattern determined by referring to a preset pattern determination table according to the combination of the winning symbol random number, reach group determination random number, reach mode determination random number, and variation pattern random number stored first. Store the command in the port output request buffer. The winning symbol random number defines the stop symbol of the special symbol, and also defines the mode (type) of the jackpot gaming state that occurs when the special symbol lottery is won. The variation pattern defines a variation time, presence / absence of reach, basic production pattern at the time of reach, and the like.

  When the special drawing lottery is won, a big hit gaming state of a mode corresponding to the winning symbol random number is generated. For example, per 2R normal per, 2R normal per change, 15R normal per, 15R per normal change, etc. are set, and the attack device 39 is opened and closed by 2 rounds per 2R, and the attack device 39 is opened per 15R. Open and close for 15 rounds. Further, in the normal hit, the game may be shifted to the normal game state or the short-time game state after the jackpot game is ended (the operation of the attacker device 39 is ended), and in the probability change, the game may be shifted to the probability change game state after the jackpot game is ended.

  In the probability variation gaming state, the success / failure determination table to be referred to in the special symbol determination process is changed from the normal low probability determination table to the high probability determination table (determination table having a higher winning probability than that for normal use). The probable gaming state continues until the next special figure winning, but the short-time gaming state is ended by executing the special drawing lottery a predetermined number of times.

  Also, in the special game management process, the start and end of the fluctuation of the first special symbol and the second special symbol, the start and end of the jackpot gaming state, the number of rounds in the jackpot gaming state, the start and end of the probability variation gaming state, the short-time gaming state Management related to such management (for example, change start instruction command indicating the start of special symbol change, change end instruction command indicating end, etc.) is stored in the port output request buffer. .

  Next, a normal game management process is executed (step S71). In the normal game management process, internal lottery (normal symbol determination process) corresponding to a normal symbol, determination of a display variation and stop display mode (symbol and variation pattern determination process) by the general symbol display device 42, and the like are executed.

  In the normal symbol determination process, the normal figure hold random number stored first in the normal figure hold random number storage area is read, and whether or not the read general figure hold random number (determined random number per common figure) is winning is set in advance The decision is made with reference to the ordinary figure determination table (normal drawing lottery). The general-purpose reserved random number is erased from the general-purpose reserved random number storage area by being read as a determined random number per general-purpose figure.

  In the symbol and variation pattern determination processing, the symbol stop symbol and variation pattern (variation pattern command) are displayed for the symbol display stored in the earliest correspondence with the read random number for each universal symbol and the random number for determining the symbol. It is determined by referring to a preset pattern determination table according to the combination of random numbers.

  In addition, when the normal symbol lottery is won in the normal symbol determination process, the electric tulip 33 is opened a predetermined number of times (in this embodiment, once). Also, in the probability variation gaming state and the short-time gaming state, the normal symbol determination table to be referred to in the normal symbol determination process is changed from the normal low probability determination table to the high probability determination table (determination table having a higher winning probability than the normal one). The pattern determination table that is changed and referred to in the symbol and variation pattern determination processing is changed from the normal pattern determination table to the time reduction pattern determination table (determination table having a shorter variation time than normal).

  Next, error management processing is executed (step S72). In the error management process, if the input of the error detection signal of the input port 0 saved in the port input process (step S122) is confirmed, there is a possibility that fraud using a magnet or the like has been performed. The predetermined error process is executed without executing the process.

  Next, a winning opening switch process is executed (step S73). In the winning opening switch processing, the winning information of the game balls to the first starting winning opening 35, the second starting winning opening 36, the general winning opening 37, and the big winning opening 52 detected in the port input process (step S65) (each ON information of on-edge flag) is acquired.

  Next, a payout control management process is executed (step S74). In the payout control management process, a prize ball instruction command for instructing the payout control device 71 to execute a prize ball operation and the number of prize balls is generated based on the prize information acquired in the prize opening switch process (step S73), and the port Store in the output request buffer.

  Next, external information processing is executed (step S75). In external information processing, an external information signal (for example, prize ball information, door opening information, symbol determination number information, jackpot information, start opening information, etc.) output to the hall computer 68 of the game hall via the external information terminal board 65 is ported. Store in the output request buffer.

  Next, a test signal management process is executed (step S76). In the test signal management process, the main control CPU 73 has various test signals representing its own internal state (for example, normal symbol game management state, special symbol game management state, jackpot, probability variation function in operation, time reduction function in operation). Are stored in the port output request buffer. With this test signal, for example, the internal state of the main control CPU 73 can be tested outside the main controller 70.

  Next, an LED display setting process is executed (step S77). In the LED display setting process, byte data applied to each LED in order to control the lighting state of the first special figure display device 40, the second special figure display device 41, the universal figure display device 42, the state display device 43, etc. Is stored in the port output request buffer.

  For example, for the first special figure display device 40 and the second special figure display device 41, a drive signal for performing lighting display with the special figure stop symbol and the variation pattern determined in the special game management process (step S70). Stored in the ordinary figure display device 42 is stored a driving signal for performing the illumination display with the ordinary figure stop symbol and the variation pattern determined in the normal game management process (step S71). For the display unit 46, a drive signal for performing lighting display indicating the number of second special figure reservation random numbers stored in the second special figure reservation random number storage area is stored. Then, a drive signal for performing a lighting display indicating the number of the general-purpose reserved random numbers stored in the general-purpose reserved random number storage area is stored, and for the round number display section 44, a special game management process (step S70). Managed in Storing a drive signal for causing the lighting display that indicates the current number of rounds in the bonus game to have.

  Next, solenoid output image composition processing is executed (step S78). In the solenoid output image composition processing, a drive signal as a control command output to the attacker drive device 54 and the electric tulip drive device 51 for opening / closing control of the attacker device 39 and the electric tulip 33 is stored in the port output request buffer. .

  For example, for the attacker drive device 54, a drive signal for opening and closing the attacker device 39 based on the round during the jackpot game managed in the special game management process (step S70) is stored, and the electric tulip drive device 51 is stored. On the other hand, a drive signal for opening the electric tulip 33 a predetermined number of times in accordance with the winning of the general drawing lottery in the normal game management process (step S71) is stored.

  Next, a port output process is executed (step S79). In the port output process, each signal stored in the port output request buffer in each process described above (step S70, step S74 to step S78) is output to the corresponding transmission target.

  For example, the variation pattern command and the effect related command stored in the special game management process (step S70) are transmitted to the sub-control device 72, and the prize ball instruction command stored in the payout control management process (step S74) is sent out. 71, the external information signal stored in the external information processing (step S75) is transmitted to the external information terminal board 65, and the drive signal stored in the LED display setting process (step S77) is transmitted to each of the display devices 40 to 43. And the drive signal stored in the solenoid output image composition process (step S78) is transmitted to the attacker drive device 54 and the electric tulip drive device 51.

  Finally, the values of all registers saved in step S61 are restored (step S80), and the timer interrupt process is terminated. Upon completion of the timer interrupt process, the process returns to the main loop (program address indicated by the stack pointer).

(Evacuation process when power is cut off)
FIG. 13 is a flowchart showing the power-off saving process executed by the main control CPU 73. When the main control CPU 73 receives a power-off notice signal while interrupting the main routine is permitted, the main control CPU 73 interrupts the saving process at power-off. Further, when the power interruption notice signal is received during execution of the timer interruption process, the interruption process is interrupted after the interruption of the timer interruption process and the return to the main loop.

  As shown in FIG. 13, in the power-off saving process, the value of the AF register is saved in the saving area of the RAM 75 (step S101), and it is determined whether or not a power-off notice signal is received (step S102). Specifically, the input port of the power-off notice signal is bit-checked to determine whether or not the power-off notice signal is input. In this way, by checking again the power-off notice signal immediately after the start of the power-off saving process, it is possible to avoid the execution of the processing after step S106 due to erroneous detection due to noise or the like.

  If the power-off notice signal has not been received (step S103: No), the value of the AF register saved in step S101 is restored (step S104), the interruption is permitted (step S105), and the power is cut off. End the save process. Upon completion of the power-off saving process, the main loop (program address indicated by the stack pointer) is restored.

  On the other hand, when the power-off notice signal is received (step S103: Yes), the clear value is output to all the output ports (output port request buffers) (step S106). As a result, all signals stored in the output port request buffer before this processing are deleted and not transmitted.

  Next, among the work areas of the RAM 75 (user work areas including the use prohibition area and the stack area), check sum values are calculated for areas excluding the backup determination storage area and the sum check buffer, and the calculated check sum values are summed. Save in the check buffer (step S108).

  Next, a backup validity judgment value (backup validity judgment flag) is stored in the backup judgment storage area (step S108), access to the work area of the RAM 75 is prohibited (step S109), and a power-off standby process is executed.

  In the power-off standby process, a certain amount of standby time (for example, about several tens of ms) is secured when the power is turned off, and the power-off notice signal of the input port 2 is checked during that time. In this embodiment, a loop counter for 80 ms is set to wait for a reset signal (step S110), and the input port of the power-off notice signal is bit-checked while decrementing the value of the loop counter (step S111). If a power-off notice signal is input before 80 ms elapses (before the loop counter reaches 0) (step S112: Yes), the process returns to the beginning of the power-off standby process (step S110). This process is continued until 80 ms elapses without inputting the power-off notice signal (Step S112: Yes → Step S110, or Step S112: No → Step S113: No → Step S111), and the power-off notice signal is input. If 80 ms elapses (step S112: No → step S113: Yes), the power-off saving process is terminated, and the process proceeds to the CPU initialization process (step S1 in FIG. 7). The power-off standby process makes it possible to shift to the CPU initialization process after a stable state in which the power-off notice signal is not input for a predetermined time (80 ms) or longer, thereby stabilizing the process and protecting the system. .

  As described above, the timer interrupt process of the main control device 70 interrupts the main loop in preference to the save process at the time of power interruption. Therefore, even if the power interruption occurs during the execution of the timer interrupt process, the timer interrupt process It is not interrupted by the power-off saving process, and the power-off saving process is started after the end of the timer interrupt process. Therefore, it is possible to minimize the amount of data to be saved in the saving process when the power is turned off, and to avoid the complicated return program.

  That is, in the saving process at power-off, the backup information saving process for saving the contents of the work area of the RAM 75 as backup information to the saving area of the RAM 75, or the saved backup information is returned to the work area of the RAM 75 and the previous power-off. Since the state return process for returning to the gaming state being executed at the time of occurrence is not executed, the storage amount of the save area of the RAM 75 can be reduced. In addition, since the backup information saving process and the state return process are not executed, the return program can be simplified.

  Further, since the power-off notice signal is not monitored by polling, the processing load on the main control CPU 73 can be reduced.

  Further, in the main interrupt process, when the power interruption notice signal is received before the winning determination process (step S125, step S128) is executed (step S124: Yes, step S127: Yes), the winning determination process is not executed. Even if the winning ball detection signal is erroneously input to the main control device due to noise caused by power interruption, payout based on the erroneous input (step S73, step S4) and winning / failing lottery (step S69 to step S71) are executed. Never happen. Therefore, for example, due to a player's fraudulent act of deliberately turning off the power, prize balls are not paid out or a jackpot gaming state is not generated, and unauthorized acquisition of prize balls can be prevented. it can.

[Description of Input Port of Dispensing Control Device 71]
Of the plurality of input / output ports of the payout control device 71, the input port 0 has a payout count signal from the payout count switch 84, a loan device READY signal from the CR unit 50 and a terminal terminal loan request completion confirmation signal, and the main control CPU 73. Are assigned a main command permission signal, a payout command transmission signal and a launch permission signal, and a power-off notice signal and an RWM clear signal from the power supply device 61. The input port is provided with a 1-bit reception storage area whose state is switched when each signal is received (switched at 1/0), and the input of each signal is confirmed by a bit check of the corresponding reception storage area. The input port 0 functions as a power-off signal receiving unit that receives a power-off notice signal when a power-off occurs, and the state of the corresponding reception storage area is switched while the power-off notice signal is input to the input port 0. .

[Control processing executed by payout control device 71]
Next, a control process executed by the payout control CPU 80 of the payout control device 71 according to a game control program (payout launch control program) stored in the ROM 81 will be described. The control process executed by the payout control CPU 80 includes a CPU initialization process as a main routine, a main loop, a serial communication reception interrupt process, a timer interrupt process (main interrupt process), and a power-off saving process. Control the execution of these processes.

  As shown in FIG. 14A, the interrupt generation factor of the serial communication reception interrupt process is established by receiving the main command, and the occurrence factor of the timer interrupt process is generated every predetermined period (1.4 ms in the present embodiment). The interruption cause of the saving process when the power is cut off is established by the occurrence of the INT interruption due to the reception of the power cut notice signal. The serial communication reception interrupt process, the timer interrupt process, and the power-off save process are set so that the interrupt priority becomes higher in this order. The serial communication reception interrupt process and the power-off save process prohibit multiple interrupts, and the timer interrupt process allows multiple interrupts.

  That is, in the payout control device 71, as shown in FIG. 14B, the main routine is repeatedly executed as the basic process, and the timer interrupt process is activated at predetermined intervals to interrupt the main loop. When a main command is received during execution of the main routine or timer interrupt processing, serial communication reception interrupt processing is activated and interrupts the main loop or timer interrupt processing (not shown). If a power-off notice signal is received during execution of the main routine (serial communication reception interrupt processing and timer interrupt processing are not being executed and the main command has not been received), the power-off save processing is activated and the main routine is entered. interrupt. Further, when the power interruption notice signal is received during the execution of the timer interruption process, the power interruption interruption process is started after the timer interruption process is completed and the process returns to the main loop. However, the serial communication reception interrupt processing and main interrupt processing are not activated during the power-off save process, and if an interrupt factor is established during the power-off save process, the power-off save process is performed. The corresponding interrupt processing is started after waiting for the end of. Note that the interrupt process is started on condition that the interrupt destination process (the process currently being executed) is in the interrupt enabled state.

  The main interrupt process includes a process for acquiring the contents of the input port 0 (including the payout count signal) (step S262 in FIG. 19) and a process for updating and storing the contents of the input port 0 (step S264 in FIG. 19). ) And a payout detection process for detecting the completion of one payout operation by the payout motor 83 (the falling edge of the updated payout count signal of the input port 0 is detected, and the falling edge is detected when the falling edge is detected (on edge) ) (Step S265 in FIG. 19)) and a payout remaining number subtraction process for subtracting one payout remaining number stored in the RAM 82 when the completion of one payout operation is detected in the payout detection process (step S265). Step S247) in FIG. 18 and payout drive control for causing the payout motor 83 to execute one payout operation when the payout remaining number stored in the RAM 82 is a positive number. Including generating a command and a (step S247 in FIG. 18), resulting payout instruction process of transmitting the payout drive control command transmitted signal to the payout motor 83 (step of FIG. 18 S252). While the main CPU 73 prohibits interruption of the power saving save process during execution of the timer interruption process, the main CPU 73 receives a power interruption notice signal before executing the payout detection process in the timer interruption process being executed (step of FIG. 19). In S263: Yes), the payout detection process is not executed.

(CPU initialization process)
When the pachinko machine P is powered on, the payout control CPU 80 starts a CPU initialization process. By the CPU initialization process, stable dispensing operation and launching operation of the dispensing control device 71 are guaranteed.

  FIG. 15 is a flowchart showing a CPU initialization process executed by the payout control CPU 80.

  When the CPU initialization process is started, the top address (address initial value) of the stack area is set in the stack pointer (step S201), and the vector type interrupt mode (interrupt mode mode 2) is set (step S202). Thus, the payout control CPU 80 can refer to an arbitrary address (however, the least significant bit is 0) as an interrupt vector and execute a specified interrupt handler.

  Next, an interrupt vector table is set (step S203), a built-in register is set (step S204), and a reset waiting process is executed. In this process, a certain waiting time (for example, about 100 ms) is secured at the start of reset (for example, power-on), and the power-off notice signal for the input port 0 is checked during that time. In this embodiment, a loop counter for 100 milliseconds is set as the supply power supply stabilization wait time (step S205), and the input port of the power-off notice signal is bit-checked while decrementing the value of the loop counter (step S206). If a power-off notice signal is input before 100 milliseconds have elapsed (before the loop counter reaches 0) (step S207: Yes), the process returns to the beginning of the reset standby process (step S205). This process is continued until 100 milliseconds elapses without inputting the power-off notice signal (Step S207: Yes → Step S205, or Step S207: No → Step S208: No → Step S206). If 100 milliseconds elapse without input (step S207: No → step S208: Yes), this process ends.

  Next, access to the work area of the RAM 82 is permitted (step S209). Specifically, the RAM protect setting value in the work area is reset. As a result, the access to the work area of the RAM 82 is permitted thereafter.

  Next, it is determined whether or not a backup validity determination value (backup validity determination flag) is stored in the RAM 82. Specifically, the data in the backup determination storage area of the RAM 82 is compared with the backup validity determination value (step S210), and if they match (when the backup validity determination flag is set), the power is turned off. It is determined that the CPU initialization process has been completed after the time saving process is properly completed (step S211: No), and if there is a mismatch (when the backup validity determination flag is not set), the power saving interruption process is performed. It is determined that the CPU initialization process has not been completed properly (step S211: Yes).

  If it is a CPU initialization process after the power-off saving process is properly completed (step S211: No), a sum check is performed on the backup information in the RAM 82. Specifically, the checksum value is calculated for the area excluding the backup determination storage area and the sum check buffer in the work area of the RAM 82 (the user work area including the use prohibition area and the stack area) (step S212). It is determined whether or not the checksum value is a normal value (step S213). Specifically, the checksum value calculated in step S212 is compared with the checksum value saved in the power-off saving process (step S280), which will be described later, and if they match, it is determined to be a normal value. If they are different, it is determined that the values are not normal.

  When the checksum value is a normal value (step S213: Yes), a return process is executed. In the recovery process, the power recovery clear area (for example, the backup determination storage area) is reset (step S214).

  On the other hand, if it is not the CPU initialization process after the power-off saving process is properly completed (step S211: Yes), or the checksum value is not normal (step S213: No), the initialization process ( Steps S215 and S216) are executed.

  In the initialization process, all storage areas other than the use-prohibited area of the RAM 82 are cleared (step S215). As a result, the work area and stack area of the RAM 82 are all initialized. Next, initial setting of the RAM 82 is performed by setting an initial value at the time of clear start in the RAM 82 (step S216).

  When the return process (step S214) or initialization process (steps S215 and S216) ends, the setting value at the time of startup is set (step S217), the timer interrupt counter is set (step S218), and the interrupt daisy chain is reset. (Step S219), the process shifts to the main loop. By resetting the interrupt daisy chain (step S219), when the determination in step S286 (see FIG. 20) in the power-off saving process, which will be described later, shifts to the CPU initialization process in Yes, the RETI when exiting from the interrupt process Since the processing is not performed, even if the interrupt is permitted in step S224 (see FIG. 16) in the main loop described later, it is prevented that the processing does not shift to each interrupt processing.

(Main loop)
FIG. 16 is a flowchart showing a main loop executed by the payout control CPU 80.

  In the main loop, interrupts are prohibited (step S221), received command analysis processing (step S222), command transmission / reception related processing (step S223) is executed, interrupts are permitted (step S224), and the process returns to step S221.

  The received command analysis process (step S222) is a process of analyzing a command received from the main control device 70. Commands received from the main control device 70 include a command related to activation, a payout stop command (for example, output when a door opening error occurs), and a command related to a prize ball (main command permission signal, payout command transmission signal). . When the payout command transmission signal is received, the payout control CPU 80 adds the remaining number of prize balls in the prize ball memory area by the number of prize balls indicated by the received payout command transmission signal (prize ball instruction command). The payout control CPU 80 executes a start process when a command related to start is received, and executes a process of interrupting the payout operation when a command related to an error is received. In the command transmission / reception related processing (step S223), processing related to the received command is executed. For example, when a dish full tank error is detected based on reception from the dish full tank SW 85, or when a ball breakage error or a ball clogging error is detected based on reception from the payout counting switch 84, the error that has occurred is indicated. An error command is transmitted to the main controller 70.

(Serial communication reception interrupt processing)
FIG. 17 is a flowchart showing serial communication reception interrupt processing executed by the payout control CPU 80. When the payout control CPU 80 receives a main command (various commands input from the main control device 70) while the main loop interrupt is permitted or the timer interrupt processing is permitted, the payout control CPU 80 preferentially processes the received main command. Interrupt serial communication reception interrupt processing.

  As shown in FIG. 17, in the serial communication reception interrupt process, the value of the AF register is saved in the save area of the RAM 82 (step S231), the contents of the status register of the SCU are loaded (step S232), and there is received data. (Step S233), the received value is obtained from the SCU data register (step S234), it is determined whether the received data is confirmed (step S235), and the received data is not confirmed (step S235). In step S235: No), the value of the AF register saved in step S231 is restored (step S237), the interrupt is permitted (step S238), and the serial communication reception interrupt process is terminated. On the other hand, if the received data is confirmed (step S235: No), the received data is stored in the serial communication buffer (step S236), the value of the AF register saved in step S231 is restored (step S237), and an interrupt is issued. After permitting (step S238), the serial communication reception interrupt process is terminated. Upon completion of the serial communication reception interrupt process, the process returns to the main loop or timer interrupt process (program address indicated by the stack pointer).

(Timer interrupt processing)
FIG. 18 is a flowchart showing timer interrupt processing executed by the payout control CPU 80. In the payout control CPU 80, the counter / timer circuit generates an interrupt request signal for every predetermined period, and based on the generation of the interrupt request signal, interrupts the timer interrupt processing to the main loop that is permitted to interrupt.

  As shown in FIG. 18, in the timer interrupt process, all register values used during the execution of the main loop are saved in the save area of the RAM 82 (step S241). Another value can be written into the register after saving the value during the timer interrupt processing.

  Next, an interrupt is permitted (step S242), an interrupt flag is initialized (step S243), and port input processing is executed (step S244). With the initialization of the interrupt flag (step S243), the interrupt flag is set every 1.4 ms, and the timer interrupt process is periodically executed every 1.4 ms.

  In the port input process (step S244), as shown in FIG. 19, the on-edge detection flag is cleared (step S261), and the contents of the input port 0 are acquired (step S262). It is determined whether or not (step S263). Specifically, the input port of the power-off notice signal is bit-checked to determine whether or not the power-off notice signal is input.

  If the power-off notice signal has not been received (step S263: No), the contents of the input port 0 are updated and stored (step S264), and the on-edge of the payout count signal of the input port 0 is stored (step S264). S265), the process ends. The reception state (level) of the reception storage area (1 bit) corresponding to the payout count SW 84 is normally set to H (High) and is changed to L (Low) by receiving the payout count signal. When a signal is not received and a change to the reception state (falling from H to L) of the reception storage area (1 bit) corresponding to the payout count SW 84 is detected, the payout count is processed by the process of step S265. The on-edge of the signal is preserved. The on-edge of the payout counting signal may be detected only by changing from H to L (H → L) or detected by maintaining L (H → L → L) after changing from H to L. May be. On the other hand, if the power-off notice signal has been received (step S263: Yes), the processing ends without updating the contents of the input port 0 and storing the on-edge of the input port 0.

  As described above, in the port input process, the input state (H / L) of the payout count signal from the payout count SW 84 is read, and when the power is not cut off, the change to the reception state of the reception storage area is detected. Thus, the payout of the game ball is detected, the on-edge of the payout count signal is stored, and then the present process is terminated. On the other hand, when the power interruption occurs, this process is terminated without detecting the payout of the game ball. When this process ends, the timer update process (step S245) in FIG. 18 is executed.

  In the timer update process (step S245), the count value of the counter / timer circuit that defines the execution interval of each process is updated to the initial value all at once, and the cycle count is restarted.

  Next, CR communication processing is executed (step S246). In the CR communication process, when reception of the terminal terminal lending request completion confirmation signal from the CR unit 50 is saved in the port input process (step S264), the remaining number of lending memory areas is added by the basic unit.

  Next, a payout motor related process is executed (step S247). In the payout motor-related process, when the on-edge of the payout count signal from the payout count SW 84 is stored in the port input process (step S265), one of the remaining winning ball numbers and the remaining loan number is given priority to the remaining loan number. Subtract. If either the remaining number of winning balls or the remaining number of loans is not zero, a payout drive control command for causing the payout motor 83 to execute a payout operation for one game ball is generated and stored in the port output request buffer. Store. In addition, in the case where processing (successful ball payout processing) is set in which a single prize ball payout is continuously performed up to a predetermined number of units (for example, 25) as an upper limit, continuous winning ball payout processing is performed. Even if the remaining number of loans is increased from zero during the process, the ongoing award ball payout process is continued without interruption. Then, after one consecutive prize ball payout process is completed, if the remaining number of prize balls is not zero even if the remaining number of prize balls has not yet reached zero, the remaining number of outstanding balls is more than the remaining number of prize balls. Priority is given to paying out.

  Next, a firing control process 248 is executed. In the firing control process, the drive of the firing motor 86 is controlled based on the firing instruction signal received from the firing volume 88. Thereby, the launch strength of the game ball is adjusted according to the operation amount of the player. However, when the detection signal from the touch sensor 89 is off (low level), when the launch stop signal is input from the launch stop switch 90, and when the CR unit 50 is not connected to the pachinko machine P, the launch is started. The drive of the motor 86 is stopped.

  Next, error-related processing is executed (step S249). In the error-related processing, when an error such as a full dish error is detected, an error command indicating the error content is stored in the port output request buffer.

  Next, external information processing is executed (step S250). In the external information processing, an external information signal (for example, prize ball information) output to the hall computer 68 of the game hall via the external information terminal board 65 is stored in the port output request buffer.

  Next, a test signal management process is executed (step S251). In the test signal management process, the payout control CPU 80 generates various test signals representing its own internal state and stores them in the port output request buffer. With this test signal, for example, the internal state of the payout control CPU 80 can be tested outside the payout control device 71.

  Next, port output processing is executed (step S252). In the port output process, each signal stored in the port output request buffer in each process described above is output to the corresponding transmission target. By this processing, in addition to transmission of a payout drive control command to the payout motor 83 and transmission of prize ball information to the hall computer 68, light emission control of the status LED is executed.

  Finally, the values of all registers saved in step S241 are restored (step S253), and the timer interrupt process is terminated. Upon completion of the timer interrupt process, the process returns to the main loop (program address indicated by the stack pointer).

(Evacuation process when power is cut off)
FIG. 20 is a flowchart showing the power-off saving process executed by the payout control CPU 80. The payout control CPU 80 interrupts the power-off saving process when receiving a power-off notice signal while interrupting the main routine. Further, when the power interruption notice signal is received during execution of the timer interruption process, the interruption process is interrupted after the interruption of the timer interruption process and the return to the main loop.

  As shown in FIG. 20, in the power-off saving process, the value of the AF register is saved in the saving area of the RAM 82 (step S271), and it is determined whether or not a power-off notice signal is received (step S272). Specifically, the input port of the power-off notice signal is bit-checked to determine whether or not the power-off notice signal is input. In this way, by checking the power-off notice signal immediately after the start of the power-off saving process, it is possible to avoid the execution of the processing from step S276 onward due to erroneous detection due to noise or the like.

  If the power-off notice signal has not been received (step S273: No), the value of the AF register saved in step S271 is restored (step S274), the interrupt is permitted (step S275), and the power is cut off. End the save process. Upon completion of the power-off saving process, the main loop (program address indicated by the stack pointer) is restored.

  On the other hand, when the power-off notice signal is received (step S273: Yes), the clear value is output to all the output ports (output port request buffers) (step S276). As a result, all signals stored in the output port request buffer before this processing are deleted and not transmitted.

  Next, a loop counter for 4.5 milliseconds is set as a command reception waiting time (step S277), and whether or not the value has reached zero while decrementing the value of the loop counter (4.5 milliseconds is Whether or not elapses is determined (step S278), and when 4.5 milliseconds elapse (step S278: Yes), data storage processing is executed (step S279). In the data storage process, the data (input port state) input to the payout control CPU 80 is stored. The data storage process is the same as steps S232 to S236 (see FIG. 17) in the serial communication reception interrupt process. The contents of the status register of the SCU are loaded, whether or not there is received data, and SCU data The received value is acquired from the register, it is determined whether or not the received data is confirmed, and when the received data is confirmed, the received data is stored in the serial communication buffer. The waiting time until the data storing process is not limited to 4.5 milliseconds, it is sufficient that it exceeds the timer interrupt processing period (4 milliseconds) executed by the main controller 71, and the timer interrupt processing period (4 More than the time obtained by adding the time required for the timer interrupt processing to (millisecond). By setting the waiting time until the data storing process as described above, the main control CPU 73 always executes the timer interrupt process once within the waiting time. Accordingly, within the standby time, the main control CPU 73 executes the payout control management process (step S74 in FIG. 11) and the port output process (step S79 in FIG. 11) at least once. In the data storage process (step S279), It is possible to receive and store the latest prize ball instruction command transmitted from the main control CPU 73 after the disconnection saving process is started.

  Next, among the work areas of the RAM 82 (user work areas including the use prohibition area and the stack area), check sum values are calculated for areas excluding the backup determination storage area and the sum check buffer, and the calculated check sum values are summed. Save in the check buffer (step S280).

  Next, a backup validity judgment value (backup validity judgment flag) is stored in the backup judgment storage area (step S281), access to the work area of the RAM 82 is prohibited (step S282), and a power-off standby process is executed.

  In the power-off standby process, a certain standby time (for example, about 10 ms) is secured when the power is turned off, and the power-off notice signal of the input port 0 is checked during that time. In this embodiment, a loop counter for 10 ms is set to wait for the reset signal (step S283), and the input port of the power-off notice signal is bit-checked while decrementing the value of the loop counter (step S284). If a power-off notice signal is input before 10 ms elapses (before the loop counter reaches 0) (step S285: Yes), the process returns to the beginning of the power-off standby process (step S283). This process is continued until 10 ms elapses without inputting the power-off notice signal (Step S285: Yes → Step S283, or Step S285: No → Step S286: No → Step S284), and the power-off notice signal is input. If 10 ms elapses (step S285: No → step S286: Yes), the power-off saving process is terminated, and the process proceeds to the CPU initialization process (step S201 in FIG. 15). The power-off standby process makes it possible to shift to the CPU initialization process after a stable state in which the power-off notification signal is not input for a predetermined time (10 ms) or longer, thereby stabilizing the process and protecting the system. .

  As described above, the timer interrupt process of the payout control device 71 also interrupts the main loop in preference to the power-off saving process, similarly to the timer interrupt process of the main control device 70. Therefore, the power interruption occurs during the execution of the timer interrupt process. Even if it occurs, the timer interrupt process is not interrupted by the power-off save process, and the power-off save process starts after the timer interrupt process ends. Therefore, it is possible to minimize the amount of data to be saved in the saving process when the power is turned off, and to avoid the complicated return program.

  That is, in the power-off saving process, the backup information saving process for saving the contents of the work area of the RAM 82 to the saving area of the RAM 82 as the backup information, or the saved backup information is restored to the work area of the RAM 82 and the previous power-off. Since the state return process for returning to the gaming state being executed at the time of occurrence is not executed, the storage amount of the save area of the RAM 82 can be reduced. In addition, since the backup information saving process and the state return process are not executed, the return program can be simplified.

  Further, since the power-off notice signal is not monitored by polling, the processing load on the payout control CPU 80 can be reduced.

  Furthermore, in the main interrupt process, when the power interruption notice signal is received before execution of the payout detection process (step S265) (step S263: Yes), the payout detection process is not executed. Even if the payout count signal is erroneously input to the payout control device 71, the payout completion of the game ball is not erroneously detected based on the erroneous input. Therefore, the payout remaining number is not subtracted improperly due to the power interruption, and an unreasonable loss of winning balls or rental balls can be prevented in advance.

  In addition, although the example which fluctuates two types of special symbols was demonstrated in the said embodiment, one type may be sufficient as a special symbol and three or more types may be sufficient as it. In addition, the winning / losing lottery with only one of the special symbols or the normal symbols may be executed to generate a jackpot gaming state.

  As mentioned above, although the embodiment to which the invention made by the present inventor is applied has been described, the present invention is not limited by the discussion and the drawings that form part of the disclosure of the present invention according to this embodiment. That is, it should be added that other embodiments, examples, operation techniques, and the like made by those skilled in the art based on this embodiment are all included in the scope of the present invention.

8: Game area 56: First special figure starting ball detection sensor 57: Second special figure starting ball detection sensor 58: Large winning ball detection sensor 59: General winning ball detection sensor 61: Power supply device 70: Main controller 71: Dispensing control device 72: sub-control device 73: main control CPU
80: Dispensing control CPU (power-off detection means, execution control means)
82: RAM (payout remaining number storage means)
83: Dispensing motor (dispensing means)
84: payout count SW (payout detection means)
96: Power-off detection circuit (power-off signal generating means)
P: Pachinko machine (ball game machine)

Claims (2)

A gaming machine comprising: game medium detection means for outputting a game medium detection signal when a game medium is detected; and a control device for executing predetermined processing based on detection of the game medium by the game medium detection means,
An abnormality detection means for detecting an abnormal state occurring in the gaming machine and outputting an abnormal signal indicating that an abnormality has occurred,
The controller is
Connection is made so that the gaming medium detection signal output from the gaming medium detection means and the abnormality signal output from the abnormality detection means are input to the same input port,
A process of determining whether it has detected the input of the abnormality signal and the processing for acquiring the game medium detection signal input to the same input port to the same input port, run in one input processing possible and then,
In a series of processes in which the input process, the predetermined process based on the game medium detection signal acquired in the input process, and the process other than the input process and the predetermined process are executed every predetermined time. Is executable,
When the input of the abnormal signal is detected in the input process, the other process can be executed without interrupting the series of processes, and the game medium detection signal is acquired in the input process. Even if it exists, the said predetermined process based on the said game medium detection signal is not performed. The gaming machine characterized by the above-mentioned. The gaming machine according to claim 1,
The controller is
An interrupt process including the series of processes is executed every predetermined time,
When the input of the abnormal signal is detected in the input process, it indicates that the game medium detection signal is acquired in the input process regardless of whether the game medium detection signal is acquired in the input process. A gaming machine characterized by not generating a detection flag.

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