JP5518620B2 - Game machine - Google Patents

Description

  In the present invention, a player can play a predetermined game using a game medium, and a predetermined payout condition is established when the game medium passes through a predetermined pass area provided in the game area. In particular, the present invention relates to gaming machines such as pachinko machines, slot machines, and parrot machines that pay out gaming media.

  As a gaming machine, a game medium such as a game ball is launched into a game area by a launching device, and when a game medium wins a prize area such as a prize opening provided in the game area, a predetermined number of game media are paid out to the player. There is something to be done. Also, when a game medium is inserted, a predetermined number of bets are set, multiple types of symbols are rotated by operating the operation lever, and a combination of stop symbols is specified when the symbols are stopped by operating the stop button There are cases where a predetermined number of premium game media are paid out to the player. Also, when a predetermined number of bets are set according to the number of game media taken in, a plurality of types of symbols are rotated by operating the operation lever, and the symbols are stopped when the symbols are stopped by operating the stop button. When the combination becomes a combination of specific symbols, a predetermined number of game media may be paid out to the player.

  In addition, as a gaming machine, in order to be able to manage the number of game media paid out externally, it indicates that the game media has been paid out based on detection of the paid game media by a sensor. Some are configured to output signals externally (see, for example, Patent Document 1). For example, in the gaming machine described in Patent Document 1, a prize ball information signal is sent to the terminal board every time the number of prize balls paid out becomes 10, based on the detection of a gaming medium by a prize ball count switch (sensor). The output is through.

JP 2002-239168 A (paragraph 0206, FIG. 32)

  In the gaming machine described in Patent Document 1, the game medium is output by externally outputting a signal indicating that the game medium has been paid out based on the fact that the paid-out game medium is detected by the sensor. The game situation such as the number of payouts can be accurately grasped outside (for example, on the hall side). However, in general, gaming machines are often configured to allow the generation of the next specific gaming state before the end of payout based on the establishment of the payout condition that occurred during the specific gaming state. Therefore, even if it is configured to externally output a signal indicating that the game medium has been paid out, if the next specific gaming state occurs before the payout is completed, the timing at which the payout condition is satisfied is set. It becomes impossible to manage, and the number of payouts during a specific game state cannot be accurately grasped outside.

  Accordingly, an object of the present invention is to provide a gaming machine capable of accurately grasping the number of payouts during a specific gaming state.

Game machine according to the present invention is that the game medium (e.g., game balls) player using it it is possible to perform Yu technique, pass is provided in the game region region (e.g., the first starting winning opening 13, The grant condition is satisfied when the game medium passes through the second start winning opening 14, the big winning opening, the normal winning openings 29, 30) (for example, the first starting winning opening 13, the second starting winning opening 14, A game machine that grants a game medium based on the winning award and the winning award 29, 30) , and can retain the stored contents for a predetermined period even when the power supply is stopped. Fluctuation data storage means for storing fluctuation data generated when performing, an initialization operation means for outputting an operation signal in response to an operation, and an operation signal from the initialization operation means only when power supply is started Fluctuation data based on the input Initialization processing execution means capable of executing initialization processing for initializing the storage contents of the data storage means, error determination means for determining whether or not a predetermined error has occurred, and at least initialization by the initialization processing execution means A gaming machine state that outputs a gaming machine state signal to the outside based on the fact that a predetermined signal output condition is satisfied, including that the determination process has been executed and that a predetermined error has been determined by the error determination means Signal external output means and detection means for detecting a game medium passing through the passage area and outputting a detection signal (for example, first start port switch 13a, second start port switch 14a, count switch 23 and winning port switch 29a, 30a), game control means (for example, a game control microcomputer 560) for executing a game control process for controlling the progress of the game, Based on the command output from the technique control means, the electric component control means (for example, the effect control microcomputer 100 or the payout) for controlling the electric parts provided in the gaming machine, for example, the effect display device 9 or the ball payout device 97). When a grant condition is established based on the control microcomputer 370 and a detection signal input from the detection means, a condition satisfaction signal (for example, indicating that the grant number reaches a predetermined number when the grant condition is satisfied) , A winning condition signal) externally output condition establishment signal external output means (for example, a part for executing steps S1021 to S1023, S1102 and S1103 in the game control microcomputer 560), the game control means from the detection means Command (for example, input port) indicating the input state of the detection signal Including command output means (for example, a part for executing the processing of steps S2111 and S2127 in the game control microcomputer 560) to output the state 1 designation command and the input port state 2 designation command) to the electrical component control means. Based on the command output from the command output means, the control means determines whether the period during which the detection signal is input or the input frequency of the detection signal is a predetermined threshold (for example, 1 second for the period, 10/10 for the input frequency). An abnormality determining means for determining that an abnormality has occurred when 0.5 seconds (see FIGS. 72 and 76) is exceeded (for example, in the production control microcomputer 100, FIGS. 74, 75, 78, 79, and 79) 81, in the part for executing the abnormality determination process shown in FIG. 85, FIG. 86, FIG. 87, FIG. 88, FIG. 89, seen including a portion) that performs an abnormality determination process shown in FIG. 90, the gaming machine state signal external output means, initialization processing is performed by the initialization process executing means The game machine state signal is output from a common output terminal provided in the gaming machine when it is determined that a predetermined error has occurred by the error determination means . With such a configuration, the number of grants in the specific gaming state can be accurately grasped by outputting the condition establishment signal to the outside. Further, it is possible to reliably detect fraud without increasing the processing load on the game control means.
The gaming machine status signal external output means extends the output period for externally outputting the gaming machine status signal when a predetermined signal output condition is newly established when the gaming machine status signal is output externally. It may be configured.

  The game control means receives a detection signal from each of the plurality of detection means as an input port (for example, the input port 0 to which the count switch 23 and the prize opening switches 29a and 30a shown in FIG. 7 are assigned. All the detection signals of the start port switch 13a, the second start port switch 14a, the count switch 23, and the winning port switches 29a and 30a may be input in a lump from the same input port. The command output means may be configured to output input data of the input port as a command collectively (for example, output as 1-byte data). According to such a configuration, the game control means can collectively transmit the detection signals of the detection means to the electrical component control means including the abnormality determination means, so that the plurality of detection means are subject to abnormality detection. Even in this case, the processing load of the game control means does not increase.

  The electrical component control means performs a payout control means (for example, the process of step S755 shown in FIGS. 47 and 84) for controlling a payout means (for example, the ball payout device 97) for paying out game media. The payout control microcomputer 370), and the payout control means outputs an abnormal signal indicating that an abnormality has occurred to the outside of the gaming machine when the abnormality determining means determines that an abnormality has occurred. (For example, the payout control microcomputer 370 may be configured to include the portions that execute the processes of steps S914, S940A, S940B, S960A, and S960B). According to such a configuration, it is possible to grasp outside the gaming machine that an abnormality has occurred with respect to the detection means, and it is possible to more reliably detect fraud.

  The abnormality determination means detects the number of detection signal inputs (see steps S1732 and S1745 in FIGS. 78 and 79 and steps S932A and S932B in FIGS. 87 and 88), and in a predetermined period (for example, 0.5 seconds). It is determined that an abnormality has occurred when the detected number of inputs exceeds a predetermined number (for example, 10) (see steps S1736 and S1749 in FIGS. 78 and 79, and steps S936A and S936B in FIGS. 87 and 88). May be. According to such a configuration, since it is possible to detect an illegal act that illegally turns on and off the detection signal of the detection means, it is possible to detect the illegal act more reliably.

  The command output means may be configured to output a command indicating the detection signal input state when the detection signal input state changes (see steps S2109 to S2111 and S2125 to S2127 in FIGS. 33 and 34). Good. According to such a configuration, an illegal act based on grasping the control cycle of the game control means based on the command output cycle can also be prevented.

  The predetermined payout conditions include a plurality of payout conditions with different numbers of game media payouts (for example, three payout conditions in the case of starting winning at the first start winning opening 13 and the second start winning opening 14) Is established, fifteen payout conditions are established when a prize is entered in the big prize opening, and ten payout conditions are established when a prize is awarded in the regular prize openings 29 and 30), and predetermined payout conditions are established. Based on the above, cumulative update means (for example, step S5118 in the game control microcomputer 560 is executed by performing a predetermined calculation using the number of payouts according to the predetermined payout condition established and updating the cumulative value. The payout condition establishment signal external output means externally outputs a payout condition establishment signal based on the fact that the cumulative value updated by the cumulative update means has reached a predetermined number (for example, game control) The microcomputer 560 executes step S5122 based on the determination of Y in step S5120 and adds the winning information storage counter, and determines that N is determined based on the value of the winning information storage counter in step S2007. The subsequent processing is executed and the output of the winning signal is started), and the accumulating update means performs a calculation in the direction opposite to the predetermined calculation using a predetermined number in accordance with the external output of the payout condition establishment signal, The cumulative value may be updated (for example, a part for executing step S5121 in the game control microcomputer 560). According to such a configuration, it is possible to accurately grasp the gaming situation when a predetermined payout condition is satisfied, without increasing the control burden.

  The gaming machine includes payout means (for example, a ball payout device 97) for paying out game media, and payout control means (for example, a payout control microcomputer 370) for controlling the payout means. Based on the accumulated update means and a predetermined payout condition, a payout number signal output that outputs a payout number signal (for example, a prize ball number command) that can specify the number of game media to be paid out to the payout control means. Means (for example, a part for executing step S52305 in the game control microcomputer 560), and the cumulative update means updates the cumulative value in the process for the payout number signal output means to output the payout number signal. (For example, the game control microcomputer 560 adds the prize ball command output counter during the prize ball processing in step S32). Updating the winning counter (step S501)) may be configured so. According to such a configuration, the process for outputting the payout number signal and the process for updating the accumulated value can be made common, and the control burden can be reduced.

  The payout control means is a game medium payout control means for executing payout control for driving the payout means to pay out the number of unpaid game media specified by the payout number signal output by the payout number signal output means ( For example, a payout signal (for example, prize ball information) that indicates that a specific number (for example, 10) of game media has been paid out by the payout means, including a part for executing step S755 in the payout control microcomputer 370. ) To output the payout signal external output means (for example, a portion for executing the steps S7901 to S7914 in the payout control microcomputer 370 to output the prize ball information. Also, for example, as shown in FIG. 160, an output system for outputting the prize ball information from the payout control board 37 (connector CN-3 → R10 → PC10 → Connector CN10) may be configured to include a portion) that is provided. According to such a configuration, the difference between the expected number of payouts based on the establishment of a predetermined payout condition and the number of game media actually paid out can be grasped externally, and an abnormal payout condition can be obtained. The presence / absence of the presence or absence can also be determined externally.

  Whether the gaming machine has used a signal output period measurement timer (for example, a winning information storage timer) to measure the output period of the payout condition establishment signal, and whether a specific period has elapsed since the start of the output of the payout condition establishment signal The signal output period determination means for determining whether or not (for example, the part that executes step S2015 in the game control microcomputer 560) and the stored contents can be retained for a predetermined period even when the power supply is stopped. Backup storage means for storing at least the value of the signal output period measurement timer (for example, a power-backed up RAM 55 for storing a prize information storage timer), and the payout condition establishment signal external output means by the signal output period determination means The output of the payout condition establishment signal is continued until it is determined that a specific period (for example, 100 ms) has elapsed (for example, The game control microcomputer 560 executes the processing of steps S2016 to S2018 and continues outputting the winning signal while it is determined to be N in step S2015), and backup storage is performed when power supply is started. Clear means for clearing the value of the signal output period measurement timer stored in the means (for example, a part for executing step S9104 in the game control microcomputer 560) may be further provided. According to such a configuration, it is possible to prevent one output of the payout condition establishment signal from being erroneously recognized as two outputs due to the interruption of power supply during the output of the payout condition establishment signal. can do.

  The gaming machine has an external output signal including a payout condition establishment signal (for example, a winning signal) (for example, a symbol determination number 1 signal, a start port signal, a jackpot 1 signal, a jackpot 2 signal, a jackpot 3 signal, a time reduction signal, a prize winning) 1 external output board (for example, terminal board 160) for outputting a signal, security signal, high-accuracy signal, prize ball information (for example, to a hall computer), and game control means (for example, game control micro) A game control board (for example, a game control board (main board) 31) on which a computer 560) is mounted, and the external output board receives an external output signal from the game control board and receives the external output signal (For example, the terminal board 160 has one signal for the number of symbol determinations input from the main board 31, one start signal, one big hit signal, two big hit signals, and three big hit signals. Time reduction signal, the winning signal, the security signal, a high 確中 signal, the winning balls information externally output) may be configured so. According to such a configuration, it is possible to facilitate the wiring of the external output signal wiring to the external output board.

It is the front view which looked at the pachinko game machine from the front. It is the rear view which looked at the gaming machine from the back. It is a block diagram which shows the structural example of a game control board (main board). It is a block diagram which shows the circuit structural example of a payout control board. It is a block diagram which shows the circuit structural example of a relay board | substrate, an effect control board | substrate, a lamp driver board | substrate, and an audio | voice output board | substrate. It is explanatory drawing which shows the example of bit allocation of the output port in a game control means. It is explanatory drawing which shows the bit allocation example of the input port in a game control means. It is a circuit diagram which shows the internal structure of a terminal board | substrate. It is a flowchart which shows the main process which the microcomputer for game control performs. It is a flowchart which shows the process example of a hot start process. It is a flowchart which shows a 4 ms timer interruption process. It is explanatory drawing which shows an example of the content of the control signal output with respect to the payout control means from a game control means. It is explanatory drawing which shows an example of the content of the control command transmitted / received between a game control means and a payout control means. It is explanatory drawing which shows the example of the error information set to a connection OK command and a prize ball preparation command. It is a block diagram which shows the signal line etc. which are used for transmission / reception of a control signal and a control command. It is a flowchart which shows an example of a prize ball process. It is explanatory drawing which shows the example of a prize ball number table. It is a flowchart which shows a prize ball command output counter addition process. It is a flowchart which shows a prize ball command output counter addition process. It is a flowchart which shows a prize ball control process. It is a flowchart which shows prize ball transmission processing 1. It is a flowchart which shows a prize ball connection confirmation process. It is a flowchart which shows the prize ball transmission process 2. FIG. It is a flowchart which shows a prize ball receipt confirmation process. It is a flowchart which shows a prize ball completion | finish confirmation process. It is a flowchart which shows a prize ball counter subtraction process. It is a flowchart which shows an example of a frame state output process. It is explanatory drawing for demonstrating an example of a cheating. It is explanatory drawing which shows an example of the content of an effect control command. It is a flowchart which shows an example of the program of a special symbol process process. It is a flowchart which shows a special symbol stop process. It is explanatory drawing which shows each 2 byte buffer formed in RAM used by switch processing. It is a flowchart which shows the process example of a switch process. It is a flowchart which shows the process example of a switch process. It is a flowchart which shows a switch normal / abnormality check process. It is a block diagram which shows the various signals output to a terminal board. It is a flowchart which shows an information output process. It is a flowchart which shows an information output process. It is a flowchart which shows an information output process. It is a flowchart which shows an information output process. It is a flowchart which shows a winning timer set process. It is explanatory drawing which shows the output timing of a highly accurate middle signal. It is explanatory drawing which shows the output timing of a security signal. It is explanatory drawing which shows the bit allocation example of the output port in a payout control means. It is explanatory drawing which shows the example of bit allocation of the input port in a payout control means. It is a flowchart which shows the main process which CPU for payout control performs. It is a flowchart which shows the timer interruption process which CPU for payout control performs. It is a flowchart which shows a main control communication process. It is a flowchart which shows a main control command reception process. It is a flowchart which shows a main control connection confirmation process. It is a flowchart which shows main control communication normal processing. It is a flowchart which shows main control communication normal processing. It is a flowchart which shows the process during main control communication. It is a flowchart which shows the process during main control communication. It is a flowchart which shows a main control communication end process. It is a flowchart which shows a main control transmission command conversion process. It is a flowchart which shows payout control processing. It is a flowchart which shows the payout start waiting process. It is a flowchart which shows a payout motor stop waiting process. It is a flowchart which shows payout passage waiting processing. It is a flowchart which shows payout passage waiting processing. It is a flowchart which shows payout passage waiting processing. It is a flowchart which shows an error process. It is a flowchart which shows an error process. It is a flowchart which shows an information output process. It is a flowchart which shows an information output process. It is a flowchart which shows the main process which the microcomputer for production control performs. It is explanatory drawing which shows the example of 1 structure of a command reception buffer. It is a flowchart which shows the specific example of a command analysis process. It is a flowchart which shows the specific example of a command analysis process. It is a flowchart which shows production control process processing. It is explanatory drawing which shows an example of the detection method of winning abnormality. It is explanatory drawing which shows an example of the timer which the microcomputer for production control uses regarding the detection of winning abnormality. It is a flowchart which shows the abnormality determination process which the microcomputer for production control performs. It is a flowchart which shows the abnormality determination process which the microcomputer for production control performs. It is explanatory drawing which shows the other example of the detection method of winning abnormality. FIG. 10 is an explanatory diagram illustrating an example of a timer, a flag, and a counter that are used by the production control microcomputer for detection of a winning abnormality. It is a flowchart which shows the abnormality determination process which the microcomputer for production control performs. It is a flowchart which shows the abnormality determination process which the microcomputer for production control performs. It is explanatory drawing which shows the further another example of the detection method of winning abnormality. It is a flowchart which shows the abnormality determination process which the microcomputer for production control performs. It is a flowchart which shows the abnormality determination process which the microcomputer for production control performs. It is explanatory drawing which shows an example of the content of the control command transmitted / received between a game control means and a payout control means. It is a flowchart which shows the timer interruption process which CPU for payout control performs. It is a flowchart which shows the abnormality determination process which the microcomputer for payout control performs. It is a flowchart which shows the abnormality determination process which the microcomputer for payout control performs. It is a flowchart which shows the abnormality determination process which the microcomputer for payout control performs. It is a flowchart which shows the abnormality determination process which the microcomputer for payout control performs. It is a flowchart which shows the abnormality determination process which the microcomputer for payout control performs. It is a flowchart which shows the abnormality determination process which the microcomputer for payout control performs. It is explanatory drawing for demonstrating a photosensor. It is explanatory drawing which shows the example of combined use of a proximity switch and a photosensor.

Embodiment 1 FIG.
DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, a first embodiment of the invention will be described with reference to the drawings.
First, the overall configuration of a pachinko gaming machine 1 that is an example of a gaming machine will be described. FIG. 1 is a front view of the pachinko gaming machine 1 as seen from the front. In the following embodiments, a pachinko gaming machine will be described as an example. However, the gaming machine according to the present invention is not limited to a pachinko gaming machine, and can be applied to other gaming machines such as a slot machine.

  The pachinko gaming machine 1 includes an outer frame (not shown) formed in a vertically long rectangular shape, and a game frame attached to the inside of the outer frame so as to be opened and closed. Further, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape that is provided in the game frame so as to be opened and closed. The game frame includes a front frame (not shown) that can be opened and closed with respect to the outer frame, a mechanism plate (not shown) to which mechanism parts and the like are attached, and various parts (games to be described later) attached to them. A structure including the board 6).

  On the lower surface of the glass door frame 2 is a hitting ball supply tray (upper plate) 3. Under the hitting ball supply tray 3, there are provided a surplus ball receiving tray 4 for storing game balls that cannot be accommodated in the hitting ball supply tray 3, and a hitting operation handle (operation knob) 5 for firing the hitting ball. A game board 6 is detachably attached to the back surface of the glass door frame 2. The game board 6 is a structure including a plate-like body constituting the game board 6 and various components attached to the plate-like body. In addition, a game area 7 is formed on the front surface of the game board 6 in which a game ball that has been struck can flow down.

  An effect display device 9 composed of a liquid crystal display device (LCD) is provided near the center of the game area 7. The display screen of the effect display device 9 includes an effect symbol display area for performing variable display of the effect symbol in synchronization with the variable display of the first special symbol or the second special symbol. Therefore, the effect display device 9 corresponds to a variable display device that performs variable display of effect symbols. The effect symbol display area includes a symbol display area for variably displaying, for example, three decorative (effect) effect symbols of “left”, “middle”, and “right”. The symbol display area includes “left”, “middle”, and “right” symbol display areas, but the position of the symbol display area does not have to be fixed on the display screen of the effect display device 9. Three areas of the display area may be separated. The effect display device 9 is controlled by an effect control microcomputer mounted on the effect control board. When the first special symbol display 8a is executing variable display of the first special symbol, the effect control microcomputer causes the effect display device 9 to execute the effect display along with the variable display, and the second special symbol display 8a executes the second special display. When the variable display of the second special symbol is executed on the symbol display 8b, the effect display is executed by the effect display device 9 along with the variable display, so that the progress of the game can be easily grasped. .

  Further, in the effect display device 9, symbols other than the symbol that will be the final stop symbol (for example, the middle symbol of the left and right middle symbols) have continued for a predetermined time, and the jackpot symbol (for example, the left middle right symbol is aligned with the same symbol) Stops, swings, scales, or deforms in a state that matches the symbol combination), or multiple symbols fluctuate synchronously in the same symbol, or the position of the display symbol is switched Thus, an effect performed in a state where the possibility of occurrence of a big hit (hereinafter, these states are referred to as reach states) before the final result is displayed is referred to as reach effect. Further, the reach state and its state are referred to as a reach mode. Furthermore, variable display including reach production is called reach variable display. And when the display result of the symbol variably displayed on the effect display device 9 is not a big hit symbol, it becomes “out” and the variation display state ends. A player plays a game while enjoying how to generate a big hit.

  In the upper right part of the display screen of the effect display device 9, there are provided fourth symbol display areas 9c and 9d for displaying a fourth symbol after the effect symbol, a special symbol described later, and a normal symbol. In this embodiment, a fourth symbol display area 9c for the first special symbol in which the variation display of the fourth symbol for the first special symbol is performed in synchronization with the variation display of the first special symbol described later, There is provided a fourth symbol display area 9d for the second special symbol in which the variation display of the fourth symbol for the second special symbol is performed in synchronization with the variation display of the special symbol.

  The 4th symbol for the first special symbol and the 4th symbol for the 2nd special symbol may be collectively referred to as the 4th symbol, and the 4th symbol display area 9c for the 1st special symbol and the 2nd special symbol The 4th symbol display area 9d for symbols may be collectively referred to as a 4th symbol display area.

  The variation (variable display) of the fourth symbol is realized by continuing the state where the fourth symbol display areas 9c and 9d are repeatedly turned on and off at a predetermined time interval in a predetermined display color (for example, blue). . The variable display of the first special symbol on the first special symbol display unit 8a is synchronized with the variable display of the fourth symbol for the first special symbol in the fourth symbol display area 9c for the first special symbol. The variable display of the second special symbol on the second special symbol display 8b is synchronized with the variable display of the fourth symbol for the second special symbol in the fourth symbol display area 9d for the second special symbol. Synchronous means that the variable display start time and end time are the same, and the variable display period is the same. When the big win symbol is stopped and displayed on the first special symbol display 8a, the fourth special symbol display area 9c for the first special symbol is kept lit in a display color (for example, red) reminiscent of the big hit. . When the big win symbol is stopped and displayed on the second special symbol display 8b, the fourth special symbol display area 9d for the second special symbol is kept lit in a display color reminiscent of the big hit (for example, red).

  On the left side of the lower part of the game board 6, a first special symbol display (first variable display portion) 8a for variably displaying the first special symbol as identification information is provided. In this embodiment, the first special symbol display 8a is realized by a simple and small display (for example, 7 segment LED) capable of variably displaying numbers 0 to 9. In other words, the first special symbol display 8a is configured to variably display numbers (or symbols) from 0 to 9. On the lower right side of the game board 6, a second special symbol display (second variable display portion) 8b for variably displaying the second special symbol as identification information is provided. The second special symbol display 8b is realized by a simple and small display (for example, 7 segment LED) capable of variably displaying numbers 0 to 9. That is, the second special symbol display 8b is configured to variably display numbers (or symbols) from 0 to 9.

  The small display is formed in a square shape, for example. In this embodiment, the type of the first special symbol and the type of the second special symbol are the same (for example, both 0 to 9), but the types may be different. Further, the first special symbol display 8a and the second special symbol display 8b may be configured to variably display numbers (or two-digit symbols) of, for example, 00 to 99, for example.

  Hereinafter, the first special symbol and the second special symbol may be collectively referred to as a special symbol, and the first special symbol indicator 8a and the second special symbol indicator 8b are collectively referred to as a special symbol indicator (variable display unit). There are things to do.

  Although this embodiment shows a case where two special symbol indicators 8a and 8b are provided, the gaming machine may be provided with only one special symbol indicator.

  For the variable display of the first special symbol or the second special symbol, the first start condition or the second start condition, which is the variable display execution condition, is satisfied (for example, the game ball has the first start winning opening 13 or the second start winning opening) 14 after passing (including winning)), the variable display start condition (for example, when the number of reserved memories is not 0 and the variable display of the first special symbol and the second special symbol is not executed) The state is started and the big hit game is not executed), and when the variable display time (fluctuation time) elapses, the display result (stop symbol) is derived and displayed. Note that the passing of a game ball means that the game ball has passed through a predetermined area such as a prize opening or a gate, and that includes a game ball entering (winning) a prize opening. It is. Deriving and displaying the display result is to finally stop and display a symbol (an example of identification information).

  A winning device having a first start winning port 13 is provided below the effect display device 9. The game ball won in the first start winning opening 13 is guided to the back of the game board 6 and detected by the first start opening switch 13a.

  A variable winning ball device 15 having a second starting winning port 14 through which a game ball can be won is provided below a winning device having a first starting winning port (first starting port) 13. The variable winning ball device 15 is configured to be able to open and close the wings, and when the wings are open, the game ball is likely to win a prize (open state), and when the wings are not open (closed). The game ball becomes difficult to win (closed state). The game ball won in the second start winning opening (second start opening) 14 is guided to the back of the game board 6 and detected by a second start opening switch 14a (for example, a proximity switch), and a winning confirmation switch 14b. (For example, a photo sensor). In this embodiment, based on the fact that a game ball has been detected by the second start port switch 14a, the variation display of the second special symbol is started, and a prize ball payout is executed. Further, as will be described later, the presence or absence of occurrence of an abnormal winning is determined based on the detection result of the winning confirmation switch 14b in addition to the detection result of the second start opening switch 14a, and the occurrence of the abnormal winning is detected. A security signal is output externally. The variable winning ball device 15 is opened by a solenoid 16.

  For each of the first start winning opening 13 and the second starting winning opening 14, a start opening switch (for example, a proximity switch) may be provided and a winning confirmation switch (for example, a photo sensor) may be provided. Then, for each of the first start winning opening and the second starting winning opening, the variation display of the special symbol is started based on the detection of the game ball by the start opening switch as in this embodiment. A ball payout may be executed. Further, for each of the first start winning opening and the second starting winning opening, whether or not an abnormal winning has occurred is determined based on the detection result of the winning confirmation switch in addition to the detection result by the start opening switch, as in this embodiment. A security signal may be output to the outside based on the determination and the occurrence of an abnormal winning.

  Further, in this embodiment, when the variable winning ball device 15 is in the open state, the game ball can be won in the second starting winning opening 14 (easier to start winning), and is in an advantageous state for the player. Become. In the state where the variable winning ball apparatus 15 is in the open state, it is easier for the game ball to win the second start winning opening 14 than the first starting winning opening 13. In addition, in a state where the variable winning ball device 15 is in the closed state, the game ball does not win the second start winning opening 14. Therefore, in a state where the variable winning ball device 15 is in the closed state, it is easier for the game ball to win the first starting winning port 13 than the second starting winning port 14. In the state where the variable winning ball apparatus 15 is in the closed state, it may be configured that the winning is possible (that is, it is difficult for the gaming ball to win) although it is difficult to win a prize.

  Hereinafter, the first start winning opening 13 and the second start winning opening 14 may be collectively referred to as a start winning opening or a starting opening.

  When the variable winning ball device 15 is controlled to be in the open state, the game ball heading for the variable winning ball device 15 is very likely to win the second start winning port 14. The first start winning opening 13 is provided directly under the effect display device 9, but the interval between the lower end of the effect display device 9 and the first start winning opening 13 is further reduced, or the first start winning opening is set. The nail arrangement around the first start winning opening 13 is made difficult to guide the game balls to the first starting winning opening 13 so that the winning rate of the second starting winning opening 14 is increased. It is also possible to make the direction higher than the winning rate of the first start winning opening 13.

  In this embodiment, as shown in FIG. 1, the variable winning ball apparatus 15 that opens and closes only the second start winning opening 14 is provided. Any of the start winning ports 14 may be provided with a variable winning ball device that performs an opening / closing operation.

  On the side of the first special symbol display 8a, the number of effective winning balls that have entered the first start winning opening 13, that is, the first reserved memory number (the reserved memory is also referred to as the start memory or the start prize memory) is displayed. A first special symbol storage memory display 18a comprising four displays is provided. The first special symbol storage memory indicator 18a increases the number of indicators to be lit by 1 each time there is an effective start winning. Then, each time the variable display on the first special symbol display 8a is started, the number of indicators to be turned on is reduced by one.

  On the side of the second special symbol display 8b, a second special symbol hold memory display 18b comprising four displays for displaying the number of effective winning balls that have entered the second start winning opening 14, that is, the second reserved memory number. Is provided. The second special symbol storage memory display 18b increases the number of indicators to be lit by 1 every time there is an effective start winning. Then, each time the variable display on the second special symbol display 8b is started, the number of indicators to be turned on is reduced by one.

  Also, at the lower part of the display screen of the effect display device 9, there are provided a first reserved memory display unit 18c for displaying the first reserved memory number and a second reserved memory display unit 18d for displaying the second reserved memory number. ing. In addition, you may make it provide the area | region (sum total pending | holding memory display part) which displays the total number (sum total pending memory count) which is the sum total of the 1st pending memory count and the 2nd pending memory count. As described above, if the summation pending storage display section for displaying the total number is provided, it is possible to easily grasp the total number of execution conditions that are not satisfied with the variable display start condition.

  The effect display device 9 is for decoration (for effects) during the variable display time of the first special symbol by the first special symbol display 8a and during the variable display time of the second special symbol by the second special symbol display 8b. A variable display of the effect symbol as the symbol is performed. The variable display of the first special symbol on the first special symbol display 8a and the variable display of the effect symbol on the effect display device 9 are synchronized. Further, the variable display of the second special symbol on the second special symbol display 8b and the variable display of the effect symbol on the effect display device 9 are synchronized. Further, when the jackpot symbol is stopped and displayed on the first special symbol display 8a and when the jackpot symbol is stopped and displayed on the second special symbol display 8b, the effect display device 9 reminds the jackpot The combination of is stopped and displayed.

  Further, as shown in FIG. 1, a special variable winning ball device 20 is provided below the variable winning ball device 15. The special variable winning ball apparatus 20 includes an opening / closing plate, and when the specific display result (big hit symbol) is derived and displayed on the first special symbol display 8a, and the specific display result (big hit symbol) on the second special symbol display 8b. When the open / close plate is controlled to be open by the solenoid 21 in the specific game state (big hit game state) that occurs when the symbol is derived and displayed, the big winning opening serving as the winning area is opened. The game ball that has won the big winning opening is detected by the count switch 23.

  In this embodiment, only the second start winning opening 14 is provided with a winning confirmation switch 14b in addition to the second start opening switch 14a. However, in addition to the count switch 23, the big winning opening is also provided. A winning confirmation switch may be provided. In this case, for example, the count switch 13 may be configured by using a proximity switch and the winning confirmation switch may be configured by using a photosensor as in the case of the second start winning opening 14 (inversely, counting The switch 13 may be configured using a photo sensor, and the winning confirmation switch may be configured using a proximity switch, or a mechanical switch such as a micro switch may be used instead of the proximity switch or the photo sensor). Further, the game control microcomputer may perform the payout of the winning ball based only on the detection result of the count switch 23 in the winning ball payout process based on the winning of the game ball to the big winning opening (step). (See S32). On the other hand, the game control microcomputer, when performing an abnormal winning to the big winning opening, may make a determination based on both the detection result of the count switch 23 and the detection result of the winning confirmation switch. . In this case, for example, in the game control microcomputer, the difference between the detected number of the count switch 23 and the detected number of the winning confirmation switch is a predetermined value (for example, 10) according to the same process as the switch normal / abnormal check process described later. Based on what has been described above, it may be determined that an abnormal winning in the special winning opening has occurred (see steps S121 to S127).

  The game area 6 is also provided with winning ports (ordinary winning ports) 29 and 30 for paying out a predetermined number of premium game balls determined in advance based on winning of game balls. The game balls that have won the winning ports 29 and 30 are detected by the winning port switches 29a and 30a.

  A normal symbol display 10 is provided on the right side of the game board 6. The normal symbol display 10 variably displays a plurality of types of identification information (for example, “◯” and “x”) called normal symbols.

  When the game ball passes through the gate 32 and is detected by the gate switch 32a, variable display of the normal symbol display 10 is started. In this embodiment, variable display is performed by alternately lighting the upper and lower lamps (the symbols can be visually recognized when turned on). For example, if the lower lamp is turned on at the end of the variable display, it is a hit. . When the stop symbol on the normal symbol display 10 is a predetermined symbol (winning symbol), the variable winning ball device 15 is opened for a predetermined number of times. In other words, the state of the variable winning ball apparatus 15 is a state that is advantageous from a disadvantageous state for the player when the normal symbol is a stop symbol (a state in which a game ball can be awarded at the second start winning port 14). To change. In the vicinity of the normal symbol display 10, a normal symbol holding storage display 41 having a display unit with four LEDs for displaying the number of winning balls that have passed through the gate 32 is provided. Each time there is a game ball passing through the gate 32, that is, every time a game ball is detected by the gate switch 32a, the normal symbol storage memory display 41 increases the number of LEDs to be turned on by one. Each time variable display on the normal symbol display 10 is started, the number of LEDs to be lit is reduced by one. In addition, a probability variation state in which the probability of being determined to be a big hit compared to the normal state is high (a state in which the probability of being determined to be a big hit as a result of fluctuation display of special symbols is increased compared to the normal state). Then, the probability that the stop symbol in the normal symbol display 10 becomes a winning symbol is increased, and the opening time and the number of times of opening of the variable winning ball device 15 are increased. Even in the short state (the game state in which the variable display time of the special symbol is shortened) when the symbol variation time is shortened although it is not the probability variation state, the opening time and the number of times of opening of the variable winning ball device 15 are increased.

  On the left and right sides of the game area 7 of the game board 6, there are provided decorative LEDs 25 that are displayed blinking during the game, and at the lower part there is an outlet 26 for taking in a hit ball that has not won. In addition, two speakers 27 that utter sound effects and sounds as predetermined sound outputs are provided on the left and right upper portions outside the game area 7. On the outer periphery of the game area 7, a frame LED 28 provided on the front frame is provided.

  The members constituting the hitting ball supply tray 3 are provided with operation buttons 120 as operation means that can be operated by the player. The operation button 120 is provided with a push button switch that can be pressed by the player. The operation button 120 is provided not only with a push button switch that can be pressed by the player, but also with a dial that can be rotated by the player. The player can perform a predetermined selection (for example, selection of effects) by rotating the dial.

  In the gaming machine, a ball striking device (not shown) that drives a driving motor in response to a player operating the batting operation handle 5 and uses the rotational force of the driving motor to launch a gaming ball to the gaming area 7. ) Is provided. A game ball launched from the ball striking device enters the game area 7 through a ball striking rail formed in a circular shape so as to surround the game area 7, and then descends the game area 7. When the game ball enters the first start winning opening 13 and is detected by the first start opening switch 13a, if the variable display of the first special symbol can be started (for example, the variable display of the special symbol ends, 1), the variable display (variation) of the first special symbol is started on the first special symbol display 8a, and the variable display of the effect symbol is started on the effect display device 9. That is, the variable display of the first special symbol and the effect symbol corresponds to winning in the first start winning opening 13. If the variable display of the first special symbol cannot be started, the first reserved memory number is increased by 1 on the condition that the first reserved memory number has not reached the upper limit value.

  When the game ball enters the second start winning opening 14 and is detected by the second start opening switch 14a, if the variable display of the second special symbol can be started (for example, the special symbol variable display ends, 2), the second special symbol display 8b starts variable display (variation) of the second special symbol, and the effect display device 9 starts variable display of the effect symbol. That is, the variable display of the second special symbol and the effect symbol corresponds to winning in the second start winning opening 14. If the variable display of the second special symbol cannot be started, the second reserved memory number is increased by 1 on condition that the second reserved memory number has not reached the upper limit value.

  In this embodiment, when the probability variation is a big hit, the game state is shifted to a high probability state, and the game ball is easily started and won (that is, in the special symbol indicators 8a and 8b and the effect display device 9). It shifts to a high base state, which is a gaming state controlled so that a variable display execution condition is easily established. In addition, when the gaming state is shifted to the short time state, the state is shifted to the high base state. In the high base state, for example, the frequency at which the variable winning ball device 15 is in the open state is increased or the time in which the variable winning ball device 15 is in the open state is extended compared to the case in which the high base state is not in the high base state. It becomes easier to win a start.

  Instead of extending the time during which the variable winning ball apparatus 15 is in the open state (also referred to as the open extended state), the normal symbol display unit 10 shifts to a normal symbol probability changing state in which the probability that the stop symbol in the normal symbol display unit 10 will be a hit symbol is increased. Depending on the situation, the high base state may be entered. When the stop symbol in the normal symbol display 10 becomes a predetermined symbol (winning symbol), the variable winning ball device 15 is opened for a predetermined number of times. In this case, by performing the transition control to the normal symbol probability changing state, the probability that the stop symbol in the normal symbol display 10 becomes a winning symbol is increased, and the frequency at which the variable winning ball apparatus 15 is opened is increased. Therefore, if the normal symbol probability changing state is entered, the opening time and the number of opening times of the variable winning ball device 15 are increased, and a state where it is easy to start a winning (high base state) is achieved. That is, the opening time and the number of times of opening of the variable winning ball device 15 can be increased when the stop symbol of the normal symbol is a winning symbol or the stop symbol of the special symbol is a probabilistic symbol. It changes to an advantageous state (a state where it is easy to win a start). It should be noted that increasing the number of times of opening is a concept including changing from a closed state to an open state.

  Moreover, you may transfer to a high base state by shifting to the normal symbol time short state where the fluctuation time (variable display period) of the normal symbol in the normal symbol display 10 is shortened. In the normal symbol short-time state, the variation time of the normal symbol is shortened, so that the frequency of starting the variation of the normal symbol increases, and as a result, the frequency of hitting the normal symbol increases. Therefore, when the frequency that the normal symbol is hit increases, the frequency that the variable winning ball apparatus 15 is opened is increased, and the start winning state is easily set (high base state).

  In addition, the change time of special symbols and production symbols will be shortened by shifting to the short time state when the variation time (variable display period) of special symbols and production symbols is shortened. The frequency of being played (in other words, the digestion of the reserved memory becomes faster), and the situation where an invalid start prize is generated can be reduced. Therefore, an effective start winning is likely to occur, and as a result, the possibility of a big hit game being increased.

  Furthermore, by making transitions to all the states shown above (open extended state, normal symbol probability change state, normal symbol short time state, and special symbol short time state), it will be easier to win a start (shift to a high base state). May be. In addition, it is easier to win a start (high base) by shifting to any one of the above states (open extended state, normal symbol probability changing state, normal symbol short time state, and special symbol short time state). Transition to a state). In addition, it is easier to win a start by shifting to any one of the above states (open extended state, normal symbol probability changing state, normal symbol short time state, and special symbol short time state). You may make it move to a base state.

  Next, the structure of the back surface of the pachinko gaming machine 1 will be described with reference to FIG. FIG. 2 is a rear view of the gaming machine as seen from the back side. As shown in FIG. 2, on the back side of the pachinko gaming machine 1, there are a variable display control unit including an effect control board 80 on which an effect control microcomputer 100 for controlling the effect display device 9 is mounted, a game control microcomputer, and the like. Various boards such as a mounted game control board (main board) 31, an audio output board 70, a lamp driver board 35, and a payout control board 37 mounted with a payout control microcomputer for performing ball payout control are installed. Yes. The game control board 31 is stored in the board storage case 200.

  Further, on the back side of the pachinko gaming machine 1, a power supply substrate 910 and a touch sensor substrate 91 on which power supply circuits for generating various power supply voltages such as DC30V, DC21V, DC12V, and DC5V are mounted. The power supply board 910 is supplied with the game control board 31 and each electrical component control board (the effect control board 80 and the payout control board 37) in the pachinko gaming machine 1 and each electrical component (power is supplied) provided in the pachinko gaming machine 1. A power switch as a power supply permission means for executing or shutting off the power supply to the component), and a clear switch for clearing the RAM 55 of the game control microcomputer 560 of the game control board 31 are provided. ing. Further, a replaceable fuse is provided inside the power switch (inside the substrate).

  In this embodiment, the main board 31 is provided on the game board side, and the payout control board 37 is provided on the game frame side. Even in such a configuration, as will be described later, the communication between the main board 31 and the payout control board 37 is performed by serial communication, thereby facilitating the routing of the wiring when replacing the game board. .

  Each control board is equipped with control means including a control microcomputer. The control means is an electrical component (game device: ball payout device 97, effect display device 9, light emission from a lamp, LED, etc.) provided in the gaming machine according to a command signal (control signal) as a command from the game control means or the like. Body, speaker 27, etc.). Hereinafter, the main board 31 may be included in the control board for explanation. In that case, the control means mounted on the control board refers to each of the game control means and the means for controlling the electrical components provided in the gaming machine in accordance with a command signal from the game control means or the like. A substrate on which a microcomputer other than the main substrate 31 is mounted may be referred to as a sub-substrate. The ball payout device 97 is a device for paying out a game ball guided by a passage for guiding the game ball and a sprocket driven by a stepping motor or the like to an upper plate or a lower plate. A payout number counting switch for counting prize balls and rental balls is also configured as part of the unit. In this embodiment, the payout detection means is realized by the payout number count switch 301 and has a function of detecting that a winning ball or a lending ball is actually paid out from the ball payout device 97. In this case, the payout number count switch 301 outputs a detection signal every time one payout of prize balls or rental balls is detected.

  On the back side of the pachinko gaming machine 1, a terminal board 160 having terminals for outputting various information to the outside of the pachinko gaming machine 1 is installed above. The terminal board 160 has, for example, an information output signal such as jackpot information indicating the occurrence of a jackpot gaming state (symbol determination frequency 1 signal shown in FIG. 36, start port signal, jackpot 1 signal, jackpot 2 signal, jackpot 3 signal, hour An information output terminal for externally outputting a short signal, a winning signal, a security signal, a high-accuracy signal, and winning ball information) is provided.

  The game ball stored in the storage tank 38 passes through a guide rail (not shown), and reaches a ball payout device 97 covered with a payout case 40A through a curve rod. Above the ball payout device 97, a ball break switch 187 is provided as a game medium break detection means. When the ball break switch 187 detects a ball break, the payout operation of the ball payout device 97 stops. The ball break switch 187 is a switch for detecting the presence or absence of a game ball in the game ball passage, but the ball break detection switch 167 for detecting the shortage of supply balls in the storage tank 38 is also an upstream portion of the guide rail (in the storage tank 38). (Proximate part). When the ball break detection switch 167 detects a shortage of game balls, the game balls are replenished to the pachinko gaming machine 1 from the replenishment mechanism provided on the gaming machine installation island.

  When a large number of game balls as prizes based on winning a prize or a game ball based on a ball lending request are paid out and the hitting ball supply tray 3 is full, the game balls are guided to the surplus ball receiving tray 4 through the surplus ball guiding path. Further, when the game ball is paid out, a sensing lever (not shown) presses the full tank switch as the storage state detection means, and the full tank switch as the storage state detection means is turned on. In this state, the rotation of the payout motor in the ball payout device is stopped, the operation of the ball payout device is stopped, and the driving of the ball hitting device is also stopped.

  FIG. 3 is a block diagram showing an example of the circuit configuration of the main board (game control board) 31. FIG. 3 also shows a payout control board 37, an effect control board 80, and the like. A game control microcomputer (corresponding to game control means) 560 for controlling the pachinko gaming machine 1 according to a program is mounted on the main board 31. The game control microcomputer 560 includes a ROM 54 for storing a game control (game progress control) program and the like, a RAM 55 as storage means used as a work memory, a CPU 56 for performing control operations in accordance with the program, and an I / O port unit 57. including. In this embodiment, the ROM 54 and the RAM 55 are built in the game control microcomputer 560. That is, the game control microcomputer 560 is a one-chip microcomputer. The one-chip microcomputer only needs to include at least the RAM 55, and the ROM 54 may be external or internal. The I / O port unit 57 may be externally attached.

  In the game control microcomputer 560, the CPU 56 executes control in accordance with the program stored in the ROM 54, so that the game control microcomputer 560 (or CPU 56) executes (or performs processing) hereinafter. Specifically, the CPU 56 executes control according to a program. The same applies to microcomputers mounted on substrates other than the main substrate 31.

  The game control microcomputer 560 includes a random number circuit 503. The random number circuit 503 is a hardware circuit that is used to generate a random number for determination to determine whether or not to win a jackpot based on a display result of variable symbol special display. The random number circuit 503 updates numerical data in accordance with a set update rule within a numerical range in which an initial value (for example, 0) and an upper limit value (for example, 65535) are set, and starts at a random timing Based on the fact that the winning time is the reading (extraction) of the numerical data, it has a random number generation function in which the numerical data to be read becomes a random value.

  The random number circuit 503 includes a numeric data update range selection setting function (initial value selection setting function and upper limit value selection setting function), numeric data update rule selection setting function, and numeric data update rule selection. It has various functions such as a switching function. With such a function, the randomness of the generated random numbers can be improved.

  Further, the game control microcomputer 560 has a function of setting an initial value of numerical data updated by the random number circuit 503. For example, a predetermined calculation is performed using the ID number of the game control microcomputer 560 stored in a predetermined storage area such as the ROM 54 (an ID number assigned with a different value for each product of the game control microcomputer 560). The numerical data obtained by the execution is set as the initial value of the numerical data updated by the random number circuit 503. By performing such processing, the randomness of the random number generated by the random number circuit 503 can be further improved.

  The game control microcomputer 560 reads the numerical data as random R from the random number circuit 503 when a start winning to the first start port switch 13a or the second start port switch 14a occurs, and starts to change the special symbol and the production symbol. Sometimes it is determined whether or not to make a big hit display result as a specific display result based on the random R, that is, whether or not to make a big hit. Then, when it is determined to be a big hit, the gaming state is shifted to a big hit gaming state as a specific gaming state advantageous to the player.

  Further, the game control microcomputer 560 has a built-in serial communication circuit 505 for inputting / outputting (transmitting / receiving) signals to / from the payout control board 37 (the payout control microcomputer 370) by serial communication. The payout control microcomputer 370 also includes a serial communication circuit for inputting / outputting signals via the serial communication with the game control microcomputer 560 (a serial communication circuit built in the payout control microcomputer 370). (See FIG. 4).

  The RAM 55 is a backup RAM as a non-volatile storage means, part or all of which is backed up by a backup power supply created on the power supply board. That is, even if the power supply to the gaming machine is stopped, a part or all of the contents of the RAM 55 is stored for a predetermined period (until the capacitor as the backup power supply is discharged and the backup power supply cannot be supplied). In particular, at least data corresponding to the game state, that is, the control state of the game control means (a special symbol process flag, a value of a reserved memory number counter for counting the number of reserved memories) and data indicating the number of unpaid winning balls ( Specifically, a value of a prize ball command output counter (to be described later) is stored in the backup RAM. In this embodiment, the value of a prize information storage timer described later is also stored in the backup RAM. The data corresponding to the control state of the game control means is data necessary for resuming the game based on the data when the power is restored after a power failure or the like occurs. Further, data corresponding to the control state and data indicating the number of unpaid prize balls are defined as data indicating the progress state of the game. In this embodiment, it is assumed that the entire RAM 55 is backed up.

  A reset signal from the power supply board is input to the reset terminal of the game control microcomputer 560. A reset circuit for generating a reset signal supplied to the game control microcomputer 560 and the like is mounted on the power supply board. When the reset signal becomes high level, the game control microcomputer 560 and the like are in an operable state, and when the reset signal becomes low level, the game control microcomputer 560 and the like are in an operation stop state. Therefore, an allowable signal that allows the operation of the game control microcomputer 560 or the like is output during a period when the reset signal is at a high level, and a game control microcomputer is output when the reset signal is at a low level. An operation stop signal for stopping the operation of 560 or the like is output. Note that the reset circuit may be mounted on each electric component control board (a board on which a microcomputer for controlling the electric parts is mounted).

  Further, a power-off signal indicating that the power supply voltage from the power supply board has dropped below a predetermined value is input to the input port of the game control microcomputer 560. That is, the power supply board monitors the voltage value of a predetermined voltage (for example, DC30V or DC5V) used in the gaming machine, and when the voltage value decreases to a predetermined value (the power supply voltage is reduced). A power supply monitoring circuit that outputs a power-off signal indicating that). Instead of mounting the power monitoring circuit on the power supply board, it may be mounted on a board that is backed up by a backup power supply (for example, the main board 31). A clear signal (not shown) indicating that the clear switch for instructing to clear the contents of the RAM is operated is input to the input port of the game control microcomputer 560.

  Also, an input driver circuit for supplying the basic circuit 53 with detection signals from the gate switch 32a, the first start port switch 13a, the second start port switch 14a, the winning confirmation switch 14b, the count switch 23, and the winning port switches 29a and 30a. 58 is also mounted on the main board 31, and an output circuit 59 for driving the solenoid 16 for opening / closing the variable winning ball apparatus 15 and the solenoid 21 for opening / closing the special variable winning ball apparatus according to a command from the basic circuit 53 is also mounted on the main board 31. A system reset circuit (not shown) for resetting the game control microcomputer 560 when the power is turned on, and an information output signal such as jackpot information indicating the occurrence of a jackpot gaming state are sent to the hall via the terminal board 160. An information output circuit 64 that outputs to an external device such as a computer is also main. It is mounted to the plate 31.

  In this embodiment, the effect control means (configured by the effect control microcomputer) mounted on the effect control board 80 receives the effect control command from the game control microcomputer 560 via the relay board 77. The display control of the effect display device 9 that receives and displays the effect symbol variably is performed.

  FIG. 4 is a block diagram showing components related to payout, such as the payout control board 37 and the ball payout device 97. As shown in FIG. 4, the payout control board 37 includes a payout control microcomputer 370 including a payout control CPU 371. In this embodiment, the payout control microcomputer 370 is a one-chip microcomputer and incorporates at least a RAM. The payout control microcomputer 370, the RAM (not shown), the ROM (not shown) storing the payout control program, the I / O port, and the like constitute the payout control means. That is, the payout control means is realized by a payout control CPU 371, a payout control microcomputer 370 having a RAM and a ROM, and an I / O port. The I / O port may be built in the payout control microcomputer 370. Note that, unlike the game control microcomputer 560, the RAM built in the payout control microcomputer 370 has not been backed up by a backup power source. Therefore, if the power supply to the gaming machine is stopped, the stored contents of the RAM built in the payout control microcomputer 370 are lost.

  The payout control microcomputer 370 performs control to pay out the game ball based on a predetermined payout condition being satisfied. The predetermined payout condition is that a game ball has won in a winning area (ordinary winning holes 29, 30, large winning opening, first starting winning opening 13, second starting winning opening 14) provided in the game area. It is established when a rental ball request is made. In addition, for example, when applied to a gaming machine such as a parrot machine or a slot machine, the predetermined payout condition is also satisfied when a game ball or medal return request is made. Further, for example, when applied to a gaming machine such as a parrot machine or a slot machine, the predetermined payout condition is also established when the symbol stop symbol becomes a predetermined winning symbol.

  Detection signals from the ball break switch 187, the full switch 48, and the payout count switch 301 are input to the I / O port 372 f of the payout control board 37 via the relay board 72. In this embodiment, the detection signal from the payout number count switch 301 is input to the payout control microcomputer 370 and then output to the main board 31 via the I / O port 372a and the output circuit 373B. .

  A detection signal from the payout motor position sensor 295 is input to the I / O port 372e of the payout control board 37 via the relay board 72. The payout motor position sensor 295 is a sensor comprising a light emitting element (LED) and a light receiving element for detecting the rotational position of the payout motor 289, and is used for detecting that the game ball is clogged, that is, so-called ball biting. . In the payout control microcomputer 370 mounted on the payout control board 37, the detection signal from the ball break switch 187 indicates that the ball is out of ball, or the detection signal from the full tank switch 48 indicates that the ball is full. Then, the ball payout process is stopped.

  Further, when the detection signal from the full tank switch 48 indicates a full state, the payout control microcomputer 370 has a low level with respect to the launch board 90 in order to stop the ball launch from the hitting ball launcher. A full tank signal is output. A launch motor signal output from the AND circuit 91 of the launch board 90 to the launch motor 94 is transmitted from the launch board 90 to the launch motor 94. A full tank signal from the payout control microcomputer 370 is input to one of the input sides of the AND circuit 91 mounted on the launch board 90, and a drive signal from the drive signal generation circuit 92 (for driving the launch motor 94). Is a signal that serves to supply power from the power supply board.) Is input to the other input side of the AND circuit 91. Then, the firing motor signal of the AND circuit 91 is input to the firing motor 94. That is, while the payout control microcomputer 370 is outputting the full tank signal, the output of the firing motor signal to the firing motor 94 is stopped. Even when the payout control microcomputer 370 is outputting a full tank signal, the output of the launch motor signal to the launch motor 94 is not stopped, and the ball launch from the hitting ball launcher is not stopped. May be.

  The payout control microcomputer 370 incorporates a serial communication circuit 380 for inputting / outputting (transmitting / receiving) signals with the game control microcomputer 560 through serial communication. In this embodiment, the game control microcomputer 560 and the payout control microcomputer 370 are connected between the game control microcomputer 560 and the payout control microcomputer 370 via serial communication circuits 505 and 380. In order to confirm, payout control commands (connection confirmation command, connection OK command) are exchanged (transmitted / received) at regular intervals (for example, 1 second). For example, the game control microcomputer 560 transmits a connection confirmation command for performing connection confirmation at regular intervals via the serial communication circuit 505, and the payout control microcomputer 370 receives the game control microcomputer 560 from the game control microcomputer 560. When the connection confirmation command is received, a connection OK command notifying that is transmitted to the game control microcomputer 560. Also, for example, when a winning occurs, the game control microcomputer 560 sets data indicating the number of winning balls to be paid out in the lower 4 bits of the winning ball number command, and the number of winning balls set in the setting. The command is transmitted to the payout control microcomputer 370. Then, the payout control microcomputer 370 transmits a prize ball number reception command indicating that the prize ball number has been received to the game control microcomputer 560. Further, when the payout control microcomputer 370 finishes the prize ball payout operation, it transmits a prize ball end command indicating the completion of the prize ball to the game control microcomputer 560. The payout control microcomputer 370 transmits a prize ball preparing command to the game control microcomputer 560 at regular intervals until the prize ball payout operation is completed. In addition, when a predetermined error (an error such as ball lending, full tank, or out of ball) has occurred, the lower 4 bits of the connection OK command or the winning ball preparation command should be made different from the data indicating the error content. The connection OK command and the winning ball preparation command in which the setting is made are transmitted to the game control microcomputer 560.

  Further, the payout control microcomputer 370 outputs an error signal to the error display LED 374 by the 7 segment LED via the output port 372c. A detection signal from an error release switch 375 for releasing the error state is input to the input port 372f of the payout control board 37. The error cancel switch 375 is used to cancel the error state by software reset.

  Further, a drive signal from the payout control microcomputer 370 to the payout motor 289 is transmitted to the payout motor 289 in the payout mechanism portion of the ball payout device 97 via the output port 372a and the relay board 72. A driver circuit (motor drive circuit) is installed outside the output port 372a, but is not shown in FIG.

  A card unit control microcomputer is mounted on the card unit 50 installed adjacent to the gaming machine. In addition, the card unit 50 is provided with a usable display lamp, a connecting table direction indicator, a card insertion display lamp, and a card insertion slot. A frequency display LED 60, a ball lending LED 61, a ball lending switch 62, and a return switch 63 provided in the vicinity of the hitting ball supply tray 3 are connected to the interface board (relay board) 66.

  A card lending switch signal indicating that the ball lending switch 62 has been operated and a return switch signal indicating that the return switch 63 has been operated are provided to the card unit 50 from the interface board 66 in accordance with the player's operation. . Further, a card balance display signal indicating a prepaid card balance and a ball lending display signal are given from the card unit 50 to the interface board 66. Between the card unit 50 and the payout control board 37, a connection signal (VL signal), a unit operation signal (BRDY signal), a ball lending request signal (BRQ signal), a ball lending completion signal (EXS signal) and a pachinko machine operation signal ( PRDY signal) is transmitted / received via the input port 372f and the output port 372d. An interface board 66 is interposed between the card unit 50 and the payout control board 37. Therefore, a signal such as a connection signal (VL signal) is transmitted and received between the card unit 50 and the payout control board 37 via the interface board 66 as shown in FIG.

  When the power of the pachinko gaming machine 1 is turned on, the payout control microcomputer 370 mounted on the payout control board 37 outputs a PRDY signal to the card unit 50. The card unit control microcomputer outputs a VL signal when the power is turned on. The payout control microcomputer 370 determines the connected / unconnected state of the card unit 50 according to the input state of the VL signal. When a card is received in the card unit 50, the ball lending switch is operated and a ball lending switch signal is input, the card unit control microcomputer outputs a BRDY signal to the payout control board 37. When a predetermined delay time elapses from this point, the card unit control microcomputer outputs a BRQ signal to the payout control board 37.

  Then, the payout control microcomputer 370 raises the EXS signal to the card unit 50 and, when detecting the fall of the BRQ signal from the card unit 50, drives the payout motor 289 to give a predetermined number of rental balls to the player. Pay out. When the payout is completed, the payout control microcomputer 370 causes the EXS signal to the card unit 50 to fall. Thereafter, on the condition that the BRDY signal from the card unit 50 is not in the ON state, the winning ball payout control is executed when a payout command signal is received from the game control means.

  The power supply voltage AC24V used in the card unit 50 is supplied from the payout control board 37. That is, power supply from the power supply board 910 to the card unit 50 is performed via the payout control board 37 and the interface board 66. In this example, a fuse for protecting the card unit 50 is provided in a 24 V AC power supply line for the card unit 50 arranged in the interface board 66, and a voltage higher than a predetermined voltage is supplied to the card unit 50. It is prevented.

  Further, in this embodiment, the case where the card unit 50 is installed adjacent to the gaming machine as a separate body from the gaming machine is taken as an example, but the card unit 50 may be integrated with the gaming machine. . Further, the present invention can be applied even in the case where game balls corresponding to the amount of money are lent out in accordance with coin insertion.

  FIG. 5 is a block diagram illustrating a circuit configuration example of the relay board 77, the effect control board 80, the lamp driver board 35, and the audio output board 70. In the example shown in FIG. 5, the lamp driver board 35 and the audio output board 70 are not equipped with a microcomputer, but may be equipped with a microcomputer. Further, without providing the lamp driver board 35 and the audio output board 70, only the effect control board 80 may be provided for effect control.

  The effect control board 80 includes an effect control CPU 101 and an effect control microcomputer 100 including a RAM for storing information related to effects such as effect symbol process flags. The RAM may be externally attached. In this embodiment, the RAM in the production control microcomputer 100 is not backed up. In the effect control board 80, the effect control CPU 101 operates in accordance with a program stored in a built-in or external ROM (not shown), and receives a capture signal from the main board 31 input via the relay board 77 ( In response to the (effect control INT signal), an effect control command is received via the input driver 102 and the input port 103. Further, the effect control CPU 101 causes the VDP (video display processor) 109 to perform display control of the effect display device 9 based on the effect control command.

  In this embodiment, a VDP 109 that performs display control of the effect display device 9 in cooperation with the effect control microcomputer 100 is mounted on the effect control board 80. The VDP 109 has an address space independent of the production control microcomputer 100, and maps a VRAM therein. VRAM is a buffer memory for developing image data. Then, the VDP 109 outputs the image data in the VRAM to the effect display device 9 via the frame memory.

  The effect control CPU 101 outputs to the VDP 109 a command for reading out necessary data from a CGROM (not shown) in accordance with the received effect control command. The CGROM stores character image data and moving image data displayed on the effect display device 9, specifically, a person, characters, figures, symbols (including effect symbols), and background image data in advance. ROM. The VDP 109 reads image data from the CGROM in response to the instruction from the effect control CPU 101. The VDP 109 executes display control based on the read image data.

  Further, the effect control CPU 101 outputs a signal for driving the LED to the lamp driver board 35 via the output port 105. Further, the production control CPU 101 outputs sound number data to the audio output board 70 via the output port 104.

  In the lamp driver board 35, a signal for driving the LED is input to the LED driver 352 via the input driver 351. The LED driver 352 supplies a current to a light emitter provided on the frame side such as the frame LED 28 based on a signal for driving the LED. Further, an electric current is supplied to the decoration LED 25 provided on the game board side.

  In the voice output board 70, the sound number data is input to the voice synthesis IC 703 via the input driver 702. The voice synthesizing IC 703 generates voice or sound effect according to the sound number data and outputs it to the amplifier circuit 705. The amplification circuit 705 outputs an audio signal obtained by amplifying the output level of the speech synthesis IC 703 to a level corresponding to the volume set by the volume 706 to the speaker 27. The voice data ROM 704 stores control data corresponding to the sound number data. The control data corresponding to the sound number data is a collection of data showing the output form of the sound effect or sound in a time series in a predetermined period (for example, the changing period of the effect design).

  FIG. 6 is an explanatory diagram showing an example of output port assignment in the game control means. As shown in FIG. 6, a payout control signal (in this example, a connection signal) transmitted to the payout control board 37 is output from the output port 0. Further, a solenoid (large winning port door solenoid) 21 for opening and closing the variable winning ball device 20 for opening and closing the big winning port, and a solenoid (normal electric accessory solenoid) 16 for opening and closing the variable winning ball device 15 are driven. The signal is also output from output port 0. In addition, a high-accuracy medium signal among signals output from the output port 0 to an external device (for example, a hall computer) via the terminal board 160 is also output.

  The logic (for example, 1 is on) opposite to the “logic” shown in FIG. 6 (for example, 0 is on) may be used. The “logic” is determined so that the payout control microcomputer 370 always detects the off state when the signal line to the terminal 37 is disconnected or when the cable is disconnected (including no cable connection). . Specifically, generally, when a disconnection or disconnection of the cable occurs, a high level is detected on the signal receiving side, so the high level on the signal line between the main board 31 and the payout control board 37 is the game control means. The “logic” is determined to be in the off state at the output port at. Therefore, if necessary, an output buffer circuit for logically inverting the signal is provided outside the output port on the main board 31.

  Then, various information output signals, that is, information relating to control (for example, 1 symbol determination number signal, start port signal, jackpot, etc.) are output from the output port 1 to the external device (for example, hall computer) via the terminal board 160. 1 signal, 2 jackpots, 3 jackpots, time-short signal, winning signal, security signal) are output. However, as already described, the high-accuracy intermediate signal among the signals output externally is output from the output port 0. In this embodiment, prize ball information (a signal outputted every time ten prize ball payouts are detected) is also outputted to an external device via the terminal board 160. In this case, on the payout control board 37 side, a prize ball payout is detected, and prize ball information is input to the main board 31. The prize ball information input to the main board 31 is output to the outside via the terminal board 160 via the main board 31 as it is without passing through the game control microcomputer 560. The prize ball information input to the main board 31 may be output to the outside via the terminal board 160 after temporarily passing through the game control microcomputer 560.

  Note that signals output to the outside via the terminal board 160 are not limited to those shown in this embodiment. For example, a door opening signal indicating that the gaming frame is in an open state, a prize ball signal 1 (a signal output every time one prize ball payout is detected), a gaming machine error status signal (a gaming machine has an error) The state (in this example, a signal indicating that the ball is out of error state or full tank error state) may also be output to the external device via the terminal board 160. In this case, on the payout control board 37 side, it is also detected that the gaming frame is in an open state, a prize ball payout, and an error state of the gaming machine, and the door opening signal, the prize ball signal 1, and the gaming machine error status signal are the main board. 31. The door opening signal, the prize ball signal 1, and the gaming machine error state signal input to the main board 31 are not transmitted through the game control microcomputer 560 but directly passed through the main board 31 to the terminal board 160. Output externally. Also in this case, the door opening signal, the prize ball signal 1 and the gaming machine error state signal input to the main board 31 pass through the gaming control microcomputer 560 once and then externally output via the terminal board 160. You may be made to do.

  Further, for example, in addition to the symbol determination frequency 1 signal as a symbol determination frequency signal for notifying the number of fluctuations of the special symbol, the symbol determination frequency 2 signal may be externally output via the terminal board 160. In this case, for example, in order to notify the number of fluctuations of both the first special symbol and the second special symbol by externally outputting the symbol determination number 2 signal as a signal for notifying only the number of fluctuations of the first special symbol. The signal may be configured to be externally output as a signal of the number of symbol determinations. With such a configuration, on the external device side such as a hall computer, in addition to the number of fluctuations of only the first special symbol, the number of fluctuations of the first special symbol and the second special symbol, or the fluctuation of only the second special symbol The number of times can also be grasped.

  FIG. 7 is an explanatory diagram showing an example of bit assignment of input ports in the game control means. As shown in FIG. 7, the detection signal of the count switch 23, the detection signals of the winning opening switches 29a and 30a, and the detection signal of the winning confirmation switch 14b are input to bits 0 and 2 to 4 of the input port 0, respectively. . In addition, a radio wave sensor signal, a magnet sensor signal, a door opening signal, and prize ball information are input to the bits 4 to 7 of the input port 1, respectively. In addition, bits 0 to 4 of the input port 2 respectively include a detection signal of the first start port switch 13a, a detection signal of the second start port switch 14a, a detection signal of the gate switch 32a, and a clear switch from the power supply board 910. A detection signal and a power-off signal are input.

  FIG. 8 is a circuit diagram showing an internal configuration of the terminal board 160. In the terminal board 160 shown in FIG. 8, the connectors CN-1 and CN-2 on the upper left side are connectors for connecting cables that transmit signals from the main board 31, and the connector CN-3 on the lower left side is This is a connector for connecting a cable for transmitting a signal from the payout control board 37 via the main board 31. The right connectors CN1 to CN10 are connectors for connecting cables that transmit signals to an external device such as a hall computer. The terminal board 160 is mounted with semiconductor relays (PhotoMOS relays) PC1 to PC10 as driver circuits.

  When the cable from the main board 31 is connected to the connectors CN-1 and CN-2, various signals are input from the main board 31 (game control microcomputer 560) to the terminal board 160. Specifically, the symbol determination number 1 signal is input to the terminal “2” of the connector CN-1, the start port signal is input to the terminal “3” of the connector CN-1, and the terminal “4” of the connector CN-1 is input. 1 signal is input to the terminal “5” of the connector CN-1, 2 signals are input to the terminal “6” of the connector CN-1, and 3 signals of the jackpot are input to the terminal “7” of the connector CN-1. To the terminal “8” of the connector CN-1, a winning signal is input to the terminal “9” of the connector CN-1, and a terminal “9” of the connector CN-2 is input. A high-accuracy signal is input.

  Further, when the cable from the payout control board 37 is connected to the connector CN-3 via the main board 31, a signal from the payout control board 37 (the payout control microcomputer 370) is input to the terminal board 160. The Specifically, the prize ball information is input to the terminal “9” of the connector CN-3.

  As shown in FIG. 8, in the terminal board 160, the signal line of the reference potential is connected to the terminal “1” of the connector CN-1, the connector CN-2, and the connector CN-3, the signal lines are branched, Are connected to the input terminal “1” of the semiconductor relays PC1 to PC10. The signal lines connected to the terminals “2” to “9” of the connector CN-1, the connector “9” of the connector CN-2, and the connector “9” of the connector CN-3 are each 1KΩ resistance R1. Are connected to the input terminal “2” of the semiconductor relays PC1 to PC10 via R10. The signal lines connected to the output terminals “4” of the semiconductor relays PC1 to PC10 are connected to the terminals “1” of the connectors CN1 to CN10, respectively. The signal lines connected to the output terminals “3” of the semiconductor relays PC1 to PC10 are connected to the terminals “2” of the connectors CN1 to CN10, respectively.

  In the semiconductor relays PC1 to PC10, when a signal current flows through the input terminal, the light emitting element (LED) on the input side emits light. The emitted light is applied to the photoelectric element (solar cell) provided opposite to the LED through the transparent silicon. The photoelectric element that has received the light exchanges a voltage according to the amount of light, and this voltage charges the MOSFET gate of the output section through the control circuit. When the MOSFET gate voltage supplied from the photoelectric element reaches the set voltage value, the MOSFET becomes conductive and turns on the load. When the signal current at the input terminal is cut off, the light emitting element (LED) stops emitting light. When the light emission of the LED stops, the voltage of the photoelectric element decreases, and when the voltage supplied from the photoelectric element decreases, the gate load of the MOSFET is rapidly discharged by the control circuit. With this control circuit, the MOSFET is turned off and the load is turned off.

  By the operation of the semiconductor relays PC1 to PC10 as described above, signals input from the input side connector CN-1, connector CN-2, and connector CN-3 are transmitted to the output side connectors CN1 to CN10, and a hall computer or the like. Output to an external device. Specifically, the design CN count 1 signal is output from the connector CN1, the start signal is output from the connector CN2, the jackpot signal is output from the connector CN3, the jackpot signal is output from the connector CN4, and the connector CN5 is output. Three jackpot signals are output, a time signal is output from the connector CN6, a winning signal is output from the connector CN7, a security signal is output from the connector CN8, a high-probability medium signal is output from the connector CN9, and a prize is output from the connector CN10. Sphere information is output. The assignment of connectors to each external output signal on terminal board 160 is not limited to that shown in this embodiment. For example, the security signal may be output from the end connector (for example, connector CN10) provided on the terminal board 160.

  Note that the winning signal output from the connector CN7 is that a predetermined payout condition for paying out a predetermined number (in this embodiment, 10 balls) of winning balls is satisfied (the first start winning port 13, This is a signal indicating that a winning has occurred in the second start winning port 14, the big winning port, and the normal winning ports 29, 30. The award ball has not been paid out. By confirming the winning signal, the expected number of prize balls to be paid out can be recognized by an external device such as a hall computer.

  Also, the prize ball information output from the connector CN10 is that a specific number (10 balls in this embodiment) of prize balls has been paid out (the ball payout device 97 is driven and the prize balls are actually paid out). This is a signal indicating that By confirming the prize ball information, the number of prize balls actually paid out can be recognized by an external device such as a hall computer. Also, by confirming the planned number of prize balls indicated by the winning signal and the number of prize balls already paid out indicated by the prize ball information, whether or not the prize balls have been paid out normally and the number of excess or insufficient prize balls are determined. It can be recognized by an external device such as a hall computer.

  The security signal output from the connector CN8 is a signal indicating the security state of the gaming machine. Specifically, as will be described later, when it is determined that an abnormal winning to the second starting winning opening 14 has occurred based on the detection result of the second starting opening switch 14a and the detection result of the winning confirmation switch 14b. In addition, a security signal is output to an external device such as a hall computer for a predetermined period (for example, 4 minutes). With such a configuration, a fraudulent act such as recognizing that the number of winnings to the second start winning opening 14 is larger than the actual winning number using radio waves or the like has been performed. Can be recognized on the external device side.

  In this embodiment, even when the gaming machine is turned on and the initialization process is executed, the security signal is output to an external device such as a hall computer for a predetermined period (for example, 30 seconds). . By configuring as such, it is recognized that the initialization process has been executed at an unnatural timing (for example, even after all the gaming machine power reset operations have been completed when the amusement store is opened). By making it possible, the external device such as a hall computer can recognize the possibility that an unauthorized act of illegally resetting the power of the gaming machine and aiming for a big hit at the power reset timing is performed. it can.

  In this embodiment, as described above, when the abnormal winning is detected and the initialization process (for example, the operation of the clear switch is performed when the power to the gaming machine is turned on) A common security signal is output from the common connector CN8 of the terminal board 160 to the outside when the processing such as clearing the stored content is executed. This is because the initialization process is usually performed only when the game machine power is reset when the amusement store is opened, so the terminal is used for a signal that is output only once a day. Providing a dedicated connector or semiconductor relay on the substrate 160 is not efficient and wasteful. Therefore, in this embodiment, an external output signal is configured by outputting a security signal from the common connector CN8 when an abnormal winning is detected and when an initialization process is executed. The waste of lines and circuit elements is reduced. That is, it is possible to prevent an increase in the number of parts of a mechanism for outputting information to an external device such as a hall computer and complication of wiring work.

  The signal output from the common connector as a security signal is not limited to that shown in this embodiment. For example, not only abnormal winning at the second starting winning opening 14, but abnormal winning at the first starting winning opening 13, the large winning opening, and the normal winning openings 29, 30 is detected, and a common connector of the terminal board 160 is detected. You may comprise so that CN8 can be externally output as a security signal. In this case, for example, the first start winning opening 13, the big winning opening, and the normal winning openings 29, 30 are also used as switches for detecting the winning of the game ball, like the second starting winning opening 14. Two different types of switches (proximity switch and photo sensor) may be provided, and the presence / absence of an abnormal prize may be determined according to the same determination method as that for the second start winning opening 14.

  Further, for example, when abnormal magnetism is detected by a magnet sensor provided in a gaming machine or when abnormal radio waves are detected by a radio wave sensor provided in a gaming machine, a security signal is output from the common connector CN8 of the terminal board 160. You may comprise so that external output is possible. Further, for example, when an abnormality of various switches provided in the gaming machine is detected (for example, when occurrence of a short circuit is detected by determining that the input value exceeds the threshold value), a common terminal board 160 is used. The connector CN8 may be configured so that it can be externally output as a security signal.

  As described above, even if there is an abnormal winning at the grand prize opening, an abnormal magnetic error, or an abnormal radio wave error, it is possible to output only one signal line as a security signal from the common connector CN8 of the terminal board 160. If connected, an error detection can be performed by an external device such as a hall computer, and the work load related to error detection can be reduced.

  In the case of detecting an abnormal winning at the big winning opening, when determining based on the number of detections by the count switch 23 and the number of detections by the winning confirmation switch being a predetermined value (for example, 10) or more. In addition, the count switch 23 when the value of the special symbol process flag is not a value indicating that the game is a big hit game (for example, when the value of the special symbol process flag is not 5 or more, see FIG. 30). Even when a game ball is detected by the above, it may be determined that an abnormal winning to the big winning opening has occurred. In addition, in this way, when it is determined that an abnormal winning to the big winning opening has occurred based on the detection result of the count switch 23 and the winning confirmation switch, or an abnormal to the big winning opening based on the value of the special symbol process flag. Even when it is determined that a winning has occurred, the security signal is externally output by setting a predetermined time (for example, 4 minutes) in the security signal information timer, as in step S128 in the switch normality / abnormality check process. You can do it.

  Further, for example, even when a communication error between the game control microcomputer 560 and the payout control microcomputer 370 is detected, it can be externally output as a security signal from the common connector CN8 of the terminal board 160. May be. In this case, for example, the game control microcomputer 560 determines that a communication error has occurred based on failure to receive a connection OK command or a prize ball number reception command (to be described later) from the payout control microcomputer 370, and the terminal The security signal may be externally output from the common connector CN8 of the board 160. Further, for example, the game control microcomputer 560 determines that a communication error has occurred based on the value of any error bit in the status register (not shown) of the serial communication circuit 505 being set, The security signal may be externally output from the common connector CN8 of the terminal board 160.

  In addition to the signal line and connector CN8 for the security signal, a signal line and connector dedicated to communication errors between the game control microcomputer 560 and the payout control microcomputer 370 may be provided on the terminal board 160. When a communication error between the game control microcomputer 560 and the payout control microcomputer 370 is detected, an external device such as a hall computer is transmitted via the terminal board 160 as a signal different from the security signal. May be output.

  In addition to the signal line for security signal output, detection of initialization processing, detection of abnormal winning at the first start winning opening 13, detection of abnormal winning at the second starting winning opening 14, and big winning opening A separate signal line is provided for detection of abnormal prize winning, detection of abnormal magnetic error, detection of abnormal radio wave error, and detection of communication error. From the terminal board 160, corresponding to each error together with the security signal. An external output signal may also be output to an external device such as a hall computer. With such a configuration, it is possible to recognize that an error has occurred by checking the security signal, and further, by checking the signal output for each type of error, the type of error can be determined on the amusement store side. Can be confirmed. Therefore, when an amusement store requires a confirmation of the type of error, an external output signal for each error type is provided separately from the security signal, so that an external output that better meets the needs of the amusement store can be provided. Can be done. On the other hand, in the case of a game shop that only requests confirmation that some kind of error has occurred, only the security signal out of the externally output signals is connected to an external device such as a hall computer. Check it.

  As described above, by providing the semiconductor relays PC1 to PC10 on the terminal board 160, signal input from the outside to the inside of the gaming machine can be prevented, and as a result, illegal acts can be reliably prevented. In the above example, the semiconductor relays PC1 to PC10 are provided on the terminal board 160. However, other relay elements such as a mechanical relay may be used instead of the semiconductor relays PC1 to PC10.

  Next, the operation of the gaming machine will be described. FIG. 9 is a flowchart showing the main processing executed by the CPU 56 of the game control microcomputer 560 in response to the start of power supply to the game machine and the reset signal to the game control microcomputer 560 becoming high level. It is. When the input level of the reset terminal to which the reset signal is input becomes a high level, the CPU 56 of the game control microcomputer 560 executes a security check process that is a process for confirming whether the contents of the program are valid. The main processing after step S1 is started. In the main process, the CPU 56 first performs necessary initial settings.

  In the initial setting process, the CPU 56 first sets the interrupt prohibition (step S1). Next, an interrupt mode for maskable interrupts is set (step S2), and a stack pointer designation address is set for the stack pointer (step S3). In step S2, the address synthesized from the value (1 byte) of the specific register (I register) of the game control microcomputer 560 and the interrupt vector (1 byte: least significant bit 0) output from the built-in device is Set to the mode indicating the interrupt address. When a maskable interrupt occurs, the CPU 56 automatically sets the interrupt disabled state and saves the contents of the program counter in the stack.

  Next, the CPU 56 starts outputting a connection signal to the payout control microcomputer 370 (step S4). When the CPU 56 starts outputting the connection signal in step S4, the CPU 56 sends a connection signal to the payout control microcomputer 370 unless the power supply of the gaming machine is stopped or the output becomes impossible due to some communication error. Output continuously.

  Next, the built-in device register is set (initialized) (step S5). By the processing in step S5, the CTC (counter / timer) and PIO (parallel input / output port) which are built-in devices (built-in peripheral circuits) are set (initialized).

  The game control microcomputer 560 used in this embodiment also incorporates an I / O port (PIO) and a timer / counter circuit (CTC) 504.

  Next, the CPU 56 sets the RAM 55 in an accessible state (step S6), and proceeds to a clear signal check process.

  Note that a software delay process for delaying the start timing of the game device control process (game control process) for controlling the progress of the game by software may be executed. By such software delay processing, the start timing of the game control processing can be delayed as compared with the case where the software delay processing is not executed. When the delay process is executed, a situation occurs in which the microcomputer of the other control board cannot receive the command transmitted from the game control board (main board 31) to the other control board (for example, the payout control board 37). Can be prevented.

  Next, the CPU 56 checks whether or not the clear switch is turned on (step S7). Note that the CPU 56 may confirm the state of the clear signal only once via the input port 0, but may confirm the state of the clear signal a plurality of times. For example, if it is confirmed that the state of the clear signal is an off state, a delay time of a predetermined time (for example, 0.1 seconds) is set, and then the state of the clear signal is reconfirmed. If it is confirmed that the clear signal is in the on state at that time, it is determined that the clear signal is in the on state. Further, at this time, if it is confirmed that the state of the clear signal is the off state, after a delay time of a predetermined time, the state of the clear signal may be confirmed again. Here, the number of reconfirmations is not limited to once or twice, but may be three or more times. It is also possible to check twice and check again when the check results do not match.

  If the clear switch is not turned on in step S7, whether or not data protection processing of the backup RAM area (for example, power supply stop processing such as addition of parity data) has been performed when power supply to the gaming machine is stopped Confirm (step S8). In this embodiment, when power supply is stopped, a process for protecting data in the backup RAM area is performed. When it is confirmed that such power supply stop processing has been performed, the CPU 56 determines that the power supply stop processing has been performed, that is, the control state at the time of power supply stop is stored. . When it is confirmed that the power supply stop process is not performed, the CPU 56 executes an initialization process.

  Whether or not the power supply stop process has been performed is determined by the value of the backup monitoring timer stored in the backup RAM area in the power supply stop process corresponding to the execution of the power supply stop process (for example, 2). ) Is confirmed by whether or not. Note that such a confirmation method is an example. For example, a flag indicating that the power supply stop process has been executed is set in the backup flag area in the power supply stop process, and the flag is set in step S8. If it is confirmed that the power supply is stopped, it may be determined that the power supply stop process has been performed.

  If it is determined that the control state at the time of stopping power supply is stored, the CPU 56 performs data check (parity check in this example) in the backup RAM area (step S9). In this embodiment, clear data (00) is set in the checksum data area, and the checksum calculation start address is set in the pointer. Also, the number of checksum calculations corresponding to the number of data to be checksum is set. Then, the exclusive OR of the contents of the checksum data area and the contents of the RAM area pointed to by the pointer is calculated. The calculation result is stored in the checksum data area, the pointer value is incremented by 1, and the checksum calculation count value is decremented by 1. The above processing is repeated until the value of the checksum calculation count becomes zero. When the value of the checksum calculation count becomes 0, the CPU 56 inverts the value of each bit of the contents of the checksum data area and uses the inverted data as the checksum.

  In the power supply stop process, a checksum is calculated by the same process as described above, and the checksum is stored in the backup RAM area. In step S9, the calculated checksum is compared with the stored checksum. When the power supply is stopped after an unexpected power failure or the like, the data in the backup RAM area should be saved, so the check result (comparison result) is normal (matched). That the check result is not normal means that the data in the backup RAM area may be different from the data when the power supply is stopped. In such a case, since the internal state cannot be returned to the state when the power supply is stopped, the initialization process (the process of steps S10 to S14) executed when the power is turned on, not when the power supply is stopped is stopped. Run.

  If the check result is normal, the CPU 56 performs a hot start process for resuming the game using the data stored in the RAM 55 that has been backed up (step S91). Further, the CPU 56 sets the head address of the backup command transmission table stored in the ROM 54 as a pointer (step S92), and proceeds to step S15. In addition, after setting in step S92, a backup command is transmitted after serial communication circuit setting processing in step S15a described later is performed.

  In the initialization process, the CPU 56 first performs a RAM clear process (step S10). Note that the predetermined data may be left as it is without initializing the entire area of the RAM 55. Further, the start address of the initialization setting table stored in the ROM 54 is set as a pointer (step S11), and the contents of the initialization setting table are sequentially set in the work area (step S12).

  By the processing of steps S11 and S12, for example, a normal symbol determination random number counter, a normal symbol determination buffer, a special symbol buffer, a special symbol process flag, a winning ball flag, a ball-out flag, and the like are selectively processed according to the control state. An initial value is set in a flag for performing the above. In addition, initial values (clear data) are also set in timers (start port information storage timer, winning information storage timer, security signal information timer, etc.) used to output external output signals described later.

  Further, the CPU 56 sets the start address of the initialization command transmission table stored in the ROM 54 as a pointer (step S13), and transmits an initialization command for initializing the sub board according to the contents to the sub board. Processing is executed (step S14). As an initialization command, a command indicating an initial symbol displayed on the effect display device 9, an initialization command to the payout control board 37, or the like can be used. After setting in step S13, an initialization command is transmitted after serial communication circuit setting processing in step S15a described later is performed.

  The CPU 56 sets a predetermined time (in this example, 30 seconds) in the security signal information timer (step S14a). The security signal information timer is a timer for measuring the ON time of the security signal output from the terminal board 160. In this embodiment, an initialization process is performed when the gaming machine is turned on by executing an information output process (see S31), which will be described later, based on the fact that a predetermined time is set in the security signal information timer in step S14a. Is executed, a security signal is externally output for a predetermined time (in this example, 30 seconds).

  Further, the CPU 56 executes a random number circuit setting process for initially setting the random number circuit 503 (step S15). In this case, the CPU 56 performs settings according to the random number circuit setting program stored in the ROM 54 in advance, so that the random number circuit 503 updates the random R value.

  Further, the CPU 56 executes a serial communication circuit setting process for initial setting of the serial communication circuit 505 (step S15a). In this case, the CPU 56 sets the data stored in the predetermined area of the ROM 54 in the serial communication circuit 505 in accordance with the serial communication circuit setting program, so that the serial communication circuit 505 performs serial communication with the payout control microcomputer. I do.

  When the serial communication circuit 505 is initialized, the CPU 56 initializes the priority of interrupt processing executed in response to the interrupt request from the serial communication circuit 505 (step S15b). In this case, the CPU 56 initializes the priority of interrupt processing by executing processing according to the interrupt priority setting program 557.

  For example, the CPU 56 initializes the priority of each interrupt process according to a predetermined interrupt process priority table including the default priority of each interrupt process. In this embodiment, the CPU 56 performs initialization according to the interrupt processing priority table so as to preferentially execute an interrupt process whose cause is the occurrence of a communication error in the serial communication circuit 505. In this case, for example, the CPU 56 sets an interrupt priority execution flag at the time of communication error indicating that priority is given to an interrupt process whose cause is an interrupt.

  In this embodiment, when a timer interrupt and an interrupt request from the serial communication circuit 505 are generated at the same time, the CPU 56 preferentially performs an interrupt process by the timer interrupt.

  In addition, the default priority of each interrupt process can be changed by the user. For example, the game control microcomputer 560 stores specification information for specifying an interrupt process set by a user (for example, a game machine manufacturer) in a predetermined storage area of the ROM 54 in advance. Then, the CPU 56 sets the priority of interrupt processing according to the designation information stored in a predetermined storage area of the ROM 54.

  In addition to steps S15 to S15b, a part of the setting process of the random number circuit 503 and the serial communication circuit 505 is also executed in the process of step S5. For example, in step S5, an initial value is set in the baud rate register, communication setting register, interrupt control register, and status register of the serial communication circuit 505 as the built-in device register.

  In the initialization process of the main process, a process of setting “250” as an initial value to a prize ball number counter used for detecting a prize ball shortage error or a prize ball excess error, which will be described later, is also executed. Note that the process of setting the initial value in the prize ball number counter may be executed, for example, in the hot start process of step S91 or the process of sequentially setting each initial value in the work area of step S12. It suffices if it is executed before the process is shifted.

  Then, the CPU 56 executes a timer interrupt setting process for setting a CTC register built in the game control microcomputer 560 so that a timer interrupt is periodically taken every predetermined time (for example, 4 ms) ( Step S16). That is, a value corresponding to, for example, 4 ms is set in a predetermined register (time constant register) as an initial value. In this embodiment, it is assumed that a timer interrupt is periodically taken every 4 ms.

  When the timer interrupt setting is completed, the CPU 56 first disables the interrupt (step S17), executes the initial value random number update process (step S18a) and the display random number update process (step S18b), The interrupt is permitted again (step S19). That is, the CPU 56 sets the interrupt disabled state when the initial value random number update process and the display random number update process are executed, and interrupts enable state when the initial value random number update process and the display random number update process are finished. To.

  The initial value random number update process is a process of updating the count value of the counter for generating the initial value random number. The initial value random number is a random number for determining the type of jackpot (for example, a jackpot symbol determining random number for determining a special symbol for generating a jackpot or whether to shift the gaming state to a probable state) Initial value of the count value such as a counter (determination random number generation counter) for generating a probability variation determining random number for generating, a normal random number for determining whether or not to generate a hit based on a normal symbol It is a random number for determining the value. A game control process described later (a process in which a game control microcomputer controls itself a game device such as an effect display device 9, a variable winning ball device 15, a ball payout device 97 provided in the gaming machine, or When the count value of the determination random number generation counter makes one round in a process of transmitting a command signal to cause another microcomputer to control, or a gaming apparatus control process), an initial value is set in the counter.

  The display random number is a random number for determining the display of the first special symbol display 8a and the second special symbol display 8b. In this embodiment, as a display random number, a random number for determining a variation pattern for determining a variation pattern of a special symbol, or a random number for determining a reach for determining whether or not to reach when a big hit is not generated, is used. Used. The display random number update process is a process for updating the count value of the counter for generating the display random number.

  In addition, when the display random number update process is executed, the interrupt disabled state is executed by the display random number update process and the initial value random number update process also in the timer interrupt process described later (that is, the timer This is because the same processing is also executed in steps S26 and S27 of the interrupt processing), so as to avoid competing with the processing in the timer interrupt processing. That is, if a timer interrupt is generated during the processing of steps S18a and S18b and the count value of the counter for generating the initial value random number and the display random number is updated during the timer interrupt processing, The continuity of values may be impaired. However, such an inconvenience does not occur if the interrupt is prohibited during the processing of steps S18a and S18b.

  When the interrupt-permitted state is set in step S19, the timer interrupt or interrupt request from the serial communication circuit 505 is permitted until the next processing in step S17 is executed and the interrupt-prohibited state is set. . When a timer interrupt occurs while the interrupt permission state is set, the CPU 56 of the game control microcomputer 560 executes a timer interrupt process to be described later. If an interrupt request is generated from the serial communication circuit 505 while the interrupt permission state is set, the CPU 56 of the game control microcomputer 560 causes each interrupt process (communication error interrupt process, reception time interrupt, Load processing, transmission completion interrupt processing). In this embodiment, priority is given to the interrupt process before the timer interrupt or the interrupt request is set to be permitted by executing step S15b before the loop process from step S17 to step S19. Processing for setting or changing the order is performed.

  Next, the hot start process in step S91 will be described. FIG. 10 is a flowchart illustrating an example of the hot start process. In the hot start process, the CPU 56 first sets the start address of the backup setting table stored in the ROM 54 as a pointer (step S9101), and sequentially stores the contents of the backup setting table in the work area (area in the RAM 55). Setting is performed (step S9102). The work area is backed up by a backup power source. Initialization data (for example, a prize ball process code, a prize ball process timer, a frame status display buffer, and a previous frame status display buffer, which will be described later) is set in the backup setting table. Has been. As a result of the processing in steps S9101 and S9102, the saved contents of the work area that should not be initialized remain as they are. The parts that should not be initialized include, for example, data indicating the gaming state before the power supply is stopped (special symbol process flag, etc.), the area where the output state of the output port is saved (output port buffer), unpaid prize balls This is the part where data indicating the number is set.

  The CPU 56 also outputs a high-probability output permission flag for permitting external output via the terminal board 160 of a high-probability signal indicating that the gaming state is controlled to a high probability state (probability change state). Is set (step S9103). Instead of unconditionally setting the high-accuracy medium output permission flag, it is first checked whether or not it is in a high-probability state (probability variation state) (specifically, the probability variation flag stored in the backup RAM). It is also possible to set the high-accuracy output permission flag on the condition that it is in a high-probability state (probability variation state). As such, at the start of power supply, the high-accuracy output permission flag may be set unconditionally, or the high-accuracy output flag may be set on the condition that it is in a high probability state (probability variation state). .

  In addition, the CPU 56 clears a prize information storage timer for measuring a prize signal output time, which will be described later (step S9104). In other words, in this embodiment, the value of the winning information storage timer is stored in the power-backed RAM 55 and is maintained for a predetermined time even when the power supply is stopped, but the process of step S9104 is executed. Cleared when power is restored. As described above, in this embodiment, in the common hot start process, the setting process of the high-accuracy output permission flag and the clearing process of the winning information storage timer can be executed, and the process routine is shared. The control burden on the game control microcomputer 560 is reduced.

  For example, in the backup setting table, a value for setting the high-accuracy output permission flag (for example, logical value “1”) or a value for clearing the winning information storage timer (for example, clear data “ 0 ") may also be set and step S9102 may be executed to turn on the high-accuracy output permission flag and clear the winning information storage timer. In this case, for example, based on the backup time setting table, the value of the high-accuracy medium output permission flag in the work area is set to the on state (for example, a logical value “1” is written), or a prize is awarded in the work area. Clear data may be written to the value of the information storage timer. By doing so, it is possible to use a single data table (setting table at the time of backup) to share the setting processing of the high-accuracy output permission flag and the clearing processing of the winning information storage timer, and the game control micro The control burden on the computer 560 can be further reduced.

  Next, the timer interrupt process will be described. FIG. 11 is a flowchart showing the timer interrupt process. When a timer interrupt occurs during execution of the main process, specifically, in a period during which interruption is permitted during execution of the loop process of steps S17 to S19, the CPU 56 of the game control microcomputer 560 A timer interrupt process that is activated in response to the occurrence of a timer interrupt is executed. In the timer interrupt process, the CPU 56 first executes a power-off process (power-off detection process) for detecting whether or not a power-off signal is output (whether the power-on signal is turned on) (step S20). Then, the CPU 56 detects switches such as the gate switch 32a, the first start port switch 13a, the second start port switch 14a, the winning confirmation switch 14b, the count switch 23, and the winning port switches 29a and 30a via the switch circuit 58. A signal is input and the input of each switch is detected (switch processing: step S21). Specifically, if the state of the input port for inputting the detection signal of each switch is ON, the value of the switch timer provided corresponding to each switch is incremented by one.

  Next, the CPU 56 has a first special symbol display 8a, a second special symbol display 8b, a normal symbol display 10, a first special symbol hold storage display 18a, a second special symbol hold storage display 18b, a normal symbol. A display control process for controlling the display of the on-hold storage display 41 is executed (step S22). For the first special symbol display 8a, the second special symbol display 8b, and the normal symbol display 10, a drive signal is output to each display according to the contents of the output buffer set in steps S36 and S37. Execute control to

  Next, the CPU 56 executes magnet sensor error notification processing for performing magnet sensor error notification based on the detection signal input from the magnet sensor (step S24).

  Next, the CPU 56 performs a process of updating the count value of each counter for generating a random number for determination such as a random number for determination per ordinary symbol used for game control (determination random number update process: step S25). Further, the CPU 56 performs a process of updating the count value of the counter for generating the initial value random number (initial value random number update process: step S26). Further, the CPU 56 performs a process of updating the count value of the counter for generating the display random number (display random number update process: step S27).

  Next, the CPU 56 performs special symbol process processing (step S28). In the special symbol process, the corresponding process is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to the gaming state. The value of the special symbol process flag is updated during each process according to the gaming state. Further, normal symbol process processing is performed (step S29). In the normal symbol process, the corresponding process is selected and executed according to the normal symbol process flag for controlling the display state of the normal symbol display 10 in a predetermined order. The value of the normal symbol process flag is updated during each process according to the gaming state.

  Next, the CPU 56 performs a process of sending an effect control command related to the effect symbol synchronized with the variation of the special symbol to the effect control microcomputer 100 (effect symbol command control process: step S30). It should be noted that the fact that the variation of the effect symbol is synchronized with the variation of the special symbol means that the variation time (variable display period) is the same.

  Next, the CPU 56 outputs, for example, data such as a symbol determination number 1 signal, a start opening signal, a jackpot signal 1-3, a time reduction signal, a winning signal, a security signal, and a high accuracy signal supplied to the hall management computer. Information output processing is performed (step S31).

  Next, the CPU 56 executes processing for transmitting / receiving (input / output) signals to / from the payout control microcomputer 370 via the serial communication circuit 505, and when a winning occurs, detection of the winning opening switches 29a, 30a, etc. Prize ball processing is performed for setting the number of prize balls based on the signal (step S32). In this embodiment, data indicating the number of winning balls is obtained by changing the lower 4 bits of the winning ball number command in response to detection of winning based on the winning opening switch 29a, 30a being turned on. The set prize ball number command is output to the payout control microcomputer 370 via the serial communication circuit 505. The payout control microcomputer 370 mounted on the payout control board 37 drives the ball payout device 97 in response to receiving a prize ball number command in which data indicating the number of prize balls is set.

  In addition, a test terminal process, which is a process for outputting a test signal for enabling the control state of the gaming machine to be confirmed outside the gaming machine, is executed (step S33). In this embodiment, a RAM area (output port buffer) corresponding to the output state of the output port is provided. However, the CPU 56 relates to the connection signal and the contents related to the solenoid in the RAM area of the output port 0. Is output to the output port (step S34: output processing). And CPU56 performs the memory | storage process which checks the increase / decrease in a pending | holding memory | storage number (step S35).

  Further, the CPU 56 performs special symbol display control processing for setting special symbol display control data for effect display of the special symbol in the output buffer for setting the special symbol display control data according to the value of the special symbol process flag ( Step S36). Further, the CPU 56 performs a normal symbol display control process for setting normal symbol display control data for effect display of the normal symbol in an output buffer for setting the normal symbol display control data according to the value of the normal symbol process flag ( Step S37).

  Next, the CPU 56 performs a status display lamp display process for setting status display control data for displaying each status display lamp in an output buffer for setting the status display control data (step S38). In this case, when the gaming state is the short time state, the state display control data for displaying the state indicator lamp indicating the short time state is set in the output buffer. When the gaming state is also controlled to a high probability state (for example, a probability variation state), state display control data for displaying a state indicator lamp indicating the high probability state is set in the output buffer. You may do it.

  Next, the CPU 56 performs a frame state output process for transmitting a frame state display command in which information indicating the error state of the gaming machine is set to the effect control microcomputer 100 in order to display the error state of the gaming machine. Execute (Step S39).

  Thereafter, the interrupt permission state is set (step S40), and the process ends.

  Next, the prize ball process (step S32) in the main process will be described. First, payout control signals (connection signals, prize ball information) and payout control commands transmitted and received between the main board 31 and the payout control board 37 will be described.

  FIG. 12 is an explanatory diagram showing an example of the content of a control signal output from the game control means to the payout control means. In this embodiment, a connection signal and prize ball information are transmitted and received as control signals between the main board 31 and the payout control board 37 in order to perform various controls relating to payout control and the like. As shown in FIG. 12, the connection signal is output when the main board 31 rises (when the game control means starts the game control process), and notifies the payout control board 37 that the main board 31 has risen. This is a signal (connection signal for the main board 31). The connection signal indicates that the prize ball can be paid out. The connection signal is output via the I / O port 57 and the output circuit 67A of the game control microcomputer 560, and is used for payout control via the input circuit 373A and the I / O port 372e of the payout control microcomputer 370. It is input to the microcomputer 370. The connection signal is 1-bit data and is transmitted through one signal line. Note that the connection signal is ready to be output by setting an initial value to the bit corresponding to the connection signal of the output port 0 by the process of step S4 executed when the power is turned on (specifically, in step S34). Although it is output by processing, it may be output at the timing of step S4). The prize ball information is information for notifying the main board 31 that ten prize balls have been detected each time ten prize balls are paid out on the payout control board 37 side. . The prize ball information is output via the I / O port 372a and the output circuit 373B of the payout control microcomputer 370, and the game control is performed via the input circuit 67B and the I / O port 57 of the game control microcomputer 560. To the microcomputer 560. The prize ball information is 1-bit data and is transmitted through one signal line.

  Similarly to the game control microcomputer 560, the payout control microcomputer 370 includes a serial communication circuit 380. Various payout control commands are transmitted and received between the serial communication circuit 505 built in the game control microcomputer 560 and the serial communication circuit 380 built in the payout control microcomputer 370. The configuration and function of the serial communication circuit 380 built in the payout control microcomputer 370 are the same as the configuration and function of the serial communication circuit 505 built in the game control microcomputer 560.

  FIG. 13 is an explanatory diagram showing an example of the contents of control commands transmitted / received between the game control means and the payout control means. In this embodiment, various payout control commands are transmitted and received between the microcomputers of the main board 31 and the payout control board 37 in order to perform various controls related to payout control and the like.

  As described above, the payout control command is composed of 8-bit data (binary 8-digit data), and is output as a control command indicating a predetermined content depending on the content of the set 8-bit data.

  The connection confirmation command is sent from the game control microcomputer 560 at regular intervals (1 s) in order to confirm whether or not the connection state between the game control microcomputer 560 and the payout control microcomputer 370 is normal. Control command to be sent. The data content of the connection confirmation command is “A0 (H)”, that is, “10100000”.

  The connection OK command is a control command for notifying that the connection state between the game control microcomputer 560 and the payout control microcomputer 370 is normal, and the payout control microcomputer 370 issues a connection confirmation command. Is a control command that is transmitted as a response signal in response to the reception of. The data content of the connection OK command is “8x (H)”, that is, “1000xxxx”. Here, with respect to “xxxx” in the second byte of the connection OK command, as shown in FIG. 14, a prize ball error (a prize ball payout operation based on winning or a ball lending operation based on a ball rental request cannot be performed normally). An abnormal state that has become a state: Specifically, when a main control unconnected error, a payout switch error detection error 1, a payout switch error detection error 2, a payout case error, or a main control communication error (described later) occurs “1” is set to “x” of the first bit (bit 0). When a full tank error occurs, “1” is set to “x” of the second bit (bit 1). When a ball break error occurs, “1” is set to “x” of the third bit (bit 2). In addition, when a payout number abnormality error occurs when the cumulative value of the number of payouts of prize balls and rental balls, which will be described later, reaches a predetermined value (for example, 2000), the fourth bit (bit 3) “1” is set to “x” of In this way, during the confirmation of the connection between the game control microcomputer 560 and the payout control microcomputer 370, the occurrence of a predetermined error in the payout control microcomputer 370 is detected. 560 can be notified. In the example shown in FIG. 14, the connection OK command is set to a value indicating a payout error (award ball error, full tank error, out of ball error, payout number error error) as a control state. A control state other than an error may be set in the connection OK command. For example, the payout control microcomputer 370 sets a value indicating that a prize ball payout operation or a lending ball payout operation is in a control state to the connection OK command, and transmits it to the game control microcomputer 560. You may make it do.

  The award ball number command is a control command for notifying the number (0 to 15) of game balls for which a payout request is made, and is a control command transmitted by the game control microcomputer 560 based on the occurrence of a win. . The content of the prize ball number command data is “5x (H)”, that is, “0101xxx”. In this embodiment, when a game ball is detected by the first start port switch 13a or the second start port switch 14a, three prize balls are paid out, and the game ball is detected by one of the winning port switches 29a and 30a. Then, 10 prize balls are paid out. When a game ball is detected by the count switch 23, 15 prize balls are paid out. Therefore, when a game ball is detected by the first start port switch 13a or the second start port switch 14a, a prize ball number command “01010011” for notifying three prize balls is transmitted, and the prize opening switches 29a, 29a, When a game ball is detected in any of 30a, a prize ball number command “01011010” for notifying 10 prize balls is transmitted, and when a game ball is detected by the count switch 23, the number of prize balls is 15 A prize ball number command “01011111” for notifying the player is transmitted.

  The prize ball number acceptance command is a control command for notifying that the prize ball number specified by the prize ball quantity command has been accepted, and the payout control microcomputer 370 responds upon receipt of the prize ball quantity command. It is a control command transmitted as a signal. The content of the prize ball number reception command data is “70 (H)”, that is, “01110000”.

  The award ball end command is a control command indicating that the award ball operation (award ball payout operation) has ended, and is a control command that the payout control microcomputer 370 transmits based on the end of the award ball operation. The data content of the winning ball end command is “50 (H)”, that is, “01010000”.

  The command for preparing a prize ball is a control command for notifying that a prize ball movement has not been completed due to a long time for a prize ball movement, a rental ball movement or a predetermined error. is there. The contents of the data of the winning ball preparation command are “4x (H)”, that is, “0100xxxx”. Here, with respect to “xxxx” of the second byte of the command for preparing a prize ball, as shown in FIG. 14, when a prize ball error occurs, “1” is set to “x” of the first bit (bit 0). Is set. When a full tank error occurs, “1” is set to “x” of the second bit (bit 1). When a ball break error occurs, “1” is set to “x” of the third bit (bit 2). In addition, when a payout number abnormality error occurs when the cumulative value of the number of payouts of prize balls and rental balls, which will be described later, reaches a predetermined value (for example, 2000), the fourth bit (bit 3) “1” is set to “x” of In this way, the payout control microcomputer 370 receives a prize ball when the prize ball operation takes a long time, or during a lending ball operation or when a predetermined error occurs during the execution of the prize ball operation. The game control microcomputer 560 can be notified that the operation has not ended, and the contents of the error can also be notified to the game control microcomputer 560. As in the case of the connection OK command, the award ball preparation command notifies that a predetermined error has occurred by changing the contents of the lower 4 bits in accordance with the error state (by changing the predetermined bits). Note that the command for preparing a prize ball is not only in a state where an error occurs and the prize ball operation cannot be executed, but also in a state where the prize ball payout operation cannot be started immediately because the ball rental operation is in progress, This command (signal) is output even in the running state (the state in which the payout operation for the number of prize balls specified by the prize ball number command has not been completed). The example shown in FIG. 14 shows a case where a value indicating a payout error (prize ball error, full tank error, out of ball error, payout number error error) is set as a control state in the command for preparing a prize ball. However, a control state other than an error may be set in the connection OK command. For example, the payout control microcomputer 370 sets a value indicating that the prize ball payout operation or the lending ball payout operation is in the control state in the award ball preparation command, and the game control microcomputer 560. You may make it transmit to.

  In this embodiment, the connection confirmation signal is realized by a connection confirmation command of the payout control command, the response signal is realized by a connection OK command, the payout number signal is realized by a prize ball number command, and the acceptance signal is It is realized by a prize ball number acceptance command, a payout end signal is realized by a prize ball end command, and a payout signal is realized by a prize ball preparation command.

  FIG. 15 is a block diagram showing signal lines and the like used for transmission / reception of the control signal shown in FIG. 12 and the control command shown in FIG. As shown in FIG. 15, the connection signal is output by the game control microcomputer 560 via the output circuit 67A, and is input to the payout control microcomputer 370 via the input circuit 373A. The prize ball information is output by the payout control microcomputer 370 via the output circuit 373B, and input to the game control microcomputer 560 via the input circuit 67B. A prize ball signal 1 and a gaming machine error state signal, which will be described later, are also output by the payout control microcomputer 370 via the output circuit 373B and input to the game control microcomputer 560 via the input circuit 67B. May be. The door opening signal may also be output by the payout control microcomputer 370 via the output circuit 373B and input to the game control microcomputer 560 via the input circuit 67B.

  Of the control commands, the connection confirmation command and the winning ball number command are output from the serial circuit 505 built in the game control microcomputer 560 and input to the serial circuit 380 built in the payout control microcomputer 370. Of the control commands, the connection OK command, the prize ball number reception command, the prize ball end command, and the prize ball preparation command are output from the serial circuit 380 built in the payout control microcomputer 370, and the game control microcomputer 560 It is input to the built-in serial circuit 505. In FIG. 15, two signal lines (signal lines for sending commands from the game control microcomputer 560 to the payout control microcomputer 370 side and payout control microcomputers) are used as signal lines for serial communication. 370 shows a signal line for transmitting a command from 370 to the game control microcomputer 560 side. A signal line for transmitting a command from the game control microcomputer 560 to the payout control microcomputer 370 side, and a signal line for transmitting a command from the payout control microcomputer 370 to the game control microcomputer 560 side. May be configured as separate signal lines.

  Next, the prize ball process (step S32) will be described. FIG. 16 is a flowchart illustrating an example of the prize ball processing in step S32. In the prize ball process, the game control microcomputer 560 (specifically, the CPU 56), the prize ball command output counter addition process (step S501), the prize ball control process (step S502), and the prize ball counter subtraction process (step S503). ).

  In the prize ball command output counter addition process, a prize ball number table shown in FIG. 17 is used. The prize ball number table is set in the ROM 54. The number of processes (in this example, “5”) is set to the start address of the prize ball number table, and then the lower address of the switch-on buffer, the lower address of the prize ball command output counter, the switch input bit designation value, The prize ball number data for designating the number of prize balls is sequentially set. The prize ball command output counter is a counter that counts the number of prizes received in the prize opening, and is set in the ROM 54, for example. The game control microcomputer 560 includes a corresponding prize ball command output counter for each number of prize balls (0 to 15). In this embodiment, the game control microcomputer 560 includes a prize ball command output counter 1 corresponding to the prize ball number “15” and prize ball command output counters 2, 3 (2) corresponding to the prize ball number “10”. Corresponding to the three normal winning openings 29 and 30) and prize ball command output counters 4 and 5 corresponding to the number of prize balls “3”. Each prize ball command output counter is counted up by prize ball command output counter addition processing, as will be described later. If the prize ball command output counter 1 set in the prize ball number table is not 0, the CPU 56 indicates the prize ball number (15) based on the prize ball number data designating the prize ball number (15). The data is set in the lower 4 bits of the winning ball number command, and the set winning ball number command is transmitted to the payout control microcomputer 370. The CPU 56 determines the number of prize balls (10) if the value of the prize ball command output counter 1 set in the prize ball number table is 0 and the value of the prize ball command output counters 2 and 3 is not 0. Data indicating the number of winning balls (10) is set in the lower 4 bits of the winning ball number command, and the set winning ball number command is transmitted to the payout control microcomputer 370. To do. Further, the CPU 56 must set the value of the prize ball command output counter 1 and the prize ball command output counters 2 and 3 set in the prize ball number table to 0, and the value of the prize ball command output counters 4 and 5 must be 0. For example, data indicating the number of winning balls (3) is set in the lower 4 bits of the winning ball number command based on the winning ball number data designating the number of winning balls (3), and the set winning ball number command is set. Is sent to the payout control microcomputer 370. In FIG. 17, the switch-on buffer 1 corresponds to the input port 0, and the switch-on buffer 2 corresponds to the input port 2.

  18 and 19 are flowcharts showing the prize ball command output counter addition processing in step S501. In the prize ball command output counter addition process, the game control microcomputer 560 (specifically, the CPU 56) sets the start address of the prize ball number table as a pointer (step S5101). Then, the data at the address pointed to by the pointer (in this case, the number of processes) is loaded (step S5102).

  Next, the CPU 56 increments the pointer value by 1 (step S5103), loads the lower address of the switch-on buffer pointed to by the pointer into the lower byte of the pointer buffer (step S5104), and loads the switch-on buffer pointed by the pointer buffer into the register. (Step S5105). Next, the CPU 56 increments the value of the pointer by 1 (step S5106), and loads the lower address of the prize ball command output counter pointed to by the pointer into the lower byte of the pointer buffer (step S5107). Next, the CPU 56 increments the value of the pointer by 1 (step S5108), and calculates the logical product of the contents of the switch-on buffer loaded into the register and the switch winning bit designation value pointed to by the pointer (step S5109). Then, the CPU 56 increases the value of the pointer by 1 (step S5110). When the pointer value is incremented by 1 in step S5110, the pointer value indicates the address where the prize ball number data in the prize ball number table is stored.

  Next, if the calculation result in step S5109 is 0 (Y in step S5111), that is, if the detection signal of the switch to be inspected is not in the ON state, the CPU 56 decreases the number of processes by 1 (step S5128). If NO is 0, the process is terminated. If the number of processes is not 0, the process returns to step S5103 (step S5129).

  If the calculation result in step S5109 is not 0 (N in step S5111), that is, if the detection signal of the switch to be inspected is on, the CPU 56 performs processing for exchanging the pointer buffer value and the pointer value. This is performed (step S5112). In this case, the value of the pointer indicates the address where the prize ball number data in the prize ball number table is stored by executing the process of step S5110, and the value of the pointer buffer is the value of step S5107. As a result, the lower address of the prize ball command output counter has been loaded, so that the value of the pointer buffer becomes the number of prize balls by executing the exchange process in step S5112. The table indicates the address where the prize ball number data is stored, and the value of the pointer indicates the lower address of the prize ball command output counter.

  Next, the CPU 56 adds 1 to the value of the prize ball command output counter pointed to by the pointer (step S5113). However, when a carry occurs in the value of the prize ball command output counter as a result of the addition, the CPU 56 subtracts 1 from the value of the prize ball command output counter and restores the original value (steps S5114 and S5115). Then, the process proceeds to step S5116. In steps S5113 to S5115, the CPU 56 first loads the value of the prize ball command output counter into the register, adds 1 to the value of the register, and that no carry has occurred in the value of the register after the addition. After confirming, the value after addition may be stored in the prize ball command output counter. By doing so, it is possible to prevent waste of adding and subtracting the value of the prize ball command output counter again.

  Next, the CPU 56 counts the cumulative value of the expected number of winning balls based on the detection of winning in any one of the winning winning openings (start winning winning openings 13, 14, large winning opening, ordinary winning openings 29, 30). The lower address of the winning counter is loaded into the lower byte of the pointer (step S5116). Next, the CPU 56 loads prize ball number data pointed to by the pointer buffer (step S5117). Next, the CPU 56 reads the value of the winning counter pointed by the pointer, and adds the read value to the number of winning balls indicated by the winning ball number data loaded in step S5117 (step S5118). By executing the calculation in step S5118, the cumulative value of the expected number of winning balls obtained by adding the number of winning balls for the newly generated winning ball is obtained. Then, the CPU 56 subtracts 1 from the value of the pointer (step S5119).

  In this embodiment, in the ROM 54, the winning information storage counter is set in the area of the address immediately before the area where the winning counter is set. The winning information storage counter is a counter for counting the number of possible output of winning signals. For example, if the value of the winning information storage counter is 1, a winning signal is output once in an information output process described later. If the value of the winning information storage counter is 2, control for outputting the winning signal twice is performed in the information output process described later. In this embodiment, the pointer value is decremented by 1 in step S5119, so that the pointer value indicates the lower address of the prize ball information output counter.

  Next, the CPU 56 checks whether or not the cumulative value of the expected number of winning balls calculated in step S5118 is equal to or greater than a predetermined winning output determination value (10 in this example) (step S5120). If the cumulative value of the planned number of winning balls is equal to or greater than a predetermined winning output determination value (10 in this example), the CPU 56 determines a predetermined winning output determination value from the cumulative value of the planned number of winning balls calculated in step S5118. (10 in this example) corresponding to is subtracted (step S5121). Then, the CPU 56 adds 1 to the value of the winning information storage counter pointed to by the pointer (step S5122). However, when a carry occurs in the value of the winning information storage counter as a result of the addition, the CPU 56 decrements the value of the winning information storage counter by 1 and restores the original value (steps S5123 and S5124). Then, the process returns to step S5120. In steps S5122 to S5124, the CPU 56 first loads the value of the winning information storage counter into the register, adds 1 to the register value, and confirms that no carry has occurred in the register value after the addition. After confirmation, the value after addition may be stored in the winning information storage counter. By doing so, it is possible to prevent wasteful re-subtraction after adding the value of the winning information storage counter.

  On the other hand, if the cumulative value of the estimated number of winning balls calculated in step S5118 is not equal to or greater than a predetermined winning output determination value (10 in this example) (that is, less than 9), the process proceeds to step S5125.

  By executing the processing of steps S5120 to S5124, in this embodiment, every time a predetermined number of payout conditions are satisfied (every time 10 winning balls are won), the winning information storage counter The value is incremented by 1, and a winning signal is output to the outside by an information output process described later.

  In addition, the cumulative value of the planned number of prize balls calculated in step S5118 may be 20 or more. For example, if the count value of the winning counter is 9, and a winning to the big winning opening occurs and 15 new winning balls are generated, the cumulative value of the expected number of winning balls in step S5118. Will be required as 24. In this case, it is determined as Y in step S5120, and the value of the winning information storage counter is incremented by 1 in step S5122 (in this case, the cumulative value of the expected number of winning balls is subtracted by 10 in the process of step S5121 to become 14). ) Once again, it is determined as Y in step S5120, the value of the prize information storage counter is incremented by 1 in step S5122, and the value of the prize information storage counter is incremented by 2 while one prize ball command output counter addition process is executed. Will be.

  In this embodiment, in the prize ball command output counter addition process during the prize ball process, whether or not the cumulative value of the planned number of prize balls is 10 or more by executing the processes of steps S5120 to S5124. It is shown that the control is performed so that the winning information storage counter is added and the winning signal is output, but the winning signal output processing method is limited to that shown in this embodiment. I can't. For example, in the prize ball command output counter addition process, only the prize counter addition process is performed. In the information output process in step S31, it is determined whether the value of the prize counter is 10 or more. If there is, it may be controlled to output a winning signal. In this case, similarly to the above, if the value of the winning counter is 20 or more, in the information output process, the process of determining whether or not the winning counter value is 10 or more is repeatedly executed, and the value of the winning information storage counter is determined. May be processed so that the winning signal can be output twice.

  Further, in this embodiment, a case is shown in which the processing of steps S5120 to S5124 is repeatedly executed until the cumulative value of the number of prize balls calculated in step S5118 is less than 10, but step S5119 is executed, for example. Later, first, it may be confirmed whether or not the cumulative value of the estimated number of prize balls calculated in step S5118 is 20 or more. If it is 20 or more, 20 is subtracted from the cumulative value of the estimated number of winning balls calculated in step S5118 and 2 is added to the value of the winning information storage counter, and the same processing as in steps S5123 and S5124 is executed. You may make it transfer to step S5125 later. In this case, if the cumulative value of the planned number of prize balls calculated in step S5118 is not 20 or more, it is next checked whether the cumulative value of the planned number of prize balls calculated in step S5118 is 10 or more. If it is equal to or greater than 10, the same processing as in steps S5121 and S5122 is executed, and 10 is subtracted from the accumulated value of the expected number of winning balls calculated in step S5118 and the value of the winning information storage counter is incremented by 1. Further, after performing the same processing as steps S5123 and S5124, the process may proceed to step S5125.

  In addition, for example, in this embodiment, after the winning information storage counter is updated, a winning signal is externally output based on the value of the winning information storage counter in the information output processing described later. Instead of using the winning information storage counter, if it is determined in step S5120 that the accumulated value is 10 or more, the winning signal external output processing may be immediately performed within the winning ball command output counter addition processing. . In this case, in this embodiment, the result accumulated value of the calculation in step S5118 is 10 or more and less than 20, and it is necessary to output the winning signal once, and the result accumulated value of the calculation in step S5118 is 20 or more (this In the embodiment, there are two cases where it is necessary to output the winning signal twice, never exceeding 30). Therefore, for example, as a table for outputting a winning signal, a table for outputting a winning signal once (a table in which the ON time and OFF time of one winning signal are set) and a winning signal are continuously provided. A table for outputting twice (a table in which the on time and off time of the winning signal for two times are set) may be prepared. Then, if the calculated accumulated value is 10 or more and less than 20, a control for outputting the winning signal once outside is performed in the winning ball command output counter addition process using the table for outputting the winning signal once. If the calculated cumulative value is 20 or more, a table for outputting the winning signal twice is used, and the control for outputting the winning signal twice continuously in the winning ball command output counter addition process is performed. May be.

  If the cumulative value calculated in step S5118 exceeds 20, as described above, the winning signal is continuously generated in the winning ball command output counter adding process using the table for outputting the winning signal twice. In the prize ball command output counter addition process, the determination process of step S5120 is repeated until the calculation result becomes less than 10, and the prize signal is externally output twice continuously. It may be. Also, for example, when the winning ball command output counter addition process executed within one timer interrupt is performed so that a winning signal is output only once, and when the next timer interrupt is executed, the winning ball command output counter addition process is executed. The next winning signal may be externally output based on the accumulated value being 10 or more.

  Next, in step S5125, the CPU 56 adds 1 to the pointer value (therefore, the pointer value returns to the state indicating the lower address of the winning counter). Next, the CPU 56 stores the calculation result of the cumulative value of the expected number of winning balls in the winning counter indicated by the pointer (step S5126). In this case, if the process proceeds to step S5125 and subsequent steps without being determined as Y once in step S5120, the cumulative value of the expected number of winning balls obtained in step S5118 is stored as it is in the winning counter. become. If it is determined as Y in step S5120 and the processing from step S5121 is executed, the cumulative value of the planned number of winning balls after subtraction is stored in the winning counter in step S5121. As a result of the determination process in step S5120 and the subtraction process in step S5121, the value less than 10 is always stored in the winning counter in step S5126.

  Next, the CPU 56 performs a process of exchanging the pointer buffer value and the pointer value (step S5127). In this case, since the address at which the winning ball number data in the winning ball number table is stored is saved in the pointer buffer by executing the process of step S5112, the processing of step S5127 is executed. The pointer value is returned to the state indicating the address where the prize ball number data in the prize ball number table is stored again.

  Then, the CPU 56 reduces the number of processes by 1 (step S5128), ends the process if the number of processes is 0, and returns to step S5103 if the number of processes is not 0 (step S5129).

  FIG. 20 is a flowchart showing the prize ball control process in step S502. In the prize ball control process, the game control microcomputer 560 (specifically, the CPU 56) executes any one of steps S521 to S525 in accordance with the value of the prize ball process code.

  FIG. 21 is a flowchart showing the prize ball transmission process 1 (step S521) executed when the value of the prize ball process code is zero. In the prize ball transmission process 1, the CPU 56 performs control to transmit a connection confirmation command to the payout control microcomputer (step S5211). Specifically, the CPU 56 performs processing for outputting a connection confirmation command to the transmission data register of the serial communication circuit 505. Then, the CPU 56 sets a value “1” indicating a prize ball connection confirmation process in the prize ball process code (step S5212), and sets a connection confirmation time 2 (for example, 10 seconds) in the prize ball process timer (step S5213). . If a connection OK command is not received even after 10 seconds have elapsed after transmitting the connection confirmation command based on the connection confirmation time 2 set in step S5213, the connection confirmation command is transmitted thereafter. It is controlled so as to extend the interval to 10 seconds. Specifically, the prize ball process timer set in step S5213 is measured in the processing of steps S5227 and S5229, which will be described later, 10 seconds elapses without receiving a connection OK command, and Y in step S5227. When the determination is made, the process returns to the prize ball transmission process 1 and the next connection confirmation command is transmitted (see steps S5228 and S5211).

  The prize ball process timer is set to a value (for example, an integral multiple of the interrupt period) in consideration of the interrupt period in the timer interrupt process executed by the game control microcomputer 560. This is because other timers used in the game control microcomputer 560, the payout control microcomputer 370, and the effect control microcomputer 100 (for example, a main control communication control timer, a payout control timer, a re-payout waiting timer, The same applies to the prize ball information output timer and prize ball signal 1 output timer.

  FIG. 22 is a flowchart showing a prize ball connection confirmation process (step S522) executed when the value of the prize ball process code is 1. In the winning ball connection confirmation process, the CPU 56 first confirms whether there is data in the reception data register of the serial communication circuit 505 (step S5221). Specifically, the CPU 56 may confirm the value of the status register of the serial communication circuit 505. If there is no data in the reception data register (that is, if no command is received), the process proceeds to step S5227.

  If there is data in the reception data register (that is, if a command is received), the CPU 56 checks whether an error has occurred in the serial communication circuit 505 (step S5222). Specifically, the CPU 56 may confirm whether any error bit value is set in the status register of the serial communication circuit 505. If an error has occurred, the process proceeds to step S5227.

  If no error has occurred in the serial communication circuit 505, the CPU 56 reads the command from the reception data register of the serial communication circuit 505, and checks whether the received command is a connection OK command (step S5223). If it is not a connection OK command, the process proceeds to step S5227.

  If the connection OK command has been received, the CPU 56 stores the error information (see FIG. 14) set in the lower 4 bits of the connection OK command in the frame state display buffer (step S5224).

  Next, the CPU 56 sets a value “2” indicating the prize ball transmission process 2 in the prize ball process code (step S5225), and sets a connection confirmation time 1 (for example, 1 second) in the prize ball process timer (step S5226). . Note that, based on the connection confirmation time 1 set in step S5226, control is performed to repeatedly transmit the next connection confirmation command every time one second elapses after reception of the connection OK command. Specifically, the prize ball process timer set in step S5226 is measured in the processing of steps S52313 and S52315, which will be described later, and one second elapses without sending a prize ball number command, and Y in step S52313. If it is determined, the process returns to the prize ball transmission process 1 and the next connection confirmation command is transmitted (see steps S52314 and S5211).

  In step S5227, the CPU 56 checks whether or not the prize ball process timer has timed out. If the winning ball process timer has timed out (that is, if the connection OK command has not been received even after 10 seconds have passed after sending the connection confirmation command), the CPU 56 sends a winning ball to the winning ball process code. A value “0” indicating the process 1 is set (step S5228), and the process ends. If the winning ball process timer has not timed out, the CPU 56 subtracts 1 from the value of the winning ball process timer (step S5229).

  FIG. 23 is a flowchart showing the prize ball transmission process 2 (step S523) executed when the value of the prize ball process code is 2. In the prize ball transmission process 2, the CPU 56 checks whether or not any prize ball command output counters 1 to 5 have a count value other than 0 (step S52301). If there is no count value other than 0, the process proceeds to step S52313.

  If any of the prize ball command output counters 1 to 5 has a count value other than 0 (that is, if the count value is 1 or more), the CPU 56 loads the contents of the frame state display buffer. Then, it is confirmed whether or not the content of the frame state display buffer is 0 (step S5232). If the content of the frame state display buffer is not 0, the processing is terminated as it is. By performing such control, when the connection OK command in which the error information is set is received and the payout control microcomputer 370 is controlled to be in the payout stop state, the processing from step S52303 is not performed. Then, control is made so that transmission of the prize ball number command is suspended. If the count value is not 0 in the prize ball command output counters 1 to 5 without executing the process in step S52302, the process proceeds to step S52303 and the prize ball number command is output. May be.

  If the content of the frame state display buffer is 0 (that is, if no error relating to payout has occurred), the payout control CPU 371 determines the number of prize balls corresponding to the prize ball command output counter whose count value is not 0. It is set in the buffer (step S52303). Specifically, in step S52301, the CPU 56 first checks whether or not the count value of the prize ball command output counter 1 is zero. If the count value of the prize ball command output counter 1 is 1 or more, in step S52303, the CPU 56 sets 15 prize balls in the number buffer. In step S52301, if the count value of the prize ball command output counter 1 is 0, the CPU 56 checks whether the count values of the prize ball command output counters 2 and 3 are 0 or not. If the count value of the prize ball command output counters 2 and 3 is 1 or more, the CPU 56 sets the number of prize balls in the number buffer in step S52303. In step S52301, if the count values of the prize ball command output counters 2 and 3 are also 0, the CPU 56 checks whether the count values of the prize ball command output counters 4 and 5 are 0 or not. . If the count value of the prize ball command output counters 4 and 5 is 1 or more, in step S52303, the CPU 56 sets the number of prize balls in the number buffer.

  In addition, the CPU 56 sets the number of prize balls corresponding to the prize ball command output counter whose count value is not 0 in the prize ball number command (step S52304), and uses the prize ball number command in which the number of prize balls is set for payout control. Control to transmit to the microcomputer 370 is performed (step S52305). Specifically, the CPU 56 performs processing for outputting a prize ball number command in which the number of prize balls is set to the transmission data register of the serial communication circuit 505.

  By executing the processing of steps S52301 and S52305, in this embodiment, if there is a prize ball command output counter whose count value is not 0 regardless of the connection confirmation command transmission timing (ie, If there is a prize ball number storage and a predetermined payout condition is established), a prize ball number command is transmitted to the payout control microcomputer 370.

  Then, the CPU 56 sets a value “3” indicating the prize ball reception confirmation process in the prize ball process code (step S52306), and sets a connection confirmation time 2 (for example, 10 seconds) in the prize ball process timer (step S52307). . It should be noted that, based on the connection confirmation time 2 set in step S52307, after transmitting the prize ball number command, it is confirmed whether a prize ball number acceptance command or a prize ball preparation command is received within 10 seconds. . Specifically, the prize ball process timer set in step S52307 is measured in the processing of steps S52409 and S52411 described later, and 10 seconds have elapsed without receiving a prize ball number acceptance command or a prize ball preparation command. If it is timed out and it is determined as Y in step S52409, the process returns to the prize ball transmission process 1 and the next connection confirmation command is transmitted (see steps S52410 and S5211).

  If the prize ball number command is transmitted in step S52305 by executing the process of step S52306, the process proceeds to the prize ball reception confirmation process without returning to the prize ball transmission process 1 including the connection confirmation command transmission process. Is done. Therefore, in this embodiment, the process of repeatedly transmitting the connection confirmation command is executed every predetermined time (for example, 1 second) until the prize ball number command is transmitted, but the prize ball number command is transmitted. In particular, the control for transmitting the connection confirmation command is stopped (more specifically, after the prize ball number command is transmitted, the process proceeds to the prize ball end confirmation process by receiving the prize ball number acceptance command described later. Connection (without returning to the prize ball transmission process 1) by repeating the prize ball receipt confirmation process (see steps S52403 to S52405) or by receiving the prize ball preparation command (see steps S52406 to S52408). In this case, the control for sending the confirmation command is stopped. Unless an abnormal state occurs in which no payout control command is returned, after the prize ball number command is transmitted, the game control microcomputer 560 is connected until the prize ball payout operation is finished and the prize ball end command is received. A confirmation command is never sent.

  Next, the CPU 56 adds the value of the number buffer set in step S52303 to the prize ball number counter (step S52308), and whether or not the added count value is equal to or greater than a predetermined prize ball shortage determination value (eg, 501). Is confirmed (step S52309). In this embodiment, the prize ball number counter is a counter used for grasping the number of prize balls that have not been paid out on the game control microcomputer 560 side, and when the prize ball number command is transmitted, The number of prize balls designated in (1) is added, and every time ten prize balls are paid out, 10 is subtracted based on the prize ball information output from the payout control microcomputer 370. Further, as described above, the prize ball number counter is set to “250” as an initial value in the initial setting process of the main process. When the count value of the prize ball counter reaches a predetermined prize ball shortage determination value (for example, 501) or more, the number of prize balls that have not been paid out is excessively large. Can be determined. Further, when the count value of the prize ball number counter is less than a predetermined prize ball excess determination value (for example, 0), an abnormally large number of game balls are paid out in excess of the number to be paid out originally. Therefore, it can be determined that an excessive number of prize balls has occurred.

  In this embodiment, the prize ball number counter is added (see step S52308) immediately after the prize ball number command is transmitted (see step S52305). However, the prize ball number command is transmitted. For example, a prize ball number command may be transmitted immediately after the addition process of the prize ball number counter is executed.

  When it is determined that there is a shortage of prize balls, the signal line for outputting the prize ball information is disconnected in addition to the case where some trouble occurs on the payout control microcomputer 370 side and the payout operation cannot be performed normally. Cases are also conceivable. On the other hand, when it is determined that the number of prize balls is excessive, a prize ball number command is transmitted in addition to the case where some kind of trouble occurs on the payout control microcomputer 370 side and the payout operation is performed more than necessary. It is also conceivable that some injustice is applied to the command line and the prize ball number command is illegally input to the payout control microcomputer 370.

  When the count value of the prize ball number counter is equal to or greater than a predetermined prize ball shortage determination value (for example, 501), the CPU 56 displays a prize ball error flag indicating that a prize ball shortage or a prize ball excess has occurred. It is confirmed whether it has already been set (step S52310). If the prize ball error flag has already been set, the process is terminated. If the prize ball error flag is not set, the CPU 56 sets a prize ball error flag (step S52311) and controls to send a prize ball shortage error command to the effect control microcomputer 100 (step S52312). Specifically, the CPU 56 performs a process of setting the address of the winning ball shortage error command transmission table as a pointer. Then, based on the fact that the address of the prize ball shortage error command transmission table is set to the pointer in step S52312, the effect symbol command command control process in step S30 is executed, so that the prize ball shortage error command is effect control. To the microcomputer 100 for use. Note that once the prize ball error flag is set, it is maintained without being cleared until the power supply to the gaming machine is turned on again after the power supply to the gaming machine is stopped. In this embodiment, regarding the communication between the game control microcomputer 560 and the effect control microcomputer 100, a command is transmitted from the game control microcomputer 560 to the effect control microcomputer 100. Only, not the other way around.

  In this embodiment, based on the reception of a prize ball shortage error command or a prize ball excess error command described later, the effect control microcomputer 100 performs an error notification of prize ball shortage or prize ball excess. However, the error notification of insufficient prize balls or excessive prize balls may be recovered when a predetermined period has elapsed from the start of notification. Further, for example, when the value of the prize ball number counter returns to a range of a predetermined prize ball shortage determination value (for example, 501) or a predetermined prize ball excess determination value (for example, 0), the prize ball shortage or the prize ball is excessive. It is also possible to recover from the error notification.

  In this embodiment, the case where the prize ball number is added to the prize ball number counter at the timing at which the prize ball number command is transmitted in step S52308 is shown. For example, the number of prize balls may be subtracted instead of the one shown in the embodiment. In this case, for example, in the process of step S5311 to be described later, on the contrary, 10 may be added to the value of the winning ball counter based on the input of winning ball information. In the process of step S52309, if the value of the prize ball number counter is less than 0, it is determined that there is a prize ball shortage error. In the process of step S5312 described later, if the value of the prize ball number counter is 501 or more, a prize ball What is necessary is just to determine with an excess error.

  In step S52313, the CPU 56 checks whether or not the prize ball process timer has timed out. If the winning ball process timer has timed out (that is, if no winning ball has been stored and no new winning has occurred by the time one second has elapsed after receiving the connection OK command), the CPU 56 Then, the value “0” indicating the prize ball transmission process 1 is set in the prize ball process code (step S52314), and the process ends. If the winning ball process timer has not timed out, the CPU 56 subtracts 1 from the value of the winning ball process timer (step S52315).

  FIG. 24 is a flowchart showing a prize ball reception confirmation process (step S524) executed when the value of the prize ball process code is 3. In the winning ball receipt confirmation process, the CPU 56 first checks whether or not there is data in the reception data register of the serial communication circuit 505 (step S52401). Specifically, the CPU 56 may confirm the value of the status register of the serial communication circuit 505. If there is no data in the reception data register (that is, if no command is received), the process proceeds to step S52409.

  If there is data in the reception data register (that is, if a command is received), the CPU 56 checks whether or not an error has occurred in the serial communication circuit 505 (step S52402). Specifically, the CPU 56 may confirm whether any error bit value is set in the status register of the serial communication circuit 505. If an error has occurred, the process proceeds to step S52409.

  If no error has occurred in the serial communication circuit 505, the CPU 56 reads the command from the reception data register of the serial communication circuit 505, and checks whether or not the received command is a prize ball number acceptance command (step S52403). . If the winning ball number reception command has been received, the CPU 56 subtracts 1 from the value of the winning ball command output counter corresponding to the winning ball number set by the transmitted winning ball number command (step S52404). In addition, the CPU 56 sets a value “4” indicating a prize ball end confirmation process in the prize ball process code (step S52405), and proceeds to step S52408.

  If the received command is not a prize ball number acceptance command, the CPU 56 checks whether or not the received command is a prize ball preparation command (step S52406). If it is not a prize ball preparation command, the process advances to step S52409.

  If the winning ball preparation command has been received, the CPU 56 stores the error information (see FIG. 14) set in the lower 4 bits of the winning ball preparation command in the frame state display buffer (step S52407). Then, the CPU 56 sets the connection confirmation time 2 (for example, 10 seconds) in the prize ball process timer (step S52408). In addition, after receiving the prize ball preparation command based on the connection confirmation time 2 set in step S52408, neither the prize ball number acceptance command nor the next prize ball preparation command can be received after 10 seconds. If it is, the process returns to the control for transmitting the connection confirmation command. Specifically, the prize ball process timer set in step S52408 is measured in the processing of steps S52409 and S52411 described later, and 10 seconds are received without receiving a prize ball number acceptance command or a next prize ball preparation command. If time elapses and it is determined as Y in step S52409, the process returns to the prize ball transmission process 1 and the next connection confirmation command is transmitted (see steps S52410 and S5211).

  In step S52409, the CPU 56 checks whether or not the prize ball process timer has timed out. If the prize ball process timer has timed out (that is, if no prize ball number acceptance command or prize ball preparation command is received after 10 seconds have passed since the prize ball number command was transmitted), the CPU 56 Then, the value “0” indicating the prize ball transmission process 1 is set in the prize ball process code (step S52410), and the process ends. If the winning ball process timer has not timed out, the CPU 56 subtracts 1 from the value of the winning ball process timer (step S52411).

  FIG. 25 is a flowchart showing the winning ball end confirmation process (step S525) executed when the value of the winning ball process code is 4. In the winning ball end confirmation process, the CPU 56 first confirms whether or not there is data in the reception data register of the serial communication circuit 505 (step S52501). Specifically, the CPU 56 may confirm the value of the status register of the serial communication circuit 505. If there is no data in the reception data register (that is, if no command is received), the process proceeds to step S52509.

  If there is data in the reception data register (that is, if a command is received), the CPU 56 checks whether an error has occurred in the serial communication circuit 505 (step S52502). Specifically, the CPU 56 may confirm whether any error bit value is set in the status register of the serial communication circuit 505. If an error has occurred, the process proceeds to step S52509.

  If no error has occurred in the serial communication circuit 505, the CPU 56 reads the command from the reception data register of the serial communication circuit 505, and checks whether the received command is a prize ball end command (step S52503). If the winning ball end command has been received, the CPU 56 sets a value “2” indicating the winning ball transmission process 2 in the winning ball process code (step S52504), and the connection check time 1 (for example, 1) is set in the winning ball process timer. Second) is set (step S52505). It should be noted that, based on the connection confirmation time 1 set in step S52505, the control for transmitting the connection confirmation command when the start winning prize does not occur even after one second has elapsed after receiving the winning ball end command. Return to. Specifically, the prize ball process timer set in step S52505 is measured by the processing in steps S52313 and S52315, and one second has elapsed without sending a prize ball number command without generating a new start prize. If time-out occurs and it is determined as Y in step S52313, the process returns to the prize ball transmission process 1 and the next connection confirmation command is transmitted (see steps S52314 and S5211).

  Since the process of step S52504 is executed, when a prize ball end command is received, the process first proceeds to prize ball transmission process 2. Therefore, when the number of prize balls is stored, the next is immediately performed. Control is performed so that a winning ball number command is transmitted. On the other hand, after the transition to the prize ball transmission process 2, there is no memorized number of prize balls, and a new prize is also generated until the connection confirmation time 1 (for example, 1 second) set in step S52505 has elapsed. If not, the process further proceeds to a prize ball transmission process 1, and the process of repeatedly transmitting the connection confirmation command is resumed.

  If the received command is not a prize ball end command, the CPU 56 checks whether or not the received command is a prize ball preparation command (step S52506). If it is not a prize ball preparation command, the process advances to step S52509.

  If the winning ball preparation command has been received, the CPU 56 stores the error information (see FIG. 14) set in the lower 4 bits of the winning ball preparation command in the frame state display buffer (step S52507). Then, the CPU 56 sets the connection confirmation time 2 (for example, 10 seconds) in the prize ball process timer (step S52508). In addition, after receiving the winning ball preparation command based on the connection confirmation time 2 set in step S52508, neither the winning ball end command nor the next winning ball preparation command could be received after 10 seconds. In this case, the process returns to the control for transmitting the connection confirmation command. Specifically, the prize ball process timer set in step S52508 is measured in the processing of steps S52509 and S52511 described later, and 10 seconds have elapsed without receiving a prize ball end command or a next prize ball preparation command. If time is out and it is determined as Y in step S52509, the process returns to the prize ball transmission process 1 and the next connection confirmation command is transmitted (see steps S52510 and S5211).

  In step S52509, the CPU 56 checks whether or not the prize ball process timer has timed out. If the prize ball process timer has timed out (that is, the prize ball end command or the prize ball preparation command cannot be received even after 10 seconds have passed since the prize ball number acceptance command or prize ball preparation command is received) In this case, the CPU 56 sets a value “0” indicating the prize ball transmission process 1 in the prize ball process code (step S52510), and ends the process. If the winning ball process timer has not timed out, the CPU 56 subtracts 1 from the value of the winning ball process timer (step S52511).

  FIG. 26 is a flowchart showing the prize ball counter subtraction process in step S503. In the prize ball counter subtraction process, the CPU 56 first checks whether or not the prize ball information input invalid timer has timed out (step S5301). The prize ball information input invalid timer is a timer that is measured in order to provide an interval period after confirming the input of prize ball information until confirming the next prize ball information. If not timed out, the CPU 56 subtracts 1 from the value of the prize ball information input invalid timer (step S5302) and ends the process.

  If the prize ball information input invalid timer has timed out, the CPU 56 inputs the contents of the input port 0 (step S5303), and checks whether or not the bit of the prize ball information is on (step S5304). If the bit of the prize ball information is on, the process proceeds to step S5305.

  In step S5305, the CPU 56 sets a predetermined prize ball information confirmation count (for example, 8) as the number of processes (step S5305). Then, the CPU 56 confirms whether or not the prize ball information is input, and if the input of the prize ball information can be confirmed, the CPU 56 adds the value of the prize ball information on counter to 1 and the number of processes (8 in this example). The process is repeated until the process is completed (steps S5306 to S5308).

  Next, the CPU 56 checks whether or not the value of the prize ball information on counter is 6 or more (step S5309). If the value of the prize ball information on counter is 6 or more, the CPU 56 sets a predetermined time (for example, 0.8 seconds) in the prize ball information input invalid timer (step S5310) and sets the value of the prize ball number counter to 10 Subtraction is performed (step S5311).

  By executing the above processing, in this embodiment, it is determined that the winning ball information is input on the condition that the input of the winning ball information is confirmed six times or more in eight confirmation processes, The value of the prize ball number counter is decremented by 10 assuming that the prize ball has been paid out. By such processing, in this embodiment, the situation where it is determined that the prize ball information is erroneously input is reduced, and the game control microcomputer 560 side cannot properly grasp the number of prize balls that have not been paid out. It is preventing.

  Next, the CPU 56 checks whether or not the count value after subtraction is less than a predetermined prize ball excess determination value (for example, 0) (step S5312). When the count value of the prize ball number counter is less than a predetermined prize ball excess determination value (for example, 0), the CPU 56 checks whether or not the prize ball error flag is already set (step S5313). If the prize ball error flag has already been set, the process is terminated. If the prize ball error flag is not set, the CPU 56 sets the prize ball error flag (step S5314) and controls to send a prize ball excess error command to the effect control microcomputer 100 (step S5315). Specifically, the CPU 56 performs a process of setting the address of the winning ball excessive error command transmission table as a pointer. Then, based on the fact that the address of the prize ball excess error command transmission table is set in the pointer in step S5315, the effect symbol command control process in step S30 is executed, so that the prize ball excess error command is effect controlled. To the microcomputer 100 for use.

  Next, the frame state output process (step S39) will be described. FIG. 27 is a flowchart illustrating an example of a frame state output process in step S39. In the frame state output process, the CPU 56 first loads the contents of the frame state display buffer (step S391). Next, the CPU 56 inputs the content of the input port 0 (step S392) and logically ANDs the input port 0 content with a predetermined door opening signal confirmation mask value (specifically 01000000). (Step S393). Further, the CPU 56 calculates the logical product of the operation result obtained by the logical product and the contents of the frame state display buffer loaded in step S391 (step S394). By executing the above processing, a calculation result is obtained in which the door opening signal input state is further added to the contents of the frame state display buffer.

  Next, the CPU 56 compares the calculation result with the contents of the previous frame state display buffer (step S395). The previous frame state display buffer stores the calculation result of step S394 calculated when the frame state output processing is executed by the previous timer interrupt. When the calculation result is different from the content of the previous frame state display buffer (Y in step S396), the CPU 56 stores the calculation result calculated in step S394 in the previous frame state display buffer and updates the previous frame state display buffer. Along with (Step S397), the calculation result calculated in Step S394 is set as it is to the frame state display command, and control is performed to transmit the frame state display command to the effect control microcomputer 100 (Step S398). Specifically, the CPU 56 performs processing for setting the address of the frame state display command transmission table in the pointer. Then, based on the fact that the address of the frame state display command transmission table is set in the pointer in step S398, the effect symbol command control process in step S30 is executed, whereby the frame state display command is changed to the effect control micro. It is transmitted to the computer 100.

  By executing the above processing, the error information set by the connection OK command or the winning ball preparation command from the payout control microcomputer 560 (the payout number error error, the ball running out error, the full tank error, the winning ball error) And the input state of the door opening signal are set in the frame state display command and transmitted to the production control microcomputer 100.

  FIG. 28 is an explanatory diagram for explaining an example of fraud. FIG. 28A shows a proximity switch which is an example of a detection unit capable of detecting a game ball. FIG. 28A shows an example in which a proximity switch is used as the count switch 23. One terminal of the count switch 23 is supplied with + 12V power supply voltage from the power supply substrate 910. A detection signal that is the voltage level of the other terminal of the count switch 23 is input to the main board 31. In the main board 31, the detection signal is input from the input driver circuit to the input port of the game control microcomputer. Further, a resistor R and a capacitor C, one end of which is grounded, are connected to the output side of the count switch 23.

  When a metal game ball passes through a hole provided in the count switch 23 that is a proximity switch, a counter electromotive force is generated in the coil L, and the equivalent resistance value of the coil L becomes extremely large. Therefore, the output of the count switch 23 becomes a low level close to 0V. That is, the detection signal is at a low level. When the metal game ball does not pass through the hole provided in the count switch 23, the output of the count switch 23 is a value obtained by dividing + 12V by the resistance value of the coil L and the resistance R, and the high A threshold level that is considered to be a level is exceeded. That is, the detection signal is at a high level. The level of the detection signal is logically inverted by the input driver circuit 58.

  When the detection signal from the input driver circuit 58 is at a high level, the game control microcomputer can determine that the game ball has passed through the switch.

  In this embodiment, in addition to the count switch 23, proximity switches are used as the winning port switches 29a and 30a, the first start port switch 13a, and the second start port switch 14a. In this embodiment, the outputs of the winning opening switches 29a and 30a are logically inverted by the input driver circuit 58 similarly to the count switch 23, but the outputs of the first starting port switch 13a and the second starting port switch 14a are It is input to the game control microcomputer 560 without being logically inverted.

  FIG. 28B is an explanatory diagram illustrating a specific example of fraud. In the example shown in FIG. 28B, a hole provided in the count switch 23 is closed with a metal sphere (for example, a sphere having a diameter larger than that of a normal game ball is used), and in that state, Radio waves are emitted from the transmitter 50 toward the sphere.

  When the hole provided in the count switch 23 is closed with a metal sphere, the count switch 23 outputs a detection signal. Specifically, as shown in the upper part of FIG. 28C, the count switch 23 sets the detection signal to a low level.

  In this state, when a radio wave is emitted toward the sphere so as to turn on and off the detection signal of the count switch 23, the detection input to the game control microcomputer 560 is performed as shown in the lower part of FIG. The signal repeats on and off. Then, the game control microcomputer 560 considers that the detection signal has been turned on many times, erroneously determines that the game ball has been won many times, and eventually the game ball is paid out as a large number of prizes.

  In this embodiment, as will be described later, when the detection signal is in a state as shown in the lower part of FIG. 28C, it is determined that there is a possibility of fraud, and a predetermined notification is made. Done. As will be described later, the game control microcomputer 560 checks the detection signal of the switch every 4 ms, and the detection signal level is L level (low level) and the detection is confirmed immediately before (4 ms before). When the signal level is the H level (high level), it is determined that the switch is turned on (the game ball is detected), but the radio wave transmitter 50 has a detection signal cycle as shown in the lower part of FIG. If the clock frequency for generating the radio wave of that cycle and the drive frequency of the game control microcomputer 560 are equal or have an integer multiple relationship, the game control micro There is an opportunity for the computer 560 to determine that the switch is turned on based on the detection signal in the state shown in the lower part of FIG. Even when the clock frequency of the radio wave transmitter 50 coincides with the driving frequency of the game control microcomputer 560 or coincides with an integral multiple, the period of the detection signal as shown in the lower part of FIG. Unless the (time from the falling edge of the signal to the next falling edge) is 4 ms or an integral fraction of 4 ms, the switch is turned on based on the detection signal in the state shown in the lower part of FIG. An opportunity to make a decision arises.

  FIG. 29 is an explanatory diagram showing an example of the contents of the effect control command transmitted by the game control microcomputer 560. In the example shown in FIG. 29, the command 80XX (H) is an effect control command (variation pattern command) for designating a variation pattern of the effect symbol that is variably displayed on the effect display device 9 in response to the variable display of the special symbol. (Corresponding to the variation pattern XX, respectively). “(H)” indicates a hexadecimal number. The effect control command for designating the variation pattern is also a command for designating the start of variation. Therefore, when receiving the command 80XX (H), the effect control microcomputer 100 controls the effect display device 9 to start variable display of effect symbols.

  Command 8CXX (H) is an effect control command indicating whether or not to make a big hit and the type of big hit. The effect control microcomputer 100 determines the display result of the effect symbol in response to the reception of the command 8CXX (H), so the command 8CXX (H) is referred to as a display result designation command.

  The command 8F00 (H) is an effect control command (symbol confirmation designation command) indicating that the variable display (fluctuation) of the effect symbol is terminated and the display result (stop symbol) is derived and displayed.

  Command A001 (H) is an effect control command (also referred to as a jackpot start designation command) for displaying a fanfare screen, that is, designating the start of a jackpot game. Command A002 (H) displays a fanfare screen for a small hit or suddenly probable big hit, that is, a production control command (small hit / suddenly probable big hit for designating start of a big hit game or start of a big hit game based on sudden probable big hit It is also called a start designation command.)

  The command A1XX (H) is an effect control command (special command during opening of a big winning opening) indicating a display during the opening of the big winning opening for the number of times (round) indicated by XX. A2XX (H) is an effect control command (designation command after opening the big winning opening) indicating the closing of the big winning opening for the number of times (round) indicated by XX.

  The command A301 (H) is an effect control command (a jackpot end designation command) for displaying the jackpot end screen, that is, designating the end of the jackpot game. Command A302 (H) displays a small hit end screen (also used as a sudden probability change big hit end screen), that is, an effect control command (small hit) that specifies the end of the small hit game or the end of the big hit game based on the sudden positive change big hit. / Suddenly a probable big hit end designation command.)

  In this embodiment, production control commands other than the production control commands shown in FIG. 29 are also used to perform production control. FIG. 29 shows main production control commands.

  The command D0XX (H) is an input port state 1 designation command indicating the input state of the input port 0 (see FIG. 7) for detecting a game ball passing through a predetermined passing area. As will be described later, when the state of the detection signal from the switch assigned to input port 0 changes, an input port state 1 designation command in which the input data of input port 0 is set in the second byte is transmitted. The command D1XX (H) is an input port state 2 designation command indicating the input state of the input port 2 (see FIG. 7) for detecting a game ball passing through a predetermined passing area. As will be described later, when the state of the detection signal from the switch assigned to the input port 2 changes, an input port state 2 designation command in which the input data of the input port 2 is set in the second byte is transmitted.

  FIG. 30 is a flowchart showing an example of a special symbol process (step S26) program executed by the game control microcomputer 560 (specifically, the CPU 56) mounted on the main board 31. As described above, in the special symbol process, a process for controlling the first special symbol display 8a or the second special symbol display 8b and the special winning opening is executed. In the special symbol process, the CPU 56 detects that the first start port switch 13a for detecting that the game ball has won the first start winning port 13 or that the game ball has won the second start winning port 14. If the second start opening switch 14a is turned on, that is, if a start winning to the first start winning opening 13 or a start winning to the second start winning opening 14 has occurred, the start opening switch passing process is performed. Execute (Steps S311 and S312). Then, any one of steps S300 to S310 is performed. If the first start winning port switch 13a or the second start port switch 14a is not turned on, any one of steps S300 to S310 is performed according to the internal state.

  The processes in steps S300 to S310 are as follows.

  Special symbol normal processing (step S300): Executed when the value of the special symbol process flag is zero. When the game control microcomputer 560 is in a state where variable display of the special symbol can be started, the game control microcomputer 560 checks the number of numerical data stored in the reserved storage number buffer (total number of reserved storage). The stored number of numerical data stored in the pending storage number buffer can be confirmed by the count value of the total pending storage number counter. If the count value of the total pending storage number counter is not 0, the game control microcomputer 560 executes a big hit determination process and sets the display result of variable display of the first special symbol or the second special symbol as a big hit. Determine whether or not. In this case, it is confirmed whether or not the probability variation state is set (specifically, whether or not the probability variation flag is set). If the probability variation state is established, a jackpot determination random number ( A lottery process using random R) is performed to determine whether or not to win. On the other hand, if it is not in a probable change state, a lottery process using a big hit determination random number (random R) is performed using the normal big hit determination table to determine whether or not to win. In the case of a big hit, a big hit flag is set. In the case of a big hit, the game control microcomputer 560 executes the big hit type determination process, and in the case of executing the variable display of the first special symbol, the big hit type determination table for the first special symbol. If a lottery process using a random number for determining the big hit type is used to display a variation display of the second special symbol, the big hit type determination is performed using the big special type determination table for the second special symbol. A lottery process using a random number is performed to determine which jackpot type is to be used. On the other hand, if not a big hit, the game control microcomputer 560 executes a small hit determination process, and if a variable display of the first special symbol is executed, the small hit determination table for the first special symbol. If the lottery process using the random number for determining the big hit (random R) is used and the variation display of the second special symbol is executed, the big hit using the small special determination table for the second special symbol is used. A lottery process using a random number for determination (random R) is performed to determine whether or not to make a small hit. Then, the internal state (special symbol process flag) is updated to a value (1 in this example) according to step S301. The jackpot flag is reset when the jackpot game ends.

  Fluctuation pattern setting process (step S301): This process is executed when the value of the special symbol process flag is 1. Also, the variation pattern is determined, and the variation time in the variation pattern (variable display time: the time from the start of variable display until the display result is derived and displayed (stop display)) is defined as the variation display variation time of the special symbol. Decide to do. Also, a variable time timer for measuring the special symbol variable time is started. Then, the internal state (special symbol process flag) is updated to a value (2 in this example) corresponding to step S302.

  Display result designation command transmission process (step S302): This process is executed when the value of the special symbol process flag is 2. Control for transmitting a display result designation command to the production control microcomputer 100 is performed. Then, the internal state (special symbol process flag) is updated to a value (3 in this example) corresponding to step S303.

  Special symbol changing process (step S303): This process is executed when the value of the special symbol process flag is 3. When the variation time of the variation pattern selected in the variation pattern setting process elapses (the variation time timer set in step S301 times out, that is, the variation time timer value becomes 0), the design control microcomputer 100 determines the symbol. Control to transmit the specified command is performed, and the internal state (special symbol process flag) is updated to a value (4 in this example) corresponding to step S304. The effect control microcomputer 100 controls the effect display device 9 to stop the fourth symbol when receiving the symbol confirmation designation command transmitted by the game control microcomputer 560.

  Special symbol stop process (step S304): executed when the value of the special symbol process flag is 4. When the big hit flag is set, the internal state (special symbol process flag) is updated to a value (5 in this example) corresponding to step S305. If the small hit flag is set, the internal state (special symbol process flag) is updated to a value (8 in this example) corresponding to step S308. If neither the big hit flag nor the small hit flag is set, the internal state (special symbol process flag) is updated to a value corresponding to step S300 (in this example, 0). In this embodiment, based on the value of the special symbol process flag being 4, special symbol display control data for stopping and displaying the special symbol stop symbol in the special symbol display control process of step S36 is provided. The special symbol display control data is set in the output buffer, and the special symbol stop symbol is actually stopped and displayed according to the setting contents of the output buffer in the display control processing in step S22.

  Preliminary winning opening opening process (step S305): This is executed when the value of the special symbol process flag is 5. In the pre-opening process for the big prize opening, control for opening the big prize opening is performed. Specifically, a counter (for example, a counter that counts the number of game balls that have entered the big prize opening) is initialized and the solenoid 21 is driven to open the big prize opening. Also, the execution time of the special prize opening opening process is set by the timer, and the internal state (special symbol process flag) is updated to a value corresponding to step S306 (6 in this example). The pre-opening process for the big winning opening is executed for each round, but when the first round is started, the pre-opening process for the big winning opening is also a process for starting the big hit game.

  Large winning opening opening process (step S306): This process is executed when the value of the special symbol process flag is 6. A control for transmitting an effect control command for round display during the big hit gaming state to the effect control microcomputer 100, a process for confirming the completion of the closing condition of the big prize opening, and the like are performed. If the closing condition for the special prize opening is satisfied and there are still remaining rounds, the internal state (special symbol process flag) is updated to a value (5 in this example) corresponding to step S305. When all the rounds are completed, the internal state (special symbol process flag) is updated to a value corresponding to step S307 (7 in this example).

  Big hit end process (step S307): executed when the value of the special symbol process flag is 7. Control is performed to cause the microcomputer 100 for effect control to perform display control for notifying the player that the big hit gaming state has ended. In addition, a process for setting a flag indicating a gaming state (for example, a probability change flag or a time reduction flag) is performed. Then, the internal state (special symbol process flag) is updated to a value (0 in this example) corresponding to step S300.

  Small hit release pre-processing (step S308): This process is executed when the value of the special symbol process flag is 8. In the pre-opening process for small hits, control is performed to open the big prize opening. Specifically, a counter (for example, a counter that counts the number of game balls that have entered the big prize opening) is initialized and the solenoid 21 is driven to open the big prize opening. Also, the execution time of the special winning opening opening process is set by the timer, and the internal state (special symbol process flag) is updated to a value corresponding to step S309 (9 in this example). Note that the pre-opening process for small hits is executed every time the big winning opening during the small hit game is opened. It is also a process to start.

  Small hit release processing (step S309): executed when the value of the special symbol process flag is 9. Processing to confirm the establishment of the closing condition of the big prize opening is performed. When the closing condition of the big prize opening is satisfied and the number of opening of the big prize opening still remains, the internal state (special symbol process flag) is set to a value (8 in this example) corresponding to step S308. Update. When all rounds are completed, the internal state (special symbol process flag) is updated to a value corresponding to step S310 (in this example, 10 (decimal number)).

  Small hit end process (step S310): executed when the value of the special symbol process flag is 10. Control is performed to cause the microcomputer 100 for effect control to perform display control for notifying the player that the small hit gaming state has ended. Then, the internal state (special symbol process flag) is updated to a value (0 in this example) corresponding to step S300.

  FIG. 31 is a flowchart showing the special symbol stop process (step S304) in the special symbol process. In the special symbol stop process, the CPU 56 checks whether or not the big hit flag is set (step S130). If the big hit flag is set, the CPU 56 resets the probability variation flag indicating the probability variation state and the time reduction flag indicating the time reduction state if set (step S135). If it is set, the hourly number counter is also reset. If it is set, the CPU 56 resets the high-accuracy output permission flag (step S136).

  Next, the CPU 56 performs control to transmit a big hit start designation command to the production control microcomputer 100 (step S137). Specifically, when the type of jackpot is a normal jackpot or a probable variation jackpot, a jackpot start designation command is transmitted. When the big hit type is sudden probability change big hit, a small hit / sudden probability sudden change big hit start designation command is transmitted. Whether the big hit type is a normal big hit, a probable big hit or a sudden probable big hit is data indicating the big hit type stored in the RAM 55 determined in the special symbol normal processing in step S300 (stored in the big hit type buffer). Data).

  In addition, the CPU 56 sets a value corresponding to the jackpot display time (time for notifying that the jackpot has occurred, for example, in the effect display device 9) in the timer before opening the big prize opening (step S138). The timer before opening the big winning opening is a timer for measuring the time until the big winning opening is released during the big hit game or the small hit game. Specifically, at the start of the big hit game, in step S138, the time required from the start of the variable display to the start of the first round (the variable display is stopped on the production control microcomputer 100 side and the jackpot symbol is displayed). The time before the first round is started until the start of the first round is set as the pre-opening timer. For the first and subsequent rounds, the interval time between the rounds (apparatus at the time of performing the interval effect between the rounds on the effect control microcomputer 100 side) is set as the timer before opening the big prize opening.

  Further, the CPU 56 sets the number of times of opening in a number-of-opening counter (a counter for counting the number of times of opening of the big winning opening during the big hit game or the small hit game) (step S139). In this embodiment, it is assumed that the fixed number of times is set to 15 in the opening number counter without distinguishing the jackpot type. It should be noted that a different number of times may be set in the opening number counter according to the big hit type. For example, in the case of a normal big hit or a probable big hit, the open count counter may be set to 15 times, and in the case of a sudden probable big hit, the open count counter may be set to 2 times. Then, the value of the special symbol process flag is updated to a value corresponding to the pre-opening process for the special winning opening (step S305) (step S140).

  On the other hand, if the big hit flag is not set in step S130, the CPU 56 checks whether or not the value of the time-count counter for counting the number of fluctuations of the special symbol in the time-short state is 0 (step S141). . If the value of the time reduction counter is not 0 (in this case, the time reduction counter is set based on a normal big hit and the time reduction counter is set), the CPU 56 The value is decremented by 1 (step S142). When the value of the time reduction counter after subtraction becomes 0 (step S143), the CPU 56 resets the time reduction flag (step S144).

  Next, the CPU 56 checks whether or not the small hit flag is set (step S145). If the small hit flag is set, the CPU 56 transmits a small hit / suddenly probable big hit start designation command to the effect control microcomputer 100 (step S146). In addition, a value corresponding to the small hit display time (time for notifying that the small hit has occurred, for example, in the effect display device 9) is set in the timer before opening the big prize opening (step S147). In the case of a small hit game, at the start of the small hit game, in step S147, the time required from the start of the variable display to the start of the small hit game is set in the timer before opening the big prize opening. . Further, during the small hit game, the interval time between each opening of the big winning opening is set in the timer before the big winning opening.

  Further, the CPU 56 sets the number of times of opening in the number of times of opening counter (step S148). In this embodiment, 15 times is set in the opening number counter in step S148. When a different number of times is set according to the big hit type in step S139, for example, in the case of a sudden probability variable big hit, when the opening number counter is set twice, the opening number counter is also set twice in step S148. May be set. Then, the value of the special symbol process flag is updated to a value corresponding to the small hit start pre-processing (step S308) (step S149).

  If the small hit flag is not set (N in step S145), the CPU 56 updates the value of the special symbol process flag to a value corresponding to the special symbol normal process (step S300) (step S150).

  Next, the switch process (step S21) in the timer interrupt process will be described. In this embodiment, when the ON state of the detection signal of each switch related to winning detection or gate passage continues for a predetermined time, it is determined that the switch is surely turned on, and processing corresponding to the switch on is started. FIG. 32 is an explanatory diagram showing each 2-byte buffer formed in the RAM 55 used in the switching process. The previous port buffer is a buffer in which the previous switch-on / off determination result (for example, 4 ms before) is stored. The port buffer is a buffer in which the contents of ports 0 and 2 input this time are stored. The switch-on buffer is a buffer in which the corresponding bit is set to 1 when switch on is detected and the corresponding bit is set to 0 when switch off is detected. Note that the previous port buffer, port buffer, and switch-on buffer shown in FIG. 32 are prepared for each of the input ports 0 and 2. For example, in this embodiment, two switch-on buffers 1 and 2 are prepared, and the switch state of the input port 0 is set to the previous port buffer 1, the port buffer 1, and the switch-on buffer 1, and the input port 2 is set to the previous port buffer 2, port buffer 2, and switch-on buffer 2.

  33 and 34 are flowcharts showing a processing example of the switch processing in step S21 in the game control processing. In the switch process, the CPU 56 first inputs data input to the input port 0 (see FIG. 7) (step S2101), and sets the input data in the port buffer 1 (step S2102).

  Next, an initial value of the weight counter formed in the RAM 55 is set (step S2103), and the value of the weight counter is decremented by 1 until the value of the weight counter becomes 0 (steps S2104 and S2105).

  When the value of the wait counter becomes 0, the data of the input port 0 is input again (step S2106), and a logical product is obtained for each bit between the input data and the data set in the port buffer 1 ( Step S2107). Then, the operation result of the logical product is set in the port buffer 1 (step S2108). Through the processing in steps S2103 to S2108, both of the two pieces of input data input from the input port 0 with a time interval of approximately [initial value of weight counter × (processing time in steps S2104 and S2105)] Only the bit that is “1” becomes “1” in the port buffer 1. That is, if the ON state of the switch detection signal continues for a predetermined period [initial value of wait counter × (processing time of steps S2104 and S2105)], the corresponding bit in port buffer 1 becomes “1”.

  Further, the CPU 56 performs exclusive OR for each bit between the data previously set in the port buffer 1 and the data set in the port buffer 1 (step S2109). In the result of the exclusive OR operation, the bit corresponding to the switch for which the previous switch-on / off determination result (for example, 4 ms before) differs from the switch-on / off determination result determined to be on this time is “ 1 ”.

  When the bit corresponding to one of the switches becomes “1” (when the state of the detection signal from the switch has changed) (Y in step S2110), the CPU 56 inputs the input port to the production control microcomputer 100. Control to transmit the state 1 designation command is performed (step S2111).

  In step S2111, the CPU 56 transmits an input port state 1 designation command when the bit corresponding to the detection signals from the count switch 23 and the winning opening switches 29a and 30a becomes “1”, and the winning confirmation switch 14b. When the bit corresponding to the detection signal from “1” becomes “1”, the input port state 1 designation command may not be transmitted. When the configuration is made so that the input port state 1 designation command is not transmitted when the bit corresponding to the detection signal from the winning confirmation switch 14b becomes “1”, between the processing of step S2110 and step S2111, When the logical product of the result of the exclusive OR operation and “0D (H)” (data that masks bit 4 of input port 0 shown in FIG. 7) becomes 0, a step that does not execute the process of step S2111 is inserted. do it. In this embodiment, the production control microcomputer 100 includes the count switch 23 of the input port 0 and the prize opening switch in the abnormality determination process (see FIGS. 74, 75, 78, 79, 81, and 82). Since only the bit corresponding to the detection signal from 29a, 30a is determined, the abnormality determination process is affected even if the bit data corresponding to the detection signal from the winning confirmation switch 14b is “1” or “0”. Not give. Further, when the input port state 1 designation command is transmitted even when the bit corresponding to the detection signal from the winning confirmation switch 14b is “1” as in this embodiment, the winning confirmation switch is used in the abnormality determination process. The bit corresponding to the detection signal from 14b may also be used as a determination target and used to detect abnormal passing of the game ball with respect to the start winning opening 14. For example, abnormal passing may be detected based on the detection of either the second start port switch 14a or the winning confirmation switch 14b being turned on, and abnormality notification may be performed.

  In step S2111, the CPU 56 performs control to transmit an input port state 1 designation command in which the data of the port buffer 1 corresponding to the input data of the input port 0 is set to the second byte. That is, the CPU 56 outputs the input data of the input port 0 as a command all at once.

  When transmitting the effect control command to the effect control microcomputer 100, the CPU 56 sets the address of the command transmission table (preliminarily set for each command in the ROM 54) according to the type of the effect control command as a pointer. To do. Then, the effect control command is transmitted in the effect symbol command control process (step S30). When transmitting non-fixed data such as input data of the input port 0, for example, MODE data (see FIG. 29) is set in the first byte of the command transmission table in the ROM 54, and the RAM 55 is set in the second byte. The address of the predetermined area is set. The CPU 56 sets the input data of the input port 0 in a predetermined area of the RAM 55, and then sets the address of the command transmission table corresponding to the input port state 1 designation command as a pointer. The address of the RAM area may be stored in the command transmission table, and the data at the corresponding address may be set in the second byte.

  Further, the CPU 56 performs a logical product for each bit between the operation result of the exclusive OR and the data set in the port buffer 1 (step S2112). As a result, of the bits corresponding to the switches for which the previous switch on / off determination result and the switch on / off determination result determined to be on this time are different (according to the exclusive OR operation result), the current on Only the bit corresponding to the switch determined to be (by AND operation) remains as “1”.

  The CPU 56 sets the logical product operation result in step S2112 in the switch-on buffer 1 (step S2113), and sets the contents of the port buffer 1 in which the operation result in step S2108 is set in the previous port buffer 1 ( Step S2114).

  By the above processing, among the switches that have been on for a predetermined period of time, the switch on / off determination result of the previous time (for example, 4 ms ago) was off, that is, the switch changed from the off state to the on state. The bit corresponding to the switch is “1” in the switch-on buffer 1.

  Next, the CPU 56 inputs the data input to the input port 2 (see FIG. 7) (step S2115), and sets the input data in the port buffer 2 (step S2116).

  Next, an initial value of the weight counter formed in the RAM 55 is set (step S2117), and the value of the weight counter is decremented by 1 until the value of the weight counter becomes 0 (steps S2118 and S2119).

  When the value of the wait counter becomes 0, the data of the input port 2 is input again (step S2120), and a logical OR is performed for each bit between the input data and the data set in the port buffer 2 ( Step S2121). In this embodiment, the detection signals of the first start port switch 13a, the second start port switch 14a and the gate switch 32a input from bits 0 to 2 among the inputs of the input port 2 are input with negative logic. As a result of the logical sum operation in step S2121, two times input from bits 0 to 2 of the input port 2 with a time interval of approximately [initial value of weight counter × (processing time in steps S2118 and S2119)]. Of the input data, only the bit that is “0” twice is “0”.

  Next, the CPU 56 inverts the operation result of the logical sum for each bit (step S2122). Next, the CPU 56 calculates a logical product of the inverted calculation result and a predetermined switch 2 input determination mask value “07 (H)” (step S2123). By executing the processing of steps S2122 and S2123, only the bit in which the ON state is detected among the inputs of the first start port switch 13a, the second start port switch 14a, and the gate switch 32a becomes “1” (note that Other clear switches and input bits of the power-off signal are set to “0” by mask processing). Then, the CPU 56 sets the calculation result after the mask processing in the port buffer 2 (step S2124).

  Through the processing of steps S2117 to S2124, out of bits 0 to 2 of the two input data input from the input port 2 with a time interval of approximately [initial value of weight counter × (processing time of steps S2118 and S2119)], Only the bit that is “0” both times becomes “1” in the port buffer 2. That is, among the detection signals input from the input port 2, the detection signals of the first start port switch 13a, the second start port switch 14a and the gate switch 32a input from bits 0 to 2 are set as a predetermined period [ When the ON state of the switch detection signal continues for the initial value of the wait counter × (processing time of steps S2118 and S2119)], the corresponding bit in the port buffer 2 becomes “1”.

  Further, the CPU 56 performs exclusive OR for each bit between the data previously set in the port buffer 2 and the data set in the port buffer 2 (step S2125). In the result of the exclusive OR operation, the bit corresponding to the switch for which the previous switch-on / off determination result (for example, 4 ms before) differs from the switch-on / off determination result determined to be on this time is “ 1 ”.

  When the bit corresponding to one of the switches becomes “1” (when the state of the detection signal from the switch has changed) (Y in step S2126), the CPU 56 inputs the input port to the production control microcomputer 100. Control to transmit the state 2 designation command is performed (step S2127).

  In step S2127, the CPU 56 determines the input port state 2 when the bit corresponding to the detection signal from the first start port switch 13a and the second start port switch 14a becomes “1” (value after logic inversion). When the designation command is transmitted and the bit corresponding to the detection signal from the gate switch 32a becomes “0” (value after logic inversion), the input port state 2 designation command may not be transmitted. When it is configured not to transmit the input port state 2 designation command when the bit corresponding to the detection signal from the gate switch 32a is “1”, an exclusive operation is not performed between the processing of step S2126 and step S2127. When the logical product of the logical OR operation result and “03 (H)” (data that masks bit 2 of input port 2 shown in FIG. 7) becomes 0, a step that does not execute step S2127 is inserted. That's fine. In this embodiment, the production control microcomputer 100 uses the first start port switch 13a of the input port 2 and the first switch in the abnormality determination process (see FIGS. 74, 75, 78, 79, 81, and 82). 2 Since only the bit corresponding to the detection signal from the start switch 14a is determined, even if the bit data corresponding to the detection signal from the gate switch 32a is “1” or “0”, the abnormality determination processing is performed. Does not affect. Further, when the bit corresponding to the detection signal from the gate switch 32a becomes “1” (value after logic inversion) as in this embodiment, an error occurs when the input port state 2 designation command is transmitted. In the determination process, the bit corresponding to the detection signal from the gate switch 32a is also set as a determination target so that abnormal passing of the game ball with respect to the gate 32 may be detected, and when abnormal passing is detected, abnormality notification may be performed.

  In step S2127, the CPU 56 performs control to transmit an input port state 2 designation command in which the data of the port buffer 2 corresponding to the input data of the input port 2 is set to the second byte. That is, the CPU 56 collectively outputs the input data of the input port 2 as a command.

  When transmitting the effect control command to the effect control microcomputer 100, the CPU 56 sets the address of the command transmission table (preliminarily set for each command in the ROM 54) according to the type of the effect control command as a pointer. To do. Then, the effect control command is transmitted in the effect symbol command control process (step S30). When transmitting non-fixed data such as input data of the input port 2, MODE data (see FIG. 29) is set in the first byte of the command transmission table in the ROM 54, and the RAM 55 is set in the second byte. The address of the predetermined area is set. Then, after setting the input data of the input port 2 in a predetermined area of the RAM 55, the CPU 56 sets the address of the command transmission table corresponding to the input port state 2 designation command as a pointer. The address of the RAM area may be stored in the command transmission table, and the data at the corresponding address may be set in the second byte.

  The CPU 56 further performs a logical product for each bit between the operation result of the exclusive OR and the data set in the port buffer 2 (step S2128). As a result, of the bits corresponding to the switches for which the previous switch on / off determination result and the switch on / off determination result determined to be on this time are different (according to the exclusive OR operation result), the current on Only the bit corresponding to the switch determined by the logical AND operation is “0” when it is negative logic, and it remains “1” when it is positive logic.

  The CPU 56 sets the logical product operation result in step S2128 in the switch-on buffer 2 (step S2129), and sets the contents of the port buffer 2 in which the operation result in step S2124 is set in the previous port buffer 2 ( Step S2130).

  By the above processing, among the switches that have been on for a predetermined period of time, the switch on / off determination result of the previous time (for example, 4 ms ago) was off, that is, the switch changed from the off state to the on state. The bit corresponding to the switch is “1” in the switch-on buffer 2.

  Further, the game control microcomputer 560 (specifically, the CPU 56) performs a switch normality / abnormality check process (step S2131).

  FIG. 35 is a flowchart showing a switch normal / abnormal check process. In the switch normal / abnormal check process shown in FIG. 35, the CPU 56 reads the contents of the switch-on buffer 2 corresponding to the input port 2 (step S121). Then, it is confirmed whether or not the value of bit 1 corresponding to the second start port switch 14a in the switch-on buffer 2 corresponding to the input port 2 is 1 (step S122). That is, it is confirmed whether or not the second start port switch 14a (proximity switch) provided in the upper part of the second start winning port 14 is turned on (a game ball is detected).

  When the value of bit 1 corresponding to the second start port switch 14a in the switch-on buffer 2 corresponding to the input port 2 is 1 (that is, when the second start port switch 14a is in the ON state), the RAM 55 stores The value of the formed switch counter is incremented by 1 (step S123).

  Further, the CPU 56 reads the contents of the switch-on buffer 1 corresponding to the input port 0 (step S124). Then, the CPU 56 checks whether or not the value of the bit 4 corresponding to the winning confirmation switch 14b in the switch-on buffer 1 corresponding to the input port 0 is 1 (step S125). That is, it is confirmed whether or not a winning confirmation switch 14b (photo sensor) provided at the lower part of the second start winning opening 14 is turned on (a game ball is detected).

  When the value of bit 4 corresponding to the winning confirmation switch 14b in the switch-on buffer 1 corresponding to the input port 0 is 1 (that is, when the winning confirmation switch 14b is in the on state), it is formed in the RAM 55. The switch counter value is decreased by 1 (step S126).

  Then, the CPU 56 checks whether or not the value of the switch counter is equal to or greater than a predetermined value (step S127). When the value of the switch counter is equal to or greater than a predetermined value, the CPU 56 determines that an abnormal winning to the second start winning port 14 has occurred, and the security signal information timer has a predetermined time (in this example, 4). Minute) is set (step S128). In this embodiment, the CPU 56 sets a predetermined time (4 minutes in this example) to the security signal information timer based on the fact that the value of the switch counter is 10 or more as a predetermined value. To do. In this embodiment, the abnormal output of the second start winning opening 14 is detected by executing the information output process (see S31) based on the fact that the predetermined time is set in the security signal information timer in step S128. When this is done, the security signal is externally output for a predetermined time (in this example, 4 minutes).

  In the process of step S127, in addition to determining that the abnormal winning to the second start winning opening 14 has occurred, the CPU 56, for example, based on the value of the switch counter being 10 or more, On the contrary, even if the value of the switch counter becomes −10 or less, it may be determined that an abnormal winning to the second start winning opening 14 has occurred. In this case, if the switch counter value is configured so that it cannot be recognized that the value is negative, for example, 10 is set as the default value of the switch counter value. Based on the fact that the counter value becomes 0 or 20 or more, it may be determined that an abnormal winning to the second start winning opening 14 has occurred.

  In this embodiment, even when a value is already set in the security signal information timer and the security signal is being output to the outside, when a new abnormal winning is detected, the process of step S128 is executed again. The security signal information timer is overwritten with a predetermined time (in this example, 4 minutes). Therefore, when a new abnormal winning is detected during the external output of the security signal, the external output period of the security signal is substantially extended, and a predetermined time (in this example) from the time when the new abnormal winning is detected. 4 minutes) The output of the security signal is continued.

  In this embodiment, the case where the abnormal winning to the second start winning opening 14 is detected using only one switch counter is shown. Different switch counters may be used depending on the number of times detected. In this case, for example, the value of the counter for the first switch is incremented by 1 each time the on state of the second start port switch 14a is detected, and the second switch is detected every time the on state of the winning confirmation switch 14b is detected. The counter value may be incremented by one. In step S127, based on the determination that the difference between the value of the first switch counter and the value of the second switch counter is equal to or greater than a predetermined value (for example, 10), the process proceeds to the second start winning prize opening 14. It may be determined that an abnormal winning has occurred and the process of step S128 is executed to output the security signal to the outside.

  If it is detected that an abnormal winning at the second start winning opening 14 has occurred, the process of step S128 is executed to output a security signal to the outside, and a predetermined error notification command is sent to the effect control microcomputer. It is desirable that error notification can be performed by displaying a predetermined error screen on the effect display device 9 on the effect control microcomputer 100 side.

  Further, for example, in addition to the abnormal winning at the second starting winning opening 14, an abnormal winning at the first starting winning opening 13, an abnormal winning at the large winning opening, an abnormal magnetic error, an abnormal radio wave error, and a communication error are detected. In such a case, if the security signal is output, a different error notification command may be transmitted to the effect control microcomputer 100 for each error type. Then, on the effect control microcomputer 100 side, error notification may be performed by causing the effect display device 9 to display different error screens for each type of error.

  In the above configuration, when power supply is resumed after the power supply to the gaming machine is stopped, an error notification is being issued before the power supply is stopped. The error notification command may be transmitted again to the effect control microcomputer 100. In other words, since the storage content such as RAM is not backed up by the backup power source on the production control microcomputer 100 side, if a power failure occurs, it is not possible to execute the production such as error notification that has been executed until then. However, the error notification can be resumed when the power failure is recovered by configuring the predetermined error notification command to be transmitted again when the power failure is recovered. The game control microcomputer 560 also backs up the value of the security signal information timer in the backup RAM. If the security signal is being output before the power supply is stopped, it is backed up when the power failure is restored. The output of the security signal may be resumed based on the value of the security signal information timer. By providing these configurations, it is possible to prevent an illegal act such as turning off the error notification or stopping the output of the security signal by intentionally turning off the power to the gaming machine.

  FIG. 36 is a block diagram showing various signals output to the terminal board 160. As shown in FIG. 36, in this embodiment, the game control microcomputer 560 mounted on the main board 31 is connected to the terminal board 160 with a symbol determination frequency of 1 signal, a start port signal, a jackpot signal, a jackpot. Two signals, three jackpot signals, a time reduction signal, a winning signal, a security signal, and a high probability signal are output by the information output process (see step S31) on the game control microcomputer 560 side. In this embodiment, the prize ball information is sent from the payout control microcomputer 370 mounted on the payout control board 37 to the terminal board 160 via the main board 31. It is output by the information output process on the 370 side (see step S759).

  The symbol determination number 1 signal is a signal for notifying the number of fluctuations of the first special symbol and the second special symbol. The starting port signal is a signal for notifying the number of winnings to the first starting winning port 13 and the second starting winning port 14. The jackpot 1 signal is a signal for notifying that the jackpot game (during the operation of the special variable winning ball apparatus) is in progress. The jackpot 2 signal is a signal for notifying that the jackpot game (during the operation of the special variable winning ball apparatus) or that the special symbol variation time shortening function is in operation (during the short-time state). The jackpot 3 signal is a signal for notifying that a 15-round jackpot game is in progress. The time reduction signal is a signal for notifying that the special symbol variation time reduction function is operating (in the time reduction state).

  In addition, as described above, the winning signal indicates that a predetermined payout condition for paying out a predetermined number (in this embodiment, 10 balls) of winning balls is satisfied (the first start winning port 13, This is a signal indicating that a winning has occurred in the second start winning port 14, the big winning port, and the normal winning ports 29, 30. The award ball has not been paid out.

  The security signal is a signal indicating the security state of the gaming machine. Specifically, when it is determined that an abnormal winning to the second starting winning opening 14 has occurred based on the detection result of the second starting opening switch 14a and the detection result of the winning confirmation switch 14b, the security signal is It is output to an external device such as a hall computer for a predetermined period (for example, 4 minutes). Also, when the gaming machine is turned on and the initialization process is executed, a security signal is output to an external device such as a hall computer for a predetermined period (for example, 30 seconds).

  It should be noted that the signal output externally as the security signal is not limited to that shown in this embodiment. For example, not only abnormal winning at the second starting winning opening 14, but abnormal winning at the first starting winning opening 13, the large winning opening, or the normal winning openings 29, 30 can be detected and output as a security signal to the outside. You may comprise as follows. In addition, for example, when abnormal magnetism is detected by a magnet sensor provided in a gaming machine or when abnormal radio waves are detected by a radio wave sensor provided in a gaming machine, it is configured so that it can be output externally as a security signal. Also good. In addition, for example, when an abnormality of various switches provided in a gaming machine is detected (for example, when an occurrence of a short circuit is detected by determining that an input value exceeds a threshold value), it can be externally output as a security signal. You may comprise as follows. In this way, even if an abnormal winning at the big prize opening, abnormal magnetic error, or abnormal radio wave error is configured to be output as a security signal from the common connector CN8 of the terminal board 160, even one signal line can be connected. In this case, error detection can be performed by an external device such as a hall computer, and the work load related to error detection can be reduced.

  Further, for example, even when a communication error between the game control microcomputer 560 and the payout control microcomputer 370 is detected, it can be externally output as a security signal from the common connector CN8 of the terminal board 160. May be. In this case, for example, the game control microcomputer 560 determines that a communication error has occurred based on failure to receive a connection OK command or a prize ball number reception command (to be described later) from the payout control microcomputer 370, and the terminal The security signal may be externally output from the common connector CN8 of the board 160. Further, for example, the game control microcomputer 560 determines that a communication error has occurred based on the value of any error bit in the status register of the serial communication circuit 505 being set, and the terminal board 160 has a common The connector CN8 may be externally output as a security signal.

  In addition to the signal line and connector CN8 for the security signal, a signal line and connector dedicated to communication errors between the game control microcomputer 560 and the payout control microcomputer 370 may be provided on the terminal board 160. When a communication error between the game control microcomputer 560 and the payout control microcomputer 370 is detected, an external device such as a hall computer is transmitted via the terminal board 160 as a signal different from the security signal. May be output.

  The high probability signal is a signal indicating that the gaming state is controlled to a high probability state (probability change state). In this embodiment, the high-accuracy signal is externally output through the terminal board 160 until a predetermined condition is satisfied after the power failure is restored (specifically, until the first big hit occurs).

  Further, as described above, the prize ball information is a signal that is output every time a specific number (10 in this example) of prize ball payouts is detected. In this embodiment, a predetermined payout condition for paying out a predetermined number of prize balls (10 balls in this embodiment) is satisfied (first start winning opening 13, second start winning prize). The winning signal is output to the outside based on the fact that the winning to the mouth 14, the big winning opening, the normal winning openings 29, 30 has occurred), and the number of winning balls can be grasped on the hall side based on the winning signal. Therefore, the prize ball information may be configured not to be output externally.

  37 to 40 are flowcharts showing the information output processing in step S31. Of the processes shown in FIGS. 37 to 40, steps S1002 to S1020 are processes for outputting a start port signal, steps S1021 to S1023 are processes for outputting a winning signal, and steps S1031 to S1036. Is a process for outputting one signal for the number of symbol determinations, and steps S1050 to S1068 are processes for outputting one signal for big hit, two signals for big hit, three signals for big hit, and a short time signal. Steps S1069 to S1074 are processes for outputting a security signal, and steps S1075 to S1077 are processes for outputting a high-accuracy signal.

  In the information output process, the CPU 56 first sets the address of the start port information setting table in the pointer (step S1002) and loads the number of processes pointed to by the pointer (step S1003). The start port information setting table includes the number of processes (= 2), two start port switch input bits (first start port switch input bit determination value (01 (H))) and second start port switch input bit determination value ( 02 (H))) is set. The first start port switch input bit determination value is a determination value for determining whether or not there is a start winning in the first start winning port 13, and the second start port switch input bit determination value is a second value. This is a determination value for determining whether or not there is a start winning in the start winning opening 14. In step S1003, since the pointer points to the address of the number of processes in the start port information setting table, the data of the number of processes (= 2) in the start port information setting table is loaded.

  Next, the CPU 56 loads the contents of the switch-on buffer into the register (step S1004), and sets the switch-on buffer as switch input data (step S1005). The pointer is incremented by 1 (step S1006), the start port switch input bit pointed to by the pointer is loaded into the register (step S1007), and the logical product of the start port switch input bit and the switch input data is obtained (step S1008). In this case, when the number of processes is 1, the first start port switch input bit is loaded and the logical product of the switch input data is obtained. When the number of processes is 2, the second start port switch input is obtained. The bit is loaded and the logical product of the switch input data is taken. When the number of processes is 1 and the first start port switch 13a is on, the logical product operation result is 01 (H). When the number of processes is 2 and the second start port switch 14a is on, the logical product operation result is 02 (H). When the first start port switch 13a and the second start port switch 14a are not turned on, the logical product operation result is 00 (H).

  If the logical operation result is 0 (Y in step S1009), the process proceeds to step S1015. If the result of the logical product is not 0 (N in step S1009), it is determined that a winning has occurred in the first starting winning port 13 or the second starting winning port 14, and the starting port information storage counter is loaded into the register. (Step S1010). The start port information storage counter is a counter that counts the number of remaining outputs of the start port signal (that is, the remaining number of start winnings that have not been output from the start port signal). Next, the CPU 56 adds 1 to the start port information storage counter (step S1011). Then, it is confirmed whether the calculation result (added result) is not 0 (step S1012). When the calculation result is 0 (N in step S1012), 1 is subtracted from the calculation result (step S1013). Then, the calculation result is stored in the start port information storage counter (step S1014).

  In this embodiment, with respect to winning at the second start winning opening 14, only the ON state of the second start opening switch 14a on the upstream side in the second start winning opening 14 is detected, step S1010. Although the case where the subsequent processing is executed and the start port signal is output is shown, the on-state of both the upstream second start port switch 14a and the downstream winning confirmation switch 14b is detected. The start port signal may be output. Similarly, when the first start winning opening 13 is also provided with a downstream winning confirmation switch, the upstream first start opening switch 13a is also provided for winning the first starting winning opening 13. And a start port signal may be output based on the detection of the ON state of both the winning prize confirmation switch and the downstream winning confirmation switch.

  Next, the CPU 56 subtracts 1 from the number of processes (step S1015), and determines whether the number of processes is not 0 (step S1016). When the number of processes is not 0 (Y in step S1016), the process proceeds to step S1004. In this embodiment, since the gaming machine includes the first start winning opening 13 and the second starting winning opening 14, 2 is set as the initial value of the number of processes, and the processing of steps S1004 to S1016 is 2. Will be executed once.

  If it is determined in step S1016 that the number of processes is 0 (N in step S1016), the CPU 56 sets an initial value (00 (H)) in the information buffer formed in the RAM 55 (step S1017). Next, the CPU 56 sets the start port output bit position (bit 1 of the output port 1 in the example shown in FIG. 6) of the information output buffer formed in the RAM 55 (step S1018). Then, the CPU 56 sets the address of the start port information storage timer in the pointer (step S1019), and executes a winning timer setting process (step S1020).

  Next, the CPU 56 sets the winning output bit position (bit 6 of the output port 1 in the example shown in FIG. 6) of the information output buffer (step S1021). Then, the CPU 56 sets the address of the winning information storage timer in the pointer (step S1022), and executes a winning timer setting process (step S1023).

  In this embodiment, a common subroutine (winning timer set process) is executed when the start signal is output externally and when the winning signal is output externally, so that the start port output bit position of the information buffer is output. Is set and a start port signal is output, a winning output bit position of the information buffer is set, and a winning signal is output. Details of the winning timer setting process will be described later (see FIG. 41).

  Next, the CPU 56 loads the symbol determination number 1 information timer into the register (step S1031), reflects the state of the symbol determination number 1 information timer in the flag register (step S1032), and the symbol determination number 1 information timer times out. It is determined whether or not (step S1033). In this embodiment, in the special symbol variation processing (see step S303), when the variation time is timed out, when the variation of the special symbol is stopped, the symbol determination number 1 information timer outputs the symbol determination number output time (in this example, 0.500 seconds) is set, and when the symbol determination count output time has not elapsed, it is determined that the symbol determination count 1 information timer has not timed out, and when the symbol determination count output time has elapsed (symbol determination count) When the value 1 information timer value is 0), it is determined that the symbol determination time 1 information timer has timed out.

  If the symbol determination count 1 information timer has not timed out (N in step S1033), the symbol determination count 1 information timer is decremented by 1 (step S1034), and the calculation result is stored in the symbol determination count 1 information timer (step S1035). . Then, the design buffer count 1 output bit position of the information buffer (bit 0 of the output port 1 in the example shown in FIG. 6) is set (step S1036). When the symbol determination number 1 output bit position of the information buffer is set, the information buffer is set to the output value in the subsequent step S1102, and the output value is output to the output port 1 in step S1103. Is output from the output port 1 (becomes ON state). If the symbol determination number 1 information timer times out (Y in step S1033), the process of step S1036 is not executed, and as a result, the symbol determination number 1 signal is turned off.

  Each time the change of the first special symbol and the second special symbol is stopped (the stopped symbol is fixed) by the processing of steps S1031 to S1036 described above, the symbol determination number 1 signal is output as the symbol determination number output time (for example, 500 ms). Turns on.

  Next, the CPU 56 loads the special symbol process flag (step S1050), compares the value of the special symbol process flag with the special winning opening opening pre-processing designation value (“5”) (step S1051), and the special symbol process flag. It is determined whether the value of is less than 5 (step S1052). When the value of the special symbol process flag is less than 5 (Y in step S1052), the process proceeds to step S1058. When the value of the special symbol process flag is 5 or more (N in step S1052), the value of the special symbol process flag is compared with the small hit release pre-processing specified value (“8”) (step S1053), and the special symbol is processed. It is determined whether or not the value of the process flag is 8 or more (step S1054). When the value of the special symbol process flag is 8 or more (Y in step S1054), the process proceeds to step S1058. When the value of the special symbol process flag is less than 8 (N in Step S1054), the output buffer position of one big hit in the information buffer is set (Step S1055). Further, the big output 2 output bit position of the information buffer is set (step S1056). When one output bit position of jackpot and two output bit positions of jackpot of the information buffer are set, the information buffer is set to an output value in the subsequent step S1102, and the output value is output to the output port 1 in step S1103. One signal and two jackpot signals are output from the output port 1 (become turned on).

  Further, the CPU 56 executes a time reduction check process for confirming whether or not it is in the time reduction state (step S1058), and determines whether or not it is in the time reduction state (step S1059). Specifically, the CPU 56 determines whether or not it is in the time reduction state by checking whether or not the time reduction flag that is set when shifting to the time reduction state is set. If the time-short state is set (Y in step S1059), the time-short output bit position of the information buffer is set (step S1060). When the time-short output bit position is set, the time buffer signal is output from the output port 1 by setting the information buffer to the output value in the subsequent step S1102 and outputting the output value to the output port 1 in step S1103. (Turns on) Also, the big output 2 output bit position of the information buffer is set (step S1061). When the jackpot 2 output bit position is set, the information buffer is set to the output value in the subsequent step S1102, and the output value is output to the output port 1 in step S1103, whereby the jackpot 2 signal is output from the output port 1. (Turns on).

  Further, the CPU 56 loads the special symbol process flag (step S1062), compares the value of the special symbol process flag with the special winning opening opening pre-processing designation value (“5”) (step S1063), and sets the special symbol process flag. It is determined whether or not the value is less than 5 (step S1064). When the value of the special symbol process flag is less than 5 (Y in step S1064), the process proceeds to step S1069. When the value of the special symbol process flag is 5 or more (N in step S1064), the value of the special symbol process flag is compared with the small hit release pre-processing designation value (“8”) (step S1065). It is determined whether or not the value of the process flag is 8 or more (step S1066). When the value of the special symbol process flag is 8 or more (Y in step S1066), the process proceeds to step S1069. When the value of the special symbol process flag is less than 8 (N in step S1066), the special symbol normal processing loads the contents of the big hit type buffer set based on the big hit type determination result, and the normal big hit or the probable big hit It is confirmed whether or not there is (step S1067). Whether or not a normal big hit or a probable big hit can be determined, for example, by checking the contents of the big hit type buffer set in the special symbol normal process. For example, the jackpot type buffer stores the contents of the jackpot type determined by the special symbol normal processing and the contents indicating the jackpot determination result. For example, “01” is a normal jackpot, “02” is a probable big hit, “ 03 ”is suddenly regarded as a promising big hit. If the contents of the big hit type buffer are “01” or “02”, it is determined that the big hit is a normal big hit or a probable big hit. In this case, the big output 3 output bit position of the information buffer is set (step S1068). When the jackpot 3 output bit position is set, the information buffer is set to the output value in the subsequent step S1102, and the output value is output to the output port 1 in step S1103, so that the jackpot 3 signal is output from the output port 1. (Turns on).

  By the processing of steps S1050 to S1068 described above, one big hit signal, two big hit signals, three big hit signals and a short time signal corresponding to the type of big hit and the gaming state are output (turned on).

  Next, the CPU 56 loads the security signal information timer (step S1069), reflects the state of the security signal information timer in the flag register (step S1070), and determines whether the security signal information timer has timed out (step S1070). S1071). In this embodiment, it is determined that the detection difference between the second start opening switch 14a and the winning confirmation switch 14b has reached a predetermined value (10 in this example) or more, and it is determined that an abnormal winning at the start winning opening has occurred. If the predetermined time (4 minutes in this example) is set in the security signal information timer (see steps S127 and S128 in the switch normality / abnormality check process), and the predetermined time has not elapsed, When it is determined that the signal information timer has not timed out and the predetermined time has elapsed (when the value of the security signal information timer is 0), it is determined that the security signal information timer has timed out.

  In this embodiment, when the power supply to the gaming machine is started and the initialization process is executed, a predetermined time (30 seconds in this example) is set in the security signal information timer (in the main process). When the predetermined time has not elapsed, it is determined that the security signal information timer has not timed out, and when the predetermined time has elapsed (when the value of the security signal information timer is 0), It is determined that the security signal information timer has timed out.

  If the security signal information timer has not timed out (N in step S1071), the security signal information timer is decremented by 1 (step S1072), and the calculation result is stored in the security signal information timer (step S1073). Then, the security signal output bit position of the information buffer (bit 7 of the output port 1 in the example shown in FIG. 6) is set (step S1074). When the security signal output bit position of the information buffer is set, the security signal is output from the output port 1 by setting the information buffer to the output value in the subsequent step S1102, and outputting the output value to the output port 1 in the step S1103. Is output (turns on). If the security signal information timer times out (Y in step S1071), the security signal is turned off as a result of not executing the process in step S1074.

  By the processing of steps S1069 to S1074 shown above, initialization processing is executed until 4 minutes have elapsed after the abnormal winning at the second start winning opening 14 is detected, or at the start of power supply to the gaming machine. Until 30 seconds elapse, a security signal is output using the common connector CN8 of the terminal board 160. If a new abnormal prize is detected during the output of the security signal, the output of the security signal is continued until 4 minutes have elapsed since the last abnormal prize was detected.

  Next, the CPU 56 checks whether or not the high-accuracy output permission flag is set (step S1075). Note that the high-accuracy output permission flag is set when the hot start process is executed at the start of power supply to the gaming machine (see step S9103). If the high-accuracy medium output permission flag is set, the CPU 56 checks whether or not the probability variation flag is set (step S1076). If the probability change flag is set, the CPU 56 sets the high-accuracy medium signal output bit position (bit 7 of the output port 0 in the example shown in FIG. 6) of the information buffer (step S1077). When the high-accuracy signal output bit position of the information buffer is set, the information buffer is set to the output value in the subsequent step S1102, and the output value is output to the output port 0 in step S1103. Output from output port 0 (becomes ON state). In this embodiment, after the power failure recovery, if the first big hit occurs, the high-accuracy output permission flag is reset (see step S136), and as a result, the high-accuracy medium signal is turned off.

  In this embodiment, the case where the high-accuracy output permission flag is reset when the first big hit occurs is shown. However, the timing when the high-accuracy output permission flag is reset is shown in this embodiment. It is not limited to what is shown. For example, the high-accuracy medium output permission flag may be reset even when a small hit occurs. In addition, for example, when the probability variation state is configured to end based on the fact that the variation display is executed a predetermined number of times after being controlled to the probability variation state, the certain number of variations display is terminated and the probability variation state is changed. It may be configured to reset the high-accuracy medium output permission flag when the process ends.

  If the probability variation flag is set after the power failure is restored by the processing of steps S1075 to S1077 described above, the high-probability medium signal is maintained until a predetermined condition is satisfied (in this example, until the first big hit occurs). Is output (turns on). That is, in this embodiment, as already described, even if the power supply to the gaming machine is stopped, the probability variation flag is held in the backup RAM for a predetermined period. Therefore, if the probability change state was controlled before the occurrence of a power failure, the probability change flag should be retained in the backup RAM. Until then, the output of the high-accuracy signal is continued.

  In this embodiment, when the first big hit occurs, the high-accuracy medium output permission flag is reset (see step S136), so that the high-accuracy medium signal is not output thereafter. Therefore, in this embodiment, if the predetermined condition is satisfied (in this example, if the first big hit occurs), the output of the high-accuracy signal is prohibited.

  In this embodiment, only the process of setting the high-accuracy medium output permission flag is performed at the time of executing the power failure recovery process of the main process, and it is confirmed whether or not the probability change flag is set in the information output process of step S31. However, the processing method for outputting the high-accuracy signal is not limited to that shown in this embodiment. For example, it is confirmed whether or not the probability change flag is set in the power failure recovery processing of the main processing, and if it is set, the high accuracy signal output bit position of the information buffer is set or A high accuracy signal may be output by performing processing such as setting a timer. Even when the probability variation flag is checked in the power failure recovery process and the output of the high-accuracy signal is started in this way, the high-level signal is output when a predetermined condition is satisfied, such as when the first big hit occurs. It may be configured to perform control so as to stop the output of the accuracy signal, and to control so as not to output the accuracy signal thereafter.

  In this embodiment, for each timer interrupt, the output bit position of the corresponding signal is set in the information output processing shown in FIGS. 37 to 40 (steps S1036, S1055, S1056, S1060, S1061, S1068, S1074). , S1077), and steps S1102 and S1103 are executed to externally output from the output ports 0 and 1, but the output bit value corresponding to the output state of each signal changes from the previous setting. It doesn't change unless it is done. For example, if the value of the corresponding output bit is set to “1”, the signal continues to be output while it is set.

  FIG. 41 is a flowchart showing the winning timer setting process executed in steps S1020 and S1023 of the information output process. In the winning timer setting process, the CPU 56 first loads the information storage timer pointed to by the pointer (step S2001), reflects the state of the loaded information storage timer in the flag register (step S2002), and a signal is being output. Is determined (step S2003). In this case, when the winning timer set process is executed in step S1020 of the information output process, the start port information storage timer is loaded and the state is reflected in the flag register, and whether or not the start port signal is being output. It will be determined. When the winning timer set process is executed in step S1023 of the information output process, the winning information storage timer is loaded and the state is reflected in the flag register to determine whether or not the winning signal is being output. Will do.

  The start port information storage timer is a timer for measuring an on time and an off time (for example, an on time of 100 ms and an off time of 100 ms) of the start port signal. If the value of the start port information storage timer is not 0, it is determined that the start port signal is being output. If the value of the start port information storage timer is 0, it is determined that the start port signal is not being output. The winning information storage timer is a timer for measuring an on time and an off time (for example, an on time of 100 ms and an off time of 100 ms) of the winning signal. If the value of the winning information storage timer is not 0, it is determined that the winning signal is being output. If the value of the winning information storage timer is 0, it is determined that the winning signal is not being output.

  If the signal (start port signal or winning signal) is being output (Y in step S2003), the process proceeds to step S2012. If the signal (start port signal or winning signal) is not being output (N in step S2003), the CPU 56 adds 1 to the pointer value (step S2004). In this embodiment, in the ROM 54, the start port information storage counter is set in the area next to the area where the start port information storage timer is set, and the area next to the area where the winning information storage timer is set. Is set with a winning information storage counter. Therefore, by executing the process of step S2004, the pointer value indicates the address of the start port information storage counter or the winning information storage counter.

  Next, the CPU 56 loads the information storage counter (start port information storage counter or winning information storage counter) pointed to by the pointer (step S2005), and the state of the loaded information storage counter (start port information storage counter or winning information storage counter) Is reflected in the flag register (step S2006), and it is determined whether there is a remaining number of output times of the signal (start port signal or winning signal) (step S2007).

  When the first start port switch 13a and the second start port switch 14a are turned on (N in step S1009), the start port information storage counter is incremented (the first start port switch 13a or the second start port switch 14a). 1 is added if either one is on, and 2 is added if both are on. (See step S1011.) Therefore, it is determined that there is a remaining number of output times of the start port signal. Become. In addition, when a winning occurs at any of the winning openings (the first starting winning opening 13, the second starting winning opening 14, the large winning opening, the normal winning openings 29, 30), the number of planned winning balls is ten. Each time it accumulates, the winning information storage counter is incremented (see step S5122), so it is determined that there is a remaining number of output times of the winning signal.

  If there is no remaining number of outputs of the signal (start port signal or winning signal) (Y in step S2007), the winning timer setting process is terminated. If there is a remaining number of output times of the signal (start port signal or winning signal) (N in step S2007), the CPU 56 subtracts 1 from the upper storage counter (start port information storing counter or winning information storing counter) pointed to by the pointer. (Step S2008) The calculation result (the result obtained by subtracting 1) is stored in the information storage counter (start port information storage counter or winning information storage counter) (Step S2009). Then, the winning information operating time (50) is set in the register (step S2010). The winning information operating time (50) is a time for which a 4 ms timer interrupt is executed 50 times, that is, a time of 0.200 seconds (200 ms). In this embodiment, the case where the same value is set as the winning information operating time is shown when the start opening signal is output and when the winning signal is output. However, different values are set. Also good.

  Next, the CPU 56 subtracts 1 from the value of the pointer (step S2011). By executing the processing in step S2011, the pointer value returns to the state indicating the address of the start port information storage timer or the winning information storage timer again. Then, the process proceeds to step S2012.

  Next, if the winning information operating time is not set in step S2010, the CPU 56 subtracts 1 from the information storage timer (start port information storing timer or winning information storing timer) pointed to by the pointer, and the winning information operating time is determined in step S2010. If it is set, 1 is subtracted from the winning information operating time (step S2012). Then, the calculation result (the result obtained by subtracting 1) is stored in the information storage timer (start port information storage timer or winning information storage timer) pointed to by the pointer (step S2013).

  The CPU 56 compares the calculation result with the winning information on time (25) (step S2014), and determines whether the calculating result is shorter than the winning information on time (step S2015). The winning information on time (25) is a time for which a 4 ms timer interruption is executed 25 times, that is, a time of 0.100 seconds (100 ms).

  When the calculation result is not shorter than the winning information on time, that is, when the calculating result (remaining time of the starting information storing timer or the winning information storing timer) is longer than the winning information on time (100 ms) ( In step S2015 N), the CPU 56 loads the information buffer (step S2016), and obtains a logical sum of the loaded information buffer value and the information output buffer value (step S2017). Then, the CPU 56 stores the calculation result of step S2017 in the information buffer (step S2018).

  If the winning timer set process is executed in step S1020 of the information output process by executing the processes of steps S2016 to S2018, the value of the information output buffer in which the start port output bit is set in step S1018 Is obtained, the start port output bit position of the information buffer (bit 1 of the output port 1 in the example shown in FIG. 6) is set. When the start port output bit position of the information buffer is set, the information buffer is set to the output value in step S1102 of the subsequent information output processing, and the output value is output to the output port 1 in step S1103, thereby starting the information buffer. The mouth signal is output from the output port 1.

  Further, when the winning timer set process is executed in step S1023 of the information output process by executing the processes of steps S2016 to S2018, the value of the information output buffer in which the winning output bit is set in step S1011 Is obtained, the winning output bit position of the information buffer (bit 6 of the output port 1 in the example shown in FIG. 6) is set. Then, when the winning output bit position of the information buffer is set, the information buffer is set to the output value in step S1102 of the subsequent information output processing, and the output value is output to the output port 1 in step S1103. Is output from the output port 1.

  In steps S1002 to S1020 of the information output process and the winning timer setting process shown in FIG. 41, the first start winning opening 13 is won (the first start opening switch 13a is turned on) and the second starting winning opening 14 is won (the first When the 2 start port switch 14a is turned on), a start port signal is output. That is, after the start port signal is turned on for 100 ms, it is turned off for 100 ms. By inputting this start port signal to the hall computer, it is possible to recognize the number of winnings to the first start winning port 13 and the second starting winning port 14.

  Since the start port signal is turned on for 100 ms and then turned off for 100 ms, the next start port is turned on after the 100 ms off state even if a start winning is continuously generated in a short time. A signal is output. That is, the start port signals are output with an interval of at least 100 ms.

  Thus, since the start port signals are output at intervals of at least 100 ms, the hall computer can reliably grasp the total number of start winning prizes.

  In addition, by the information output processing steps S1021 to S1023 and the winning timer setting process shown in FIG. 41, any one of the winning ports (first starting winning port 13, second starting winning port 14, large winning port, ordinary winning port 29, A winning signal is output every time the winning number 30) is won and the planned number of winning balls is accumulated. That is, after the winning signal is turned on for 100 ms, it is turned off for 100 ms. By inputting this winning signal to the hall computer, the expected number of winning balls can be recognized.

  Since the winning signal is turned on for 100 ms and then turned off for 100 ms, even if a start winning is continuously generated in a short time, the next winning signal is displayed after the off state for 100 ms. Is output. In other words, the winning signals are output with an interval of at least 100 ms.

  Thus, the winning signals are output at intervals of at least 100 ms, so that the hall computer can reliably grasp the total number of planned winning balls.

  In this embodiment, when the winning signal is output to the outside, first, the process of step S2012 is executed to subtract the value of the winning information storage timer, and then the steps S2018, S1102, and S1103 are executed to receive the winning signal. However, the processing order of the subtraction processing of the winning information storage timer and the external output processing of the winning signal is not limited to that shown in this embodiment. For example, first, the same processing as in steps S2018, S1102, and S1103 is executed to execute the external output processing of the winning signal, and then the same processing as in step S2012 is performed to subtract the value of the winning information storage timer. Also good.

  Next, the output timing of the high-accuracy signal will be described. FIG. 42 is an explanatory diagram showing the output timing of the high-accuracy signal. In this embodiment, when the hot start process is executed at the start of power supply to the gaming machine (see step S91), the information output is based on the fact that the high-accuracy output permission flag is set (see step S9103). In the processing (see step S31), the processing of steps S1075 to S1103 is executed, and as shown in FIG. 42, the output of the high-accuracy signal to the external device such as the hall computer is started from the connector CN9 of the terminal board 160. Is done.

  Thereafter, the game control process can be executed, and when a game is played by the player, as shown in FIG. 42, the variable display is executed in accordance with the start winnings to the first starting winning port 13 and the second starting winning port 14 Is done. In this case, even if the fluctuation display is executed, if the fluctuation display result is “out of range”, the information output process (see step S31) is performed in step S1075 based on the fact that the high-accuracy output permission flag is maintained. Through the process of S1103, the output of the high-accuracy signal is continued.

  When the first big hit occurs as a result of the variable display, the high-accuracy output permission flag is reset at the end of the variable display (see step S136). Thereafter, when it is determined as N in step S1075 of the information output process (see step S31), the processes of steps S1076 and S1077 are not executed, and the output of the high-accuracy signal is stopped as shown in FIG.

  Next, the security signal output timing will be described. FIG. 43 is an explanatory diagram showing the output timing of the security signal. In this embodiment, when initialization processing is executed at the start of power supply to the gaming machine (see steps S10 to S14), a predetermined time (in this example, 30 seconds) is set in the security signal information timer. Based on the above (see step S14a), the processing of steps S1069 to S1074, S1102, and S1103 is executed in the information output processing (see step S31), and the connector CN8 of the terminal board 160 is connected as shown in FIG. A security signal is output to an external device such as a hall computer. Further, after the power supply to the gaming machine is started, the detection error between the detection number of the start port switch 14a and the detection number of the winning confirmation switch 14b becomes a predetermined value (10 in this example) or more. Even when it is determined that an abnormal winning at the second start winning opening 14 has occurred (see steps S121 to S127), a predetermined time (4 minutes in this example) is set in the security signal information timer. Based on the above (see step S128), the processing of steps S1069 to S1074, S1102, and S1103 is executed in the information output process (see step S31), and as shown in FIG. 43 (A), from the connector CN8 of the terminal board 160. A security signal is output to an external device such as a hall computer. As described above, in this embodiment, the common terminal board 160 is used when the initialization process is executed when power supply to the gaming machine is started and when the abnormal winning at the second start winning opening 14 is detected. A security signal is externally output from the connector CN8.

  Further, in this embodiment, when the security signal is being output to the outside, when an abnormal winning to the second start winning opening 14 is newly detected, the security signal output period is substantially extended, Finally, the output of the security signal is continued until a predetermined time (4 minutes in this example) has elapsed since the abnormal winning to the second start winning opening 14 was detected. For example, in the case where the output of the security signal is started based on the fact that the initialization process is executed when the power supply to the gaming machine is started, as shown in FIG. Security signal output should continue. However, as shown in FIG. 43B, even before 30 seconds have elapsed, the detection error between the number of detections of the second start port switch 14a and the number of detections of the winning confirmation switch 14b is a predetermined value (this In the example, there is a possibility that it becomes 10) or more and it is determined that an abnormal winning to the second start winning opening 14 has occurred. In this case, a predetermined time (4 minutes in this example) is overwritten and written in the security signal information timer based on the detection of the occurrence of the abnormal winning (see step S128), and the information output process (step S31). In step S1069 to S1074, S1102, and S1103, the security signal is output as it is as shown in FIG. However, since the value of the security signal information timer has been overwritten to 4 minutes, in this case, as shown in FIG. 43 (B), 4 minutes have elapsed since the abnormal winning to the start winning opening 14 was detected. Until then, the output of the security signal is continued, and the output of the security signal is substantially extended.

  Further, for example, in the case where the output of the security signal is started based on the detection of the abnormal winning at the second start winning opening 14, as shown in FIG. Security signal output should continue. However, as shown in FIG. 43C, even before the lapse of 4 minutes, the detection error between the number of detections of the second start port switch 14a and the number of detections of the winning confirmation switch 14b is a predetermined value (this In the example, 10) or more, there is a possibility that it is determined that a new abnormal winning to the second start winning opening 14 has occurred. In this case, a predetermined time (4 minutes in this example) is overwritten and written in the security signal information timer based on the newly detected occurrence of an abnormal winning (see step S128), and information output processing ( In step S31), the processing of steps S1069 to S1074, S1102, and S1103 is executed, and the output of the security signal is continued as shown in FIG. However, since the value of the security signal information timer is overwritten in 4 minutes, in this case, as shown in FIG. 43 (C), from the time when the abnormal winning to the second start winning opening 14 is newly detected. The output of the security signal is continued until 4 minutes have elapsed, and the output of the security signal is substantially extended.

  If an abnormal winning to the second start winning port 14 is detected while the security signal is already being output, the output of the security signal being output is terminated and the next security signal is output again. In this embodiment, as shown in FIGS. 43 (B) and 43 (C), the security signal is output by extending the output time of the security signal being output as it is. The processing load for the output process of the security signal is reduced, and the program capacity for the output process of the security signal is reduced. In other words, when it is configured to start the output of the next security signal after the output of the security signal being output is completed, the output of the next security signal is started after the output of the security signal is completed. For example, a process for measuring the interval time until completion is required, which increases the processing load and the program capacity. In contrast, in this embodiment, since the value of the security signal information timer is overwritten as it is, if only the process of setting the value of the security signal information timer is performed (see steps S14a and S128), the security signal is output. It is possible to prevent the increase in processing load and program capacity.

  In this embodiment, when the initialization process is executed at the start of power supply to the gaming machine, a security signal is output for 30 seconds, and an abnormal winning at the second start winning opening 14 is detected. In this case, the case where the security signal is output for 4 minutes is shown, but the output time of the security signal is not limited to that shown in this embodiment. In other words, it is possible to recognize whether the initialization process has been executed or whether an abnormal winning to the second start winning opening 14 has been detected, and when the initialization process has been executed and the second start winning opening 14. What is necessary is just to output a security signal over an output time different from when an abnormal winning is detected.

  In this embodiment, the security signal output period when an abnormal winning to the second starting winning opening 14 is detected is set to 4 minutes in the case of an abnormal winning to the second starting winning opening 14. In order to output a security signal for as long a time as possible, it is set to a substantially maximum time that can be set. That is, in this embodiment, since the game control microcomputer 560 can set a 2-byte value as the value of the security signal information timer, the maximum value is set to “FFFF (H) = 65535 in the security signal information timer. "Can be set. Therefore, in this embodiment, “60000”, which is almost the maximum value, is set in the security signal information timer, and the timer interruption period is 4 ms. Therefore, security is performed for 4 ms × 60000 = 4 minutes. A signal is output.

  Next, the operation of the payout control means (the payout control microcomputer 370) will be described. FIG. 44 is an explanatory diagram showing an example of output port assignment in the payout control means. As shown in FIG. 44, the output port 0 outputs a signal of each phase supplied to the payout motor 289 by the stepping motor. In addition, a PRDY signal or an EXS signal is output from the output port 0 to the card unit 50, and a game indicating that the gaming machine is in an error state (in this example, a ball-out error state or a full tank error state). A machine error state signal and a prize ball signal 1 indicating that a prize ball payout has been detected are also output. Further, from the output port 1, each segment output signal of the error display LED 374 by 7 segment LED is output. The output port 1 also outputs prize ball information indicating that ten prize ball payouts have been detected.

  FIG. 45 is an explanatory diagram showing an example of bit assignment of input ports in the payout control means. As shown in FIG. 45, the VL signal, the BRDY signal, and the BRQ signal from the card unit 50 are input to bits 0 to 2 of the input port 0, respectively. A connection signal from the main board 31 is input to bit 4 of the input port 0. In addition, the detection signal of the full switch 48, the detection signal of the ball break switch 187, and the detection signal of the payout motor position sensor 295 are input to the bits 5 to 7 of the input port 0, respectively. In addition, the operation signal from the error release switch 375 and the detection signal of the payout number count switch 301 are input to the bits 0 and 1 of the input port 1, respectively.

  Next, the operation of the payout control means will be described. FIG. 46 is a flowchart showing main processing executed by the payout control means. In the main process, the payout control CPU 371 of the payout control microcomputer 370 first performs necessary initial settings. That is, the payout control CPU 371 first sets the interruption prohibition (step S701). Next, the interrupt mode is set to interrupt mode 2 (step S702), and a stack pointer designation address is set to the stack pointer (step S703).

  Next, the payout control CPU 371 sets a built-in device register (step S704). In the process of setting the internal device register in step S704, the payout control CPU 371 sets the CTC. In this embodiment, one channel of the built-in CTC is used in the timer mode. Therefore, the payout control CPU 371 performs register setting for setting the channel to be used to timer mode, register setting for permitting interrupt generation, and register setting for setting an interrupt vector. The interrupt by the channel is used as a timer interrupt. For example, when it is desired to generate a timer interrupt every 1 ms, a value corresponding to 1 ms is set as an initial value in a predetermined register (time constant register).

  In step S704, the payout control CPU 371 initializes the priority of interrupt processing executed in response to the interrupt request from the serial communication circuit 380. In this case, the payout control CPU 371 initializes the priority order of the interrupt process according to the same process as the priority order initial setting process (see step S15b) performed by the CPU 56 of the game control microcomputer 560.

  In step S <b> 704, the payout control CPU 371 sets the serial communication circuit 380. In this case, the payout control CPU 371 sets the baud rate of the receiving circuit, sets the receiving mode (either 8-bit or 9-bit data format), and sets the parity (the presence or absence of parity, even parity or odd parity). Set). In addition, the control registers of the receiving circuit are initialized and the status registers are initialized. Also, the payout control CPU 371 sets the baud rate of the transmission circuit, sets the transmission mode (either 8-bit or 9-bit data format), and sets the parity (the presence / absence of parity, even parity or odd parity) )I do. Also, each control register of the transmission circuit is initialized.

  The interrupt vector set for the channel set to the timer mode (channel 3 in this embodiment) corresponds to the start address of the timer interrupt process. Specifically, the start address of the timer interrupt process is specified by the value set in the I register and the interrupt vector. In the timer interruption process, a payout control process for controlling the payout means (including at least a process of driving the ball payout device 97 in response to a command signal related to award ball payout from the main board, and a ball payout device 97 in response to a ball lending request. A process for driving the program may be included.

  In this embodiment, the interruption mode 2 is also set in the payout control microcomputer 370. Therefore, an interrupt process based on counting up the built-in CTC can be used. Also, an interrupt processing start address can be set according to the interrupt vector sent by the CTC. The interrupt based on CTC channel 3 (CH3) count-up is an interrupt that occurs when the CPU internal clock (system clock) counts down and the register value becomes “0”, and is used as a timer interrupt. .

  Next, the payout control CPU 371 sets the RAM in an accessible state (step S705), and performs a RAM clear process (step S706). In addition, initial values are set in the flags and counters of the RAM area (step S707). Note that the processing in step S707 includes processing for setting the unpaid-off number counter initial value in the unpaid-out number counter. In the process of step S707, the payout control CPU 371 also performs a process of clearing an error flag indicating a detection state of a payout number abnormality error, a full tank error, and a ball breakage error. In this embodiment, when it is determined that there is a payout number error and the payout number error error specification bit is set in the error flag, the payout number error error specification bit is not cleared until the power is reset. Although it does not recover from the number abnormality error, specifically, when the process of step S707 is executed when the power is turned on, the payout number abnormality error designation bit in the error flag is cleared and the payout number abnormality error is recovered.

  The payout control CPU 371 executes serial communication circuit setting processing for initial setting of the serial communication circuit 380 (step S708). In this case, the payout control CPU 371 causes the serial communication circuit 380 to serially communicate with the game control microcomputer 560 according to the same process as the serial communication circuit setting process (see step S15a) performed by the CPU 56 of the game control microcomputer 560. Make settings for As described above, a part of the initial setting of the serial communication circuit 380 is executed in the setting process of the built-in device register in step S704. Note that all the setting processing of the serial communication circuit 380 may be performed by the serial communication circuit setting processing in step S708.

  Since interruption is prohibited in step S701 of the initial setting process, interruption is permitted before the initialization process is completed (step S709). Thereafter, a loop process for monitoring the occurrence of a timer interrupt is entered.

  As described above, in this embodiment, the built-in CTC of the payout control microcomputer 370 is set so as to repeatedly generate a timer interrupt. When a timer interrupt occurs, the payout control CPU 371 of the payout control microcomputer 370 executes a timer interrupt process.

  FIG. 47 is a flowchart showing an example of timer interrupt processing executed by the payout control means. In the timer interrupt process, the payout control CPU 371 of the payout control microcomputer 370 executes the following process. First, the payout control CPU 371 performs a switch check process (step S751). In the switch check process, the payout control CPU 371 performs a process of confirming the on / off state of the payout number count switch 301 and the error release switch 375 based on the input of the input port 1. Next, the payout control CPU 371 performs an input determination process (step S752). The input determination process is a process of detecting the state of bits 0 to 7 (see FIG. 45) of the input port 0 and reflecting the detection result in a predetermined 1 byte of the RAM (referred to as a sensor input state flag). The payout control CPU 371 checks the state of the sensor input state flag instead of directly checking the state of the input port when performing control based on the state of bits 0 to 7 of the input port 0.

  Next, the payout control CPU 371 executes a prepaid card unit control process for communicating with the card unit 50 (step S753). Next, the payout control CPU 371 executes main control communication processing for communicating with the game control means of the main board 31 (step S754).

  Next, the payout control CPU 371 performs control for paying out the lent balls in response to a ball lending request from the card unit 50, and performs control for paying out the number of prize balls indicated by the prize ball number command from the main board 31. A payout control process to be executed is executed (step S755). In this embodiment, in the case of a big hit game state, and when paying a winning ball based on a win to a big winning opening during a big hit game, at least a predetermined time (in this example, 30 seconds after finishing the final round of the big hit game, and 20 seconds after finishing the ending effect.)

  Next, the payout control CPU 371 executes a payout motor control process (step S756). In the payout motor control process, when the payout motor 289 is to be driven, a process for outputting the patterns of the payout motors φ1 to φ4 to the output port 0 is performed.

  Next, the payout control CPU 371 executes error processing for detecting various errors (step S757). Next, the payout control CPU 371 executes a prepaid card unit error control process for performing error control of the card unit 50 (step S758). Next, the payout control CPU 371 executes information output processing for outputting prize ball information to the main board 31 and outputting the prize ball signal 1 and the gaming machine error state signal to the outside (step S759). Further, display control processing for performing a predetermined display on the error display LED 374 according to the result of the error processing is executed (step S760).

  In the present embodiment, when various errors (for example, a payout number error error, a full tank error, a ball shortage error, a prepaid card unit unconnected error) are detected in error processing to be described later, an error corresponding to the detected error is detected. Bit is set. In the display control process in step S760, the payout control CPU 371 performs a predetermined display on the error display LED 374 based on the fact that the error bit is set.

  In this embodiment, a RAM area (output port 0 buffer, output port 1 buffer) corresponding to the output state of the output port is provided. However, the payout control CPU 371 includes an output port 0 buffer and an output port. The contents of the port 1 buffer are output to the output port (step S761: output processing). The output port 0 buffer and the output port 1 buffer include a payout motor control process (step S756), a prepaid card control process (step S753), a main control communication process (step S754), an information output process (step S759), and a display control process ( It is updated in step S760).

  FIG. 48 is a flowchart showing the main control communication process in step S754. In the main control communication process, the payout control microcomputer 370 (specifically, the payout control CPU 371) executes a main control command reception process (step S740). Then, the payout control CPU 371 executes one of steps S741 to S744 according to the value of the main control communication control code.

  FIG. 49 is a flowchart showing the main control command reception process of step S740 in the main control communication process. In the main control command receiving process, the payout control CPU 371 first checks whether or not a connection signal is input (step S74001). If no connection signal is input, the payout control CPU 101 initializes the transmission circuit and the reception circuit of the serial communication circuit 380 (step S74002). As described above, when the connection signal cannot be received, the transmission circuit and the reception circuit of the serial communication circuit 380 are initialized, so that the command is transmitted even though the connection state with the main board 31 is under an abnormal state. It is possible to prevent a situation in which data is stored in the register or the reception data register. Next, the payout control CPU 371 loads the value of the main control communication control code (step S74003), and checks whether the value of the main control communication control code is a value “0” indicating the main control connection confirmation processing. (Step S74004).

  In this embodiment, in the main control communication process, input of a connection signal from the game control microcomputer 560 is started after power supply to the gaming machine is started, and reception of the first connection confirmation command can be confirmed. The main control connection confirmation process in step S741 is executed. Then, when the reception of the connection confirmation command can be confirmed, the process proceeds to step S742 and subsequent steps, and transmission / reception processing of various payout control commands is executed. Thereafter, if the communication state with the game control microcomputer 560 is maintained normally, one of the processes of steps S742 to S744 is executed, and the main control connection confirmation process of step S741 is basically a game. It will be executed only when the machine is powered on. In step S74004, the fact that the value of the main control communication control code indicates a value other than the main control connection confirmation processing means that after shifting to the processing after step S742, some communication error occurs and the connection signal cannot be input. This is the case. Therefore, if the value of the main control communication control code indicates a value other than the main control connection confirmation process in step S74004, the payout control CPU 371 determines the main control communication error designation bit (game control microcomputer) of the error flag. A bit indicating that an abnormality has occurred in the communication state with 560) is set (step S74005). The error flag is a flag in which various prize ball errors are set, and is formed in a RAM provided in the payout control microcomputer 370. The payout control CPU 371 sets a value “0” indicating main control connection confirmation processing in the main control communication control code (step S74006). If the value of the main control communication control code is “0” indicating the main control connection confirmation process in step S74004, the process proceeds to step S74006.

  Note that the main control confirmation process in step S741 may be executed exceptionally even after the power is turned on to the gaming machine. Specifically, as described above, after determining that the connection signal is not input in step S74001, if the main control connection confirmation process is not being executed in step S74004, the connection signal is not displayed after the game machine is turned on. It is determined that there is a possibility of being disconnected, and the process returns to the main control connection confirmation process (see step S74006), and again confirms the connection state with the game control microcomputer 560 (specifically, a connection confirmation command is issued). Confirm that it can be received (see step S7412). Further, in the main control communication normal processing described later, even if a predetermined period (1050 ms in this example) has elapsed since the connection OK command was transmitted, the connection confirmation command and the prize ball number command are received from the game control microcomputer 560. If not, it is determined that some communication abnormality has occurred, and the process returns to the main control connection confirmation process (see steps S74202 and S74203), and the connection state with the game control microcomputer 560 is confirmed again (specifically, Confirm that the connection confirmation command can be received (see step S7412).

  If the connection signal is input, the payout control CPU 371 checks whether or not the reception error flag is set in the status register of the serial communication circuit 380 (step S74007). For example, the payout control CPU 371 receives the serial communication circuit 380 if a flag indicating a parity error, framing error, noise error, overrun error, or idle line error is set in the status register of the serial communication circuit 380. It is determined that there is an error state.

  If the reception error flag is set, the payout control CPU 371 initializes the reception circuit of the serial communication circuit 380 (step S74008). In this way, by initializing the receiving circuit of the serial communication circuit 380 in the case of a reception error state, it is possible to prevent a situation in which a reception command is stored in the reception data register even though some reception abnormality has occurred. can do. Then, the payout control CPU 371 sets the main control communication error designation bit of the error flag (step S74009).

  If the reception error flag is not set, the payout control CPU 371 loads the contents of the reception buffer (step S74010) and checks whether or not a connection confirmation command is received (step S74011). Specifically, the payout control CPU 371 checks whether or not the content of the loaded reception buffer is “A0 (H)” (see FIG. 13). If the connection confirmation command has been received, the payout control CPU 371 proceeds to step S74014.

  If a connection confirmation command has not been received, the payout control CPU 371 checks whether or not a prize ball number command has been received. In this embodiment, as shown in FIG. 13, the contents of the connection number command should be at least “51 (H)” and less than “60 (H)”. Accordingly, the payout control CPU 371 first checks whether or not the content of the loaded reception buffer is equal to or greater than the minimum prize ball number command value “51 (H)” (step S74012). Next, if the prize ball number command minimum determination value is “51 (H)” or more, the payout control CPU 371 determines whether the content of the loaded reception buffer is less than the prize ball number command maximum determination value “60 (H)”. It is confirmed whether or not (step S74013). If it is less than the winning ball number command maximum determination value “60 (H)”, the payout control CPU 371 determines that a winning ball number command has been received, and proceeds to step S74014.

  In step S74014, the payout control CPU 371 stores the contents of the reception buffer (connection confirmation command, prize ball number command) in the main control communication reception buffer. The main control communication reception buffer is composed of 1 byte and can store only one reception command at a time. Even with this configuration, in this embodiment, the timer interrupt period (1 ms in this example) in the payout control microcomputer 370 is equal to the timer interrupt period (in this example, the game control microcomputer 560). 4 ms), a situation in which a plurality of payout control commands are received within one timer interrupt does not occur, and there is no inconvenience. In addition, even if the award ball number command is received before receiving the first connection confirmation command due to erroneous processing after turning on the power to the gaming machine, the connection confirmation command is subsequently issued. If it is received, it is overwritten and stored in the main control communication reception buffer. Therefore, there is a situation in which the connection confirmation command cannot be confirmed at all in the main control connection confirmation process (step S741) described later, and it becomes impossible to shift to the main control communication normal process. Can be prevented.

  FIG. 50 is a flowchart showing main control connection confirmation processing (step S741) executed when the value of the main control communication control code is zero. In the main control connection confirmation process, the payout control CPU 371 loads the contents of the main control communication reception buffer (step S7411), and confirms whether or not a connection confirmation command is received (step S7412). If a connection confirmation command has been received, the payout control CPU 371 sets a connection OK command (step S7413) and executes main control transmission command conversion processing (step S7414). In the main control transmission command conversion process in step S7414, a process of setting a control state (an error state such as a payout number error error, a ball runout error, a full tank error, a prize ball error, etc.) in the lower 4 bits of the connection OK command is performed. Done. Then, the payout control CPU 371 performs control to transmit the converted connection OK command to the game control microcomputer 560 (step S7415). Specifically, the payout control CPU 371 performs processing for outputting a connection OK command to the transmission register of the serial communication circuit 380.

  The payout control CPU 371 clears the main control communication reception buffer when transmitting the connection OK command in step S7415. By doing so, it is possible to prevent a situation in which the received command is erroneously recognized in the subsequent processing and the erroneous processing is executed.

  Next, the payout control CPU 371 sets a value “1” indicating the main control communication normal process in the main control communication control code (step S7416). Then, the payout control CPU 371 sets a predetermined value (1050 ms in this example) to the main control communication control timer (step S7417).

  51 and 52 are flowcharts showing the main control communication normal process (step S742) executed when the value of the main control communication control code is 1. In the main control communication normal process, the payout control CPU 371 subtracts 1 from the value of the main control communication control timer (step S74201), and checks whether the main control communication control timer has timed out (step S74202).

  In this embodiment, as described above, every time one second elapses after the connection OK command is received from the payout control microcomputer 370, the next connection confirmation command is transmitted from the game control microcomputer 560. Therefore, if the main control communication control timer has timed out in step S74202, it means that the next connection confirmation command is issued even if 1050 ms (see steps S7417 and S74209) elapses more than 1 second after the transmission of the connection OK command. This is a case where reception was not possible. Therefore, the payout control CPU 371 sets a value “0” indicating the main control connection confirmation process in the main control communication control code (step S74203), returns to the main control connection confirmation process, and controls to wait for the recovery of the communication state. To do.

  The payout control CPU 371 clears the main control communication reception buffer if the main control communication control timer has timed out in step S74202. By doing so, it is possible to prevent a situation in which the received command is erroneously recognized in the subsequent processing and the erroneous processing is executed.

  If the main control communication control timer has not timed out, the payout control CPU 371 checks whether or not a reception command is stored in the main control communication reception buffer (step S74204). If a reception command is stored in the main control communication reception buffer, the payout control CPU 371 checks whether or not the received command is a connection confirmation command (step S74205). If a connection confirmation command has been received, the payout control CPU 371 sets a connection OK command (step S74206) and executes main control transmission command conversion processing (step S74207). In the main control transmission command conversion process in step S74207, a process for setting a control state (an error state such as a payout number error error, a ball out error, a full tank error, a prize ball error) in the lower 4 bits of the connection OK command is performed. Done. Then, the payout control CPU 371 performs control to transmit the converted connection OK command to the game control microcomputer 560 (step S74208). Specifically, the payout control CPU 371 performs processing for outputting a connection OK command to the transmission register of the serial communication circuit 380.

  The payout control CPU 371 clears the main control communication reception buffer when the connection OK command is transmitted in step S74208. By doing so, it is possible to prevent a situation in which the received command is erroneously recognized in the subsequent processing and the erroneous processing is executed.

  Then, the payout control CPU 371 sets a predetermined value (1050 ms in this example) in the main control communication control timer (step S74209).

  If the command received in step S74205 is not a connection confirmation command, it means that a prize ball number command has been received. In this case, the payout control CPU 371 checks whether or not the value of the error flag is 0 (step S74210). If the value of the error flag is not 0 (that is, if it is an error state and any error bit is set), the process proceeds to step S74219. If the value of the error flag is 0 (that is, if no error state is set and no error bit is set), the payout control CPU 371 checks whether a BRDY signal is input. (Step S74211). If the BRDY signal is input, the process proceeds to step S74219.

  If the BRDY signal is not input, the payout control CPU 371 loads a payout control state flag indicating the payout control state (step S74212), and confirms whether the winning ball payout operation or the ball lending payout operation is in progress. (Step S74213). Specifically, the payout control CPU 371 specifies a prize ball payout operation designation bit (a bit indicating that a prize ball payout operation is in progress) or a ball lending payout operation designation bit (in a ball lending payout operation) in the payout control state flag. It is confirmed whether or not a bit indicating that is set. If the winning ball payout operation or the ball lending payout operation is being performed, the process proceeds to step S74219. In this embodiment, since the next prize ball number command is transmitted after the prize ball payout operation is finished and the prize ball end command is received, the step is performed unless an abnormality such as a communication error occurs. In S74213, it is not determined that the prize ball payout operation is in progress.

  If neither the winning ball payout operation nor the ball lending payout operation is in progress, the winning ball payout operation based on the received winning ball number command can be started immediately. In this case, the payout control CPU 371 sets the lower 4 bits of the main control communication reception buffer (that is, the number of winning balls set in the winning ball number command) in the unpaid-out number counter (step S74214). The unpaid-out number counter is a counter for counting the number of unpaid out prize balls and rental balls.

  Next, the payout control CPU 371 performs control to transmit a prize ball number acceptance command to the game control microcomputer 560 (step S74215). Specifically, the payout control CPU 371 performs processing for outputting a prize ball number acceptance command to the transmission register of the serial communication circuit 380.

  The payout control CPU 371 clears the main control communication reception buffer when it transmits a prize ball number acceptance command in step S74215. By doing so, it is possible to prevent a situation in which the received command is erroneously recognized in the subsequent processing and the erroneous processing is executed.

  Next, the payout control CPU 371 sets a value “3” indicating the main control communication end process in the main control communication control code (step S74216). Then, the payout control CPU 371 sets a predetermined value (1 second in this example) in the main control communication control timer (step S74218). It should be noted that if a prize ball payout operation is not completed after one second has elapsed after the prize ball number acceptance command is transmitted based on the value set in step S74218, a prize ball preparation command is transmitted.

  In step S74219, the payout control CPU 371 stores the lower 4 bits of the main control communication reception buffer (that is, the number of prize balls set with the prize ball number command) in the main control communication prize ball number buffer. That is, in this case, an error state has occurred, or during the winning ball payout operation, the ball lending payout operation, or during the ball lending preparation, the winning ball payout operation based on the received winning ball number command is immediately performed. Can't start. Therefore, the payout control CPU 371 suspends the reply of the prize ball number acceptance command and temporarily saves the prize ball number set in the prize ball number command in the main control communication prize ball number buffer.

  Next, the payout control CPU 371 sets a command for preparing a prize ball (step S74220), and executes main control transmission command conversion processing (step S74221). In the main control transmission command conversion process in step S74221, a control state (error state such as a payout number error error, a ball runout error, a full tank error, a prize ball error, etc.) is set in the lower 4 bits of the command for preparing a prize ball. Processing is performed. Then, the payout control CPU 371 performs control to transmit the converted prize ball preparing command to the game control microcomputer 560 (step S74222). Specifically, the payout control CPU 371 performs processing for outputting a prize ball preparing command to the transmission register of the serial communication circuit 380.

  Note that the payout control CPU 371 clears the main control communication reception buffer when the award ball preparing command is transmitted in step S74222. By doing so, it is possible to prevent a situation in which the received command is erroneously recognized in the subsequent processing and the erroneous processing is executed.

  Next, the payout control CPU 371 sets a value “2” indicating the main control communication process to the main control communication control code (step S74223). Then, the payout control CPU 371 sets a predetermined value (1 second in this example) to the main control communication control timer (step S74224). It should be noted that, after the command for preparing a prize ball is transmitted based on the value set in step S74224, the command for preparing the next prize ball is transmitted if it is not ready to start the prize ball payout operation after one second has elapsed. Will be.

  53 and 54 are flowcharts showing the main control communication in-process (step S743) executed when the value of the main control communication control code is 2. In the main control communication process, the payout control CPU 371 first checks whether or not a reception command is stored in the main control communication reception buffer (step S74301). If a reception command is stored in the main control communication reception buffer, the payout control CPU 371 checks whether or not the received command is a connection confirmation command (step S 74302). If it is not a connection confirmation command, the process proceeds to step S74306. If a connection confirmation command has been received, the payout control CPU 371 sets a connection OK command (step S74303) and executes main control transmission command conversion processing (step S74304). In the main control transmission command conversion process in step S74304, a process of setting a control state (an error state such as a payout number error error, a ball out error, a full tank error, a prize ball error) in the lower 4 bits of the connection OK command is performed. Done. Then, the payout control CPU 371 performs control to transmit the converted connection OK command to the game control microcomputer 560 (step S74305). Specifically, the payout control CPU 371 performs processing for outputting a connection OK command to the transmission register of the serial communication circuit 380. Then, the process proceeds to step S74306.

  In step S74306, the payout control CPU 371 sets a main control communication error designation bit in the error flag. That is, the main control communication process is a process that is executed after receiving the prize ball number command until the prize ball payout operation can be started based on the received prize ball number command. Since the response of the command is suspended, the game control microcomputer 560 is in a waiting state for receiving the award ball number reception command. During this time, a new payout control command is received from the game control microcomputer 560. There is no trap. Nevertheless, since receiving a new command can determine that some abnormality has occurred in the communication state, the payout control CPU 371 performs processing for setting a main control communication error designation bit.

  The payout control CPU 371 clears the main control communication reception buffer when the main control communication error designation bit is set in step S74306. By doing so, it is possible to prevent a situation in which the received command is erroneously recognized in the subsequent processing and the erroneous processing is executed.

  Next, the payout control CPU 371 sets a value “1” indicating the main control communication normal process in the main control communication control code (step S74307). Then, the payout control CPU 371 sets a predetermined value (1050 ms in this example) in the main control communication control timer (step S74308).

  If there is no reception command in the main control communication reception buffer, the payout control CPU 371 subtracts 1 from the value of the main control communication control timer (step S74309), and checks whether the main control communication control timer has timed out (step S74309). S74310).

  If the main control communication control timer has timed out (Y in step S74310), it means that one second or more has elapsed since the previous prize ball preparation command was transmitted. In this case, the payout control CPU 371 sets a winning ball preparing command in order to transmit the next winning ball preparing command (step S74311), and executes main control transmission command conversion processing (step S74312). In the main control transmission command conversion process of step S74312, the control state (error status such as a payout number error error, a ball outage error, a full tank error, a prize ball error, etc.) is set in the lower 4 bits of the winning ball preparation command. Processing is performed. Then, the payout control CPU 371 performs control to transmit the converted prize ball preparing command to the game control microcomputer 560 (step S74313). Specifically, the payout control CPU 371 performs processing for outputting a prize ball preparing command to the transmission register of the serial communication circuit 380.

  Then, the payout control CPU 371 sets a predetermined value (1 second in this example) in the main control communication control timer (step S74314). It should be noted that, after the command for preparing a prize ball is transmitted based on the value set in step S74314, a command for preparing the next prize ball is issued if it is not yet ready to start a prize ball payout operation after one second has passed. Will be sent.

  If the main control communication control timer has not timed out, the payout control CPU 371 checks whether or not the value of the error flag is 0 (step S74315). If the value of the error flag is not 0 (that is, if it is in an error state and one of the error bits is set), the winning ball payout operation cannot be started yet, so the processing is ended as it is. If the value of the error flag is 0 (that is, if no error state is set and no error bit is set), the payout control CPU 371 checks whether a BRDY signal is input. (Step S74316). If the BRDY signal has been input, the winning ball payout operation cannot be started yet, and the process is terminated as it is.

  If the BRDY signal is not input, the payout control CPU 371 loads a payout control state flag indicating the payout control state (step S74317), and confirms whether the winning ball payout operation or the ball lending payout operation is in progress. (Step S74318). Specifically, the payout control CPU 371 specifies a prize ball payout operation designation bit (a bit indicating that a prize ball payout operation is in progress) or a ball lending payout operation designation bit (in a ball lending payout operation) in the payout control state flag. It is confirmed whether or not a bit indicating that is set. If the winning ball payout operation or the ball lending payout operation is in progress, the winning ball payout operation cannot be started yet, so the processing is ended as it is. In this embodiment, since the next prize ball number command is transmitted after the prize ball payout operation is finished and the prize ball end command is received, the step is performed unless an abnormality such as a communication error occurs. In S74318, it is not determined that a prize ball payout operation is in progress.

  If neither the winning ball payout operation nor the ball lending payout operation is in progress, it means that the winning ball payout operation based on the received winning ball number command can be started. In this case, the payout control CPU 371 sets the lower 4 bits of the main control communication prize ball number buffer (that is, the temporarily saved prize ball number) in the unpaid number counter (step S74319).

  In this embodiment, as described above, when the winning ball payout operation cannot be started immediately when the winning ball number command is received, the winning ball number specified by the winning ball number command is immediately set to the unpaid number. Instead of being set in the counter, it is temporarily saved in the main control communication award ball number buffer. This is to prevent inconvenience in processing related to payout control, such as preventing a situation where the number of winning balls cannot be accurately managed.

  Next, the payout control CPU 371 performs control to transmit a prize ball number acceptance command to the game control microcomputer 560 (step S74320). Specifically, the payout control CPU 371 performs processing for outputting a prize ball number acceptance command to the transmission register of the serial communication circuit 380.

  Next, the payout control CPU 371 sets a value “3” indicating the main control communication end process in the main control communication control code (step S74321). Then, the payout control CPU 371 sets a predetermined value (1 second in this example) in the main control communication control timer (step S74322). It should be noted that if a prize ball payout operation is not completed after a lapse of one second after the prize ball number acceptance command is transmitted based on the value set in step S74322, a prize ball preparing command is transmitted.

  FIG. 55 is a flowchart showing a main control communication end process (step S744) executed when the value of the main control communication control code is 3. In the main control communication end process, the payout control CPU 371 first checks whether or not a reception command is stored in the main control communication reception buffer (step S74401). If a reception command is stored in the main control communication reception buffer, the payout control CPU 371 checks whether or not the received command is a connection confirmation command (step S74402). If it is not a connection confirmation command, the process proceeds to step S74406. If a connection confirmation command has been received, the payout control CPU 371 sets a connection OK command (step S74403) and executes main control transmission command conversion processing (step S74404). In the main control transmission command conversion process of step S74404, a process of setting a control state (an error state such as a payout number error error, a ball out error, a full tank error, a prize ball error) in the lower 4 bits of the connection OK command is performed. Done. Then, the payout control CPU 371 performs control to transmit the converted connection OK command to the game control microcomputer 560 (step S74405). Specifically, the payout control CPU 371 performs processing for outputting a connection OK command to the transmission register of the serial communication circuit 380. Then, control goes to a step S74406.

  In step S74406, the payout control CPU 371 sets a main control communication error designation bit in the error flag. That is, the main control communication end process is a process executed after receiving the prize ball number command and starting the prize ball payout operation until the prize ball payout operation based on the received prize ball number command is ended. Since the microcomputer for use 560 is in a waiting state for receiving the winning ball end command, it is unlikely that a new payout control command will be received from the game control microcomputer 560 during this period. Nevertheless, since receiving a new command can determine that some abnormality has occurred in the communication state, the payout control CPU 371 performs processing for setting a main control communication error designation bit.

  The payout control CPU 371 clears the main control communication reception buffer when the main control communication error designation bit is set in step S74406. By doing so, it is possible to prevent a situation in which the received command is erroneously recognized in the subsequent processing and the erroneous processing is executed.

  Next, the payout control CPU 371 sets a value “1” indicating the main control communication normal process in the main control communication control code (step S74407). Then, the payout control CPU 371 sets a predetermined value (1050 ms in this example) in the main control communication control timer (step S74408).

  If there is no reception command in the main control communication reception buffer, the payout control CPU 371 subtracts 1 from the value of the main control communication control timer (step S74409), and checks whether the main control communication control timer has timed out (step S74409). S74410).

  If the main control communication control timer has timed out (Y in step S74410), it means that one second or more has elapsed since the last time a prize ball acceptance command or a prize ball preparation command was transmitted. In this case, the payout control CPU 371 sets a prize ball preparing command in order to transmit the next prize ball preparing command (step S74411), and executes main control transmission command conversion processing (step S74412). In the main control transmission command conversion process in step S74412, a control state (error state such as a payout number error error, a ball runout error, a full tank error, a prize ball error, etc.) is set in the lower 4 bits of the command for preparing a prize ball. Processing is performed. Then, the payout control CPU 371 performs control to transmit the converted prize ball preparing command to the game control microcomputer 560 (step S74413). Specifically, the payout control CPU 371 performs processing for outputting a prize ball preparing command to the transmission register of the serial communication circuit 380.

  Then, the payout control CPU 371 sets a predetermined value (1 second in this example) in the main control communication control timer (step S74414). It should be noted that, based on the value set in step S74414, after the command for preparing a prize ball is transmitted, if the prize ball payout operation is not yet completed after another one second, the next command for preparing a prize ball is transmitted. It will be.

  If the main control communication control timer has not timed out, the payout control CPU 371 loads a payout control state flag (step S74415), and checks whether or not a prize ball payout operation is in progress (step S74416). Specifically, the payout control CPU 371 checks whether or not a prize ball payout operation specifying bit is set in the payout control state flag. If the winning ball payout operation is in progress, it means that the winning ball payout operation based on the received winning ball number command has not been finished yet, and the payout control CPU 371 ends the process as it is. If no winning ball payout operation is in progress, it means that the winning ball payout operation based on the received winning ball number command has ended. Therefore, the payout control CPU 371 performs control to transmit a prize ball end command to the game control microcomputer 560 (step S74417). Specifically, the payout control CPU 371 performs a process of outputting a prize ball end command to the transmission register of the serial communication circuit 380.

  The payout control CPU 371 clears the main control communication reception buffer when it transmits the winning ball end command in step S74417. By doing so, it is possible to prevent a situation in which the received command is erroneously recognized in the subsequent processing and the erroneous processing is executed.

  Next, the payout control CPU 371 sets a value “1” indicating the main control communication normal process in the main control communication control code (step S74418). Then, the payout control CPU 371 sets a predetermined value (1050 ms in this example) in the main control communication control timer (step S74419).

  FIG. 56 is a flowchart showing main control transmission command conversion processing executed in steps S7414, S74207, S74221, S74304, S74312, S74404, and S74412. In the main control transmission command conversion process, the payout control CPU 371 first loads an error flag and checks whether or not the payout number abnormality error designation bit is set (step S731). If the payout number abnormality error designation bit is set, the payout control CPU 371 sets a main control communication payout number error error output bit (specifically, bit 3) in the conversion buffer (step S732).

  Next, the payout control CPU 371 checks whether or not the ball break error designation bit is set (step S733). If the ball-out error designation bit is set, the payout control CPU 371 sets the main control communication ball-out output bit (specifically bit 2) in the conversion buffer (step S734).

  Next, the payout control CPU 371 checks whether or not the full error designation bit is set (step S735). If the full error specification bit is set, the payout control CPU 371 sets the full output bit for main control communication (specifically bit 1) of the conversion buffer (step S736).

  Next, the payout control CPU 371 checks whether or not other prize ball error designation bits are set (step S737). Specifically, the payout control CPU 371 includes a main control communication error designation bit, a main control unconnected error designation bit, a withdrawal switch abnormality detection error 1 designation bit, a withdrawal switch abnormality detection error 2 designation bit, a withdrawal in the error flag. Check if the case error specification bit is set. If any other prize ball error designation bit is set, the payout control CPU 371 sets a main control communication ball out output bit (specifically bit 0) in the conversion buffer (step S738).

  Then, the payout control CPU 371 sets the contents of the conversion buffer in the payout control command (connection OK command or prize ball preparing command) set for transmission (step S739).

  FIG. 57 is a flowchart showing the payout control process in step S755. In the payout control process, the payout control CPU 371 confirms that the detection signal of the payout number count switch 301 is turned on (step S7501), and checks whether the value of the unpaid number counter is 0. (Step S7502). If the value of the unpaid number counter is 0, the payout control CPU 371 adds 1 to the value of the payout number abnormality counter for counting the cumulative number of abnormal payouts (step S7503). In other words, Y in step S7502 means that the unpaid number to be paid out is not set in the unpaid-out number counter, so that the payout operation is performed even though the game ball should not be paid out. And the payout count switch 301 detects the payout of the game ball. For this reason, there is a possibility that the payout operation has been performed by some kind of fraud, so the payout control CPU 101 cumulatively adds 1 to the value of the payout number abnormality counter.

  The payout number abnormality counter indicates the number of payouts exceeding the number of unpaid game balls to be paid out and the number of payout shortages that did not meet the number of unpaid game balls to be paid out. This is a counter for cumulatively counting. As will be described later, in this embodiment, when the value of the payout number abnormality counter becomes equal to or greater than a predetermined payout number error error determination value (2000 in this example), it is determined that a payout number error has occurred and the payout is stopped. Processing to control the state is performed. Note that the process of step S7503 corresponds to a process of cumulatively counting the excess payout in the payout number abnormality counter.

  In this embodiment, without distinguishing whether the ball is a winning ball or a lending ball, the payout excess number and the payout shortage number are cumulatively counted in the payout number abnormality counter. For only one of the rented balls, the excessive payout and the shortage payout may be cumulatively counted in the payout number abnormality counter. Further, for example, with respect to prize balls and lending balls, it is possible to cumulatively count the excess payout and the shortage payout using separate counters. In this case, it may be determined that a payout number error occurs when the value of one of the counters reaches a predetermined threshold value, or a payout number error error when the total value of both counters reaches a predetermined threshold value. May be determined.

  Further, in this embodiment, the case where the value of the payout number abnormality counter is incremented by 1 when an excessive payout is detected in step S7503 has been shown, but the method of counting up the value of the payout number abnormality counter is described in this embodiment. It is not limited to what is shown in the form. For example, conversely, the excessive payout number may be subtracted from the value of the payout number abnormality counter, and the insufficient payout number may be added to the value of the payout number abnormality counter. In this case, for example, the payout control CPU 371 sets “2000” as the initial value in the payout number abnormality counter in the initial setting process when the power is turned on, and subtracts 1 from the value of the payout number abnormality counter in step S7503. In steps S75320, S75325, and S75335, which will be described later, a value corresponding to the insufficient payout number may be added to the value of the payout number abnormality counter. For example, in the processing of steps S7504, S75321, and S7725, which will be described later, it is determined that a payout number abnormality error has occurred based on the value of the payout number abnormality counter being 2000 or less. Good.

  Next, the payout control CPU 371 checks whether or not the value of the added payout number abnormality counter is equal to or greater than a predetermined payout number error error determination value (for example, 2000) (step S7504). If it is equal to or greater than a predetermined payout number error error determination value (for example, 2000), the payout control CPU 371 determines that a payout number error error has occurred, and indicates a payout number error error indicating that a payout number error error has occurred. A flag is set (step S7505). That is, in this embodiment, the number of abnormal payouts detected is cumulatively managed on the payout control microcomputer 370 side, and if the accumulated value is equal to or greater than a predetermined payout number abnormal error determination value (for example, 2000), It is determined that there is an extremely high possibility that a payout operation is being performed due to some sort of fraud, and it is determined that a payout number abnormality error (an error indicating that the number of game balls paid out is abnormal) has occurred. In addition, there are not a few cases where game balls are paid out excessively or insufficient due to malfunctions, etc., so when an abnormality in the number of payouts is detected, it is immediately determined as a payout number error. The frequency determined to be a payout number abnormality error becomes higher than necessary, and the game is hindered. Therefore, in this embodiment, the number of abnormal payouts detected is cumulatively managed, and the payout number abnormality error is determined on the condition that the accumulated value is equal to or greater than a predetermined payout number abnormality error determination value (for example, 2000). By determining, it is prevented that it is determined that the payout number abnormality error is more than necessary.

  In this embodiment, if it is determined that there is a payout number error and the payout number error error flag is set once, the payout number error error flag is not cleared until the power is reset, and the payout number error error is not recovered. When the payout number abnormality error flag is set, the processes in steps S7504 and S7505 and the processes in S75321, S75322, S7725, and S7726 described later may not be executed. By doing so, it is possible to prevent useless processing after it has once been determined as a payout number abnormality error, and to reduce the processing burden.

  Further, in this embodiment, “2000” corresponding to the number of game balls that can be stored in a game ball storage box (so-called dollar box) generally used in a game store is set as a predetermined payout number abnormality error determination value. Although the case where it uses is shown, other values (for example, 1000 or 3000) may be used as the predetermined payout number abnormality error determination value.

  In this embodiment, the payout control process shown in FIG. 57 is a process that is commonly executed when the prize ball payout operation is executed and when the lending ball payout operation is executed. This counter is used in common when counting the number of game balls that have not been paid out with prize balls and when counting the number of game balls that have not been paid out with lending balls. When an abnormality in the number of payouts is detected, the value of the payout number abnormality counter is incremented without distinguishing between payout with a prize ball and payout with a lending ball, and whether or not a payout number abnormality error has occurred. A determination is made.

  If the value of the unpaid-out number counter is not 0, the payout control CPU 371 subtracts 1 from the value of the unpaid-out number counter (step S7506), and a payout ball detection designation bit (game ball payout) is added to the flag of the payout control state. A bit indicating detection) is set (step S7507). The payout ball detection designation bit is a bit that is set when the payout number count switch 301 is turned on, and indicates that the payout number count switch 301 has detected at least one game ball during the payout operation. is there.

  Thereafter, the payout control CPU 371 executes any one of steps S7511 to S7513 according to the value of the payout control code.

  FIG. 58 is a flowchart showing the payout start waiting process (step S7511) executed when the payout control code is 0. In the payout start waiting process, the payout control CPU 371 first checks whether or not the value of the error flag is 0 (step S75101). If an error bit (one or more of all error bits in the error flag) is set, the payout control CPU 371 controls not to execute the subsequent processing. In this embodiment, by executing the processing of step S75101, it is determined that there is a payout number abnormal error, and the payout number abnormal error designation bit of the error bit is set, so that the steps after step S75102 are set. Control is performed so as not to shift to processing, and the payout is stopped.

  If the value of the error flag is 0, the payout control CPU 371 checks whether or not the BRDY signal is input (step S75102). If the BRDY signal is input, the payout control CPU 371 loads a payout control state flag (step S75103), and checks whether or not a ball lending request is being made (step S75104). Specifically, the payout control CPU 371 checks whether or not a ball lending request specifying bit (a bit indicating that a ball lending request is being made) is set in the payout control state flag. The payout control CPU 371 may determine whether or not a ball lending request is being made by confirming whether or not a BRQ signal is input. If a ball lending request is being made (that is, when a ball lending payout operation is started), the payout control CPU 371 resets the ball lending request specifying bit of the payout control state flag (step S75105) and at the same time a payout control state flag. The designated bit during the ball lending / dispensing operation is set (step S75016). Next, the payout control CPU 371 sets a predetermined ball lending number (25 in this example) in the unpaid number counter (step S75107) and a predetermined ball lending number (25 in this example) in the payout motor rotation number buffer. Is set (step S75108). Then, control goes to a step S75113.

  The payout motor rotation frequency buffer is referred to in the payout motor control process (step S756). That is, in the payout motor control process, control is performed to rotate the payout motor 289 by the number of rotations corresponding to the value set in the payout motor rotation frequency buffer.

  If the BRDY signal is not input, the payout control CPU 371 checks whether or not the value of the unpaid-out number counter is 0 (step S75109). If the value of the unpaid number counter is not 0 (that is, when the prize ball payout operation is started), the payout control CPU 371 sets the value of the unpaid number counter in the payout motor rotation number buffer (step S75110). That is, in this case, since the number of prize balls designated by the received prize ball number command should be set in the unpaid quantity counter (see steps S74214 and S74319), the prize ball dispensing operation is started. Then, a process of setting the number of prize balls in the payout motor rotation frequency buffer is performed. Next, the payout control CPU 371 loads a payout control state flag (step S75111), and sets a prize ball payout operation specifying bit in the payout control state flag (step S75112). Then, control goes to a step S75113.

  In step S75113, the payout control CPU 371 sets a value in the payout motor control code for selecting a process to be executed in the payout motor control process according to the payout motor activation process. Thereby, in the payout motor control process in step S756, a payout motor starting process for starting the payout motor 289 is executed, and a lending ball payout operation or a prize ball payout operation is started. Then, the payout control CPU 371 sets a value “1” indicating the payout motor stop waiting process in the payout control code (step S75114), and ends the process.

  FIG. 59 is a flowchart showing a payout motor stop waiting process (step S7512) executed when the payout control code is 1. In the payout motor stop waiting process, the payout control CPU 371 first loads a payout control state flag (step S7521), and checks whether or not the payout operation is completed (step S7522). Specifically, the payout control CPU 371 checks whether or not a payout operation end designation bit (a bit indicating that the payout operation has ended) is set in the payout control state flag. The payout operation end designation bit is set in the payout motor brake process and the payout motor ball biting release process in the payout motor control process in step S756 shown in FIG.

  In the payout motor control processing, the payout control CPU 371 performs payout motor normal processing (processing such as setting the pointer at the head address of the table stored in the ROM), payout, according to the value of the payout motor control code. Motor start-up processing (processing such as setting the initial value of the excitation pattern in bits 4 to 7 of the port 0 buffer corresponding to the output state of the output port 0), payout motor slow-up processing (starting the rotation of the payout motor 289 smoothly) Therefore, the output state of the output port 0 is read out by reading the contents of the payout motor excitation pattern table at intervals longer than those in the case of constant speed processing and gradually approaching the time intervals in the case of constant speed processing. , Processing of setting bits 4 to 7 in the port 0 buffer corresponding to), payout motor constant speed processing (periodic payout motor excitation pattern) The process of reading the contents of the table and setting the bits 4 to 7 of the port 0 buffer corresponding to the output state of the output port 0), the dispensing motor brake process (the constant speed process to smoothly stop the dispensing motor 289) Port 0 buffer corresponding to the output state of the output port 0 by reading out the contents of the payout motor excitation pattern table at intervals longer than those in the case of, and gradually away from the time interval in the case of constant speed processing Processing of setting the bits 4 to 7), the payout motor ball biting process (when the ball biting state is detected, in order to release the ball biting, the contents of the payout motor excitation pattern table are read and the output port 0 is set. Processing to set bits 4 to 7 in the port 0 buffer corresponding to the output state), and the payout motor ball biting release processing (ball biting state is released) Either processing shifts to the payout motor normal processing process returns to the normal motor control state) execution.

  If the payout operation has been completed, the payout control CPU 371 resets the payout operation end designation bit of the payout control state flag (step S7523) and stops the payout motor used to set a payout passage monitoring time to be described later. The waiting process setting table 2 is set (step S7524).

  Next, the payout control CPU 371 checks whether or not the payout ball number inspected designation bit is set in the payout control state flag (step S7525). The designated number of paid-out balls inspected is a bit indicating that the detection of the number-of-payout count switch 301 has been determined at the end of the payout operation by the payout motor 289 (at the end of normal operation). If the payout ball number inspected designation bit is set, the process proceeds to step S7527. If the payout ball number inspected designation bit is not set, the payout control CPU 371 sets a payout motor stop waiting process setting table (step S7526). That is, the payout control CPU 371 replaces the table set in step S7524 with a payout motor stop waiting process setting table. Then, control goes to a step S7527.

  In step S7527, the payout control CPU 371 sets a value “2” indicating payout passing waiting processing in the payout control code. The payout control CPU 371 sets the payout passing monitoring time in the payout control timer based on the table set in steps S7524 and S7526 (step S7527). The payout passing monitoring time is a time that has a margin in the time from when the last payout ball is paid out by the payout motor 289 until it passes through the payout number count switch 301. In this embodiment, when the payout ball number inspected bit is set in step S7525, 1 second is set as the payout passing monitoring time based on the payout motor stop waiting process setting table 2 set in step S7524. To do. If the paid ball number inspected bit is not set in step S7525, 0.6 seconds is set as the payout passing monitoring time based on the payout motor stop waiting process setting table replaced in step S7526.

  60 to 62 are flowcharts showing a payout passing waiting process (step S7513) executed when the value of the payout control code is 2. In the payout passing waiting process, the payout control CPU 371 first checks the value of the payout control timer (step S75301). If the value is 0, the process proceeds to step S75304. If the value of the payout control timer is not 0, the value of the payout control timer is decremented by 1 (step S75302). If the value of the payout control timer is not 0 (step S75303), that is, if the payout control timer has not timed out, the process is terminated.

  If the payout control timer has timed out, the payout control CPU 371 loads the error flag, and sets the payout number abnormality error designation bit, the dispensing switch abnormality detection error 1 designation bit, or the dispensing switch abnormality detection error 2 designation bit. It is confirmed whether or not (step S75304). If any one of the payout number abnormality error designation bit, the dispensing switch abnormality detection error 1 designation bit, or the dispensing switch abnormality detection error 2 designation bit is set, it is determined that the dispensing operation cannot be continued any more, and the process proceeds to step S75306. Transition. If none of the payout number error error specification bit, the payout switch error detection error 1 specification bit, and the payout switch error detection error 2 specification bit is set, the payout control CPU 371 sets the value of the unpaid number counter to 0. It is confirmed whether or not (step S75305). If the value of the unpaid-out counter is 0, the payout control CPU 371 assumes that the payout operation has ended normally, loads a payout control state flag (step S75306), and is requesting a ballot for the payout control state flag. Bits other than the designated bit and the payout operation end designation bit are reset (step S75307). Then, the payout control CPU 371 sets a value “0” indicating the payout start waiting process in the payout control code (step S75308), and ends the process.

  If the value of the unpaid-out number counter is not 0, the payout control CPU 371 loads an error flag and confirms whether or not the ball breakage error designation bit or the full tank error designation bit is set (step S75309). . If the ball breakage error designation bit or the full tank error designation bit is set, the processing is terminated as it is. If neither the ball breakage error designation bit nor the full tank error designation bit is set, the payout control CPU 371 checks whether or not the payout case error designation bit is set in the error flag (step S75310). If the payout case error designation bit is set, the payout control CPU 371 loads the payout control status flag (step S75311), and sets the payout ball number checked designation bit in the payout control status flag (step S75312). . The payout control CPU 371 also includes a 1 designation bit during re-payout operation (bit indicating execution of the first re-payout operation) and a 2 designation bit during re-payout operation (execution of the second re-payout operation). Is reset (step S75313), and the process is terminated.

  Note that the designated number of paid-out balls has been inspected is a bit indicating that the detection of the number-of-payout count switch 301 has been determined at the end of the payout operation by the payout motor 289 (at the end of normal operation). Note that, when the value of the unpaid-out number counter remains two or more despite the end of the payout operation, the remaining number is added to the payout number abnormality counter. Further, the detection determination by the payout number count switch 301 at the end of the payout operation is executed only once every time the payout operation is executed, and the payout motor ball biting process or the payout motor ball bite releasing process is executed. It is not executed when the biting operation is finished (specifically, since the payout case error designation bit is set in the ball biting state, the ball biting operation is performed by setting the payout ball number checked designation bit in advance in step S75312. Even if the operation is finished, the detection by the payout number count switch 301 is not determined). It should be noted that the payout ball number inspected designation bit is also set when the payout motor constant speed process in the payout motor control process becomes full.

  If the payout case error designation bit is not set in step S75310, the payout control CPU 371 loads a payout control state flag (step S75314) and performs processing for executing re-payout processing after step S75315.

  In order to execute the re-payout process, the pay-out control CPU 371 first checks whether or not the 2 designation bit during re-payout operation of the payout control state flag is set (step S75315). If it is not set, the payout control CPU 371 checks whether or not the 1 designation bit during re-payout operation of the payout control state flag is set (step S75316). If the 1 designation bit during re-payout operation is not set, the payout control CPU 371 sets the 1 designation bit during re-payout operation in the payout control state flag in order to execute the first re-payout operation (step S75317). .

  Next, the payout control CPU 371 checks whether or not the payout ball number inspected designation bit is set in the payout control state flag (step S75318). If the specified number of paid-out balls is inspected, the process proceeds to step S75326. If the specified number of paid-out balls has been inspected, the payout control CPU 371 checks whether or not the value of the unpaid-out number counter is 2 or more (step S75319). If the value of the unpaid-out number counter is not 2 or more, the process proceeds to step S75326. If the value of the unpaid number counter is 2 or more, the payout control CPU 371 adds the value of the unpaid number counter to the payout number abnormality counter (step S75320). Note that the process of step S75320 corresponds to a process of cumulatively counting the number of shortage payouts in the payout number abnormality counter. Next, the payout control CPU 371 checks whether or not the value of the added payout number abnormality counter is equal to or greater than a predetermined payout number error error determination value (for example, 2000) (step S75321). If it is equal to or greater than a predetermined payout number error error determination value (for example, 2000), the payout control CPU 371 determines that a payout number error error has occurred, and indicates a payout number error error indicating that a payout number error error has occurred. A flag is set (step S75322).

  In this embodiment, the payout is performed on condition that the value of the unpaid-out number counter remains at a predetermined reference number (2 in this example) even though the payout operation is finished by the process of step S75319. The value of the unpaid number counter is added to the number abnormality counter. That is, since the payout operation is terminated due to a malfunction or the like, the value of the unpaid-out number counter remains in a small number (1 in this example). If even one unsettled number counter value remains, the accumulated number is immediately counted as a cumulative number in the payout number abnormality counter, and the frequency determined as a payout number abnormality error is increased more than necessary, causing problems to the game. End up. Therefore, in this embodiment, on the condition that the value of the unpaid-out number counter remains 2 or more with a little allowance, the accumulated number is counted in the payout number abnormality counter, and it is determined that there is an unnecessarily large number of payout errors. Is prevented. The process of step S75319 shows a case where the payout number abnormality counter is cumulatively counted up on condition that the payout shortage number is equal to or greater than a predetermined reference number (2 in this example). Alternatively, the payout number abnormality counter may be counted up cumulatively on condition that the number is a predetermined reference number (2 in this example) or more. In this case, for example, on the condition that the number of times determined as Y in step S7502 shown in FIG. Count up. In the processing of steps S75319 and S75320, the value of the unpaid number counter is always used as it is in the payout number abnormality counter regardless of whether or not the value of the unpaid number counter remains at a predetermined reference number (2 in this example). You may make it add.

  If the 1 designation bit during re-payout operation is set in step S75316, the payout control CPU 371 checks whether or not the dispensed ball detection designation bit is set in the payout control state flag (step S75323). If the payout ball detection designation bit is set, the payout control CPU 371 proceeds to step S75326. If the payout ball detection designation bit is not set, the payout control CPU 371 sets the 2 designation bit during re-payout operation in the payout control state flag to execute the second re-payout operation (step S75324). Then, 1 is added to the value of the payout number abnormality counter (step S75325). Note that the process of step S75325 corresponds to a process of cumulatively counting the number of shortage payouts in the payout number abnormality counter. Then, control goes to a step S75326. Note that by executing the processing of step S75325, the value of the payout number abnormality counter is incremented by 1 when the re-payout operation is not performed normally despite the execution of the first re-payout operation. The Even when the payout is completed normally, the value of the unpaid-out number counter may not be 0 due to an erroneous count or the like. Therefore, if the payout ball detection designation bit is set by executing the process of step S75323, that is, if the payout number count switch 301 detects the payout of at least one game ball during the payout operation. Since there is a possibility that the payout has been completed normally, the process proceeds to step S75326 without performing the cumulative count of the payout number abnormality counter.

  In step S75326, the payout control CPU 371 sets 1 as the number of repaid operations in order to execute the first repaid operation. Next, the payout control CPU 371 sets the number of re-payout operations (1 in this example) in the payout motor rotation frequency buffer (step S75327). Next, the payout control CPU 371 loads the payout control state flag (step S75328), and resets the payout ball detection designation bit of the payout control state flag (step 75329).

  Next, the payout control CPU 371 sets a value in the payout motor control code for selecting a process executed in the payout motor control process in accordance with the payout motor activation process (step S75330). Thereby, in the payout motor control process of step S756, the payout motor starting process for starting the payout motor 289 is executed, and the re-payout operation is started. Then, the payout control CPU 371 sets a value “1” indicating the payout motor stop waiting process in the payout control code (step S75331), and ends the process.

  If the 2 designation bit during re-payout operation is set in step S75315, the payout control CPU 371 resets the 2 designation bit during re-payout operation of the payout control state flag (step S75332). Next, the payout control CPU 371 checks whether or not the payout ball detection designation bit of the payout control state flag is set (step S75333). If the payout ball detection designation bit is set, the process proceeds to step S75326. If the payout ball detection designation bit is not set, the payout control CPU 371 resets the 2 designation bit during re-payout operation of the payout control state flag (step S75334) and adds 1 to the value of the payout number abnormality counter (step S75334). Step S75335). Note that the process of step S75335 corresponds to a process of cumulatively counting the number of shortage payouts in the payout number abnormality counter. Also, by executing the process of step S75335, even if the second re-payout operation is executed, if the re-payout operation is not performed normally, the value of the payout number abnormality counter is incremented by one. Even when the payout is completed normally, the value of the unpaid-out number counter may not be 0 due to an erroneous count or the like. Therefore, if the payout ball detection designation bit is set by executing the process of step S75333, that is, if the payout number count switch 301 detects the payout of at least one game ball during the payout operation. Since there is a possibility that the payout has been completed normally, the process proceeds to step S75326 without performing the cumulative count of the payout number abnormality counter.

  Next, the payout control CPU 371 loads an error flag, and sets a payout case error designation bit in the error flag (step S75336). Then, the payout control CPU 371 sets a predetermined time (for example, 2 minutes) in the re-payout waiting timer (step S75337) and ends the process. The re-payout waiting timer set in step S57337 is measured by an error process described later (see step S7710), and the payout case error designation bit in the error flag is reset based on the time-out of the re-payout timer. (See steps S7711 and S7712). By executing such processing, in this embodiment, after the payout case error is detected, the error state is automatically recovered based on the fact that two minutes have passed.

  Next, error processing will be described. 63 and 64 are flowcharts showing the error processing in step S757. In the error processing, the payout control CPU 371 first loads an error flag, and the error flag payout switch abnormality detection error 2 designation bit, a payout case error designation bit, a main control communication error designation bit, and a payout number abnormality error designation bit. The other error bits are reset (step S7701). Next, the payout control CPU 371 checks whether or not the value of the error flag is 0 (step S7702). If the value of the error flag is 0, the process proceeds to step S7710. If the value of the error flag is not 0 (that is, if the payout switch abnormality detection error 2 designation bit, the withdrawal case error designation bit, the main control communication error designation bit, or the withdrawal number abnormality error designation bit is set) The control CPU 371 checks whether or not the operation signal is turned on from the error release switch 375 (step S7703). When the operation signal is turned on, the error recovery time is set in the pre-error recovery timer (step S7709). The error recovery time is the time from when the error release switch 375 is operated until the actual return from the error state to the normal state.

  If the operation signal from the error release switch 375 is not on, the value of the timer before error recovery is confirmed (step S7704). If the value of the timer before error recovery is 0, that is, if the timer before error recovery is not set, the process proceeds to step S7710. If the pre-error recovery timer is set, the value of the pre-error recovery timer is decremented by -1 (step S7705). If the pre-error recovery timer value becomes 0 (step S7706), the payout switch of the error flags The abnormality detection error 2 designation bit, the payout case error designation bit, and the main control communication error designation bit are reset (step S7707), and if set, the re-payout waiting timer is reset (step S7708). Then, control goes to a step S7710. If the pre-error recovery timer has not timed out, the process proceeds to step S7713.

  When the processing of step S7707 is executed, there may be an error bit that is not in the set state among the payout switch abnormality detection error 2 designation bit, the payout case error designation bit, and the main control communication error designation bit. There is no problem even if the error bit that is not in the set state is reset. As described above, in this embodiment, when an error that causes the setting of the payout switch abnormality detection error 2, the payout case error, and the main control communication error bit occurs, the error release switch 375 is pressed. The error is canceled by being done.

  In step S7710, if set, the payout control CPU 371 subtracts 1 from the value of the re-payout waiting timer, and checks whether the re-payout wait timer after the subtraction has timed out (step S7711). If the re-payout waiting timer has timed out, the payout control CPU 371 resets the payout case error designation bit of the error flag (step S7712). Then, control goes to a step S7713.

  As described above, in this embodiment, when the payout case error is detected and the payout detection error designation bit is set by executing the processes of steps S7707 and S7712, the error release switch 375 is pressed. On the condition that the error has been canceled (more precisely, the time before error recovery has passed) and on the condition that a predetermined time (2 minutes in this example) has passed after detection of the payout case error The error may be automatically canceled. In this embodiment, regarding the payout number abnormality error, once detected, it is not canceled unless the power supply to the gaming machine is reset.

  When the processing of steps S7707 and S7712 is executed and the payout case error designation bit is reset, the payout control code is “2” (corresponding to the execution of the payout passing waiting processing shown in FIGS. 60 to 62). Then, the game ball payout retry operation is started. That is, when the payout control process in step S755 is executed next, if the payout passing waiting process in step S7513 is executed, the repayout process is performed again. For example, if a prize ball payout process has been performed and the value of the unpaid-out number counter is not 0, the process proceeds from step S75305 to steps S75309 and S75310, and the payout case error designation bit is in the reset state in step S75310. Therefore, the process for starting the re-payout process after step S75314 is executed again, and the re-payout process is executed.

  As described above, the payout control means is used to pay out a game ball when the payout number count switch 301 detects no game ball even though the ball payout device 97 pays out a game ball. After performing the correct payout control for causing the ball payout device 97 to execute the retry operation for a predetermined number of times (for example, twice) as a limit, the payout number count switch 301 has detected no game balls. When it is detected (see step S75314 and subsequent steps in FIGS. 60 to 62), the control state related to payout is shifted to an error state, and an error release signal is output from the error release switch 375 in the error state, or a payout case Corrected payout that makes correction payout control again on condition that a predetermined time (2 minutes in this example) has passed since the error was detected To run the control restart processing.

  Further, even during the re-payout process in the error state (specifically, during the re-payout process before setting the payout case error and during the re-payout process after the error release switch 375 is pressed), step S7501 shown in FIG. S7502 and S7506 are executed. That is, even when an error relating to payout occurs, if the game ball passes the payout number count switch 301, the value of the unpaid-off number counter is subtracted. Accordingly, the value of the unpaid-out number counter when returning from the error state is a value reflecting the number of game balls actually paid out. That is, even if an error related to payout occurs, the number of game balls actually paid out can be accurately managed.

  Also, in the payout passing waiting process shown in FIGS. 60 to 62, even if it is confirmed that the game ball has been paid out as a result of the re-payout process, the payout case error bit is not reset. The bit of the payout case error is reset only when the error release switch 375 is operated (specifically, when an error return time after operation has elapsed) or when a payout case error is detected for a predetermined time. (2 minutes in this example) has elapsed (steps S7707, S7712). That is, until a predetermined time (in this example, 2 minutes) has passed since the detection of the payout case error, the payout case error (insufficient payout) is automatically determined based on the fact that the game ball has passed through the payout number count switch 301. The error) state is not canceled, and the payout case error is not canceled without an artificial operation. Therefore, the game store clerk and the like can surely recognize that a shortage of payout has occurred. However, in this embodiment, at least a long time (2 minutes in this example) after the occurrence of the payout case error is configured to automatically cancel the payout case error so that the payout case error is generated. Prevents continued for longer than necessary.

  In some cases, a gaming machine may be configured such that a hardware reset (reset to the payout control CPU 371) is performed by operating the error release switch 375. However, when such a gaming machine is configured, When the error release switch 375 is operated, for example, the value of the unpaid number counter is also cleared. However, in this embodiment, since the payout control means is configured to perform the re-payout operation again by operating the error release switch 375, the payout process is executed reliably, which is disadvantageous to the player. Can not be given.

  In step S7713, the payout control CPU 371 checks the detection signal of the full switch 48. If the detection signal of the full tank switch 48 is output (if it is in the ON state), the full tank error designation bit in the error flag is set (step S7714).

  Further, the payout control CPU 371 checks the detection signal of the ball break switch 187 (step S7715). If the detection signal of the ball break switch 187 is output (if it is on), the ball break error designation bit in the error flag is set (step S7716).

  Furthermore, the payout control CPU 371 checks the state of the connection signal from the main board 31 (step S7717), and if the connection signal is not output (if it is in the off state), sets the main board unconnected error designation bit. (Step S7718).

  Further, the payout control CPU 371 checks the value of the switch timer corresponding to the payout number count switch 301 among the switch timers in which the state of the detection signal of each switch is set, and the value is the switch on maximum time (for example, “ 250 ") (step S7719), the bit of the payout switch abnormality detection error 1 is set in the error flag (step S7720). It should be noted that the value of each switch timer is incremented by 1 when the state of the input port to which the detection signal of each switch is input is switched on in the input determination process of step S752, and cleared by 0 when it is off. Accordingly, the fact that the value of the switch timer corresponding to the payout number count switch 301 exceeds the switch on maximum time means that the payout number count switch 301 is in the on state exceeding the switch on maximum time. Then, it is determined that the game ball is clogged at the disconnection of the payout number count switch 301 or at the portion of the payout number count switch 301.

  Further, the payout control CPU 371 loads the payout control state flag when the value of the switch timer corresponding to the payout number count switch 301 becomes a switch-on determination value (for example, “4”) (step S7721). In step S7722), it is confirmed whether the winning ball payout operation or the ball lending payout operation is in progress (step S7723). Specifically, the payout control CPU 371 checks whether or not a prize ball payout operation specifying bit or a ball lending payout operation specifying bit is set in the payout control state flag. If the designated bit during the winning ball payout operation and the designated bit during the ball lending payout operation are both in the reset state, the payout control CPU 371 determines that the game ball has passed through the payout number count switch 301 even though the payout operation is not in progress, an error flag. Among these, the bit of the payout switch abnormality detection error 2 is set (step S7724).

  Further, the payout control CPU 371 checks whether or not the value of the payout number abnormality counter is equal to or greater than a predetermined payout number error error determination value (for example, 2000) (step S7725). If it is equal to or greater than a predetermined payout number error error determination value (for example, 2000), the payout control CPU 371 determines that a payout number error has occurred and sets a payout number error error flag (step S7726).

  Next, the payout control CPU 371 resets the prepaid card unit error flag for setting the error state of the prepaid card unit 50 (step S7727). Further, the payout control CPU 371 checks the input state of the VL signal from the card unit 50 (step S7728), and if the VL signal is not input (if it is in the off state), the prepaid card unit error flag The prepaid card unit unconnected error designation bit is set (step S7729).

  In the display control process of step S760, the error display LED 374 performs notification by display (numerical display) according to the error flag and the error bit in the prepaid card unit error flag. Therefore, a communication error can be notified by the error display LED 374. Further, since the communication error is detected on the payout control means side, the communication error can be detected without increasing the burden on the game control means.

  In this embodiment, the main board unconnected error is automatically canceled when the connection signal is turned on (see steps S7701, S7717, and S7718), but the condition that the error cancel switch 375 is further operated is set. In addition, the error state may be eliminated.

  In this embodiment, a communication error is reported so as to be distinguishable from a communication error with the card unit 50 (a prepaid card unit unconnected error and a prepaid card unit communication error) and other errors. Therefore, a communication error between the game control microcomputer 560 and the payout control microcomputer 370 is easily identified.

  In this embodiment, in error processing, first of the error flags, other than the payout switch abnormality detection error 2 designation bit, the payout case error designation bit, the main control communication error designation bit, and the withdrawal number abnormality error designation bit. After the bit is reset once (see step S7701), it is checked every time error processing is executed whether a full error, a ball break error, or a main control unconnected error has occurred. The payout switch abnormality detection error 2 designation bit, the payout case error designation bit, and the main control communication error designation bit are reset on the condition that the error release switch 375 has been operated. However, the payout number abnormality error is not canceled once it is set. Therefore, in this embodiment, when a payout number error occurs, the payout number error is canceled as a condition that the power supply is reset.

  65 and 66 are flowcharts showing the information output processing in step S759. In the information output process, the payout control CPU 371 first loads a payout control state flag (step S7901), and checks whether or not a ball lending payout operation is in progress (step S7902). Specifically, the payout control CPU 371 checks whether or not the designated bit during the ball lending payout operation of the payout control state flag is set. If the ball lending / dispensing operation is in progress, the process proceeds to step S7909. If the ball lending payout operation is not in progress, the payout control CPU 371 checks whether or not the payout number count switch 301 is in the on state (step S7903). If the payout number count switch 301 is in the ON state (in this case, the payout by the winning ball is detected), the payout control CPU 371 adds 1 to the value of the winning ball signal 1 output number counter (step S7904). At the same time, the value of the prize ball payout number counter is incremented by 1 (step S7905). The prize ball signal 1 output number counter is a counter for counting the number of times the condition for outputting the prize ball signal 1 is satisfied. The prize ball payout number counter is a counter for counting the number of game balls paid out by the prize ball payout.

  Next, the payout control CPU 371 checks whether or not the value of the added prize ball payout counter is equal to or greater than a predetermined prize ball information output determination value (10 in this example) (step S7906). If it is equal to or greater than the predetermined prize ball information output determination value (10 in this example), the payout control CPU 371 resets the prize ball payout number counter (step S7907) and sets the value of the prize ball information output number counter. 1 is added (step S7908). The prize ball information output count counter is a counter for counting the number of times that the condition for outputting prize ball information is satisfied.

  Next, if it is set, the payout control CPU 371 subtracts 1 from the prize ball information output timer (step S7909), and checks whether the prize ball information output timer after the subtraction has timed out (step S7910). The prize ball information output timer is a timer for measuring the output duration time of prize ball information. If not timed out, the process proceeds to step S7914. If time-out has occurred, the payout control CPU 371 checks whether or not the value of the prize ball information output number counter is 0 (step S7911). If the value of the prize ball information output number counter is 0, the process proceeds to step S7915. If the value of the winning ball information output number counter is not 0 (that is, if the number of winning ball information output conditions is still satisfied), the payout control CPU 371 subtracts 1 from the value of the winning ball information output number counter. (Step S7912). Next, the payout control CPU 371 sets a prize ball information output timer in order to start outputting the next prize ball information (step S7913). Then, the payout control CPU 371 performs control to output the prize ball information to the game control microcomputer 560 (step S7914). Specifically, the payout control CPU 371 performs a process of setting output data in a prize ball information output bit (bit 7, see FIG. 44) of the output port 1.

  Next, if it is set, the payout control CPU 371 subtracts 1 from the prize ball signal 1 output timer (step S7915), and checks whether the prize ball signal 1 output timer after the subtraction has timed out (step S7916). ). The prize ball signal 1 output timer is a timer for measuring the output duration time of the prize ball signal 1. If not timed out, the process proceeds to step S7920. If time-out has occurred, the payout control CPU 371 checks whether or not the value of the prize ball signal 1 output number counter is 0 (step S7917). If the value of the winning ball signal 1 output number counter is 0, the process proceeds to step S7921. If the value of the prize ball signal 1 output number counter is not 0 (that is, if the number of established conditions for the prize ball signal 1 still remains), the payout control CPU 371 determines the value of the prize ball signal 1 output number counter. 1 is subtracted (step S7918). Next, the payout control CPU 371 sets a prize ball signal 1 output timer to start outputting the next prize ball signal 1 (step S7919). Then, the payout control CPU 371 performs control to output the prize ball signal 1 to the outside (step S7920). Specifically, the payout control CPU 371 performs processing for setting output data in a prize ball signal 1 output bit (bit 0; see FIG. 44) of the output port 0. In this embodiment, the winning ball signal 1 is not directly input to the terminal board 160 from the payout control board 31 and output to the outside, but is input to the terminal board 160 once through the main board 31. Is output externally.

  Next, the payout control CPU 371 performs processing for setting output data in the gaming machine error state signal output bit (bit 1, see FIG. 44) of the output port 0 (step S7921), and loads an error flag (step S7922). ). If either the ball breakage error designation bit or the full tank error designation bit is set in the error flag (Y in steps S7923 and S7924), the gaming machine error status signal output bit of the output port 0 remains set. The process ends. In this case, the gaming machine error status signal is output to the outside based on the fact that the gaming machine error status signal output bit of the output port 0 is set in step S7921. In this embodiment, the gaming machine error state signal is not directly input from the payout control board 31 to the terminal board 160 but externally output, but is input to the terminal board 160 once via the main board 31. And output externally. On the other hand, if neither the ball breakage error designation bit nor the full tank error designation bit is set in the error flag, the payout control CPU 371 clears the gaming machine error state signal output bit of the output port 0 (step S7925), and processing Exit.

  By executing the above processing, in this embodiment, the prize ball signal 1 is output to the outside every time one prize ball payout is detected on the payout control means side. Further, prize ball information is output to the game control means side every time ten payout balls are detected on the payout control means side. Further, when a ball break error or a full tank error is detected on the payout control means side, a gaming machine error state signal is output to the outside.

  Next, the operation of the effect control means will be described. FIG. 67 is a flowchart showing main processing executed by the effect control microcomputer 100 (specifically, the effect control CPU 101) as effect control means mounted on the effect control board 80. The effect control CPU 101 starts executing the main process when the power is turned on. In the main processing, first, initialization processing for clearing the RAM area, setting various initial values, and initializing a timer for determining the activation control activation interval (for example, 4 ms) is performed (step S701). . Thereafter, the effect control CPU 101 proceeds to a loop process for monitoring a timer interrupt flag (step S702). When a timer interrupt occurs, the effect control CPU 101 sets a timer interrupt flag in the timer interrupt process. If the timer interrupt flag is set in the main process, the effect control CPU 101 clears the flag (step S703) and executes the following effect control process.

  In the effect control process, the effect control CPU 101 first analyzes the received effect control command and performs a process of setting a flag according to the received effect control command (command analysis process: step S704).

  Next, the effect control CPU 101 performs effect control process processing (step S705). In the effect control process, the process corresponding to the current control state (effect control process flag) is selected from the processes corresponding to the control state, and display control of the effect display device 9 is executed.

  Next, the production control CPU 101 performs the fourth symbol process (step S706). In the 4th symbol process, the process corresponding to the current control state (4th symbol process flag) is selected from the processes corresponding to the control state, and the 4th symbol display areas 9c and 9d of the effect display device 9 are selected. The display control of the 4th symbol is executed.

  Next, a random number update process for updating a count value of a counter for generating a random number such as a jackpot symbol determining random number is executed (step S707).

  Next, when the effect control process of steps S704 to S707 is executed, the effect control CPU 101 executes an abnormality determination process for detecting an abnormality in the state of the detection signal of the winning opening switch (step S708). Thereafter, the process proceeds to step S702.

  FIG. 68 is an explanatory diagram showing a configuration example of a command reception buffer for storing an effect control command received from the game control microcomputer 560 of the main board 31. In this example, a command reception buffer of a ring buffer type capable of storing six 2-byte configuration effect control commands is used. Therefore, the command reception buffer is configured by a 12-byte area of reception command buffers 1 to 12. A command reception number counter indicating in which area the received command is stored is used. The command reception number counter takes a value from 0 to 11. The ring buffer format is not necessarily required.

  The effect control command transmitted from the game control microcomputer 560 is received by an interrupt process based on the effect control INT signal, and is stored in a buffer area formed in the RAM. In the command analysis process, it is analyzed which command (see FIG. 29) the effect control command stored in the buffer area is.

  69 and 70 are flowcharts showing a specific example of the command analysis processing (step S704). The effect control command received from the main board 31 is stored in the reception command buffer, but in the command analysis process, the effect control CPU 101 confirms the content of the command stored in the command reception buffer.

  In the command analysis process, the effect control CPU 101 first checks whether or not a reception command is stored in the command reception buffer (step S611). Whether it is stored or not is determined by comparing the value of the command reception number counter with the read pointer. The case where both match is the case where the received command is not stored. When the reception command is stored in the command reception buffer, the effect control CPU 101 reads the reception command from the command reception buffer (step S612). When read, the value of the read pointer is incremented by +2 (step S613). The reason for +2 is that 2 bytes (1 command) are read at a time.

  If the received effect control command is a frame state display command (step S614), the effect control CPU 101 sets a prize ball error bit (bit 0, see FIG. 14) among the lower 4 bits of the frame state display command. It is confirmed whether it has been done (step S615). If set, the effect control CPU 101 performs control to superimpose and display predetermined prize ball error notification information on the display screen of the effect display device 9 (step S616). For example, the effect control CPU 101 performs control to display a character string such as “A prize ball error has occurred” on the display screen of the effect display device 9.

  In addition, the effect control CPU 101 checks whether or not the full error bit (bit 1, see FIG. 14) of the lower 4 bits of the frame state display command is set (step S617). If set, the effect control CPU 101 performs control to superimpose and display predetermined full tank error notification information on the display screen of the effect display device 9 (step S618). For example, the effect control CPU 101 performs control to display a character string such as “a full tank error has occurred” on the display screen of the effect display device 9.

  Further, the effect control CPU 101 checks whether or not the ball break error bit (bit 2; see FIG. 14) in the lower 4 bits of the frame state display command is set (step S619). If set, the effect control CPU 101 performs control to superimpose and display predetermined ball-out error notification information on the display screen of the effect display device 9 (step S620). For example, the effect control CPU 101 performs control to display a character string such as “A ball break error has occurred” on the display screen of the effect display device 9.

  Further, the production control CPU 101 checks whether or not the payout number error error bit (bit 3; see FIG. 14) in the lower 4 bits of the frame state display command is set (step S621). If set, the effect control CPU 101 performs control to superimpose and display predetermined payout number abnormality error notification information on the display screen of the effect display device 9 (step S622). For example, the effect control CPU 101 performs control to display a character string such as “A payout number error has occurred” on the display screen of the effect display device 9.

  If the received effect control command is a prize ball shortage error command (step S623), the effect control CPU 101 performs control to superimpose and display predetermined prize ball shortage error notification information on the display screen of the effect display device 9 (step S623). S624). For example, the effect control CPU 101 performs control to display a character string such as “A shortage of prize balls has occurred” on the display screen of the effect display device 9.

  If the received effect control command is a prize ball excess error command (step S625), the effect control CPU 101 performs control to superimpose and display predetermined prize ball excess error notification information on the display screen of the effect display device 9 (step S625). S626). For example, the CPU 101 for effect control performs control to display a character string such as “An excessive prize ball error has occurred” on the display screen of the effect display device 9.

  In addition, each error display may not be simply displayed in a superimposed manner, but may be prioritized and notified of an error having a high priority by ranking from the viewpoint of fraud importance. For example, a payout number abnormality error may be preferentially notified with the highest priority, or a newly generated error may be preferentially notified when the error state changes.

  Further, in this embodiment, a case is shown in which each error notification is performed by performing a predetermined error display on the display screen of the effect display device 9 (see steps S616, S618, S620, S622, S624, and S626). The error notification method is not limited to that shown in this embodiment. For example, an error may be notified by outputting a predetermined warning sound using the speaker 27, or an error may be notified by lighting or blinking the decoration LED 25 or the frame LED 28 in a predetermined lighting / flashing pattern. Further, any two or all of the display on the display screen of the effect display device 9, the sound output using the speaker 27, and the lighting / flashing display using the decoration LED 25 and the frame LED 28 are used in combination for error notification. May be performed.

  If the received production control command is an input port state 1 designation command (see FIG. 29) (step S627), the production control CPU 101 designates the input port state 1 designation command as an input port state 1 designated in the RAM. Store in the command storage area (step S628). Then, an input port state 1 designation command reception flag is set (step S629).

  If the received production control command is an input port state 2 designation command (see FIG. 29) (step S630), the production control CPU 101 designates the input port state 2 designation command as an input port state 2 designated in the RAM. Store in the command storage area (step S631). Then, an input port state 2 designation command reception flag is set (step S632).

  If the received effect control command is another command, effect control CPU 101 sets a flag corresponding to the received effect control command (step S633). Then, control goes to a step S611. For example, when a variation pattern command or a display result designation command is received, the effect control CPU 101 also stores the received variation pattern command or display result designation command in a predetermined storage area formed in the RAM. Do.

  FIG. 71 is a flowchart showing the effect control process (step S705) in the main process shown in FIG. In the effect control process, the effect control CPU 101 performs one of steps S800 to S807 according to the value of the effect control process flag. In each process, the following process is executed. In the effect control process, the display state of the effect display device 9 is controlled and variable display of the effect symbol is realized. However, control related to variable display of the effect symbol synchronized with the change of the first special symbol is also the second. Control related to the variable display of the effect symbol synchronized with the change of the special symbol is also executed in one effect control process. It should be noted that the variable display of the effect symbol synchronized with the variation of the first special symbol and the variable display of the effect symbol synchronized with the variation of the second special symbol may be executed by separate effect control process processing. Good. Further, in this case, it may be determined which special symbol variation display is being executed depending on which representation control process processing is performing the variation display of the representation symbol.

  Fluctuation pattern command reception waiting process (step S800): It is confirmed whether or not a variation pattern command has been received from the game control microcomputer 560. Specifically, it is confirmed whether or not the variation pattern command reception flag set in the command analysis process is set. If the change pattern command has been received, the value of the effect control process flag is changed to a value corresponding to the effect symbol change start process (step S801).

  Production symbol variation start processing (step S801): Control is performed so that the variation of the production symbol is started. Then, the value of the effect control process flag is updated to a value corresponding to the effect symbol changing process (step S802).

  Production symbol variation processing (step S802): Controls the switching timing of each variation state (variation speed) constituting the variation pattern and monitors the end of the variation time. When the variation time ends, the value of the effect control process flag is updated to a value corresponding to the effect symbol variation stop process (step S803).

  Effect symbol variation stop processing (step S803): Control is performed to stop the variation of the effect symbol and derive and display the display result (stop symbol). Then, the value of the effect control process flag is updated to a value corresponding to the jackpot display process (step S804) or the variation pattern command reception waiting process (step S800).

  Big hit display process (step S804): When the big hit is reached, after the variation time is over, the effect display device 9 is controlled to display a screen for notifying the occurrence of the big hit. In the case of a small hit, control is performed to display a screen for notifying the effect display device 9 of the occurrence of the small hit after the end of the variation time. For example, when a fanfare designation command designating the start of a big hit is received, a fanfare effect is executed. Then, the value of the effect control process flag is updated to a value corresponding to the in-round processing (step S805).

  In-round processing (step S805): Display control during round is performed. For example, if a display command indicating that the special winning opening is open is received, the display control of the number of rounds is performed.

  Post-round processing (step S806): Display control between rounds is performed. For example, when a display command after opening the big prize opening indicating that the big prize opening is after being opened (closed), an interval display is performed.

  Big hit end effect processing (step S807): In the effect display device 9, display control is performed to notify the player that the big hit game state has ended. For example, when an ending designation command for designating the end of the big hit is received, an ending effect is executed. Then, the value of the effect control process flag is updated to a value corresponding to the variation pattern command reception waiting process (step S800).

  Next, the winning abnormality processing executed by the production control microcomputer 100 will be described. FIG. 72 is an explanatory diagram showing an example of a winning abnormality detection method. In the example shown in FIG. 72, for each of the winning opening switches (the first starting opening switch 13a, the second starting opening switch 14a, the count switch 23, and each winning opening switch 29a, 30a), the ON state of the detection signal is 1 second. If it continues beyond, it is determined that a winning abnormality has occurred. The time of 1 second is an example, and the time for detecting an abnormality is not limited to 1 second. Also, the winning abnormality is an abnormality in the state of the detection signal of the winning opening switch.

  FIG. 73 is an explanatory diagram showing an example of a timer used by the production control microcomputer 100 for detection of a winning abnormality. As shown in FIG. 73, as timers used for detection of winning abnormality, a timer corresponding to the second starting port switch 14a, a timer corresponding to the first starting port switch 13a, a timer corresponding to the winning port switch 30a, a winning port There is a timer corresponding to the switch 29a and a timer corresponding to the count switch 23. Each timer is formed in the RAM.

  74 and 75 are flowcharts showing the abnormality determination processing in step S708. In the abnormality determination process, the effect control CPU 101 includes a timer corresponding to the second start port switch 14a, a timer corresponding to the first start port switch 13a, a timer corresponding to the winning port switch 30a, and a timer corresponding to the winning port switch 29a. Then, it is checked whether or not the value of any one of the timers corresponding to the count switch 23 is a value other than 0 (corresponding to being in operation) (step S1711). If there is an operating timer, the timer value is incremented by 1 (step S1712). It should be noted that a timer operating flag is used as in another example of the winning abnormality detection method (see FIGS. 76 to 79), and whether or not the timer is operating is confirmed by the timer operating flag. Good.

  In addition, the effect control CPU 101 checks whether or not the value of any timer exceeds 250 (corresponding to 1 second) (step S1713). If there is a timer exceeding 250, the effect display device 9 displays “A prize abnormality has occurred” (step S1714). Further, the sound number data corresponding to the abnormality notification sound is output to the sound output board 70 (step S1715).

  Through the processing in steps S1714 and S1715, an abnormality notification is displayed on the effect display device 9, and an abnormality notification sound is output from the speaker 27. In addition, in the processing of steps S1714 and S1715, display and sound output capable of distinguishing which switch has caused the winning abnormality may be performed.

  In addition, the effect control CPU 101 checks whether or not the input port state 1 designation command reception flag indicating that the input port state 1 designation command has been received is set (step S1716). If the input port state 1 designation command reception flag is not set, the process ends. If the input port state 1 designation command reception flag is set, the input port state 1 designation command reception flag is reset (step S1717), and the input port state 1 stored in the input port state 1 designation command storage area is reset. In the data indicating the state of the input port 0 (input port 0 in the game control means) that is the data of the designated command, it is confirmed whether any one or more of the bits 0, 2, and 3 has changed to “1” ( Step S1718).

  In step S1718, the effect control CPU 101 compares the previous value stored in the RAM in the process of step S1721 with the data of the input port state 1 designation command.

  If there is a bit that is “1”, “1” is set in the timer corresponding to that bit (the timer corresponding to the winning port switch 30a, the timer corresponding to the winning port switch 29a, or the timer corresponding to the count switch 23). (Step S1720). Then, control goes to a step S1721.

  Further, when there is no bit that is “1” in the data indicating the state of the input port 0 (data indicating the state of the count switch 23 and the prize opening switches 29a and 30a), it corresponds to the bit that is “0”. The timer value to be initialized is initialized to 0 (step S1719). Then, control goes to a step S1721. Note that the game control microcomputer 560 transmits an input port state 1 designation command when any bit of the input port 0 changes, so that there is no bit changed to “1”. ”Means that there is a bit changed.

  Then, the production control CPU 101 stores the data in the input port state 1 designation command storage area in the RAM as the previous value (step S1721).

  The game control microcomputer 560 changes the value of any bit of the input port 0 (any one of the bits 0, 2, 3 of the input port 0 shown in FIG. 7) (the state of the switch detection signal changes). Since the input port state 1 designation command in which the state of each bit of the input port 0 is set is output, the timer corresponding to the switch changed to the ON state by the processing of steps S1718 and S1719 is operating. become. Since the timer value advances unless the value of the bit corresponding to the timer that is in operation becomes “0” (by the processing of steps S 1711 and S 1712), that the timer value has exceeded 250. This means that the state of the detection signal of the switch was an on state that continued for more than 1 second.

  In addition, the effect control CPU 101 checks whether or not the input port state 2 designation command reception flag indicating that the input port state 2 designation command has been received is set (step S1722). If the input port state 2 designation command reception flag is not set, the process ends. If the input port state 2 designation command reception flag is set, the input port state 2 designation command reception flag is reset (step S1723), and the input port state 2 stored in the input port state 2 designation command storage area. In the data indicating the state of the input port 2 (input port 2 in the game control means) that is the data of the designated command, it is confirmed whether or not one or more of the bits 0 and 1 is “1” (step S1724). .

  In step S <b> 1724, the effect control CPU 101 compares the previous value stored in the RAM in the process of step S <b> 1727 with the data of the input port state 2 designation command.

  If there is a bit that is “1”, “1” is set in the timer corresponding to that bit (the timer corresponding to the first start port switch 13a and the timer corresponding to the second start port switch 14a) (step S1726). . Then, control goes to a step S1727.

  In addition, when there is no bit that is “1” in the data indicating the state of the input port 2 (data indicating the state of the first start port switch 13a and the second start port switch 14a), the value is “0”. The timer value corresponding to the bit is initialized to 0 (step S1725). Then, control goes to a step S1727. Note that the game control microcomputer 560 transmits an input port state 2 designation command when any bit of the input port 2 changes, so that there is no bit changed to “1”. ”Means that there is a bit changed.

  Then, the production control CPU 101 stores the data in the input port state 2 designation command storage area in the RAM as the previous value (step S1727).

  When the value of any bit of the input port 2 (any one of the bits 0 and 1 of the input port 2 shown in FIG. 7) changes (the state of the detection signal of the switch changes) Since the input port state 2 designation command in which the state of each bit of the input port 2 is set is output, the timer corresponding to the switch changed to the ON state is in operation by the processing of steps S1724 and S1725. . Since the timer value advances unless the value of the bit corresponding to the timer that is in operation becomes “0” (by the processing of steps S 1711 and S 1712), that the timer value has exceeded 250. This means that the state of the detection signal of the switch was an on state that continued for more than 1 second.

  Further, the effect control CPU 101 can perform the abnormality determination as shown in FIG. 72 by executing the processes of steps S1713, S1714, and S1715.

  FIG. 76 is an explanatory diagram showing another example of a method for detecting a prize abnormality. In the example shown in FIG. 76, each of the winning opening switches (the first starting opening switch 13a, the second starting opening switch 14a, the count switch 23, and each winning opening switch 29a, 30a) is within a predetermined time (shown in FIG. 76). In the example, when the state of the detection signal is turned on more than a predetermined number of times (in the example shown in FIG. 76, it has exceeded 10 times) in 0.5 seconds) (specifically, the state has changed from on to off). It is determined that a winning abnormality has occurred. Note that 0.5 seconds is an example, and the predetermined time for detecting an abnormality is not limited to 0.5 seconds. Another example is exceeding 10 times.

  FIG. 77 is an explanatory diagram showing an example of a timer, a flag, and a counter used by the effect control microcomputer 100 for detection of winning abnormality. As shown in FIG. 77, as timers used for detection of winning abnormality, a timer corresponding to the second starting port switch 14a, a timer corresponding to the first starting port switch 13a, a timer corresponding to the winning port switch 30a, and a winning port There is a timer corresponding to the switch 29a and a timer corresponding to the count switch 23. Further, as flags to be used for detection of winning abnormality, a timer operating flag corresponding to the second starting port switch 14a, a timer operating flag corresponding to the first starting port switch 13a, and a timer operating corresponding to the winning port switch 30a are operating. There are a flag, a timer operating flag corresponding to the winning port switch 29a, and a timer operating flag corresponding to the count switch 23. Further, as counters used for detection of winning abnormality, a counter corresponding to the second starting port switch 14a, a counter corresponding to the first starting port switch 13a, a counter corresponding to the winning port switch 30a, and a winning port switch 29a. There are counters and counters corresponding to the count switch 23. Each counter is formed in the RAM.

  78 and 79 are flowcharts showing the abnormality determination process in step S708 when abnormality detection as exemplified in FIG. 76 is performed. In the abnormality determination process, the effect control CPU 101 includes a timer corresponding to the second start port switch 14a, a timer corresponding to the first start port switch 13a, a timer corresponding to the winning port switch 30a, and a timer corresponding to the winning port switch 29a. Then, it is checked whether or not the value of any one of the timers corresponding to the count switch 23 is operating (timer operating flag is on) (step S1711). If there is an operating timer, the timer value is incremented by 1 (step S1712).

  In addition, the effect control CPU 101 checks whether or not the input port state 1 designation command reception flag indicating that the input port state 1 designation command has been received is set (step S1716). If the input port state 1 designation command reception flag is not set, the process proceeds to step S1735. If the input port state 1 designation command reception flag is set, the input port state 1 designation command reception flag is reset (step S1717), and the input port state 1 stored in the input port state 1 designation command storage area is reset. In the data indicating the state of the input port 0 (input port 0 in the game control means) that is the data of the designated command, it is confirmed whether any one or more of the bits 0, 2, and 3 has changed to “1” ( Step S1731).

  In step S1731, the effect control CPU 101 compares the previous value stored in the RAM in the process of step S1739 with the data of the input port state 1 designation command.

  If there is a bit changed to “1”, the value of the counter corresponding to that bit (the counter corresponding to the winning port switch 30a, the counter corresponding to the winning port switch 29a, or the counter corresponding to the count switch 23) is incremented by one. (Step S1732). If the timer corresponding to the bit changed to “1” is not operating (step S 1733), the timer operating flag corresponding to the bit is set (turned on) (step S 1734).

  In addition, the CPU 101 for effect control has a value of any timer (timer corresponding to the prize opening switch 30a, timer corresponding to the prize opening switch 29a, or timer corresponding to the count switch 23) of 125 (in 0.5 seconds). It is confirmed whether or not (equivalent) is exceeded (step S1735). If there is no timer exceeding 125, the process proceeds to step S1739. If there is a timer exceeding 125, the value of the counter corresponding to the timer is confirmed (step S1736). If the value of the counter exceeds 10, the effect display device 9 displays “A prize abnormality has occurred” (step S1740). Further, the sound number data corresponding to the abnormality notification sound is output to the sound output board 70 (step S1741).

  If there is a counter having a value of 10 or less, the effect control CPU 101 clears the value of the counter to 0 (step S1737). In addition, the corresponding timer operating flag is reset (turned off), and the value of the corresponding timer is initialized to 0 (step S1738).

  Then, the data in the input port state 1 designation command storage area is stored in the RAM as the previous value (step S1739).

  The game control microcomputer 560 changes the value of any bit of the input port 0 (any one of the bits 0, 2, 3 of the input port 0 shown in FIG. 7) (the state of the switch detection signal changes). The input port state 1 designation command in which the state of each bit of the input port 0 is set is output, but the fact that there is a bit changed to “1” in the process of step S1731 indicates that the input port state 1 This means that the state of the relevant bit of 0 has changed from “0” to “1” (corresponding to the change of the switch detection signal from the OFF state to the ON state). Therefore, the process of step S1732 is a process of counting the number of times the switch detection signal has changed from the off state to the on state.

  Checking the counter value when 0.5 second has elapsed in the processing of steps S1735 and S1736 is equivalent to confirming the number of times that the switch detection signal has been turned on for 0.5 seconds. . That is, the abnormality determination as shown in FIG. 76 is executed.

  In addition, the effect control CPU 101 checks whether or not the input port state 2 designation command reception flag indicating that the input port state 2 designation command has been received is set (step S 1742). If the input port state 2 designation command reception flag is not set, then the flow shifts to step S1748. If the input port state 2 designation command reception flag is set, the input port state 2 designation command reception flag is reset (step S1743), and the input port state 2 stored in the input port state 2 designation command storage area. In the data indicating the state of the input port 2 (input port 2 in the game control means) which is the data of the designated command, it is confirmed whether or not any one or more of the bits 0 and 1 has changed to “1” (step S1744). ).

  In step S1744, the effect control CPU 101 compares the previous value stored in the RAM in the process of step S1752 with the data of the input port state 2 designation command.

  If there is a bit changed to “1”, the value of the counter corresponding to that bit (the counter corresponding to the second start port switch 14a, the counter corresponding to the first start port switch 13a) is incremented by 1 (step S1745). If the timer corresponding to the bit changed to “1” is not operating (step S1746), the timer operating flag corresponding to the bit is set (turned on) (step S1747).

  In addition, the production control CPU 101 determines whether the value of any one of the timers (the counter corresponding to the second starting port switch 14a and the counter corresponding to the first starting port switch 13a) exceeds 125 (corresponding to 0.5 seconds). It is confirmed whether or not (step S1748). If there is no timer exceeding 125, the process proceeds to step S1752. If there is a timer exceeding 125, the value of the counter corresponding to the timer is confirmed (step S1749). If the counter value exceeds 10, the effect display device 9 displays “A prize abnormality has occurred” (step S1753). Further, sound number data corresponding to the abnormality notification sound is output to the sound output board 70 (step S1754).

  If there is a counter having a value of 10 or less, the effect control CPU 101 clears the counter value to 0 (step S1750). In addition, the corresponding timer operating flag is reset (turned off), and the value of the corresponding timer is initialized to 0 (step S1751).

  Then, the data in the input port state 2 designated command storage area is stored in the RAM as the previous value (step S1752).

  When the value of any bit of the input port 2 (any one of the bits 0 and 1 of the input port 2 shown in FIG. 7) changes (the state of the detection signal of the switch changes) The input port state 2 designation command in which the state of each bit of the input port 2 is set is output. In step S1744, there is a bit that has changed to “1”. This means that the state after the logic inversion of the bit has changed from “0” to “1” (corresponding to the change of the switch detection signal from the OFF state to the ON state). Therefore, the process of step S1745 is a process of counting the number of times the switch detection signal has changed from the off state to the on state.

  Checking the counter value when 0.5 seconds have elapsed in the processing of steps S1748 and S1749 is equivalent to confirming the number of times that the switch detection signal has been turned on for 0.5 seconds. . That is, the abnormality determination as shown in FIG. 76 is executed.

  When an illegal act illustrated in FIG. 28B is performed, the state of the detection signal of the switch may be as illustrated in the lower part of FIG. 28C. When the signal state as shown in the lower part of FIG. 28C is generated by the processing shown in FIG. 79, an abnormality is detected (see FIG. 76). That is, the process shown in FIGS. 78 and 79 is a process capable of detecting an illegal act illustrated in FIG.

  FIG. 80 is an explanatory diagram showing still another example of a winning abnormality detection method. In the example shown in FIG. 80, when the game ball normally passes the winning opening switch, the winning opening switch (the first starting opening switch 13a, the second starting opening switch 14a, the count switch 23, and each winning opening switch 29a is displayed. , 30a) is assumed to be a proximity switch in which the ON state continues for at least 50 milliseconds (50 ms).

  As shown in FIG. 80, when the game ball passes through the switch, the on state should normally continue for, for example, 50 ms or longer, while the detection signal is in the on state (for example, 50 ms). In the case where the switch is forcibly turned off, it is determined that the switch is turned on a plurality of times even though one game ball is actually detected by the switch. Therefore, the production control microcomputer 100 measures the time until the switch enters the off state when the detection signal of each switch changes to the on state based on the input port state 1 designation command or the input port state 2 designation command. When the measured time is shorter than, for example, 50 ms, it is preferable to determine that an abnormality has occurred (for example, an illegal act has been received). Note that 50 ms is an example, and may vary depending on the characteristics of the switch used.

  In addition, even when the game ball passes through the switch continuously, the switch detects the completion of the passage of the first game ball (corresponding to when the detection signal is turned off) and then detects the second game ball. There is at least a predetermined time (for example, 32 ms) before the start is detected (corresponding to when the detection signal is turned on). Therefore, if the detection signal OFF period (the period from when the ON state is changed to the OFF state until the ON state is again turned on) is shorter than the predetermined period (that is, 32 ms in this example), an abnormality has occurred. (For example, a cheating is received.) In this example, it is determined that an abnormality has occurred when the off period is 32 ms or less. Note that 32 ms is an example, and the predetermined period for detecting an abnormality is not limited to 32 milliseconds.

  Further, in this example, similarly to the example shown in FIG. 77, regarding the detection of the winning abnormality, the timer corresponding to the second start port switch 14a, the timer corresponding to the first start port switch 13a, and the winning port switch 30a A corresponding timer, a timer corresponding to the winning prize switch 29a, and a timer corresponding to the count switch 23 are used. Further, as flags to be used for detection of winning abnormality, a timer operating flag corresponding to the second starting port switch 14a, a timer operating flag corresponding to the first starting port switch 13a, and a timer operating corresponding to the winning port switch 30a are operating. A flag, a timer operating flag corresponding to the winning port switch 29a, and a timer operating flag corresponding to the count switch 23 are used. However, the counter is not used.

  81 and 82 show the abnormality in step S708 in the case of performing the abnormality detection illustrated in FIG. 80 (determining that an abnormality has occurred when the detection signal OFF period is equal to or shorter than a predetermined period (for example, 32 ms)). It is a flowchart which shows a determination process. In the abnormality determination process, the effect control CPU 101 includes a timer corresponding to the second start port switch 14a, a timer corresponding to the first start port switch 13a, a timer corresponding to the winning port switch 30a, and a timer corresponding to the winning port switch 29a. Then, it is checked whether or not the value of any one of the timers corresponding to the count switch 23 is operating (timer operating flag is on) (step S1711). If there is an operating timer, the timer value is incremented by 1 (step S1712).

  In addition, the effect control CPU 101 checks whether or not the input port state 1 designation command reception flag indicating that the input port state 1 designation command has been received is set (step S1716). If the input port state 1 designation command reception flag is not set, the process ends. If the input port state 1 designation command reception flag is set, the input port state 1 designation command reception flag is reset (step S1717), and the input port state 1 stored in the input port state 1 designation command storage area is reset. In the data indicating the state of the input port 0 (input port 0 in the game control means) that is the data of the designated command, it is confirmed whether any one or more of the bits 0, 2, and 3 has changed to “0” ( Step S1761).

  In the process of step S1761, the CPU 101 for effect control compares the previous value stored in the RAM in the process of step S1766 with the data of the input port state 1 designation command.

  If there is a bit changed to "0", the timer operating flag corresponding to the bit is set (turned on) (step S1762).

  Further, the effect control CPU 101 uses any one of bits 0, 2 and 3 in the data indicating the state of the input port 0 which is the data of the input port state 1 specifying command stored in the input port state 1 specifying command storage area. It is confirmed whether or not one or more has changed to “1” (step S1763). If there is no bit changed to “1”, the process shifts to step S1766.

  In the process of step S1763, the effect control CPU 101 compares the previous value stored in the RAM in the process of step S1766 with the data of the input port state 1 designation command.

  If there is a bit changed to “1”, the timer value corresponding to the bit is confirmed (step S1764). In step S1764, the CPU 101 for effect control confirms whether or not the timer value is 8 or less (corresponding to 32 ms or less). When the timer value exceeds 8, the timer operating flag corresponding to the bit is reset (turned off), and the corresponding timer value is initialized to 0 (step S1765). Further, the data in the input port state 1 designated command storage area is stored in the RAM as the previous value (step S1766).

  When the value of the timer is 8 or less, the effect control CPU 101 displays “effect of winning abnormality” on the effect display device 9 (step S1767). Further, the sound number data corresponding to the abnormality notification sound is output to the sound output board 70 (step S1768).

  The game control microcomputer 560 changes the value of any bit of the input port 0 (any one of the bits 0, 2, 3 of the input port 0 shown in FIG. 7) (the state of the switch detection signal changes). The input port state 1 designation command in which the state of each bit of the input port 0 is set is output, but the fact that there is a bit changed to “0” in the process of step S1761 This means that the state of the relevant bit of 0 has changed from “1” to “0” (corresponding to the change of the switch detection signal from the ON state to the OFF state). Therefore, the process of step S1762 corresponds to a process of starting a timer when the switch detection signal changes from the on state to the off state.

  In addition, when there is a bit that has changed to “1” in the process of step S1763, the state of the bit of input port 0 has changed from “0” to “1” (the switch detection signal has changed from OFF to ON It is equivalent to changing to a state). Therefore, the process of step S1763 is a process of determining whether or not the switch detection signal has changed from the off state to the on state. Checking the value of the timer in the process of step S1764 corresponds to determining whether or not the period in which the detection signal is in the off state is 32 ms or less. That is, the abnormality determination as shown in FIG. 80 is executed.

  In addition, the effect control CPU 101 checks whether or not the input port state 2 designation command reception flag indicating that the input port state 2 designation command has been received is set (step S 1742). If the input port state 2 designation command reception flag is not set, the process ends. If the input port state 2 designation command reception flag is set, the input port state 2 designation command reception flag is reset (step S1743), and the input port state 2 stored in the input port state 2 designation command storage area. In the data indicating the state of the input port 2 (input port 2 in the game control means) that is the data of the designated command, it is confirmed whether or not any one of bits 0 and 1 has changed to “0” (step S1771). .

  In the process of step S1771, the CPU 101 for effect control compares the previous value stored in the RAM in the process of step S1776 with the data of the input port state 2 designation command.

  If there is a bit changed to “0”, the timer operating flag corresponding to the bit is set (turned on) (step S1772).

  In addition, the effect control CPU 101 uses any one of bits 0 and 1 in the data indicating the state of the input port 2 which is data of the input port state 2 designation command stored in the input port state 2 designation command storage area. It is confirmed whether or not the above has changed to “1” (step S1773). If there is no bit changed to “1”, the process shifts to step S1776.

  In the process of step S1773, the effect control CPU 101 compares the previous value stored in the RAM in the process of step S1776 with the data of the input port state 2 designation command.

  If there is a bit changed to “1”, the timer value corresponding to the bit is confirmed (step S1774). In step S1774, the effect control CPU 101 checks whether or not the timer value is 8 or less (corresponding to 32 ms or less). If the timer value exceeds 8, the timer operating flag corresponding to that bit is reset (turned off), and the corresponding timer value is initialized to 0 (step S1775). Further, the data of the input port state 2 designated command storage area is stored in the RAM as the previous value (step S1776).

  When the value of the timer is 8 or less, the effect control CPU 101 displays “effect of winning abnormality” on the effect display device 9 (step S1777). Further, the sound number data corresponding to the abnormality notification sound is output to the sound output board 70 (step S1778).

  When the value of any bit of the input port 2 (any one of the bits 0 and 1 of the input port 2 shown in FIG. 7) changes (the state of the detection signal of the switch changes) The input port state 2 designation command in which the state of each bit of the input port 2 is set is output. However, the fact that there is a bit changed to “0” in the process of step S1771 indicates that the input port 2 This means that the state after the logic inversion of the bit has changed from “1” to “0” (corresponding to the change of the switch detection signal from the ON state to the OFF state). Therefore, the process of step S1772 corresponds to a process of starting a timer when the switch detection signal changes from the on state to the off state.

  In addition, when there is a bit that has changed to “1” in the process of step S1773, the state after the logic inversion of the bit of the input port 2 has changed from “0” to “1” (the switch detection signal is Equivalent to a change from an off state to an on state). Therefore, the process of step S1773 is a process of determining whether or not the switch detection signal has changed from the off state to the on state. Checking the timer value in the process of step S1774 is equivalent to determining whether or not the period in which the detection signal is matched in the off state is 32 ms or less. That is, the abnormality determination as shown in FIG. 80 is executed.

  When an illegal act illustrated in FIG. 28B is performed, the state of the detection signal of the switch may be as illustrated in the lower part of FIG. 28C. If the signal state as shown in the lower part of FIG. 28C is generated by the processing shown in FIG. 82 and the detection signal is in the OFF state for a predetermined period (32 ms in this example) or less, Are detected as abnormal (see FIG. 80). That is, the process shown in FIGS. 81 and 82 is a process capable of detecting an illegal act illustrated in FIG.

  The effect control CPU 101 performs the processing shown in FIGS. 74 and 75, the processing shown in FIGS. 78 and 79, and the processing shown in FIGS. 81 and 82 in the abnormality determination processing in step S708. However, two or more of the processes may be executed.

  In this embodiment, when the effect control CPU 101 determines that a prize abnormality has occurred, the effect display CPU 9 displays “A prize abnormality has occurred” on the effect display device 9 and an abnormality notification sound on the audio output board 70. Although the sound number data for outputting is output, abnormality notification may be performed by a light emitter (such as an LED) provided in the gaming machine. In addition, you may use any one or two of the display of the production | presentation display apparatus 9, the output of an abnormality notification sound, and alerting | reporting by a light-emitting body.

  The abnormality notification may be ended at any time, for example, until the predetermined time has elapsed from when it is determined that a winning abnormality has occurred, until the effect control CPU 101 does not determine that the winning abnormality has occurred, or It is conceivable that the abnormality notification is continued until the power supply is stopped.

  In this embodiment, the effect control CPU 101 adds the timer value, and the timer value is a predetermined value (250 in the example shown in FIG. 74, 125 in the examples shown in FIGS. 78 and 79). ), It is determined that a winning abnormality has occurred (see steps S1713 and S1714 in FIG. 74), or it is determined that a winning abnormality has occurred on condition that the counter value is equal to or greater than a predetermined value (see FIG. 78 and FIG. 79 (see steps S 1735, S 1736, S 1740, S 1748, S 1749, S 1750) and the value of the timer is less than or equal to a predetermined value (8 or less in the examples shown in FIG. 81 and FIG. 82) (See steps S1764, S1767, S1774, S1777 in FIGS. 81 and 82), The value may be subtracted to the.

  For example, the CPU 101a for effect control sets 250 in the timer in the process of step S1720 in FIG. 74 and subtracts 1 from the timer value in the process of step S1712, or in the processes of steps S1738 and S1751 in FIGS. 78 and 79. The timer is initially set to 125 and the timer value is decremented by 1 in the process of step S1712, or the timer is initially set to 8 in the processes of steps S1765 and S1775 in FIGS. 81 and 82, and the timer value is set in the process of step S1712. 1 is subtracted. In that case, the effect control CPU 101 confirms whether or not the timer value has become 0 in the processing of step S1713 in FIG. 74 and the processing of steps S1735 and S1748 in FIG. 78 and FIG. Also, in the processing of steps S1764 and S1774 in FIGS. 81 and 82, it is confirmed whether or not the timer value is 0 or a negative value.

  In this embodiment, the game control microcomputer 560 transmits the input port state 1 designation command and the input port state 2 designation command only when the state of the detection signal from any one of the prize opening switches changes. However, regardless of whether the state of the detection signal changes or not, the input port state 1 designation command or the input port state 2 designation command is transmitted every start period of the game control process (4 ms in this embodiment). It may be.

  When the input port state 1 designation command or the input port state 2 designation command is transmitted every start period of the game control process, the game control microcomputer 560 performs step S2109 in the switch process (see FIGS. 33 and 34). Regardless of the result of the calculation in S2125, control is performed to transmit the input port state 1 designation command and the input port state 2 designation command.

  If the CPU 101 for effect control confirms that there is no bit changed to “1” in the data indicating the states of the input ports 0 and 2 in the processing of steps S1718 and S1724 shown in FIGS. 74 and 75, There is a bit changed to “0” in the data indicating the states of the input ports 0 and 2 by comparing the previous value stored in the RAM with the data of the input port state 1 designation command or the input port state 2 designation command. If it is confirmed that there is a bit changed to “0”, the processing of steps S1719 and S1725 is executed. In the processing shown in FIGS. 74 and 75, whether or not there is a bit changed to “0” in the data indicating the states of the input ports 0 and 2 is determined by the game control microcomputer 560. , 2 when the input port state 1 designation command or the input port state 2 designation command is transmitted on the assumption that the bit of the detection signal changes / does not change. Regardless of this, when an input port state 1 designation command or an input port state 2 designation command is transmitted at each start period of the game control process, the bit changed to “1” in the data indicating the states of the input ports 0 and 2 is also “0”. This is because there may be no bit changed to "."

  Even when the input port state 1 designation command or the input port state 2 designation command is transmitted every start cycle of the game control process regardless of whether the state of the detection signal changes or not, the processes shown in FIGS. As for the processes shown in FIGS. 81 and 82, the effect control CPU 101 may perform the same process.

  As described above, according to this embodiment, when a predetermined payout condition is satisfied (the first start winning opening 13, the second starting winning opening 14, the big winning opening, the normal winning openings 29, 30). A payout condition establishment signal (winning signal) indicating that a predetermined payout condition for paying out a predetermined number of game balls (10 balls in this example) is satisfied Output. Therefore, by outputting the payout condition establishment signal (winning signal) to the outside, the number of payouts in the big hit gaming state can be accurately grasped.

  In addition, according to this embodiment, the electric component control means (effect display device 9) for controlling the electric components (the effect display device 9 and the ball payout device 97) provided in the gaming machine based on the command output by the game control means. Control means or payout control means) based on a command from the game control means, the period during which the detection signal is input from the switch for detecting a winning (see FIG. 72) or the input frequency of the detection signal is predetermined. Since it is determined that an abnormality has occurred when the threshold value is exceeded (see FIG. 76), it is possible to reliably detect fraudulent acts on the switch that detects winnings without increasing the processing load on the game control means.

  Also, since the game control means outputs a command indicating the detection signal input state only when the detection signal input state changes, an illegal act based on grasping the control cycle of the game control means by the command output cycle Can also be prevented. That is, for example, when a command is always output for each control cycle of the game control means, the control cycle of the game control means is set by monitoring the command between the game control means and the electrical component control means. Although it is possible to grasp, it is difficult to grasp the control cycle of the game control means based on the command by configuring the command indicating the detection signal input state only when the detection signal input state changes. .

  Further, according to this embodiment, based on the establishment of a predetermined payout condition, a predetermined calculation (in this example, the number of prize balls) is performed using the number of prize balls according to the established payout condition. (Addition) is performed to update the accumulated value (value of the winning counter) (see step S5118), and a payout condition establishment signal is externally output based on the updated accumulated value reaching a predetermined number. Then, in accordance with the external output of the payout condition establishment signal, a predetermined number is used to perform a calculation in the direction opposite to the predetermined calculation (in this example, 10 subtraction) to update the accumulated value (see step S5121). Therefore, the game situation (for example, the expected number of winning balls) when a predetermined payout condition is satisfied can be accurately grasped outside without increasing the control burden.

  In general, in a gaming machine, at least a predetermined period (for example, 30 seconds after finishing the final round of the jackpot game, 20 seconds after finishing the ending effect) has passed after the jackpot gaming state is finished. In many cases, the payout control based on the specific payout condition (winning in the big winning opening) established during the big hit gaming state is often completed. In such a case, after the big hit gaming state is finished, it is possible to control to the next big hit gaming state even before the end of the payout control based on the fact that the big hit symbol is derived and displayed before the predetermined period elapses. It is. Thus, even in a gaming machine configured such that the next jackpot can be generated before the payout control for the previous jackpot game is completed, in this embodiment, a predetermined number of game balls are paid out. Since a payout condition satisfaction signal (winning signal) indicating that a predetermined payout condition is satisfied is output to the outside, the number of payouts in the big hit gaming state can be accurately grasped.

  For example, in order to be able to recognize the number of prize balls on the external device side such as a hall computer, only a signal (for example, prize ball information shown in this embodiment) indicating that game balls are actually paid out is used. It is also conceivable to configure to output externally. However, as described above, if the gaming machine is configured such that the next jackpot can be generated before the payout control for the previous jackpot game is finished, the current jackpot information is simply output to the outside. There is a case where it is impossible to know whether the winning ball is a winning ball during a game or a winning ball during a previous jackpot game, and the award is given to an external device such as a hall computer. A situation will occur in which the number of balls cannot be accurately recognized. Therefore, in this embodiment, when a predetermined payout condition is satisfied (a stage where a winning occurs), the winning signal is output to the outside, and when the signal is output to the outside, the next big hit has already occurred. Such a situation can be prevented, and a situation in which the number of prize balls cannot be accurately recognized by an external device such as a hall computer is prevented.

  For example, if a gaming machine described in Japanese Patent Application Laid-Open No. 2006-296570 is used, a predetermined payout condition for paying out a predetermined number of game balls is satisfied based on the fact that the predetermined payout condition is satisfied. It is possible to output a signal indicating that this has occurred. However, in the gaming machine described in Japanese Patent Application Laid-Open No. 2006-296570, the first prize ball information is externally output based on the fact that a predetermined number (10) of payout conditions are satisfied in a normal state. When a ball payout error occurs, the second prize ball information is externally output based on the fact that a predetermined number (10 pieces) of payout conditions have been established. Is output externally. Further, in the gaming machine described in Japanese Patent Application Laid-Open No. 2006-296570, the second prize ball information is only output externally when the prize ball dispensing operation is stopped when a prize ball dispensing error occurs, and the previous big hit If the next jackpot occurs before the payout control for the game is completed, the information regarding the number of prize balls may not be output to the outside. In contrast, in this embodiment, assuming that the gaming machine is configured such that the next jackpot can be generated before the payout control for the previous jackpot game is completed, a stage where a predetermined payout condition is established. By outputting a winning signal externally (when a winning occurs), the number of winning balls can be accurately recognized by an external device such as a hall computer.

  In addition, the gaming machine described in Japanese Patent Application Laid-Open No. 2006-296570 does not assume a case where there are a plurality of types of payout conditions with different award balls as the predetermined payout conditions. On the other hand, in this embodiment, the number of prize balls according to the predetermined payout condition established is accumulated, and a winning signal is output to the outside based on the accumulated value reaching the prescribed number. Even when there are multiple types of payout conditions, such as three, ten, fifteen, etc., the predetermined payout conditions for paying out a predetermined number (for example, ten) of game balls are established. It is possible to prevent the determination process for determining whether or not the game has been performed from being complicated, and to prevent an increase in the control burden for externally outputting the payout condition establishment signal (winning signal).

  In this embodiment, more precisely, in the prize ball command output counter addition process executed immediately before the winning signal is output in the information output process in step S31, the accumulated value (value of the prize counter) is decremented by 10. The cumulative value is updated before the winning signal is output. However, the method of updating the cumulative value is not limited to that shown in this embodiment. For example, as long as it is updated with an external output of a winning signal, the cumulative value may be updated after outputting the winning signal.

  In this embodiment, the number of winning balls is added to the value of the winning counter as a predetermined calculation in response to the establishment of a predetermined payout condition (see step S5118), and the reverse direction is accompanied by the external output of the payout condition establishment signal. In this calculation, the value of the winning counter is decremented by 10 (see step S5121), but the method of updating the winning counter is not limited to that shown in this embodiment. For example, the number of winning balls is subtracted from the value of the winning counter as a predetermined calculation in accordance with the establishment of a predetermined payout condition, and 10 is added to the value of the winning counter as a reverse calculation in accordance with the external output of the payout condition establishment signal. You may comprise as follows.

  In this embodiment, the game control microcomputer 560 updates the accumulated value and externally outputs the winning signal. However, the payout control microcomputer 370 receives the winning ball number command. The cumulative value may be updated on the basis and the winning signal may be output to the outside. In this case, for example, the payout control microcomputer 370 updates the cumulative value of the planned number of prize balls based on the number of prize balls indicated by the received prize ball number command, and every time the cumulative value becomes 10 or more, A winning signal may be output externally. In this configuration, the gaming control microcomputer 560 newly establishes a payout condition even before the payout of the number of prize balls specified by the prize ball number command transmitted last time is completed (either The next prize ball number command is transmitted at the timing when the winning prize is received), and the payout control board 37 is backed up by a backup power source, so that even if a power failure occurs, the payout is made for a predetermined time. It is desirable to be able to hold cumulative values and the like that are updated on the control microcomputer 370 side. If configured in such a way, a winning signal can be output to the outside at the timing when any winning opening is generated, and even if the power supply to the gaming machine is cut off, it is disadvantageous to the player Can be prevented. Further, the payout control microcomputer 370 may output the winning signal directly to the outside via the terminal board 160 or may output it to the outside via the game control board (main board) 31 once. .

  Further, when the payout control microcomputer 370 side is configured to output the winning signal externally, for example, the processing for outputting the winning signal and the processing for outputting the winning ball information are configured as a common routine. You may do it. In this case, for example, in the information output processing (see step S759) executed on the payout control microcomputer 370 side by the same configuration as the winning timer set processing (see FIG. 41) shown in this embodiment, the winning signal is displayed. What is necessary is just to make the process for outputting and the process for outputting prize ball information into a common routine.

  In addition, according to this embodiment, the game control microcomputer 560 is informed that the initialization process has been executed when the game machine is powered on, and that a predetermined error (in this example, to the second start winning opening 14). A security signal is output to the outside of the gaming machine based on the establishment of a predetermined signal output condition including that it is determined that the (abnormal winning) has occurred. In this case, the game control microcomputer 560 has a common output terminal (a terminal board of the terminal board) provided in the gaming machine when the initialization process is executed and when it is determined that a predetermined error has occurred. A security signal is output from the common connector CN8). Therefore, by outputting a security signal based on the execution of the initialization process, the possibility that an illegal act aiming for a big hit by performing the initialization process (such as clearing the RAM) illegally is performed. Can be recognized by a hall computer, etc., and an illegal act performed when a gaming machine is powered on can be prevented. In addition, since the security signal is output to the common output terminal when the initialization process is executed and when it is determined that a predetermined error has occurred, the waste of the signal line for external output is reduced. Can do. Therefore, it is possible to reduce the waste of the signal line for external output while preventing an illegal act performed when the power to the gaming machine is turned on.

  Further, according to this embodiment, a predetermined signal output condition is newly established when a security signal is output (in this example, an abnormal winning to the second start winning opening 14 is newly detected). If so, the output time for outputting the security signal is extended. Therefore, when a predetermined signal output condition is newly established, instead of outputting a new security signal, the control signal load is reduced by extending the output time of the security signal being output. can do.

  In addition, according to this embodiment, the game control microcomputer 560 is based on the detection signal input from the second start port switch 14a (proximity switch) and the detection signal input from the winning confirmation switch 14b (photo sensor). Thus, the difference between the number of game balls detected by the second start port switch 14a and the number of game balls detected by the winning confirmation switch 14b exceeds a predetermined threshold (in this example, 10 or more). If it is determined that, an abnormal winning to the second start winning opening 14 has occurred as a predetermined error. In this embodiment, the second start port switch 14a and the winning confirmation switch 14b are constituted by sensors of different detection methods (in this example, a proximity switch and a photo sensor). For this reason, it is possible to more reliably detect fraudulent acts with respect to the switch that detects the game ball, and to take certain measures against fraud.

  Further, according to this embodiment, the game control microcomputer 560 executes the special symbol variation display based on only the detection signal input from the second start port switch 14a and performs the winning ball payout process. Run. Further, the detection signal input from the winning confirmation switch 14b is used only for determining whether or not an abnormal winning to the second start winning opening 14 has occurred. Therefore, since the special symbol variation display and the prize ball payout process are performed based on the detection result of one of the switches, it is possible to prevent an increase in the processing burden accompanying the strengthening of countermeasures against fraud.

  In this embodiment, the game control microcomputer 560 determines that the difference between the number of game balls detected by the second start port switch 14a and the number of game balls detected by the winning confirmation switch 14b is a predetermined value. As a threshold value, a difference (for example, three) between the number of detected game balls in the second start port switch 14a and the number of detected game balls in the winning confirmation switch 14b when the inside of the second start winning port 14 becomes clogged. It may be configured to determine whether or not a value greater than (for example, 10) is exceeded. According to such a configuration, when the inside of the second start winning opening 14 becomes clogged, it is possible to prevent erroneous determination that an abnormal winning to the second starting winning opening 14 has occurred. it can. Accordingly, it is possible to prevent erroneous determinations associated with strengthening countermeasures against fraud.

  In addition, according to this embodiment, the game control microcomputer 560 is connected to the predetermined error (in this example, to the second start winning port 14) when the initialization process is executed when the gaming machine is powered on. A security signal is output over a different period of time when it is determined that (abnormal winning) has occurred. Specifically, in this embodiment, when an initialization process is executed when the gaming machine is turned on, a security signal is output to the outside for 30 seconds, and an abnormal winning is given to the second start winning opening 14. If a security signal is detected, a security signal is externally output for 4 minutes. Therefore, by determining the output time of the security signal, it is possible to determine whether the initialization process has been performed or a predetermined error has occurred in an external device such as a hall computer. It becomes.

  Further, according to this embodiment, when a power failure is restored, a high probability state signal (high probability signal) is generated based on the fact that the high probability state information (probability change flag) is stored in the backup RAM. Output externally through the terminal board 160. In this case, the output of the high-accuracy signal is continued until the predetermined condition is satisfied after the power failure is restored (in this example, until the first big hit occurs), and the output of the high-accuracy signal is prohibited when the predetermined condition is satisfied. To do. Therefore, it is possible to check the presence / absence of a high-accuracy signal output on the hall side, and it is possible to save the trouble of checking whether or not the gaming machines have been initialized one by one. . Therefore, in a gaming machine configured not to notify that it is in a high-probability state, it is possible to reduce the work load when the gaming machine is initialized.

  Further, according to this embodiment, a winning area passing signal (starting port signal) is output to the outside based on the starting winning combination at the first starting winning port 13 and the second starting winning port 14. Further, according to this embodiment, the payout is performed using a signal output routine (a winning timer setting process in steps S1020 and S1023 during the information output process) common to a signal output routine used for externally outputting the winning area passing signal. A condition satisfaction signal (winning signal) is output externally. Therefore, the winning area passing signal and the payout condition establishment signal can be externally output using a common signal output routine, and the program capacity for externally outputting the signal can be reduced.

  Further, according to this embodiment, the game control microcomputer 560 uses a payout number signal (prize ball number command) for specifying a prize ball number for payout control based on a predetermined payout condition being satisfied. A process of updating the accumulated value in the process for outputting to the microcomputer 370 and outputting the payout number signal (the prize ball command output counter addition process (see step S501) during the prize ball process (see step S32)) is executed. To do. Therefore, the process for outputting the payout number signal and the process for updating the accumulated value can be made common, and the control burden can be reduced. For example, as shown in FIGS. 18 and 19, in the prize ball command output counter addition process, the prize ball command output counter used for outputting the prize ball number command is updated and the prize counter used for outputting the prize signal. This update process can be executed using a single pointer, and the processing load on the game control microcomputer 560 can be reduced.

  Further, according to this embodiment, in addition to the winning signal, it is shown that a specific number (10 in this example) of game balls is actually paid out by the payout means (ball payout device 97). A payout signal (prize ball information) is output externally. Therefore, the difference between the expected number of winning balls based on the establishment of the predetermined payout conditions and the number of game balls actually paid out can be grasped externally, and whether or not there is an abnormality in the payout situation can also be externally determined. It can be possible to do.

  In this embodiment, the case where the predetermined number used for determining the output of the winning signal and the specific number used for determining the output of the winning ball information are both 10 has been described. The predetermined number or specific number used for output determination is not limited to that shown in this embodiment. For example, a winning signal is output based on the fact that a predetermined payout condition for paying out 15 game balls as a predetermined number is satisfied, and based on the fact that 15 specific game balls are paid out. And prize ball information may be output. Also, for example, the predetermined number and the specific number do not need to be the same number, and a winning signal is output based on a predetermined payout condition for paying out 15 game balls as the predetermined number, Various modes are conceivable, such as outputting prize ball information based on the payout of 20 game balls as a specific number.

  Further, according to this embodiment, when the payout condition establishment signal (winning signal) is output to the outside, the output of the payout condition establishment signal is started using the signal output period measurement timer (winning information storage timer). It is determined whether or not the specific period (100 ms in this example) has elapsed, and the output of the payout condition establishment signal is continued until it is determined that the specific period has elapsed. The value of the signal output period measurement timer is stored in the power-backed RAM 55, and when the power supply is started, the value of the signal output period measurement timer stored in the backup RAM is cleared (see step S9104). For this reason, it is possible to prevent one output of the payout condition establishment signal from being erroneously recognized externally as two outputs due to the interruption of power supply during the output of the payout condition establishment signal.

  Further, according to this embodiment, when the power supply is started, the high probability state signal (high probability state) is based on the fact that the high probability state state information (probability change flag) is stored in the backup RAM. Signal output permission information (high-accuracy medium output permission flag) permitting external output of the signal (see step S9103 of the hot start process shown in FIG. 10) is set, and the signal output permission information is set. First, a high probability state signal is output externally. Further, in the process for setting the signal output permission information by the signal output permission information setting means (hot start process shown in FIG. 10), the value of the signal output period measurement timer stored in the backup RAM is cleared (shown in FIG. 10). (See step S9104 of the hot start process). Therefore, the process for setting the signal output permission information and the process for clearing the value of the signal output period measurement timer can be shared, and the control burden can be reduced.

  In other words, in this embodiment, the RAM 55 in which the value of the winning information storage timer is stored is backed up, so that if a power failure occurs while outputting the winning signal, the winning signal is output due to the power failure. Is temporarily interrupted, the output of the winning signal is resumed based on the value of the winning information storage timer that is backed up after the power is restored. Therefore, even though the output of the winning signal is only interrupted and resumed halfway, when viewed from an external device such as a hall computer, the kite is mistakenly recognized as having been output twice. Will happen. Therefore, in this embodiment, when a power failure occurs during the output of the winning signal, the value of the winning information storage timer is forcibly cleared when power is restored so that the output of the winning signal is not resumed. This prevents the output of one signal from being mistakenly recognized externally as the output of two times.

  Further, according to this embodiment, an external output signal including a payout condition establishment signal (winning signal) (symbol confirmation number 1 signal, start port signal, jackpot 1 signal, jackpot 2 signal, jackpot 3 signal, time reduction signal) , A game in which an external output board (terminal board 160) for outputting a security signal, high-accuracy signal, prize ball information) to an external device (for example, hall computer) and a game control microcomputer 560 are mounted. And a control board (main board) 31. The external output board receives an external output signal from the game control board 31 and outputs the input external output signal to the external device. Therefore, it is possible to facilitate the routing of the external output signal wiring to the external output board.

  In this embodiment, the game control microcomputer 560 is configured to transmit a prize ball number command on condition that a confirmation command (connection OK command) is received from the payout control microcomputer 370. However, the RAM included in the payout control microcomputer 370 may be backed up so that the award ball number command can be transmitted without waiting for a confirmation command from the payout control microcomputer 370. . Also in the gaming machine configured as described above, according to the same configuration as this embodiment, it is confirmed that a predetermined payout condition for paying out a predetermined number (10 in this example) of game balls is satisfied. If the payout condition establishment signal (winning signal) is output to the outside, similarly, the game situation (for example, the expected number of winning balls) when the predetermined payout condition is established without increasing the control burden. It can be accurately understood externally.

  Further, according to this embodiment, the game control microcomputer 560 and the payout control microcomputer 370 transmit and receive control commands by serial communication. Further, the game control microcomputer 560 sends a connection confirmation command for confirming the communication connection state with the payout control microcomputer 370 every time a predetermined period (1 second in this example) elapses. To 370. The payout control microcomputer 370 transmits a connection OK command to the game control microcomputer 560 based on the reception of the connection confirmation command. In this case, the payout control microcomputer 370 is connected in such a manner that the game control microcomputer 560 can recognize the control state (in this example, a prize ball error, a full tank error, a ball shortage error, and a payout number error error). The command is transmitted to the game control microcomputer 560. With such a configuration, by using a serial communication method, it is possible to facilitate wiring between the game control microcomputer 560 and the payout control microcomputer 370. In addition, the control state signal (response signal to which the control state is added) is transmitted by placing the control state on the connection OK command that the payout control microcomputer 370 periodically outputs based on the reception of the connection confirmation command. Can do. Therefore, it is possible to prevent the control state signal from being missed without considering the output timing of the control state signal, and the communication between the game control microcomputer 560 and the payout control microcomputer 370 is reliably performed. be able to. In this embodiment, the cycle (interval) for transmitting the connection confirmation command is 1 second, but it may be 0.5 seconds or the like.

  Further, according to this embodiment, the game control microcomputer 560 resets a predetermined period (1 second in this example) to the prize ball process timer when the execution of the payout control is finished, and the prize ball process. Measurement control by the timer is started (see step S52505). If the number of prize balls is not stored (specifically, if no prize ball command output counter has a count value of 1 or more in step S52301), the game control microcomputer 560 resets the game. A new connection confirmation command is transmitted to the payout control microcomputer 370 based on the time-out of the prize ball process timer. For this reason, an interval period can be provided between the end of execution of payout control and the transmission of a new connection confirmation command, and processing at the end of execution of payout control is concentrated, and a new connection check command is overwritten. Can be prevented.

  Further, according to this embodiment, the game control microcomputer 560 transmits a winning ball number command to the payout control microcomputer 370 based on the detection of a winning regardless of the transmission timing of the connection confirmation command. To do. Further, the payout control microcomputer 370 transmits a prize ball number reception command based on the reception of the prize ball number command, and receives a prize ball preparation command during execution of the payout control. The signal is transmitted to the game control microcomputer 560 every signal output period (1 second in this example). In this case, the payout control microcomputer 370 receives the prize ball in such a manner that the game control microcomputer 560 can recognize the control state (in this example, a prize ball error, a full tank error, an out of ball error, and a payout number error error). The preparing command is transmitted to the game control microcomputer 560. Further, the game control microcomputer 560 stops the transmission of the connection confirmation command based on the reception of the prize ball number reception command. Therefore, it is possible to reduce the control burden of the game control microcomputer 560 by not performing connection control command transmission control unnecessarily during execution of payout control. Even when the payout control is being executed, the control state signal can be output by adding the control state to the award ball preparation command, so that the game control microcomputer 560 can recognize the control state. it can.

  Further, according to this embodiment, the game control microcomputer 560 receives the award ball end command and then stores the number of award balls (specifically, the prize ball command output counter in step S52301). If the count value is 1 or more), a new prize ball number command is immediately transmitted to the payout control microcomputer 370 regardless of the transmission of the connection confirmation command. Therefore, it is possible to speed up the execution process of the payout control.

  In addition, according to this embodiment, the game control microcomputer 60 determines whether a predetermined error (in this example, a prize ball error, a full tank error, a full ball error, etc.) based on the control state indicated by the received connection OK command. , And a payout quantity abnormality error). Then, the game control microcomputer 60 transmits a prize ball number command to the payout control microcomputer 370 on the condition that it is determined that a predetermined error has not occurred. Therefore, it is possible to prevent the inconvenience of sending a prize ball number command when the payout control cannot be normally performed due to an error state. In particular, in this embodiment, since the RAM provided in the payout control microcomputer 370 is not backed up by the backup power supply, if a prize ball number command is transmitted when there is an abnormality in the payout control, the power is reset. For example, the memorized number of prize balls may be lost, which may cause a great disadvantage to the player. Therefore, in this embodiment, when there is an abnormality in the payout control, the prize ball number command is transmitted while the memory of the prize ball number is retained on the game control microcomputer 560 side backed up by the backup power source. It is possible to prevent such a disadvantage from occurring by controlling to hold.

  Further, according to this embodiment, the game control microcomputer 560 increases the time interval for transmitting the connection confirmation command when the connection OK command cannot be received after transmitting the connection confirmation command. Whenever a specific period (10 seconds in this example) elapses, the control is switched to the connection confirmation command transmission. Therefore, in a state where the communication state between the game control microcomputer 560 and the payout control microcomputer 370 is unstable, the connection confirmation command transmission process is performed by extending the interval period until the connection confirmation command is transmitted. Can be performed less frequently, and a wasteful processing load can be reduced.

  Further, according to this embodiment, the payout control microcomputer 370 causes the game to occur when a predetermined error (in this example, a prize ball error, a full tank error, a ball shortage error, and a payout number error) occurs. Information that allows the control microcomputer 560 to recognize a predetermined error is set by changing a specific bit of the connection OK command, and the connection OK command in which the setting has been made is transmitted to the game control microcomputer 560. The game control microcomputer 560 transmits a frame state display command in which information capable of recognizing a predetermined error set in the received connection OK command is set as it is to the effect control microcomputer 100. Then, based on the reception of the frame state display command, the production control microcomputer 100 controls the production device (the production display device 9 in this example) to notify that a predetermined error has occurred. Do. Therefore, it is possible to notify that a predetermined error has occurred using the effect device, and to reduce the processing load on the game control microcomputer 560.

  In addition, according to this embodiment, the payout control microcomputer 370 has a payout excess exceeding the number of unpaid game balls to be paid out and the number of unpaid games to be paid out. The number of shortage payouts that did not reach the ball is cumulatively counted using a payout number abnormality counter. When the value of the payout number abnormality counter becomes equal to or greater than a predetermined payout number error error determination value (2000 in this example), execution of the payout control is stopped and the payout stop state is controlled. Therefore, instead of judging each payout control, the payout control is executed by comprehensively judging the payout control executed under an abnormal condition based on the value of the payout number abnormality counter counted up cumulatively. Can be stopped. Therefore, it is possible to more accurately prevent the act of illegally paying out the game ball.

  Further, according to this embodiment, the payout control microcomputer 370 counts up the value of the payout number abnormality counter when a payout shortage number equal to or greater than a predetermined reference number (2 in this example) occurs. Therefore, it is possible to prevent inconvenience that the execution of the payout control is stopped more than necessary. In other words, since there are not a few small numbers (1 in this example) of insufficient payouts in the operating state of the gaming machine, the number of insufficient payouts exceeding the predetermined reference number (2 in this example) has occurred. By counting up on the condition, it is possible to prevent the execution of the payout control from being stopped more than necessary.

  Further, according to this embodiment, the payout control microcomputer 370 executes re-payout control for driving and controlling the ball payout device 97 to pay out only one game ball when a payout shortage occurs. . If the payout of the game ball is not detected even after the re-payout control is executed, the value of the payout number abnormality counter is counted up. Therefore, even if the number of payout shortages is small, it is possible to appropriately stop the execution of payout control by reflecting it in the count value of the payout number abnormality counter, and to take illegal measures to prevent the act of illegally paying out game balls. Can be strengthened.

  Further, according to this embodiment, when the payout number abnormality error is detected and controlled to the payout stop state, the payout stop state is canceled on condition that the power of the gaming machine is reset. Therefore, in order to release the payout stop state, the game store clerk must confirm the abnormal state and then perform the release operation. Therefore, the payout stop state is canceled illegally and the game is continued in the abnormal state. This can be prevented.

  Further, according to this embodiment, the RAM 55 provided in the gaming control microcomputer 560 can retain the stored contents for a predetermined period by the backup power supply even when the power supply to the gaming machine is stopped. In addition, when the game control microcomputer 560 is controlled to be in the payout stop state, the game control microcomputer 560 prohibits the transmission of the winning ball number command even if a winning occurs. For this reason, the number of prize balls stored in the RAM 55 (specifically, the value of the prize ball command output counter) is cleared even though the payout is stopped due to an abnormality caused by the gaming machine side that is not caused by fraud. It is possible to prevent such a situation from occurring, and it is possible to prevent the player from being disadvantaged.

  Further, according to this embodiment, the game control microcomputer 560 adds the prize ball number to the prize ball number counter at the timing of sending the prize ball number command, and receives the prize ball information based on the received prize ball information. Subtract 10 from the value of the ball counter. Then, based on the fact that the value of the prize ball number counter is equal to or greater than a predetermined prize ball shortage determination value (501 in this example), it is determined that there is a prize ball shortage error. Based on the fact that it is less than the determination value (0 in this example), it is determined that there is an excessive prize ball error. Therefore, the abnormal state can be detected by both the game control microcomputer 560 and the payout control microcomputer 370. Therefore, a fraud countermeasure for preventing an act of illegally paying out the game ball can be strengthened.

  Further, according to this embodiment, the game control microcomputer 560 transmits a connection signal indicating a connection state of communication with the payout control microcomputer 370 to the payout control microcomputer 370 via the output port 57. Since the payout control microcomputer 370 can confirm the communication connection state at any timing, the payout of the prize ball is performed when the communication connection state is abnormal. This can be surely prevented.

  In the above embodiment, the game control microcomputer 560 normally transmits a connection confirmation command 1 second after the connection OK command is received, and when a communication error occurs (for example, connection When the OK command cannot be received), the connection confirmation command is transmitted 10 seconds after the connection confirmation command is transmitted, and the period of 1 second or 10 seconds is measured by a timer (a counter configured by software). However, the connection confirmation command may be transmitted by an internal interrupt that occurs when the counter updated as hardware by the internal clock reaches a predetermined value (1 second or 10 seconds). In that case, the counter may be cleared by reception of the connection OK command, or the counter may be cleared if an internal interrupt is generated with a predetermined value.

Embodiment 2. FIG.
Next, a second embodiment will be described. In the first embodiment, the effect control means performs the abnormality detection process for the winning opening switch. In the second embodiment, the payout control means performs the abnormality detection process for the winning opening switch.

  FIG. 83 is an explanatory diagram showing an example of the contents of a control command transmitted / received between the game control unit and the payout control unit in the second embodiment. As shown in FIG. 83, in the second embodiment, the subsequent 8-bit data is the input port state designation data of the input port 0 with respect to the control command (see FIG. 13) in the first embodiment. An input port state 1 specifying command (“30 (H)”) indicating that there is an input port, and an input port state 2 specifying command (“31” indicating that the subsequent 8-bit data is input port state specifying data of the input port 2 (H) ") is added.

  In the second embodiment, the game control microcomputer 560 uses the input port state 1 designation command and the state of the input port 0 in place of the control for transmitting the effect control command in the process of step S2111 shown in FIG. Control is performed to transmit the indicated data (data specifying the input port state of the input port 0) to the payout control microcomputer 370 via the serial communication circuit 505. That is, when the input port state 1 designation command is set in the data register of the serial communication circuit 505 and bit 6 (TC) of the status register is set to “1” (meaning that the transmission of the “input port state 1 designation command” is completed). ), Input port state designation data of the input port 0 is set in the data register of the serial communication circuit 505.

  In the second embodiment, the game control microcomputer 560 replaces the control for transmitting the effect control command in the process of step S2127 shown in FIG. Control is performed to transmit data indicating the status (data specifying the input port status of the input port 2) to the payout control microcomputer 370 via the serial communication circuit 505. That is, when an input port state 2 designation command is set in the data register of the serial communication circuit 505 and bit 6 (TC) of the status register is set to “1” (which means that transmission of the “input port state 2 designation command” is completed). ), Input port state designation data of the input port 2 is set in the data register of the serial communication circuit 505.

  The input port status designation data for input ports 0 and 2 is 8-bit data following the input port status 1 designation command (“30 (H)”) and the input port status 2 designation command (“31 (H)”). May be set in the lower 4 bits of the input port state 1 designation command or the input port state 2 designation command. In this case, the game control microcomputer 560 sets the values of bits 3, 2, 0 of the input port 0 (see FIG. 7) to bits 3, 2, 0 of the input port state 1 designation command, The value of bits 1 and 0 of input port 2 (see FIG. 7) is set to bits 1 and 0 of the input port state 2 designation command.

  Also, the input port status 1 designation command (“30 (H)”) and the input port status 2 designation command (“31 (H)”) are not used, and the status of the input ports 0 and 2 is utilized using an existing command. May be transmitted. For example, it is set in the lower 4 bits of the connection confirmation command (see FIG. 83).

  FIG. 84 is a flowchart showing a timer interrupt process executed by the payout control CPU of the payout control microcomputer 370 in the second embodiment. In contrast to the timer interrupt process in the first embodiment shown in FIG. 47, the abnormality determination process in step S762 is added in the second embodiment.

  In the second embodiment, the production control microcomputer 100 does not execute the process of step S708 shown in FIG. 67, but may execute the process of step S708.

  In the second embodiment, the payout control microcomputer 370, for example, in the main control command reception process shown in FIG. 48, in addition to the process shown in the first embodiment, an input port in the serial communication circuit 380 After confirming that the state 1 designation command has been received, processing for storing the data received by the serial communication circuit 380 in the input port state 1 designation command storage area in the RAM is also executed. Further, after confirming that the input port state 2 designation command has been received in the serial communication circuit 380, the data received in the serial communication circuit 380 is subsequently stored in the input port state 2 designation command storage area in the RAM. Also execute.

  85 and 86 are flowcharts showing an example of the abnormality determination process in step S762 when the abnormality determination as shown in FIG. 72 is executed. As shown in FIG. 73, the payout control microcomputer 370 has a timer corresponding to the second starting port switch 14a, a timer corresponding to the first starting port switch 13a, and a winning port switch as timers used for detection of a prize abnormality. A timer corresponding to 30a, a timer corresponding to the winning opening switch 29a, and a timer corresponding to the count switch 23 are used. Each timer is formed in the RAM.

  The payout control CPU 371 includes a timer corresponding to the second start port switch 14a, a timer corresponding to the first start port switch 13a, a timer corresponding to the winning port switch 30a, a timer corresponding to the winning port switch 29a, and the count switch 23. It is checked whether or not the value of any one of the corresponding timers is a value other than 0 (corresponding to being in operation) (step S911). If there is an operating timer, the timer value is incremented by 1 (step S912). It should be noted that a timer operating flag is used as in another example of the winning abnormality detection method (see FIGS. 87, 88, 89, and 90), and whether or not the timer is operating is determined by the timer operating flag. You may make it confirm.

  Further, the payout control CPU 371 checks whether or not the value of any one of the timers exceeds 1000 (corresponding to 1 second) (step S913). If there is a timer exceeding 1000, a signal indicating a prize abnormality is output to the terminal board 160 (step S914). The signal is output to a hall computer or the like outside the gaming machine.

  In the process of step S914, a signal that can distinguish which switch has a prize abnormality may be output.

  Also, the payout control CPU 371 checks whether or not an input port state 1 designation command reception flag indicating that an input port state 1 designation command has been received is set (step S916A). If the input port state 1 designation command reception flag is not set, the process ends. If the input port state 1 designation command reception flag is set, the input port state 1 designation command reception flag is reset (step S917A), and the input port state 1 stored in the input port state 1 designation command storage area is reset. In the data indicating the state of the input port 0 (input port 0 in the game control means) that is the data of the designated command, it is confirmed whether any one or more of the bits 0, 2, and 3 has changed to “1” ( Step S918A).

  In step S918A, the payout control CPU 371 compares the previous value stored in the RAM in the process of step S921A with the data of the input port state 1 designation command.

  If there is a bit that is “1”, “1” is set to the timer corresponding to the bit (the timer corresponding to the winning port switch 30a, the timer corresponding to the winning port switch 29a, or the timer corresponding to the count switch 23). Set (step S920A). Then, control goes to a step S921A.

  If there is no bit that is “1” in the data indicating the state of the input port 0, the timer value corresponding to the bit that is “0” is initialized to 0 (step S919A). Then, control goes to a step S921A. Note that the game control microcomputer 560 transmits an input port state 1 designation command when any bit of the input port 0 changes, so that there is no bit changed to “1”. ”Means that there is a bit changed.

  Then, the payout control CPU 371 stores the data in the input port state 1 designation command storage area in the RAM as the previous value (step S921A).

  The game control microcomputer 560 changes the value of any bit of the input port 0 (any one of the bits 0, 2, 3 of the input port 0 shown in FIG. 7) (the state of the switch detection signal changes). Since the input port state 1 designation command in which the state of each bit of the input port 0 is set is output, the timer corresponding to the switch changed to the ON state by the processing of steps S918A and S919A is operating. become. Since the timer value advances unless the value of the bit corresponding to the timer that is in operation becomes “0” (by the processing in steps S911 and S912), the timer value has exceeded 1000. This means that the state of the detection signal of the switch was an on state that continued for more than 1 second.

  The payout control CPU 371 checks whether or not an input port state 2 designation command reception flag indicating that an input port state 2 designation command has been received is set (step S916B). If the input port state 2 designation command reception flag is not set, the process ends. If the input port state 2 designation command reception flag is set, the input port state 2 designation command reception flag is reset (step S917B), and the input port state 2 stored in the input port state 2 designation command storage area. In the data indicating the state of the input port 2 (input port 2 in the game control means) which is the data of the designated command, it is confirmed whether or not one or more of the bits 0 and 1 has changed to “1” (step S918B). ).

  In step S918B, the payout control CPU 371 compares the previous value stored in the RAM in the process of step S921B with the data of the input port state 2 designation command.

  If there is a bit that is “1”, “1” is set to the timer corresponding to that bit (the timer corresponding to the first start port switch 13a, the timer corresponding to the second start port switch 14a) (step S920B). ). Then, control goes to a step S921B.

  If there is no bit that is “1” in the data indicating the state of the input port 2, the timer value corresponding to the bit that is “0” is initialized to 0 (step S919B). Then, control goes to a step S921B. Note that the game control microcomputer 560 transmits an input port state 2 designation command when any bit of the input port 2 changes, so that there is no bit changed to “1”. ”Means that there is a bit changed.

  Then, the payout control CPU 371 stores the data in the input port state 2 designation command storage area in the RAM as the previous value (step S921B).

  When the value of any bit of the input port 2 (any one of the bits 0 and 1 of the input port 2 shown in FIG. 7) changes (the state of the detection signal of the switch changes) Since the input port state 2 designation command in which the state of each bit of the input port 2 is set is output, the timer corresponding to the switch changed to the ON state is in operation by the processing of steps S918B and S919B. . Since the timer value advances unless the value of the bit corresponding to the timer that is in operation becomes “0” (by the processing in steps S911 and S912), the timer value has exceeded 1000. This means that the state of the detection signal of the switch was an on state that continued for more than 1 second.

  Also, the payout control CPU 371 can perform the abnormality determination as shown in FIG. 72 by executing the processes of steps S913 and S914.

  85 and 86 (excluding step S914) is the same as the processing in steps S1711 to S1727 (excluding steps S1714 and S1715) shown in FIGS. 74 and 75. It is. However, the production control means takes a timer interruption every 4 ms, whereas the payout control means takes a timer interruption every 1 ms. Therefore, the value for determination in step S913 is the same as that for determination in step S1713. Different from the value.

  87 and 88 are flowcharts illustrating another example of the abnormality determination process in step S762. In this example, the payout control microcomputer 370 executes abnormality determination as shown in FIG.

  As shown in FIG. 77, the payout control microcomputer 370 has a timer corresponding to the second start port switch 14a, a timer corresponding to the first start port switch 13a, and a win as timers used for detection of a prize abnormality. A timer corresponding to the mouth switch 30a, a timer corresponding to the winning port switch 29a, and a timer corresponding to the count switch 23 are used. Further, as flags to be used for detection of winning abnormality, a timer operating flag corresponding to the second starting port switch 14a, a timer operating flag corresponding to the first starting port switch 13a, and a timer operating corresponding to the winning port switch 30a are operating. A flag, a timer operating flag corresponding to the winning port switch 29a, and a timer operating flag corresponding to the count switch 23 are used. Further, as counters used for detection of winning abnormality, a counter corresponding to the second starting port switch 14a, a counter corresponding to the first starting port switch 13a, a counter corresponding to the winning port switch 30a, and a winning port switch 29a. A counter corresponding to the counter and the count switch 23 is used. Each counter is formed in the RAM.

  In the abnormality determination process, the payout control CPU 371 includes a timer corresponding to the second starting port switch 14a, a timer corresponding to the first starting port switch 13a, a timer corresponding to the winning port switch 30a, and a timer corresponding to the winning port switch 29a. Then, it is confirmed whether or not the value of any one of the timers corresponding to the count switch 23 is operating (the timer operating flag is on) (step S911). If there is an operating timer, the timer value is incremented by 1 (step S912).

  Also, the payout control CPU 371 checks whether or not an input port state 1 designation command reception flag indicating that an input port state 1 designation command has been received is set (step S916A). If the input port state 1 designation command reception flag is not set, the process proceeds to step S935A. If the input port state 1 designation command reception flag is set, the input port state 1 designation command reception flag is reset (step S917A), and the input port state 1 stored in the input port state 1 designation command storage area is reset. In the data indicating the state of the input port 0 (input port 0 in the game control means) that is the data of the designated command, it is confirmed whether any one or more of the bits 0, 2, and 3 has changed to “1” ( Step S931A).

  In step S931A, the payout control CPU 371 compares the previous value stored in the RAM in the process of step S939A with the data of the input port state 1 designation command.

  If there is a bit changed to “1”, the value of the counter corresponding to that bit (the counter corresponding to the winning port switch 30a, the counter corresponding to the winning port switch 29a, or the counter corresponding to the count switch 23) is incremented by one. (Step S932A). If the timer corresponding to the bit changed to “1” is not operating (step S933A), the timer operating flag corresponding to the bit is set (turned on) (step S934A).

  In addition, the payout control CPU 371 sets the value of any timer (the timer corresponding to the winning port switch 30a, the timer corresponding to the winning port switch 29a, or the timer corresponding to the count switch 23) to 500 (in 0.5 seconds). It is confirmed whether or not (equivalent)) has been exceeded (step S935A). If there is no timer exceeding 500, the process proceeds to step S939A. If there is a timer exceeding 500, the value of the counter corresponding to the timer is confirmed (step S936A). If the value of the counter exceeds 10, a signal indicating a winning abnormality is output to the terminal board 160 (step S940A). The signal is output to a hall computer or the like outside the gaming machine.

  If there is a counter having a value of 10 or less, the payout control CPU 371 clears the counter value to 0 (step S937A). In addition, the corresponding timer operating flag is reset (turned off), and the corresponding timer value is initialized to 0 (step S938A).

  Then, the data of the input port state 1 designation command storage area is stored in the RAM as the previous value (step S939A).

  The game control microcomputer 560 changes the value of any bit of the input port 0 (any one of the bits 0, 2, 3 of the input port 0 shown in FIG. 7) (the state of the switch detection signal changes). The input port state 1 designation command in which the state of each bit of the input port 0 is set is output, but the fact that there has been a bit changed to “1” in the process of step S931A This means that the state of the relevant bit of 0 has changed from “0” to “1” (corresponding to the change of the switch detection signal from the OFF state to the ON state). Therefore, the process of step S932A is a process of counting the number of times the switch detection signal has changed from the off state to the on state.

  Checking the counter value when 0.5 seconds have elapsed in the processes of steps S935A and S936A corresponds to confirming the number of times that the switch detection signal has been turned on for 0.5 seconds. . That is, the abnormality determination as shown in FIG. 76 is executed.

  The payout control CPU 371 checks whether or not an input port state 2 designation command reception flag indicating that an input port state 2 designation command has been received is set (step S916B). If the input port state 2 designation command reception flag is not set, the process proceeds to step S935B. If the input port state 2 designation command reception flag is set, the input port state 2 designation command reception flag is reset (step S917B), and the input port state 2 stored in the input port state 2 designation command storage area. In the data indicating the state of the input port 2 (input port 2 in the game control means) that is the data of the designated command, it is confirmed whether or not one or more of the bits 0 and 1 has changed to “1” (step S931B). ).

  In step S931B, the payout control CPU 371 compares the previous value stored in the RAM in the process of step S939B with the data of the input port state 2 designation command.

  If there is a bit changed to “1”, the value of the counter corresponding to that bit (the counter corresponding to the second starting port switch 14a, the counter corresponding to the first starting port switch 13a) is incremented by 1 (step S932B). If the timer corresponding to the bit changed to “1” is not operating (step S933B), the timer operating flag corresponding to the bit is set (turned on) (step S934B).

  In addition, the payout control CPU 371 determines whether the value of any timer (a counter corresponding to the second start port switch 14a or a counter corresponding to the first start port switch 13a) exceeds 500 (corresponding to 0.5 seconds). Whether or not is confirmed (step S935B). If there is no timer exceeding 500, the process proceeds to step S939B. If there is a timer exceeding 500, the value of the counter corresponding to the timer is confirmed (step S936B). If the value of the counter exceeds 10, a signal indicating a prize abnormality is output to the terminal board 160 (step S940B). The signal is output to a hall computer or the like outside the gaming machine.

  If there is a counter with a value of 10 or less, the payout control CPU 371 clears the counter value to 0 (step S937B). In addition, the corresponding timer operating flag is reset (turned off), and the corresponding timer value is initialized to 0 (step S938B).

  Then, the data in the input port state 2 designated command storage area is stored in the RAM as the previous value (step S939B).

  When the value of any bit of the input port 2 (any one of the bits 0 and 1 of the input port 2 shown in FIG. 7) changes (the state of the detection signal of the switch changes) The input port state 2 designation command in which the state of each bit of the input port 2 is set is output. However, the fact that there is a bit changed to “1” in the process of step S931B indicates that the input port 2 This means that the state of the bit has changed from “0” to “1” (corresponding to the change of the switch detection signal from the OFF state to the ON state). Therefore, the process of step S932B is a process of counting the number of times the switch detection signal has changed from the off state to the on state.

  Checking the counter value when 0.5 seconds have elapsed in the processes of steps S935B and S936B corresponds to confirming the number of times the switch detection signal has changed to the ON state for 0.5 seconds. . That is, the abnormality determination as shown in FIG. 76 is executed.

  When an illegal act as illustrated in FIG. 28B is performed, the state of the detection signal of the switch may be as illustrated in the lower part of FIG. 28C. When the signal state as shown in the lower part of FIG. 28C is generated by the processing shown in FIG. 88, an abnormality is detected (see FIG. 76). That is, the process shown in FIGS. 87 and 88 is a process capable of detecting an illegal act illustrated in FIG.

  Note that the processing in steps S911 to S939B (excluding step S940A) shown in FIGS. 87 and 88 is the same as the processing in steps S1711 to S1752 (excluding steps S1740 and S1741) shown in FIGS. 78 and 79. . However, the production control means takes a timer interruption every 4 ms, whereas the payout control means takes a timer interruption every 1 ms. Therefore, the determination values in steps S935A and S935B are the values in steps S1735 and S1748. It is different from the value for judgment.

  89 and 90 are flowcharts showing still another example of the abnormality determination process in step S762. In this example, the payout control microcomputer 370 executes an abnormality determination (determination that an abnormality has occurred when the detection signal OFF period is equal to or shorter than a predetermined period (for example, 32 ms)) as shown in FIG. .

  Similarly to the example shown in FIGS. 87 and 88, the payout control microcomputer 370 corresponds to the timer corresponding to the second start port switch 14a and the first start port switch 13a with respect to detection of the winning abnormality. A timer, a timer corresponding to the winning port switch 30a, a timer corresponding to the winning port switch 29a, and a timer corresponding to the count switch 23 are used. Further, as flags to be used for detection of winning abnormality, a timer operating flag corresponding to the second starting port switch 14a, a timer operating flag corresponding to the first starting port switch 13a, and a timer operating corresponding to the winning port switch 30a are operating. A flag, a timer operating flag corresponding to the winning port switch 29a, and a timer operating flag corresponding to the count switch 23 are used. However, the counter is not used.

  In the abnormality determination process, the payout control CPU 371 includes a timer corresponding to the second starting port switch 14a, a timer corresponding to the first starting port switch 13a, a timer corresponding to the winning port switch 30a, and a timer corresponding to the winning port switch 29a. Then, it is confirmed whether or not the value of any one of the timers corresponding to the count switch 23 is operating (the timer operating flag is on) (step S911). If there is an operating timer, the timer value is incremented by 1 (step S912).

  Also, the payout control CPU 371 checks whether or not an input port state 1 designation command reception flag indicating that an input port state 1 designation command has been received is set (step S916A). If the input port state 1 designation command reception flag is not set, the process ends. If the input port state 1 designation command reception flag is set, the input port state 1 designation command reception flag is reset (step S917A), and the input port state 1 stored in the input port state 1 designation command storage area is reset. In the data indicating the state of the input port 0 (input port 0 in the game control means) that is the data of the designated command, it is confirmed whether any one or more of the bits 0, 2, and 3 has changed to “0” ( Step S951A).

  In the process of step S951A, the payout control CPU 371 compares the previous value stored in the RAM in the process of step S956A with the data of the input port state 1 designation command.

  If there is a bit changed to “0”, the timer operating flag corresponding to the bit is set (turned on) (step S952A).

  In addition, the payout control CPU 371 selects one of bits 0, 2, and 3 in the data indicating the state of the input port 0 that is the data of the input port state 1 designation command stored in the input port state 1 designation command storage area. It is checked whether one or more has changed to “1” (step S953A). If there is no bit changed to “1”, the process proceeds to step S956A.

  In the process of step S953A, the payout control CPU 371 compares the previous value stored in the RAM in the process of step S956A with the data of the input port state 1 designation command.

  If there is a bit changed to “1”, the timer value corresponding to the bit is confirmed (step S954A). In step S954A, the payout control CPU 371 checks whether the timer value is 32 or less (corresponding to 32 ms or less). If the timer value exceeds 32, the timer operating flag corresponding to the bit is reset (turned off), and the corresponding timer value is initialized to 0 (step S955A). Further, the data of the input port state 1 designation command storage area is stored in the RAM as the previous value (step S956A).

  If the value of the timer is 32 or less, the payout control CPU 371 outputs a signal indicating a prize abnormality to the terminal board 160 (step S960A). The signal is output to a hall computer or the like outside the gaming machine.

  The game control microcomputer 560 changes the value of any bit of the input port 0 (any one of the bits 0, 2, 3 of the input port 0 shown in FIG. 7) (the state of the switch detection signal changes). The input port state 1 designation command in which the state of each bit of the input port 0 is set is output, but the fact that there is a bit changed to “0” in the process of step S951A This means that the state of the relevant bit of 0 has changed from “1” to “0” (corresponding to the change of the switch detection signal from the ON state to the OFF state). Therefore, the process of step S952A corresponds to a process of starting a timer when the switch detection signal changes from the on state to the off state.

  In addition, when there is a bit that has changed to “1” in the process of step S953A, the state of the bit of input port 0 has changed from “0” to “1” (the switch detection signal has changed from OFF to ON). It is equivalent to changing to a state). Therefore, the process of step S953A is a process of determining whether or not the switch detection signal has changed from the off state to the on state. Checking the value of the timer in the process of step S954A corresponds to determining whether or not the period in which the detection signal is in the off state is 32 ms or less. That is, the abnormality determination as shown in FIG. 80 is executed.

  The payout control CPU 371 checks whether or not an input port state 2 designation command reception flag indicating that an input port state 2 designation command has been received is set (step S916B). If the input port state 2 designation command reception flag is not set, the process ends. If the input port state 2 designation command reception flag is set, the input port state 2 designation command reception flag is reset (step S917B), and the input port state 2 stored in the input port state 2 designation command storage area. In the data indicating the state of the input port 2 (input port 2 in the game control means) that is the data of the designated command, it is confirmed whether or not one or more of the bits 0 and 1 has changed to “0” (step S951B). ).

  In the process of step S951B, the payout control CPU 371 compares the previous value stored in the RAM in the process of step S956B with the data of the input port state 2 designation command.

  If there is a bit changed to “0”, the timer operating flag corresponding to the bit is set (turned on) (step S952B).

  Further, the payout control CPU 371 selects one of bits 0 and 1 in the data indicating the state of the input port 2 which is the data of the input port state 2 designation command stored in the input port state 2 designation command storage area. It is confirmed whether or not the above has changed to “1” (step S953B). If there is no bit changed to “1”, the process proceeds to step S956B.

  In the process of step S953B, the payout control CPU 371 compares the previous value stored in the RAM in the process of step S956B with the data of the input port state 2 designation command.

  If there is a bit changed to “1”, the timer value corresponding to the bit is confirmed (step S954B). In step S954B, the payout control CPU 371 checks whether the timer value is 32 or less (corresponding to 32 ms or less). If the timer value exceeds 32, the timer operating flag corresponding to the bit is reset (turned off), and the corresponding timer value is initialized to 0 (step S955B). Further, the data of the input port state 2 designated command storage area is stored in the RAM as the previous value (step S956B).

  When the value of the timer is 32 or less, the payout control CPU 371 outputs a signal indicating a prize abnormality to the terminal board 160 (step S960B). The signal is output to a hall computer or the like outside the gaming machine.

  When the value of any bit of the input port 2 (any one of the bits 0 and 1 of the input port 2 shown in FIG. 7) changes (the state of the detection signal of the switch changes) The input port state 2 designation command in which the state of each bit of the input port 2 is set is output. In step S951B, there is a bit that has changed to “0”. This means that the state of the bit has changed from “1” to “0” (corresponding to the change of the switch detection signal from the on state to the off state). Therefore, the process of step S952B corresponds to a process of starting a timer when the switch detection signal changes from the on state to the off state.

  In addition, when there is a bit that has changed to “1” in the process of step S953B, the state of the bit of the input port 2 has changed from “0” to “1” (the switch detection signal has changed from OFF to ON). It is equivalent to changing to a state). Therefore, the process of step S953B is a process of determining whether or not the switch detection signal has changed from the off state to the on state. Checking the timer value in the process of step S954B corresponds to determining whether or not the period in which the detection signal is in the OFF state is 32 ms or less. That is, the abnormality determination as shown in FIG. 80 is executed.

  When an illegal act illustrated in FIG. 28B is performed, the state of the detection signal of the switch may be as illustrated in the lower part of FIG. 28C. When the signal state as shown in the lower part of FIG. 28C is generated by the processing shown in FIG. 90, if the period during which the detection signal is in the off state is equal to or shorter than the predetermined period (32 ms in this example) Are detected as abnormal (see FIG. 80). That is, the process shown in FIGS. 89 and 90 is a process capable of detecting an illegal act illustrated in FIG.

  Note that the processing in steps S911 to S956B (excluding step S960A) shown in FIGS. 89 and 90 is the same as the processing in steps S1711 to S1776 (excluding steps S1767 and S1768) shown in FIGS. 81 and 82. . However, the production control means takes a timer interruption every 4 ms, whereas the payout control means takes a timer interruption every 1 ms. Therefore, the values for determination in steps S954A and S954B are the values in steps S1764 and 1774. It is different from the value for judgment.

  Also, the payout control CPU 370 performs the processing shown in FIGS. 85 and 86, the processing shown in FIGS. 87 and 88, and the processing shown in FIGS. 89 and 90 in the abnormality determination processing in step S762. However, two or more of the processes may be executed.

  In this embodiment, the payout control CPU 371 adds the timer value, and the timer value is a predetermined value (in the example shown in FIGS. 85 and 86, 1000, 87 and 88 are shown). In the example, it is determined that a winning abnormality has occurred (see steps S913 and S914 in FIGS. 85 and 86) or a winning abnormality has occurred on condition that the counter value is equal to or greater than a predetermined value. (See steps S935A, S936A, S940A, S935B, S936B, and S940B in FIGS. 87 and 88), and the timer value is less than or equal to a predetermined value (32 or less in the examples shown in FIGS. 89 and 90). In this case, it is determined that a winning abnormality has occurred (steps S954A, S960A, and S954B in FIGS. 89 and 90). S960B reference), it may be subtracted the value of the timer.

  For example, the payout control CPU 371 sets 1000 in the timer in the processing of steps S920A and S920B in FIGS. 85 and 86, and subtracts 1 from the timer value in the processing of step S912, or in step S938A in FIGS. 87 and 88. , S938B is initialized to 500, and the timer value is decremented by 1 in step S912. Alternatively, the timer is initialized to 32 in steps S955A and S955B in FIGS. 89 and 90, and step S912 is processed. Or subtract 1 from the timer value. In that case, the payout control CPU 371 checks whether or not the timer value has become 0 in the processing of step S913 in FIGS. 85 and 86 and the processing of steps S935A and S935B in FIGS. Also, in the processing of steps S954A and S954B in FIGS. 89 and 88, it is confirmed whether or not the timer value is 0 or a negative value.

  In this embodiment, the game control microcomputer 560 transmits the input port state 1 designation command and the input port state 2 designation command only when the state of the detection signal from any one of the prize opening switches changes. However, regardless of whether the state of the detection signal changes or not, the input port state 1 designation command or the input port state 2 designation command is transmitted every start period of the game control process (4 ms in this embodiment). It may be.

  When the input port state 1 designation command or the input port state 2 designation command is transmitted every start period of the game control process, the game control microcomputer 560 performs step S2109 in the switch process (see FIGS. 33 and 34). Regardless of the result of the calculation in S2125, control is performed to transmit the input port state 1 designation command and the input port state 2 designation command.

  When the payout control CPU 371 confirms that there is no bit changed to “1” in the data indicating the states of the input ports 0 and 2 in the processing of steps S918A and S918B shown in FIGS. 85 and 86, There is a bit changed to “0” in the data indicating the states of the input ports 0 and 2 by comparing the previous value stored in the RAM with the data of the input port state 1 designation command or the input port state 2 designation command. If it is confirmed that there is a bit changed to “0”, the processing of steps S919A and S919B is executed. In the processing shown in FIGS. 85 and 86, whether or not there is a bit changed to “0” in the data indicating the states of the input ports 0 and 2 is determined by the game control microcomputer 560. , 2 when the input port state 1 designation command or the input port state 2 designation command is transmitted on the assumption that the bit of the detection signal changes / does not change. Regardless of this, when an input port state 1 designation command or an input port state 2 designation command is transmitted every start period of the game control process, the bit changed to “1” in the data indicating the states of the input ports 0 and 2 is also “0” This is because there may be no bit changed to "."

  Even when the input port state designation command is transmitted at each start period of the game control process regardless of whether the state of the detection signal changes, the process shown in FIGS. 87 and 88 and FIGS. As for the processing, the payout control CPU 371 may execute similar processing.

  In the processes shown in FIGS. 85 to 90, when the payout control CPU 370 determines that a winning abnormality has occurred, it outputs a signal indicating a winning abnormality to the terminal board 160. You may make it transmit to 31.

  When a signal indicating a winning abnormality is transmitted to the main board 31, as an example, a signal indicating a winning abnormality is assigned to bit 4 in the connection OK command and the winning ball preparation command shown in FIGS. . That is, when bit 4 is “1”, it indicates that a winning abnormality has occurred. Note that a signal indicating a prize abnormality may be assigned only to the connection OK command.

  When the payout control CPU 370 determines that a winning abnormality has occurred (“Y” in steps S913, S936A, S936B, S954A, and S954B), the payout control CPU 370 outputs a signal indicating the winning abnormality to the terminal board 160. Instead, data indicating that a winning abnormality has occurred is set in a predetermined area of the RAM.

  Then, the payout control CPU 370 transmits the main control in step S7414, step S74207, step S74221, step S74304, step S74312, step S74404, and step S74412 shown in FIGS. 50, 51, 52, 53, and 55. In the command conversion process, when data indicating that a winning abnormality has occurred is set in a predetermined area of the RAM, a process of setting bit 4 of the connection OK command to “1” is also performed.

  The CPU 56 in the game control microcomputer 560 confirms bit 4 of the connection OK command in the process of step S5224 when it is confirmed that the connection OK command is received in the process of step S5223 shown in FIG. When bit 4 is “1”, a process of outputting a signal indicating a prize abnormality to the terminal board 160 is also performed. In addition, when it is confirmed that the command for preparing a prize ball is received in the process of step S52406 shown in FIG. 24 and the process of step S52506 shown in FIG. 25, in the process of step S52407 and step S52507, A process of outputting a signal indicating a prize abnormality to the terminal board 160 when the bit 4 of the command for preparing a winning ball is confirmed and the bit 4 is “1” is also performed.

  Further, when a signal indicating a winning abnormality is output to the terminal board 160 or a signal indicating a winning abnormality is transmitted to the main board 31, the payout control microcomputer 370 receives a winning ball payout process (in addition to the winning ball payout process). It is also possible to shift to a state in which the ball lending process is not executed) or to output an error signal to the error display LED 374 to display a predetermined error code. Further, the transition to the state where the payout process is not executed and the display of the error code may be executed together. Further, the game control microcomputer 560 executes at least one of the transition to a state where the payout control microcomputer 370 does not execute the payout process and the display of the error code, or without executing them. As described above, when a signal indicating a prize abnormality is received from the payout control microcomputer 370 by a connection OK command or a winning ball preparation command, a command indicating a prize abnormality is transmitted to the effect control microcomputer 100. Good. When the effect control microcomputer 100 receives a command indicating an award abnormality, for example, the effect display device 9 performs an abnormality notification.

  As described above, in the second embodiment, whether or not a winning abnormality has occurred is determined by the payout control microcomputer 370, and when it is determined that a winning abnormality has occurred, the payout control microcomputer 370 directly Alternatively, a signal indicating an award abnormality is output to the outside of the gaming machine via the gaming control microcomputer 560. Therefore, it is confirmed that a prize abnormality has occurred outside the gaming machine (for example, a hall computer).

  In the second embodiment, when a signal indicating a prize abnormality is not directly output from the game control microcomputer 370 to the outside of the gaming machine, a signal indicating a prize abnormality is played through the game control microcomputer 560. Although it is output to the outside of the machine, a signal indicating a winning abnormality may be output to the outside of the gaming machine by passing through the main board 31 but not via the game control microcomputer 560. In this case, the payout control microcomputer 370 outputs a signal indicating a winning abnormality to the main board 31 with one signal line. Then, the input is connected to the wiring to the connector reaching the terminal board 160 inside the main board 31 by the signal line.

  According to the first embodiment and the second embodiment, the game control microcomputer 560 inputs a detection signal from each of the plurality of switches through one input port, and the input port Outputs input data as a command in a batch. For example, the detection signals of the count switch 23 and the winning switches 29a and 30a are collectively input from the input port 0 and the input port state 1 designation command is transmitted, and the first start port switch 13a and the second start port switch 14a are transmitted. The detection signals are collectively input from the input port 2 and an input port state 2 designation command is transmitted. Therefore, the game control microcomputer 560 collectively transmits switch detection signals to the electrical component control means (in this example, the effect control microcomputer 100 or the payout control microcomputer 370) that performs abnormality determination processing. Therefore, even if a plurality of switches are targeted for abnormality detection, the processing load on the game control microcomputer 560 does not increase.

  In the first and second embodiments described above, the detection signals of the count switch 23 and the winning port switches 29a and 30a are input from the input port 0 as positive logic, and the first start port switch 13a. Although the case where the detection signal of the second start port switch 14a is input from the input port 2 as negative logic is shown, the input form of the detection signal from each switch is limited to that shown in each of the above embodiments. I can't. For example, the detection signals of the count switch 23 and the prize opening switches 29a and 30a may not be logically inverted by the input driver circuit 58 and may be input as they are as negative logic signals (in this case, step S2121 in the switch processing). The logic of the first start port switch 13a and the second start port switch 14a is inverted by the input driver circuit 58, and the logic of the positive logic is reversed. You may make it input as a signal.

  Further, for example, the logics of all detection signals of the first start port switch 13a, the second start port switch 14a, the count switch 23, and the winning port switches 29a and 30a are made the same, and all the input signals are input from the same input port. It may be. For example, the input driver circuit 58 logically inverts all detection signals of the first start port switch 13a, the second start port switch 14a, the count switch 23, and the winning port switches 29a and 30a, and inputs the input port 0 as a positive logic signal. Input port status designation command including all statuses of the first start port switch 13a, the second start port switch 14a, the count switch 23, and the winning port switches 29a and 30a in a lump. It may be. With such a configuration, all the detection signals of the first start port switch 13a, the second start port switch 14a, the count switch 23, and the winning port switches 29a and 30a can be transmitted in a lump. The processing burden on the microcomputer 560 can be further reduced.

  Note that all the detection signals of the first start port switch 13a, the second start port switch 14a, the count switch 23, and the winning port switches 29a and 30a are input all at once from the same input port, and the first start port switch 13a. When the input port state designation command including all the states of the second start port switch 14a, the count switch 23, and the winning port switches 29a and 30a is transmitted, the first start port switch 13a, The logic of all the detection signals of the second start port switch 14a, the count switch 23, and the winning port switches 29a and 30a may not be the same. That is, an input port state designation command including all the states of the first start port switch 13a, the second start port switch 14a, the count switch 23, and the winning port switches 29a and 30a in a mixed form of positive logic and negative logic. May be transmitted. In this case, for example, depending on whether the effect control microcomputer 100 or the payout control microcomputer 370 has received the input port state designation command, it is positive logic or negative logic for each bit. What is necessary is just to determine whether the ON state was detected about each of the 1st starting port switch 13a, the 2nd starting port switch 14a, the count switch 23, and the prize winning port switches 29a and 30a.

  In the first and second embodiments, as shown in FIGS. 76 to 79 and FIGS. 87 and 88, the number of detection signal inputs is detected and a predetermined period (in this example, 0. 0) is detected. If it is configured to determine that an abnormality has occurred when the number of inputs detected in 5 seconds) exceeds a predetermined number (10 in this example), an illegal act of illegally turning on / off the detection signal of the switch is performed. Since it can be detected, fraud can be detected more reliably.

  In each of the above embodiments, the proximity switch is used as the first start port switch 13a, the second start port switch 14a, the count switch 23, and the winning port switches 29a and 30a, but a photo sensor may be used. . FIG. 91A is an explanatory diagram showing a reflective photosensor that can be used as the first start port switch 13a, the second start port switch 14a, the count switch 23, and the winning port switches 29a and 30a. The photosensor illustrated in FIG. 91A includes a light-emitting diode (LED) 341 that emits light and a phototransistor 342 that receives light and outputs current. When the game ball passes in the vicinity of the light-emitting diode 341 and the phototransistor 342, the phototransistor 342 receives light from the light-emitting diode 341 reflected by the game ball and causes a current to flow to the output side. The output side is connected to the main board 31, and the detection signal of the photo sensor is input from the input driver circuit to the input port of the game control microcomputer. When a current flows to the output side of the photosensor (specifically, the output side of the phototransistor 342), the input driver circuit outputs a high level detection signal to the game control microcomputer.

  FIG. 91 (B) is an explanatory view showing a transmissive photosensor that can be used as the first start port switch 13a, the second start port switch 14a, the count switch 23, and the winning port switches 29a and 30a. The photosensor illustrated in FIG. 91B is provided with a light-emitting element (LED 341) and a light-receiving element (phototransistor 342) facing each other with a winning ball path interposed therebetween, so that the game ball blocks light from the light-emitting element. A transmission type photosensor that detects a game ball that has passed between the light emitting element and the light receiving element may be used by preventing the light receiving element from detecting light. When a transmissive photosensor is used, as shown in the lower part of FIG. 91B, the optical axis of the light emitting element (illustrated by a black circle in FIG. 91B) is a game ball path (winning ball). It is preferable to install the light emitting element and the light receiving element so as to deviate from the center of the game ball passing through the route. Compared with the case where the optical axis corresponds to the central portion of the game ball, a portion where the interval between the two game balls passing through is relatively wide (the portion of “void” in FIG. 91B) This is because the game ball can be detected at, and the two game balls can be easily detected separately. For the same reason, when using the reflective photosensor illustrated in FIG. 91A, the light emitting element and the light receiving element are installed so that the reflection point of the light from the light emitting element is shifted from the center of the game ball. It is preferable to do.

  In each of the above-described embodiments, the proximity switch and the photosensor are used in combination for the second start winning opening 14, the second start opening switch 14a is configured using the proximity switch, and the winning confirmation switch 14b is a photosensor. It is configured using. FIG. 92 is an explanatory diagram showing a combination example of a proximity switch and a photosensor. FIG. 92 shows an example applied to the second start winning opening 14. In each of the above embodiments, as shown in FIG. 92 (A), the second start winning opening 14 includes a second start opening switch (proximity switch) 14a and a winning confirmation switch (photo sensor) 14b. In the second start winning opening 14, the proximity switch 14a and the photosensor 14b are arranged so that the game ball first passes through the proximity switch 14a and then passes through the photosensor 14b.

  As shown in FIG. 92 (A), an electromagnetic proximity switch is provided in the upper part (upstream side of the game ball flow path) in the switch, and an optical photosensor is provided in the lower part (downstream side of the game ball flow path). Therefore, when a switch for detecting a game ball receives a fraudulent act by radio waves, the fraudulent act can be reliably detected. As shown in FIG. 92B, a photo sensor may be provided in the upper portion and a proximity switch may be provided in the lower portion. In such a configuration, when a switch for detecting a game ball receives a fraudulent act of light, the fraudulent act can be reliably detected.

  The switch is preferably formed as a switch module (sensor unit) in which the proximity switch 14a and the photosensor 14b are housed in one package.

  In each of the above-described embodiments, the case where the proximity switch and the photo sensor are used in combination with respect to the second start winning opening 14 has been described. However, the same as in FIG. According to the configuration, the proximity switch and the photosensor may be used in combination.

  In the above embodiment, the case where the pachinko machine is applied as the gaming machine according to the present invention has been described. However, it is also possible to apply a parrot machine or a slot machine as the gaming machine according to the present invention. In a parrot machine, a predetermined number of bets are set according to the number of game balls taken in, a plurality of kinds of symbols are rotated by operating the operation lever, and stopped when the symbols are stopped by operating the stop button. When the symbol combination becomes a specific symbol combination, a predetermined number of prize balls are paid out to the player. In addition, in the slot machine, a medal is inserted, a predetermined bet number is set, a plurality of kinds of symbols are rotated by operating the operation lever, and the symbols are stopped when the symbols are stopped by operating the stop button. When the combination becomes a combination of specific symbols, a predetermined number of medals are paid out to the player.

  The parrot machine and slot machine as described above are generally configured so that the payout is completed and the next game is started each time one game is completed. Therefore, for example, a parrot machine or a slot machine may be configured such that the next game can be started before the payout is completed, and the configuration described in the above embodiment may be applied. For example, the configuration shown in the above embodiment is applied to a parrot machine, and the number of game balls to be returned in the parrot machine is cumulatively counted up to a counter. You may comprise so that it may output. In addition, for example, the configuration shown in the above embodiment is applied to a slot machine, and the planned payout number of medals from the hopper tank in the slot machine is cumulatively counted up to a counter, and the cumulative value becomes 10 or more. The winning signal may be output to the outside.

  The present invention can be suitably applied to gaming machines such as pachinko gaming machines and slot machines.

DESCRIPTION OF SYMBOLS 1 Pachinko machine 9 Production display device 13 1st start winning opening 14 2nd starting winning opening 13a 1st starting opening switch 14a 2nd starting opening switch 14b Winning confirmation switch 15 Variable winning ball apparatus 31 Game control board (main board)
37 Dispensing control board 56 CPU
80 Production control board 100 Production control microcomputer 101 Production control CPU
160 Terminal Board 370 Discharge Control Microcomputer 371 Discharge Control CPU
380 Serial communication circuit (withdrawal control side)
505 Serial communication circuit (game control side)
560 Microcomputer for game control

Claims (2)

Player using a game medium is capable of performing Yu technique, game imparting game medium based on the grant condition is satisfied by the game medium passage area provided in the game region has passed Machine,
It is possible to retain the stored contents for a predetermined period even when the power supply is stopped, and the fluctuation data storage means for storing the fluctuation data generated when performing the control,
Initialization operation means for outputting an operation signal in response to an operation;
An initialization process that can execute an initialization process that initializes the storage contents of the variation data storage means based on the input of the operation signal from the initialization operation means only when power supply is started Execution means;
Error determination means for determining whether or not a predetermined error has occurred;
Based on that a predetermined signal output condition is satisfied, including at least that the initialization process is executed by the initialization process execution means and that the error determination means determines that the predetermined error has occurred. A gaming machine state signal external output means for outputting a gaming machine state signal externally;
Detecting means for detecting a game medium passing through the passage area and outputting a detection signal;
Game control means for executing a game control process for controlling the progress of the game;
An electric component control means for controlling an electric component provided in the gaming machine based on a command output by the game control means;
Wherein when the applied condition said detection signal based on that input of the detecting means is satisfied, the satisfaction signal imparted number with the passage of the grant condition is externally outputs the condition satisfaction signal indicating that reaches a predetermined number An external output means,
The game control means includes command output means for inputting the detection signal from the detection means and outputting a command indicating an input state of the detection signal to the electrical component control means,
The electrical component control means, based on the command output from the command output means, that an abnormality has occurred in a period during which the input of the detection signal continues or when the input frequency of the detection signal exceeds a predetermined threshold an abnormality determination means for determining seen including,
The gaming machine state signal external output means is connected to the gaming machine when the initialization process is executed by the initialization process execution means and when the predetermined error is determined by the error determination means. A gaming machine, wherein the gaming machine state signal is output from a common output terminal provided . The gaming machine status signal external output means extends an output period for externally outputting the gaming machine status signal when a predetermined signal output condition is newly established when the gaming machine status signal is output externally.
The gaming machine according to claim 1.

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