JP6151377B2 - データキャッシュウェイ予測 - Google Patents

データキャッシュウェイ予測 Download PDF

Info

Publication number
JP6151377B2
JP6151377B2 JP2015552807A JP2015552807A JP6151377B2 JP 6151377 B2 JP6151377 B2 JP 6151377B2 JP 2015552807 A JP2015552807 A JP 2015552807A JP 2015552807 A JP2015552807 A JP 2015552807A JP 6151377 B2 JP6151377 B2 JP 6151377B2
Authority
JP
Japan
Prior art keywords
instruction
way
entry
execution
prediction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2015552807A
Other languages
English (en)
Japanese (ja)
Other versions
JP2016507097A5 (enExample
JP2016507097A (ja
Inventor
サッソーネ、ピーター・ジー．
ベンクマハンティ、スレシュ・ケー．
コドレスク、ルシアン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of JP2016507097A publication Critical patent/JP2016507097A/ja
Publication of JP2016507097A5 publication Critical patent/JP2016507097A5/ja
Application granted granted Critical
Publication of JP6151377B2 publication Critical patent/JP6151377B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/345—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes of multiple operands or results
    • G06F9/3455—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes of multiple operands or results using stride
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G06F9/3832—Value prediction for operands; operand history buffers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/608—Details relating to cache mapping
    • G06F2212/6082—Way prediction in set-associative cache

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
JP2015552807A 2013-01-15 2014-01-10 データキャッシュウェイ予測 Expired - Fee Related JP6151377B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/741,917 2013-01-15
US13/741,917 US9367468B2 (en) 2013-01-15 2013-01-15 Data cache way prediction
PCT/US2014/011051 WO2014113288A1 (en) 2013-01-15 2014-01-10 Data cache way prediction

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2017056153A Division JP6342537B2 (ja) 2013-01-15 2017-03-22 データキャッシュウェイ予測

Publications (3)

Publication Number Publication Date
JP2016507097A JP2016507097A (ja) 2016-03-07
JP2016507097A5 JP2016507097A5 (enExample) 2016-12-22
JP6151377B2 true JP6151377B2 (ja) 2017-06-21

Family

ID=50029280

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2015552807A Expired - Fee Related JP6151377B2 (ja) 2013-01-15 2014-01-10 データキャッシュウェイ予測
JP2017056153A Expired - Fee Related JP6342537B2 (ja) 2013-01-15 2017-03-22 データキャッシュウェイ予測

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2017056153A Expired - Fee Related JP6342537B2 (ja) 2013-01-15 2017-03-22 データキャッシュウェイ予測

Country Status (6)

Country Link
US (1) US9367468B2 (enExample)
EP (1) EP2946285B1 (enExample)
JP (2) JP6151377B2 (enExample)
KR (1) KR101710438B1 (enExample)
CN (1) CN104903851B (enExample)
WO (1) WO2014113288A1 (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10157137B1 (en) 2015-09-22 2018-12-18 Apple Inc. Cache way prediction
US11709679B2 (en) * 2016-03-31 2023-07-25 Qualcomm Incorporated Providing load address predictions using address prediction tables based on load path history in processor-based systems
US10684859B2 (en) * 2016-09-19 2020-06-16 Qualcomm Incorporated Providing memory dependence prediction in block-atomic dataflow architectures
US20180081815A1 (en) * 2016-09-22 2018-03-22 Qualcomm Incorporated Way storage of next cache line
CN206485775U (zh) 2017-01-19 2017-09-12 科丝美诗(中国)化妆品有限公司 一种盖子及具有该盖子的包装
US11281586B2 (en) 2017-05-09 2022-03-22 Andes Technology Corporation Processor and way prediction method thereof
US10877894B2 (en) * 2019-05-16 2020-12-29 Micron Technology, Inc. Memory-side transaction context memory interface systems and methods, wherein first context and first address are communicated on plural wires during different clock cycles and second context (of block of the first context) is communicated on additional wire during one of the different clock cycles
CN112559049A (zh) * 2019-09-25 2021-03-26 阿里巴巴集团控股有限公司 用于指令高速缓存的路预测方法、访问控制单元以及指令处理装置
KR20210097345A (ko) 2020-01-30 2021-08-09 삼성전자주식회사 캐시 메모리 장치, 이를 포함하는 시스템 및 캐시 메모리 장치의 동작 방법
US11397685B1 (en) * 2021-02-24 2022-07-26 Arm Limited Storing prediction entries and stream entries where each stream entry includes a stream identifier and a plurality of sequential way predictions
US11487667B1 (en) 2021-08-09 2022-11-01 Apple Inc. Prediction confirmation for cache subsystem
CN114816032B (zh) * 2022-06-30 2022-09-23 飞腾信息技术有限公司 一种数据处理方法、装置、电子设备及存储介质

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5640532A (en) 1994-10-14 1997-06-17 Compaq Computer Corporation Microprocessor cache memory way prediction based on the way of previous memory read
US5752069A (en) 1995-08-31 1998-05-12 Advanced Micro Devices, Inc. Superscalar microprocessor employing away prediction structure
US6055622A (en) * 1997-02-03 2000-04-25 Intel Corporation Global stride prefetching apparatus and method for a high-performance processor
US6401193B1 (en) 1998-10-26 2002-06-04 Infineon Technologies North America Corp. Dynamic data prefetching based on program counter and addressing mode
US6314504B1 (en) * 1999-03-09 2001-11-06 Ericsson, Inc. Multi-mode memory addressing using variable-length
US6643739B2 (en) * 2001-03-13 2003-11-04 Koninklijke Philips Electronics N.V. Cache way prediction based on instruction base register
US6678792B2 (en) * 2001-06-22 2004-01-13 Koninklijke Philips Electronics N.V. Fast and accurate cache way selection
US7406569B2 (en) * 2002-08-12 2008-07-29 Nxp B.V. Instruction cache way prediction for jump targets
US20050050278A1 (en) 2003-09-03 2005-03-03 Advanced Micro Devices, Inc. Low power way-predicted cache
US7117290B2 (en) 2003-09-03 2006-10-03 Advanced Micro Devices, Inc. MicroTLB and micro tag for reducing power in a processor
US7594223B2 (en) * 2005-06-27 2009-09-22 Hewlett-Packard Development Company, L.P. Straight-line post-increment optimization for memory access instructions
US7657708B2 (en) 2006-08-18 2010-02-02 Mips Technologies, Inc. Methods for reducing data cache access power in a processor using way selection bits
US7917702B2 (en) 2007-07-10 2011-03-29 Qualcomm Incorporated Data prefetch throttle
US7827356B2 (en) 2007-09-10 2010-11-02 Qualcomm Incorporated System and method of using an N-way cache
US8151084B2 (en) * 2008-01-23 2012-04-03 Oracle America, Inc. Using address and non-address information for improved index generation for cache memories
US8145874B2 (en) * 2008-02-26 2012-03-27 Qualcomm Incorporated System and method of data forwarding within an execution unit
US8151096B2 (en) 2008-08-06 2012-04-03 Intel Corporation Method to improve branch prediction latency
US8327121B2 (en) 2008-08-20 2012-12-04 Mips Technologies, Inc. Data cache receive flop bypass
US8392651B2 (en) * 2008-08-20 2013-03-05 Mips Technologies, Inc. Data cache way prediction
JP2011257800A (ja) * 2010-06-04 2011-12-22 Panasonic Corp キャッシュメモリ装置、プログラム変換装置、キャッシュメモリ制御方法及びプログラム変換方法
US8533422B2 (en) 2010-09-30 2013-09-10 Intel Corporation Instruction prefetching using cache line history
US8635408B2 (en) 2011-01-04 2014-01-21 International Business Machines Corporation Controlling power of a cache based on predicting the instruction cache way for high power applications

Also Published As

Publication number Publication date
WO2014113288A1 (en) 2014-07-24
CN104903851A (zh) 2015-09-09
CN104903851B (zh) 2018-04-20
US9367468B2 (en) 2016-06-14
JP2017152001A (ja) 2017-08-31
EP2946285A1 (en) 2015-11-25
JP2016507097A (ja) 2016-03-07
US20140201449A1 (en) 2014-07-17
EP2946285B1 (en) 2017-11-29
JP6342537B2 (ja) 2018-06-13
KR101710438B1 (ko) 2017-02-27
KR20150106881A (ko) 2015-09-22

Similar Documents

Publication Publication Date Title
JP6342537B2 (ja) データキャッシュウェイ予測
JP5172942B2 (ja) プロセッサによる電力消費を低減する方法、プロセッサ、及び、情報処理システム
JP5254342B2 (ja) ｎ−ウェイキャッシュを用いるシステムおよび方法
KR20180127379A (ko) 프로세서-기반 시스템들 내의 로드 경로 이력에 기반한 어드레스 예측 테이블들을 사용하는 로드 어드레스 예측들의 제공
US20170046158A1 (en) Determining prefetch instructions based on instruction encoding
US20160139933A1 (en) Providing loop-invariant value prediction using a predicted values table, and related apparatuses, methods, and computer-readable media
TW201908966A (zh) 針對固定方向分支指令的分支預測
JP2018523239A (ja) 電力効率的なフェッチ適合
JP2017537408A (ja) アウトオブオーダー（ｏｏｏ）プロセッサにおける早期命令実行を提供すること、ならびに関連する装置、方法、およびコンピュータ可読媒体
JP6212133B2 (ja) マルチビットウェイ予測マスクを有する命令キャッシュ
US20160077836A1 (en) Predicting literal load values using a literal load prediction table, and related circuits, methods, and computer-readable media
US20110219212A1 (en) System and Method of Processing Hierarchical Very Long Instruction Packets
US9075620B2 (en) Instruction execution circuit
US20130145097A1 (en) Selective Access of a Store Buffer Based on Cache State
CN104252334B (zh) 分支目标地址获取方法和装置
CN119645496B (zh) 缓存及操作方法、处理器核、指令处理方法、设备和介质
CN113227970B (zh) 指令紧密耦合存储器和指令缓存访问预测
CN114116010B (zh) 一种针对处理器循环体的体系结构优化方法及装置
CN120560724A (zh) 处理装置、指令处理方法、处理芯片及电子设备

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20161104

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20161104

A871 Explanation of circumstances concerning accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A871

Effective date: 20161104

A975 Report on accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A971005

Effective date: 20161122

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20161129

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20170228

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20170322

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20170425

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20170524

R150 Certificate of patent or registration of utility model

Ref document number: 6151377

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

LAPS Cancellation because of no payment of annual fees