JP2016507097A5 - - Google Patents
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- JP2016507097A5 JP2016507097A5 JP2015552807A JP2015552807A JP2016507097A5 JP 2016507097 A5 JP2016507097 A5 JP 2016507097A5 JP 2015552807 A JP2015552807 A JP 2015552807A JP 2015552807 A JP2015552807 A JP 2015552807A JP 2016507097 A5 JP2016507097 A5 JP 2016507097A5
- Authority
- JP
- Japan
- Prior art keywords
- instruction
- way
- entry
- execution
- data cache
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 claims description 29
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/741,917 | 2013-01-15 | ||
| US13/741,917 US9367468B2 (en) | 2013-01-15 | 2013-01-15 | Data cache way prediction |
| PCT/US2014/011051 WO2014113288A1 (en) | 2013-01-15 | 2014-01-10 | Data cache way prediction |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2017056153A Division JP6342537B2 (ja) | 2013-01-15 | 2017-03-22 | データキャッシュウェイ予測 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2016507097A JP2016507097A (ja) | 2016-03-07 |
| JP2016507097A5 true JP2016507097A5 (enExample) | 2016-12-22 |
| JP6151377B2 JP6151377B2 (ja) | 2017-06-21 |
Family
ID=50029280
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2015552807A Expired - Fee Related JP6151377B2 (ja) | 2013-01-15 | 2014-01-10 | データキャッシュウェイ予測 |
| JP2017056153A Expired - Fee Related JP6342537B2 (ja) | 2013-01-15 | 2017-03-22 | データキャッシュウェイ予測 |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2017056153A Expired - Fee Related JP6342537B2 (ja) | 2013-01-15 | 2017-03-22 | データキャッシュウェイ予測 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US9367468B2 (enExample) |
| EP (1) | EP2946285B1 (enExample) |
| JP (2) | JP6151377B2 (enExample) |
| KR (1) | KR101710438B1 (enExample) |
| CN (1) | CN104903851B (enExample) |
| WO (1) | WO2014113288A1 (enExample) |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10157137B1 (en) | 2015-09-22 | 2018-12-18 | Apple Inc. | Cache way prediction |
| US11709679B2 (en) * | 2016-03-31 | 2023-07-25 | Qualcomm Incorporated | Providing load address predictions using address prediction tables based on load path history in processor-based systems |
| US10684859B2 (en) * | 2016-09-19 | 2020-06-16 | Qualcomm Incorporated | Providing memory dependence prediction in block-atomic dataflow architectures |
| US20180081815A1 (en) * | 2016-09-22 | 2018-03-22 | Qualcomm Incorporated | Way storage of next cache line |
| CN206485775U (zh) | 2017-01-19 | 2017-09-12 | 科丝美诗(中国)化妆品有限公司 | 一种盖子及具有该盖子的包装 |
| US11281586B2 (en) | 2017-05-09 | 2022-03-22 | Andes Technology Corporation | Processor and way prediction method thereof |
| US10877894B2 (en) * | 2019-05-16 | 2020-12-29 | Micron Technology, Inc. | Memory-side transaction context memory interface systems and methods, wherein first context and first address are communicated on plural wires during different clock cycles and second context (of block of the first context) is communicated on additional wire during one of the different clock cycles |
| CN112559049A (zh) * | 2019-09-25 | 2021-03-26 | 阿里巴巴集团控股有限公司 | 用于指令高速缓存的路预测方法、访问控制单元以及指令处理装置 |
| KR20210097345A (ko) | 2020-01-30 | 2021-08-09 | 삼성전자주식회사 | 캐시 메모리 장치, 이를 포함하는 시스템 및 캐시 메모리 장치의 동작 방법 |
| US11397685B1 (en) * | 2021-02-24 | 2022-07-26 | Arm Limited | Storing prediction entries and stream entries where each stream entry includes a stream identifier and a plurality of sequential way predictions |
| US11487667B1 (en) | 2021-08-09 | 2022-11-01 | Apple Inc. | Prediction confirmation for cache subsystem |
| CN114816032B (zh) * | 2022-06-30 | 2022-09-23 | 飞腾信息技术有限公司 | 一种数据处理方法、装置、电子设备及存储介质 |
Family Cites Families (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5640532A (en) | 1994-10-14 | 1997-06-17 | Compaq Computer Corporation | Microprocessor cache memory way prediction based on the way of previous memory read |
| US5752069A (en) | 1995-08-31 | 1998-05-12 | Advanced Micro Devices, Inc. | Superscalar microprocessor employing away prediction structure |
| US6055622A (en) * | 1997-02-03 | 2000-04-25 | Intel Corporation | Global stride prefetching apparatus and method for a high-performance processor |
| US6401193B1 (en) | 1998-10-26 | 2002-06-04 | Infineon Technologies North America Corp. | Dynamic data prefetching based on program counter and addressing mode |
| US6314504B1 (en) * | 1999-03-09 | 2001-11-06 | Ericsson, Inc. | Multi-mode memory addressing using variable-length |
| US6643739B2 (en) * | 2001-03-13 | 2003-11-04 | Koninklijke Philips Electronics N.V. | Cache way prediction based on instruction base register |
| US6678792B2 (en) * | 2001-06-22 | 2004-01-13 | Koninklijke Philips Electronics N.V. | Fast and accurate cache way selection |
| US7406569B2 (en) * | 2002-08-12 | 2008-07-29 | Nxp B.V. | Instruction cache way prediction for jump targets |
| US20050050278A1 (en) | 2003-09-03 | 2005-03-03 | Advanced Micro Devices, Inc. | Low power way-predicted cache |
| US7117290B2 (en) | 2003-09-03 | 2006-10-03 | Advanced Micro Devices, Inc. | MicroTLB and micro tag for reducing power in a processor |
| US7594223B2 (en) * | 2005-06-27 | 2009-09-22 | Hewlett-Packard Development Company, L.P. | Straight-line post-increment optimization for memory access instructions |
| US7657708B2 (en) | 2006-08-18 | 2010-02-02 | Mips Technologies, Inc. | Methods for reducing data cache access power in a processor using way selection bits |
| US7917702B2 (en) | 2007-07-10 | 2011-03-29 | Qualcomm Incorporated | Data prefetch throttle |
| US7827356B2 (en) | 2007-09-10 | 2010-11-02 | Qualcomm Incorporated | System and method of using an N-way cache |
| US8151084B2 (en) * | 2008-01-23 | 2012-04-03 | Oracle America, Inc. | Using address and non-address information for improved index generation for cache memories |
| US8145874B2 (en) * | 2008-02-26 | 2012-03-27 | Qualcomm Incorporated | System and method of data forwarding within an execution unit |
| US8151096B2 (en) | 2008-08-06 | 2012-04-03 | Intel Corporation | Method to improve branch prediction latency |
| US8327121B2 (en) | 2008-08-20 | 2012-12-04 | Mips Technologies, Inc. | Data cache receive flop bypass |
| US8392651B2 (en) * | 2008-08-20 | 2013-03-05 | Mips Technologies, Inc. | Data cache way prediction |
| JP2011257800A (ja) * | 2010-06-04 | 2011-12-22 | Panasonic Corp | キャッシュメモリ装置、プログラム変換装置、キャッシュメモリ制御方法及びプログラム変換方法 |
| US8533422B2 (en) | 2010-09-30 | 2013-09-10 | Intel Corporation | Instruction prefetching using cache line history |
| US8635408B2 (en) | 2011-01-04 | 2014-01-21 | International Business Machines Corporation | Controlling power of a cache based on predicting the instruction cache way for high power applications |
-
2013
- 2013-01-15 US US13/741,917 patent/US9367468B2/en not_active Expired - Fee Related
-
2014
- 2014-01-10 WO PCT/US2014/011051 patent/WO2014113288A1/en not_active Ceased
- 2014-01-10 JP JP2015552807A patent/JP6151377B2/ja not_active Expired - Fee Related
- 2014-01-10 EP EP14701881.6A patent/EP2946285B1/en not_active Not-in-force
- 2014-01-10 CN CN201480003975.8A patent/CN104903851B/zh not_active Expired - Fee Related
- 2014-01-10 KR KR1020157017911A patent/KR101710438B1/ko not_active Expired - Fee Related
-
2017
- 2017-03-22 JP JP2017056153A patent/JP6342537B2/ja not_active Expired - Fee Related
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