JP6143925B2 - Data access device using memory element - Google Patents

Description

  The present invention relates to a data access device, and more particularly, uses a memory element that can easily read / write (Read / Write) data of 16 bits or more using one 8-bit memory element. The present invention relates to a data access device.

  In general, a central processing unit (CPU) responsible for overall control of an electronic control system performs access (Access) for reading or writing data in a memory device (Memory Device) that is a storage device. .

  That is, the central processing unit (CPU) performs access to read / write data to the memory element. Thus, reading or writing means reading or writing with reference to a central processing unit (CPU). Reading means transferring data in the memory element to the central processing unit (CPU), and writing means transferring data from the central processing unit (CPU) to the memory element.

On the other hand, a solar inverter system that has recently been in the spotlight among electronic control systems is a system that generates electric power by converting direct current (DC) energy supplied from a solar module into alternating current (AC) energy. .
When such a solar inverter system is operated, various types of information such as voltage / current / power generation amount are stored in the memory element, and the stored information on the memory element is transferred via a communication line to the outside. It is stored in a device (for example, a monitoring device).

  The power generation amount of the solar inverter system is very important data, and the cumulative power generation amount (that is, the total power generation amount from the past to the present when the solar inverter started generating power) is very important for the user. Information.

  On the other hand, the existing 8-bit (16-bit) or 16-bit (bit) memory elements have 256 and 65536 data that can be recorded at maximum, respectively. The capacity is too small to display. Accordingly, the accumulated power generation amount can be displayed in units of MW (megawatts) only after a minimum of 24 bits (maximum recordable data is 16777216). This raises the need for a method that can store 24-bit data in 8-bit memory devices commonly sold in the market.

  Recently, with the development of communication technology, the amount of data that can be transferred to external devices of the solar inverter system has increased to 8 bits / 16 bits / 24 bits and so on. In addition, the amount of data transmitted to users by communication is gradually increasing. Nevertheless, no communication speed reduction phenomenon has occurred.

  However, most of the memory elements (in particular, nonvolatile memory elements) that store data acquired by communication are 8-bit memory elements, and the 24-bit memory elements have a disadvantage that they are very expensive.

  In addition, even if an attempt is made to read / write important data to / from the memory element in the solar inverter system, a commercially available 8-bit memory element must be used, so that the data capacity is limited to 8 bits. is there. In addition, in order to read / write data of 24-bit capacity, a commercially available 24-bit memory device must be purchased. However, the 24-bit memory device has a disadvantage that its price is very high. is there.

A memory element (a commercially available memory element) mainly used in the solar inverter system is an 8-bit product. An 8-bit memory device is used for general purposes and has the lowest price.
And when storing the main data (for example, cumulative power generation amount, etc.) of the solar inverter system using a commercially available 8-bit memory element, the 8-bit memory element is limited by the capacity limit of the memory element (8 bits). Only capacity data can be stored.

  The present invention has been devised to solve the above-described problems. The object of the present invention is to easily read / write data of 16 bits or more using a single 8-bit memory element. It is an object of the present invention to provide a data access device using a memory element that can operate (Read / Write).

  To achieve the above object, the present invention provides a memory device having an address space composed of a plurality of memory addresses so that data can be read or written, and the address space of the memory device is defined as N. (N is a natural number greater than or equal to 2) divided into equal parts and defined as first to Nth areas, corresponding to the memory addresses of the memory elements and the address spaces of the first to Nth areas, respectively. An address mapping unit that maps so that specific memory addresses that are set correspond to each other, and data division that divides M (M is a natural number of 2 or more) bits into N equal parts and divides the data into first to Nth data And the first to Nth data divided from the data dividing unit and the specific memory addresses respectively set in the first to Nth areas are mapped. The first to Nth data divided by the data mapping unit and the data dividing unit are designated by the specific memory addresses of the first to Nth areas and the memory addresses of the mapped memory elements, respectively. And a control unit that controls to be stored in the storage area.

  Here, each of the specific memory addresses in the first to Nth areas and the first to Nth data stored in the storage area specified by the memory address of the mapped memory element are combined. It is preferable that a data restoration unit for restoring original M-bit data is further included.

  Preferably, the address mapping unit may define the first to Nth regions by dividing the address space of the memory device into N equal parts according to a user setting.

  Preferably, each of the specific memory addresses in the first to Nth areas may be composed of the memory addresses located in the same order or in a random order according to a user setting.

  Preferably, the memory device is an 8-bit memory device, and N = 2, M = 16, N = 3, M = 24, N = 4, and M = 32. Can be done in one case.

  According to the data access device using the memory element of the present invention as described above, it is possible to easily read / write (Read / Write) data of 16 bits or more using one 8-bit memory element. it can. Accordingly, it is possible to efficiently access a large amount of data to an inexpensive and small capacity memory element, and there is an advantage that the cost can be effectively reduced.

FIG. 10 is a diagram for explaining a method of performing 8-bit data read / write operation on an 8-bit memory device according to a conventional technique. FIG. 10 is a diagram for explaining a method of performing a read / write operation of 24-bit data using a plurality of 8-bit memory elements according to a conventional technique. 1 is an overall block configuration diagram for explaining a data access device using a memory device according to an embodiment of the present invention; FIG. 5 is a diagram for explaining a method of performing read / write operation of 24-bit data using one 8-bit memory device according to an embodiment of the present invention. 3 is an overall flowchart illustrating a method for accessing data using a memory device according to an embodiment of the present invention.

  The above-described objects, features, and advantages will be described in detail later with reference to the accompanying drawings, so that those skilled in the art can easily implement the technical idea of the present invention. Will be able to. In describing the present invention, when it is determined that a specific description of a known technique related to the present invention is misleading in the gist of the present invention, a detailed description is omitted.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the embodiments of the present invention exemplified below can be modified into various other forms, and the scope of the present invention is not limited to the embodiments described in detail below. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. In the drawings, the same reference numerals are used to indicate the same or similar components.

  FIG. 1 is a diagram for explaining a method of reading / writing 8-bit data in an 8-bit memory device according to the prior art. One 8-bit memory device has “0 × 0000- It has memory addresses (Address) up to address “0 × NNNN”. Therefore, 8-bit data is stored in a storage area specified by each memory address of the 8-bit memory element by performing a write operation, and if necessary, a read operation is performed to read the data.

  FIG. 2 is a diagram for explaining a method of reading / writing 24-bit data using an 8-bit memory device having a plurality of memory addresses according to the prior art. For example, in a solar inverter system, three 8-bit memory elements must be used to store 24-bit data.

  In the solar inverter system, the 24-bit data to be stored in the 8-bit memory element is divided into three equal parts and divided into three 8-bit data. Thereafter, the divided three 8-bit data are respectively written (write) to the 8-bit memory element, and if necessary, the read (read) operation is performed to read the data.

  However, the conventional technology has a disadvantage in that the data that can be stored in the solar inverter system is limited to 8 bits, 24 bits, etc., depending on the capacity of the memory element used (8 bits, 24 bits, etc.). That is, the capacity of data that can be read / written in the memory element is determined by the capacity of the memory element to be used, and in addition to the commercially available 8-bit memory element, a memory element of 16 bits or more is priced. There are high disadvantages.

  In addition, 24-bit data cannot be stored in a commercially available 8-bit memory element. If 24-bit data is to be stored using an 8-bit memory element, three 8-bit memory elements must be used as shown in FIG. 2, which increases the price. There is.

  In order to solve such a conventional problem, for example, the present invention easily reads / writes data of 16 bits or more (Read / Write) to one 8-bit memory element used in a solar inverter system or the like. ) It is a characteristic technology that enables operation.

  When such a data access device using a memory device according to an embodiment of the present invention is applied, a solar inverter is used depending on the capacity (8 bits, 24 bits, etc.) of the memory device used in a conventional solar inverter system or the like. The problem that the data that can be stored in the system is limited to 8 bits, 24 bits, etc. can be solved. Further, it is possible to effectively solve the problem that the capacity of data that can be read / written in the memory element is determined by the capacity of the memory element to be used.

  That is, according to the embodiment of the present invention, data of a large capacity (for example, 16 bits, 24 bits, 32 bits, etc.) stored in an inexpensive small capacity (8 bits) memory element is efficiently accessed (Access). And can save costs effectively.

  FIG. 3 is an overall block diagram illustrating a data access device using a memory device according to an embodiment of the present invention, and FIG. 4 illustrates one 8-bit data according to an embodiment of the present invention. It is a figure for demonstrating the system which reads / writes data of 24 bits using the memory element of.

  Referring to FIGS. 3 and 4, a data access device using a memory device according to an embodiment of the present invention includes an 8-bit memory device 100, an address mapping unit 200, a data dividing unit 300, a data mapping unit 400, and a control. Part 500 and the like.

  Here, the 8-bit memory device 100 can read or write 8-bit data, so that a plurality of memory addresses (for example, addresses “0 × 0000 to 0 × NNNN”) can be read. It can be configured from a memory IC (Integrated Circuit) having an address space up to.

  Such an 8-bit memory device 100 has a memory address that designates a data storage position, and a data bus exists as a path through which data is transmitted. If data is read by the control unit 500 and the memory address of the data to be read is transmitted to the 8-bit memory device 100, the 8-bit memory device 100 places the data at the designated memory address on the data bus and controls the control unit 500. 500 reads. When writing data, if a specific memory address is given, the 8-bit memory device 100 writes the data to the storage area specified by the memory address.

  Then, the control unit 500 sends a memory address, which is position information of the 8-bit memory element 100, on an address bus. When the 8-bit memory device 100 receives the memory address information, it reads or writes data in the storage area specified by the corresponding memory address information.

  On the other hand, the 8-bit memory device 100 can maintain stored data information even when power is not supplied, and can perform a read / write operation (Non-volatile memory). , NVM, NVRAM). Non-volatile memory includes, for example, ROM (Electrically Erasable Programmable Read-Only Memory), flash memory (Flash Memory), phase change memory (Phase Change Memory), resistance memory (Resist Memory), resistance memory (Me) Memory).

  The address mapping unit 200 defines the first to third regions (A to C) by dividing the address space of the 8-bit memory device 100 into three equal parts. Thereafter, the memory address (0 × 0000 to 0 × NNNN) of the 8-bit memory device 100 and the memory addresses (0 × 000 to 0 ×) already set in the defined first to third areas (A to C), respectively. GGGG, 0 × GGGG + 0 × 01 to 0 × HHHH, 0 × HHHH + 0 × 01 to 0 × NNNN) performs mapping so as to correspond to each other one to one (1: 1).

  As shown in FIG. 4, the address mapping unit 200 divides the memory address corresponding to the address space of the 8-bit memory device 100 into three equal parts according to the address address order. A to C) are preferably defined. However, the present invention is not limited to this, and the first to third regions (A to C) can be defined by dividing into three equal parts randomly regardless of the address address order.

  The data dividing unit 300 functions to divide 24-bit data, which is composed of three 8-bit data, into eight equal bits and divide them into first to third 8-bit data.

  As shown in FIG. 4, the data dividing unit 300 divides 24-bit data into 8 equal bits, upper 8 bits, middle 8 bits, and lower 8 bits. It is preferable to divide the data into first to third 8-bit data. However, the present invention is not limited to this, and the 24-bit data can be divided into three equal parts randomly and divided into first to third 8-bit data.

  The data mapping unit 400 is set to the first to third 8-bit data divided from the data dividing unit 300 and the first to third areas (A to C) defined from the address mapping unit 200, respectively. It performs a function of mapping a specific memory address.

  At this time, it is preferable that the specific memory addresses in the first to third areas (A to C) defined by the address mapping unit 200 include memory addresses located in the same order. For example, when mapping the first 8-bit data to the address “0 × 0000” located first in the first area (A), the first position is located in the second and third areas (B and C). The second and third 8-bit data are mapped to the addresses “0 × GGGG + 0 × 01” and “0 × HHHH + 0 × 01”, respectively.

  On the other hand, the specific memory addresses of the first to third areas (A to C) defined from the address mapping unit 200 may be memory addresses located in different orders or random orders depending on the setting of the user. .

  The control unit 500 converts the first to third 8-bit data divided by the data dividing unit 300 and the specific memory addresses of the first to third areas (A to C) defined from the address mapping unit 200. It performs the function of controlling to be stored in the storage area specified by the memory address of the 8-bit memory element 100 to be mapped.

  The data access device has a storage area designated by the specific memory addresses of the first to third areas (A to C) defined by the address mapping unit 200 and the memory address of the 8-bit memory element 100 to be mapped. Further included is a data restoration unit 600 that combines the stored first to third 8-bit data and restores the original 24-bit data.

  On the other hand, the address mapping unit 200, the data division unit 300, the data mapping unit 400, and the data restoration unit 600 applied to one embodiment of the present invention are programmed by software, and are the control unit 500 or the central processing unit (CPU). It is preferable to be implemented so as to be operated inside. However, the present invention is not limited to this, and the address mapping unit 200, the data division unit 300, the data mapping unit 400, and the data restoration unit 600 are implemented in hardware separately from the control unit 500 or the central processing unit (CPU). You can also.

  On the other hand, the address mapping unit 200, the data division unit 300, the data mapping unit 400, the control unit 500, and the data restoration unit 600 applied to one embodiment of the present invention are included in one central processing unit (CPU). You can also

Hereinafter, a method for accessing data using a memory device according to an embodiment of the present invention will be described in detail.
FIG. 5 is an overall flowchart illustrating a method for accessing data using a memory device according to an embodiment of the present invention.

  Referring to FIGS. 3 to 5, when 24-bit data is to be stored (written) in the 8-bit memory device 100 by the control unit 500 applied to the embodiment of the present invention, first, the address mapping unit 200. Then, the address space of the 8-bit memory device 100 is divided into three equal parts and defined as first to third regions (A to C) (S100).

  At this time, it is preferable to define the memory addresses of the 8-bit memory element 100 as the first to third regions (A to C) by dividing the memory address into three equal parts according to the order of the preset memory addresses (see FIG. 4).

  Thereafter, the memory address of the 8-bit memory device 100 and the memory addresses already set in the first to third areas (A to C) are mapped so as to have a one-to-one (1: 1) correspondence (S200). . Thereafter, the 24-bit data to be stored through the data dividing unit 300 is divided into three equal parts of 8 bits and divided into first to third 8-bit data (S300).

  At this time, the 24-bit data is divided into three equal parts, the upper 8 bits of data, the middle 8 bits of data, and the lower 8 bits of data sequentially in 8 bits (bits). It is preferable to divide the data.

  Thereafter, the first to third 8-bit data divided in step S300 through the data mapping unit 400 and the specific memory addresses already set in the first to third areas (A to C) defined in step S100. Are mapped (S400). At this time, it is preferable that the specific memory addresses of the first to third areas (A to C) defined in step S100 include memory addresses located in the same order.

  Next, the first to third 8-bit data divided in step S300 through the control unit 500 is mapped to the specific memory addresses in the first to third areas (A to C) defined in step S100. The data is stored in a storage area specified by the memory address of the 8-bit memory element 100 (S500).

  That is, the first 8-bit data of the 24-bit data to be stored is stored in the first area (A), and the second 8-bit data of the 24-bit data to be stored is stored in the second area (A). B), and the third 8-bit data of the 24-bit data to be stored is stored in the third area (C).

  On the other hand, as described above, when data stored in the 8-bit memory device 100 is to be read (Read), the data in the first to third regions (A to C) defined in step S100 through the data restoration unit 600 is read. The original 24-bit data is restored by combining the first to third 8-bit data stored in the storage area specified by the specific memory address and the memory address of the 8-bit memory device 100 mapped. Thereafter, a reading operation can be performed.

  The data access device using the memory element according to the embodiment of the present invention described above is preferably applied to a solar inverter system. However, the present invention is not limited to this, and the present invention can be applied to all electronic control apparatuses and systems that can access data to the memory based on the control module.

  In one embodiment of the present invention, 24-bit data can be read or written in one 8-bit memory device. However, the present invention is not limited to this, and a large capacity data (for example, 32 bits, 64 bits, 128 bits, etc.) is read into one small capacity memory element (for example, 16 bits, 32 bits, 64 bits, etc.), Alternatively, it can be implemented so that it can be written.

  For example, 16-bit data can be divided into two equal parts and read or written into one 8-bit memory element, and 32-bit data can be equally divided into four 8-bit memory elements. It can be implemented so that it can be read or written to. That is, it can be implemented so that data of 16 bits or more can be read or written to one 8-bit memory device. On the other hand, a memory device having 16 bits or more can also be implemented so as to be able to read or write a large amount of data (for example, 32 bits, 64 bits, 128 bits, etc.). A specific implementation method relating to this can be performed in the same manner as in the above-described embodiment of the present invention.

  Meanwhile, a data access method using a memory device according to an embodiment of the present invention may also be embodied as a computer readable code on a computer readable recording medium. Computer-readable recording media include all types of recording devices that store data that can be read by a computer system.

  For example, as a computer-readable recording medium, ROM (ROM), RAM (RAM), CD ROM (CD-ROM), magnetic tape, hard disk, floppy disk, mobile storage device, non-volatile memory (Flash Memory) And optical data storage devices.

  Further, the computer-readable recording medium can be distributed in a computer system connected via a computer communication network and stored and executed as a code that can be read in a distributed manner.

  According to the data access apparatus using the memory device of the present invention as described above, it is possible to easily perform read / write (Read / Write) operation of data of 16 bits or more using one 8-bit memory device. can do. As a result, there is an advantage that large capacity data can be efficiently accessed to an inexpensive small capacity memory element, and the cost can be effectively reduced.

  A preferred embodiment of the data access device using the memory device according to the present invention has been described. However, the present invention is not limited to this, and various modifications can be made within the scope of the claims, the detailed description of the invention and the attached drawings, and this is also applicable to the present invention. Belongs to the invention.

The present invention can be used for a data access device using a memory element.

DESCRIPTION OF SYMBOLS 100 Memory element 200 Address mapping part 300 Data division part 400 Data mapping part 500 Control part

Claims (5)

A memory element having an address space composed of a plurality of memory addresses so that data can be read or written;
The address space of the memory element is divided into N (N is a natural number equal to or greater than 2) and defined as first to Nth areas, and the memory address of the memory element and the first to Nth areas are defined. An address mapping unit that performs mapping so that specific memory addresses respectively set corresponding to the address space correspond to each other;
A data dividing unit that divides M (M is a natural number of 2 or more) bits into N equal parts and divides the data into first to Nth data;
A data mapping unit that maps the first to Nth data divided from the data dividing unit and the specific memory addresses set in the first to Nth areas;
The first to Nth data divided by the data dividing unit is stored in each of the specific memory addresses of the first to Nth areas and a storage area specified by the memory address of the mapped memory element. And a data access device using a memory element.   Each of the specific memory addresses of the first to Nth areas and the first to Nth data stored in the storage area specified by the memory address of the mapped memory element are combined to provide an original 2. The data access device using a memory device according to claim 1, further comprising a data restoring unit for restoring data of M bits.   3. The memory device according to claim 1, wherein the address mapping unit divides the address space of the memory device into N equal parts according to a user setting and defines the first to Nth regions. 4. Data access device using   4. The memory device according to claim 1, wherein each of the specific memory addresses in the first to Nth areas is the memory address located in the same order or in a random order according to a user setting. 5. A data access device using the memory element according to one item. The memory device is an 8-bit memory device,
The case of N = 2, M = 16, N = 3, M = 24, N = 4, and M = 32 is performed in any one of the cases. A data access device using the memory element according to any one of claims 1 to 4.

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