JP6138900B2 - Liquid crystal display - Google Patents

Description

  The present invention relates to a wall electrode type liquid crystal display device, and more particularly to a liquid crystal display device in which a wall structure and a planar distribution of electrodes are optimized.

  Liquid crystal display devices are widely used from small portable terminals to large televisions because of their high display quality and features such as thin and light weight and low power consumption.

  On the other hand, in the liquid crystal display device, viewing angle characteristics are a problem, and in order to realize a wide viewing angle, an IPS (In-Plane Switching) type liquid crystal display device has been proposed. In the IPS system, an image is displayed by controlling the amount of light of the backlight by applying an electric field in a direction parallel to the substrate and rotating the liquid crystal director in the plane of the liquid crystal layer in a homogeneously oriented liquid crystal layer.

  Patent Document 1 has m × n matrix pixels, active elements in the pixels, driving means for applying a predetermined voltage waveform, and electrode pairs in the pixels that keep the gap between the upper and lower substrates constant. In addition, there is disclosed a liquid crystal display device having a predetermined structure capable of controlling the alignment state of liquid crystal molecules and modulating light by applying an electric field parallel to the substrate surface between the electrode pairs (see summary).

  Further, Patent Document 2 includes a pair of substrates at least one of which is transparent and a liquid crystal layer disposed between the pair of substrates, and the substrate surface is disposed on any one of the pair of substrates. A pixel electrode and a common electrode capable of forming an electric field having a main component in a parallel direction are provided, the pixel electrode and the common electrode are provided on a wall having a predetermined height, and the wall is an auxiliary capacitance electrode and the auxiliary capacitance. A lateral electric field drive type liquid crystal electro-optical device comprising an insulator covering an electrode is disclosed (see abstract).

JP-A-6-214244 Japanese Patent Laid-Open No. 9-211477

  A wall electrode type IPS was studied in which an ideal lateral electric field was applied to the liquid crystal layer to achieve a transmittance higher than that of the current IPS method. The height of the wall structure of the wall electrode type IPS is equal to the thickness of the liquid crystal layer, for example, about 4 μm. In the production, the photo process of the transparent electrode (ITO electrode) became a problem. If the slits that serve as the boundary between the two transparent electrodes are distributed both on the top of the wall structure and on the flat part, the thickness of the resist and the focus of the exposure machine at the top and the flat part of the wall structure are collectively processed. The way of matching is different. Therefore, overetching tends to occur at the top of the wall structure, and underetching tends to occur at the flat portion. In order to cope with this, for example, it is conceivable that the slit width on the mask is made narrower than the finished dimension at the top of the wall structure and wider at the flat part. However, if the slit crosses the wall structure, how to determine the slit width in the vicinity of the crossing portion becomes a problem. Even if the mask is completely drawn including the vicinity of the overpass portion, the effect cannot be obtained if misalignment occurs between the wall structure and the electrode. Thus, the wall electrode type IPS has a problem of optimizing the planar structure of the wall structure and the electrodes.

  Patent Document 1 and Patent Document 2 describe a liquid crystal display device having electrodes that are independently controlled on both wall surfaces of the wall structure, but do not describe optimization of the planar distribution of the wall structure and the electrodes. Absent.

  It is an object of the present invention to optimize the wall structure and the planar distribution of electrodes in a wall electrode type IPS and improve the yield.

  In order to solve the above problems, for example, the configuration described in the claims is adopted.

  To give an example of the liquid crystal display device of the present invention, a plurality of pixels are arranged in a matrix, and each pixel is formed on the side wall of the insulator wall structure formed at the pixel boundary and the wall structure at the pixel boundary. And a source electrode composed of a planar electrode continuous with the wall electrode and extending in a planar direction from a position where the wall electrode is in contact with the substrate, and the source electrode on both sides of the pixel, and the plane electrode via the insulating layer. In a liquid crystal display device having a first common electrode that forms a storage capacitor by partially overlapping with an electrode, and a second common electrode provided between wall electrodes on both sides of the pixel, two adjacent electrodes A slit serving as a boundary between pixel wall electrodes is selectively disposed at the top of the wall structure.

  Further, if an example of the method of manufacturing the liquid crystal display device of the present invention is given, a plurality of pixels are arranged in a matrix, and each pixel has an insulator wall structure formed at the pixel boundary and a wall of the pixel boundary. A wall electrode formed from the side surface to the upper surface of the structure, and a source electrode composed of a planar electrode continuous with the wall electrode and extending in a planar direction from a position where the wall electrode is in contact with the substrate, and a source electrode on both sides of the pixel, A liquid crystal display having a first common electrode that forms a storage capacitor by partially overlapping the planar electrode via an insulating layer, and a second common electrode provided between the wall electrodes on both sides of the pixel A method of manufacturing an apparatus, comprising: forming a transparent electrode on the entire surface of the TFT-side substrate on the wall structure; applying a resist on the transparent electrode; and a top of the wall structure Adjacent to A step of exposing the resist to expose the transparent electrode on the wall structure by using a mask that disposes a slit serving as a boundary between the wall electrodes of the two pixels, and the transparent electrode on the exposed wall structure. Forming a wall electrode in which a slit serving as a boundary between the wall electrodes of two pixels adjacent to the top of the wall structure is disposed.

  In another example of the method for manufacturing a liquid crystal display device according to the present invention, a plurality of pixels are arranged in a matrix, and each pixel includes an insulator wall structure formed at a pixel boundary and the pixel boundary. A wall electrode formed on a side surface of the wall structure, and a source electrode composed of a planar electrode continuous with the wall electrode and extending in a planar direction from a position where the wall electrode is in contact with the substrate, and a source electrode on both sides of the pixel, A liquid crystal display having a first common electrode that forms a storage capacitor by partially overlapping the planar electrode via an insulating layer, and a second common electrode provided between the wall electrodes on both sides of the pixel A method of manufacturing an apparatus, comprising: forming a transparent electrode on the entire surface of the TFT-side substrate on the wall structure; applying a resist on the transparent electrode; and ashing the resist about More, the method comprising exposing the transparent electrode on the wall structure, by removing the transparent electrode on the exposed wall structure, is intended to include a step of forming a wall electrode on the side surfaces of the wall structure.

  According to the present invention, the height of the portion where the slit serving as the boundary between the transparent electrodes of two adjacent pixels is constant, the processing conditions are uniquely determined, and the yield of the wall electrode type IPS is improved. . And the wall electrode system IPS of the transmittance | permeability exceeding the present IPS system can be supplied stably.

It is a figure which shows the planar structure of the pixel of the liquid crystal display device of Example 1 of this invention. It is a figure which shows the cross-section of the pixel of the liquid crystal display device of Example 1 of this invention. It is a figure which shows the equipotential surface formed between the common electrode and source electrode of Example 1 of this invention. It is a figure explaining the method of patterning the source electrode of a wall structure top part. It is a figure which shows the planar structure of the pixel of the liquid crystal display device of Example 2 of this invention. It is a figure which shows the planar structure of the pixel of the liquid crystal display device of Example 3 of this invention. It is a figure which shows the cross-section of the pixel of the liquid crystal display device of Example 3 of this invention. It is a figure explaining the patterning by the mask exposure of Example 3 of this invention. 6 is a diagram illustrating a planar structure of a pixel of a liquid crystal display device of Comparative Example 1. FIG. It is a figure explaining the case where a slit distributes continuously between a wall structure top part and a flat part. It is a figure explaining the patterning by the mask exposure of the comparative example 1. FIG. It is a figure explaining the patterning by the mask exposure of the comparative example 2. FIG. It is a figure explaining the patterning by the mask exposure of the comparative example 2. FIG. It is a figure which shows an example of the equalization circuit of the liquid crystal display device with which this invention is applied.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.

  First, FIG. 14 shows an example of an equivalent circuit of a liquid crystal display device to which the present invention is applied. A scanning line 104 and a signal line 103 are wired in a matrix on the substrate 102, and a pixel 106 is connected to each intersection of the scanning line 104 and the signal line 103 via a TFT (Thin Film Transistor) element 110. A scanning driving circuit 108 and a signal driving circuit 107 are connected to the scanning line 104 and the signal line 103, respectively, and a voltage is applied to the scanning line 104 and the signal line 103. A common line 105 is disposed on the substrate 102 in parallel with the signal line 103 so that a common voltage can be applied to all pixels from a common voltage generation circuit 109. A liquid crystal composition is sealed between the substrate 102 and the substrate 101 to constitute a liquid crystal display device as a whole.

  FIG. 1 shows a planar structure of one pixel according to Embodiment 1 of the present invention, and FIG. 2 shows a sectional structure of one pixel. FIG. 1 includes an entire pixel and a part of a pixel adjacent to the pixel. FIG. 2 shows a cross-sectional structure of the A-A ′ plane of FIG. 1.

  In FIG. 2, the signal wiring 15 and the first common electrode 12 are disposed on the first substrate 20 via the first insulating layer 21, and the second insulating layer 22 is formed thereon. An insulating wall structure 10 is provided at the pixel boundary on both sides of the pixel. The wall structure is formed of, for example, an organic film. A wall electrode 111 is formed on the side surface of the wall structure 10 arranged on both sides of the pixel, and a planar electrode 112 extending in a planar direction from a position where the wall electrode is in contact with the substrate is formed continuously with the wall electrode. In the present embodiment, the wall electrode 111 and the planar electrode 112 form one source electrode 11. The first common electrode 12 and the planar electrode 112 of the source electrode 11 partially overlap with each other via the second insulating layer 22, and the overlapped portion forms a storage capacitor. A third insulating layer 23 is provided on the upper layer of the source electrode 11, and is disposed on the third insulating layer 23 between the wall electrodes 111 of both source electrodes 11 provided on the wall structure 10. An electrode 13 is disposed. A first alignment film 24 is formed to cover the second common electrode 13 and the wall structure 10. A first polarizing plate 25 is formed on the opposite side of the first substrate 20. And these constitute a TFT side substrate.

On the other hand, a black matrix (BM) 31, a color filter (CF) 32, and a protective film (OC: Over Coat) 33 are formed on the second substrate 30. Then, the third common electrode 14 is disposed between the source electrodes 11 provided on the wall structure on the protective film 33, and the second alignment film 34 is formed, whereby the CF side substrate is configured. The
Then, the TFT side substrate and the CF side substrate are bonded together, and a liquid crystal layer 28 containing liquid crystal molecules 29 is sealed between the two substrates.

  In FIG. 1, the wall structure 10 is arranged in the longitudinal direction on both sides of the pixel as indicated by a one-dot chain line. And the signal wiring 15 is arrange | positioned along the wall structure 10, and the gate wiring 16 is arrange | positioned so that this may be crossed. A source electrode 11 is disposed on the side surface of the wall structure 10, and a first common electrode 12, a second common electrode 13, and a third common electrode 14 are disposed between the source electrodes. The overlapping portion of the first common electrode 12 and the source electrode 11 is indicated by hatching. The overlapping portion of the first common electrode 12 and the source electrode 11 functions as a storage capacitor. A polysilicon layer 17 is disposed on the gate wiring 16 to constitute a TFT. Reference numeral 17 denotes a first contact hole, and reference numeral 18 denotes a second contact hole.

  In the present embodiment, as shown in FIG. 2, the wall structure 10 is distributed under the BM 31 forming the pixel boundary, and has the source electrode 11 on both wall surfaces of the wall structure 10. The source electrodes 11 on both wall surfaces are separated by the slit 26 at the top of the wall structure, and the source electrodes 11 on both wall surfaces belong to different pixels. As shown in FIG. 1, the wall structure 10 overlaps with a slit separating the source electrode 11 and is distributed longer than the slit. As a result, the slit is located only at the top of the wall structure.

  FIG. 3 is a schematic diagram in which the equipotential surface 36 formed between the common electrode and the source electrode in FIG. A third common electrode 14 and a second common electrode 13 are arranged to face the upper and lower substrates in the center of the pixel, and further, the first common electrode 12 is arranged therebelow. As shown by a broken line in FIG. 3, a part of the equipotential surface 36 is formed so as to surround the third common electrode 14 and the second common electrode 13. The common electrode 13 exhibits properties like a wall electrode. Since the source electrode 11 is arranged on the top of the wall structure on both sides of the pixel and the pair of common electrodes 13 and 14 are arranged in the center of the pixel, the effective distance between the wall electrodes is half the pixel width. For example, the pixel width is 30 μm. Even in this case, it is possible to drive with the same voltage as the conventional IPS-Pro system.

  The planar shape of the pixel is an open V shape as shown in FIG. 1, and the wall structure 10 is inclined to the left in the upper half of the pixel, and is inclined to the right in the lower half of the pixel. The liquid crystal alignment direction AD is the vertical direction, and the liquid crystal director rotates clockwise when a voltage is applied in the upper half of the pixel, and rotates counterclockwise in the lower half. In both the upper half and the lower half of the pixel, the angle formed by the extension direction of the wall structure 10 and the liquid crystal alignment direction AD is 5 degrees. This is a multi-domain structure in which two portions having different liquid crystal alignments are formed in one pixel, and the viewing angle dependence of the coloring of each domain is offset, so that a more uncolored viewing angle characteristic can be obtained. The wall surface of the wall structure 10 has an inclination angle of about 85 degrees, and the photo-alignment method is suitable for performing an alignment treatment on the wall surface having such a steep inclination angle. Here, the liquid crystal director is an average alignment direction of liquid crystal molecules in a minute region in the liquid crystal layer.

  Further, as shown in FIG. 1, the wall structure 10 has a planar distribution cut off at the pixel end. For example, when the liquid crystal layer is formed by a vacuum sealing method, the liquid crystal mainly flows along the wall structure 10. Since it is possible to move to the adjacent wall structure at the cut portion of the wall structure, it becomes easy to form a liquid crystal layer by a vacuum sealing method.

  FIG. 4A is a cross-sectional view of a state in which a resist 41 is applied when patterning the source electrode 11 at the top of the wall structure 10. The resist 41 is thinner at the top of the wall structure and thicker at the flat portion. Yes. Such a resist thickness distribution is caused by the resist flowing from the top of the wall structure to the wall structure after coating on the wall structure having a height equal to or higher than the liquid crystal layer thickness. The resist generally has such fluidity because it enables easy film formation by means such as spin coating or printing.

  Although the source electrode 11 has a boundary other than the slit 26, the electrode of the adjacent pixel is not adjacent to the boundary other than the slit, so that the accuracy of the photo process is not strictly required. Since it is a slit that causes a fatal defect such as a short circuit with an adjacent electrode, the processing of the slit is particularly important in the photo process of the source electrode. In the case of the present embodiment, the slit distribution is limited to the top of the wall structure. Therefore, if the slit processing conditions are optimized according to the thin resist, the slit can be processed with a high yield. Further, since the distribution in the thickness direction of the slit is also limited to the top of the wall structure, even when an exposure apparatus having a shallow depth of focus is used, the slit can be processed with a high yield by focusing on the top of the wall structure.

  FIG. 5 shows a planar structure of one pixel according to the second embodiment of the present invention. In the first embodiment, the wall structure 10 is cut off at the pixel end as shown in FIG. 1, but in this embodiment, it is continuous at the pixel end as shown in FIG. Therefore, the wall structure 10 distributed in one pixel is longer than that in the first embodiment. Thereby, the source electrode 11 can also be formed longer in the pixel long side direction. Higher transmittance can be obtained by increasing the aperture ratio by increasing the transparent portion in the pixel.

  In this embodiment, since the wall structure is continuous at the pixel end, the slits are distributed only at the top of the wall structure even if the source electrode is formed longer in the long side direction of the pixel. Therefore, it is possible to process the slits with a high yield as in the first embodiment.

  FIG. 6 shows a planar structure of one pixel according to Embodiment 3 of the present invention, and FIG. 7 shows a sectional structure of one pixel. As shown in FIG. 6, the width of the wall structure 10 is narrower than that of FIG. 1, and the boundary between the source electrode 11 and the wall structure 10 coincides. As shown in FIG. 7, the source electrode 11 is distributed only on the wall surface of the wall structure 10 and is not distributed on the top of the wall structure 10. The wall electrode structure as shown in FIGS. 6 and 7 can be realized by forming a slit at the top of the wall structure by a self-alignment process described below.

  As shown in FIG. 4A, the resist 41 tends to be thin at the top of the wall structure 10 and thick at the flat portion. If ashing is performed using a plasma asher, the resist 41 is uniformly removed from the surface in proportion to time as shown in FIG. The broken line in FIG. 4B is the resist surface at the time of application. Therefore, if the resist is removed by an amount slightly exceeding the thickness of the top of the wall structure, the electrode 11 at the top of the wall structure is selectively exposed as shown in FIG. If etching is performed in this state, the electrode on the wall electrode can be selectively removed as shown in FIG. 4D, and FIG. 4E shows a completed state in which the resist 41 is removed from FIG. Thus, if the film thickness distribution of the resist applied on the wall structure is used, the electrode on the wall structure can be removed by self-alignment.

  Parts other than the wall electrode need to be patterned by mask exposure separately, which is affected by the alignment accuracy of the wall structure and the mask. However, if the slits are distributed only at the top of the wall structure, no short circuit occurs as described below. FIG. 8 is a plan view paying attention to one wall structure and an electrode superimposed on the wall structure. The wall structure has a boundary indicated by a bold line, and the electrode is hatched by a hatched line. FIG. 8A shows a state in which electrodes are formed on the entire surface. Next, as shown in FIG. 8B, the electrodes at the top of the wall structure are removed by the self-alignment process described above. Next, as shown in FIG. 8C and FIG. 8D, the electrodes other than the top of the wall structure are patterned using mask exposure. FIG. 8C shows a state in which the mask is superimposed on FIG. 8B, and a broken line in FIG. 8C is a light shielding portion boundary of the mask. FIG. 8D shows a wall electrode structure finally formed with the mask arrangement shown in FIG. 8C. The wall electrode has a plane distribution similar to the light shielding portion boundary of the mask shown in FIG. It has become. At this time, there is a possibility that misalignment of the mask may occur. However, if the length of the portion of the wall structure protruding from the slit exceeds the alignment accuracy of the mask, a short circuit occurs even if misalignment of the mask occurs. There is nothing.

  Further, by applying the self-alignment process, it is not necessary to design the likelihood in consideration of the mask alignment accuracy at the slit portion, and the width of the wall structure can be reduced to a width determined by the processing accuracy. For example, if the mask alignment accuracy is 1.5 μm with respect to the reference layer and the slit width is 3.0 μm, the width of the wall structure is required to stably form electrodes on both wall surfaces of the wall structure. Must be 9.0 μm. On the other hand, since the processing accuracy of the wall structure is, for example, 4.0 μm, the width of the wall structure can be reduced to half or less by using the self-alignment process. As a result, the aperture ratio can be increased and higher transmittance can be realized.

Comparative Example 1

  FIG. 9 shows a planar structure of one pixel in the first comparative example. In Example 1, the slits are distributed only at the top of the wall structure, but as shown in FIG. 9, the slits 26 are distributed at both the top of the wall structure 10 and the flat part. In FIG. 9, since the slits are continuously distributed between the top portion and the flat portion of the wall structure, the slits 26 are distributed across the boundary of the wall structure. 10A and 10B show a cross section in a state where a resist 41 is applied when forming a slit in the source electrode 11. FIGS. 10A and 10B are cross-sectional views of the top portion and the flat portion of the wall structure, respectively, and correspond to the dashed lines A-A ′ and B-B ′ of the plan view shown in FIG. 9. In FIGS. 10A and 10B, an effective resist film thickness is indicated by an arrow in slit formation. Similar to FIG. 4, the resist 41 is thin in FIG. 10A corresponding to the top of the wall structure, and the resist 41 is thick in FIG. 10B corresponding to the flat portion. Therefore, the top of the wall structure tends to be over-etched and the flat portion tends to be under-etched.

  In order to collectively process the slits at the top of the wall structure and the flat portion with the same width, it is conceivable to change the slit width on the mask as shown in FIG. FIG. 11A shows the relationship between the slit width on the mask and the wall structure, and it is assumed that there is no misalignment of the mask. FIG. 11B shows a completed state corresponding to FIG. As shown in FIG. 11 (a), the slit width on the mask may be narrower than the completed dimension at the top of the wall structure and wider at the flat part. Here, how to determine the slit width of the overpass portion is a problem. For this, the resist thickness distribution in the vicinity of the overpass portion is helpful. FIG. 10C is a cross-sectional view including the vicinity of the overpass portion, and corresponds to the one-dot chain line C-C ′ in FIG. 9. FIG. 10D is a diagram in which the resist thickness distribution is obtained from FIG. 10C, and the resist thickness becomes maximum at the flat portion adjacent to the overpass portion. For example, the slit width may be changed continuously so as to correspond to the resist thickness distribution before and after the overpass portion. Specifically, as shown in FIG. Maximize and continuously reduce the slit width in the direction of the wall structure. As a result, as shown in FIG. 11 (b), slits can be formed collectively at both the top and the flat portion of the wall structure, and slits should be formed at the overpass.

  However, in reality, an example has been found in which the slit shape at the time of completion is greatly different from that in FIG. An example of these is shown in FIG. In the overetched portion 43 in FIG. 11 (d), the slit width is greatly increased near the overpass portion, and in the underetched portion 44 in FIG. 11 (d), the slit disappears in the vicinity of the overpass portion. In particular, in the underetched portion 44, the source electrodes of two adjacent pixels are short-circuited, resulting in a point defect. The slit shape shown in FIG. 11D is generated when the mask for slit processing is shifted downward as shown in FIG. 11C with respect to the wall structure. In FIG. 11C, the boundary of the mask light shielding portion is indicated by a broken line. The overetched portion 43 in FIG. 11D is caused by overetching because the portion with the widest slit width on the mask is located on the upper portion of the wall electrode with a thin resist film thickness. The under-etched portion 44 in FIG. 11D is caused by under-etching because the portion with a narrow slit width on the mask is located in a flat portion close to the overpass portion where the resist film thickness is thick.

  As described above, when a wall structure having a height equivalent to the thickness of the liquid crystal layer is present, slits distributed over the wall structure cannot be collectively processed with a high yield in consideration of the alignment accuracy of the mask. Even if the slit width on the mask is changed to correspond to the resist thickness distribution, the misalignment of the mask is larger than the range in which the slit width fluctuates, so the resist film thickness change cannot be corrected as designed. is there.

  In the liquid crystal display device according to the first embodiment of the present invention, the resist is exposed by using a mask in which slits 26 serving as boundaries between the wall electrodes 111 of two pixels adjacent to only the top of the wall structure 10 are distributed, By exposing the transparent electrode on the structure and removing the transparent electrode on the exposed wall structure, the wall electrode in which slits 26 serving as the boundary between the wall electrodes 111 of two pixels adjacent to only the top of the wall structure 10 are distributed. Can be formed.

Comparative Example 2

  The self-alignment process of Example 3 is applied to a structure in which slits are distributed on both the top and the flat part of the wall structure. As described in the third embodiment, the advantage of the self-alignment process is that the aperture ratio can be increased by reducing the width of the wall structure to the processing accuracy of the wall structure. In this case, the slit in the flat portion is formed by mask exposure, but a short circuit may occur depending on the alignment accuracy of the mask. FIG. 12 is a plan view paying attention to one wall structure and an electrode overlapping therewith, FIG. 12A shows a state in which an electrode is formed on the entire surface including the wall structure, and FIG. 12B shows self-alignment. The top of the wall structure is selectively etched by the process. FIG. 12C shows a state in which the mask is superimposed on FIG. 12B, and when there is no misalignment as shown in FIG. 12C, it is flat without short-circuiting as shown in FIG. Part slits can be formed. However, when misalignment occurs in the vertical direction as shown in FIG. 12E, the slit disappears in either one of the upper and lower flat portions of the wall structure as shown in FIG. The source electrode of the pixel is short-circuited.

  As a countermeasure against misalignment, it is conceivable to extend a slit formed by mask exposure from a flat portion to a part of the top of the wall structure. FIG. 13A shows a state in which such a mask is superimposed on FIG. 12B. If there is no misalignment as shown in FIG. 13B, overetching or underetching does not occur even in this case. A source electrode can be formed. However, when the mask misalignment occurs in the vertical direction as shown in FIG. 13C, overetched portions 43 are generated at the upper and lower ends of the wall structure as shown in FIG. The electrode disappears from the wall. In the portion where the electrode disappears from the wall surface, the electric field strength applied to the liquid crystal layer is lowered, and thus the transmittance is lowered. The advantage of the self-alignment process is that the width of the wall structure can be reduced to the processing accuracy of the wall structure. In this case, the width of the wall structure is almost the same as the mask width for forming the slit in the flat part where the resist film is thick. Become. Therefore, when the mask misalignment occurs, the ITO film on the wall surface is etched, and the electrode disappears from the wall surface.

  In this way, when a wall structure having a height equivalent to the liquid crystal layer thickness exists, if the mask alignment accuracy is taken into consideration, slits distributed over the wall structure are processed with a high yield even if the self-alignment process is used. I can't do that.

10 Wall Structure 11 Source Electrode 12 First Common Electrode 13 Second Common Electrode 14 Third Common Electrode 15 Signal Wiring 16 Gate Wiring 17 Polysilicon Layer 18 First Contact Hole 19 Second Contact Hole 20 First Substrate 21 First insulating layer 22 Second insulating layer 23 Third insulating layer 24 First alignment film 25 First polarizing plate 26 Slit 28 Liquid crystal layer 29 Liquid crystal molecule 30 Second substrate 31 Black matrix BM32 Color filter CF33 Overcoat layer 34 Second alignment film 35 Second polarizing plate 36 Equipotential surface 41 Resist 43 Overetched portion 44 Underetched portion 101 Substrate 102 Substrate 103 Signal line 104 Scan line 105 Common line 106 Pixel 107 Signal drive circuit 108 Scan driving circuit 109 Common voltage generating circuit 1 10 TFT element

Claims (7)

A plurality of pixels are arranged in a matrix, and each pixel has a wall structure of an insulator formed at a pixel boundary, a wall electrode formed on a side surface of the wall structure of the pixel boundary, and a wall wall continuous with the wall electrode. A source electrode composed of a planar electrode extending in a planar direction from a position where the electrode is in contact with the first substrate, a wall electrode formed on both sides of the pixel, and the wall electrode are provided between the planar electrode and an insulating layer. In a liquid crystal display device having a first common electrode that forms a storage capacitor by overlapping portions, and a second common electrode provided between the source electrode and the source electrode formed on both sides of the pixel,
The top of the wall structure has a portion in contact with a portion of the second substrate facing the first substrate,
A signal voltage is applied to the source electrode, a common voltage is applied to the first common electrode and the second common electrode,
A liquid crystal display device, wherein a slit which becomes a boundary between wall electrodes of two adjacent pixels is selectively arranged at the top of the wall structure. The liquid crystal display device according to claim 1.
The liquid crystal display device, wherein the wall electrode is formed up to an upper surface of a wall structure at the pixel boundary. The liquid crystal display device according to claim 1.
The liquid crystal display device, wherein the wall electrode is formed only on a side surface of the wall structure at the pixel boundary. The liquid crystal display device according to claim 1,
2. The liquid crystal display device according to claim 1, wherein the wall structure is cut off at an end portion in the longitudinal direction of the pixel, and the wall electrode of the source electrode is formed inside the end portion of the wall structure. The liquid crystal display device according to claim 1,
The liquid crystal display device, wherein the wall structure is continuous at an end portion in a longitudinal direction of a pixel. In the liquid crystal display device according to any one of claims 1 to 5,
A liquid crystal display device comprising a third common electrode on a color filter side substrate between source electrodes on both sides of the pixel. In the liquid crystal display device according to any one of claims 1 to 6,
The pixel has a V-shaped shape, the liquid crystal alignment direction is constant in the pixel, and the angle between the extension direction of the wall structure and the liquid crystal alignment direction is equal between one and the other in the pixel. The liquid crystal display device according to claim 1, wherein the extending direction of the wall structure is inclined in opposite directions with respect to the liquid crystal alignment direction between one and the other.

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