JP6132478B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device applicable to a vertical-structure diode, a field effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), and the like.

  Conventionally, for example, in a semiconductor device having a vertical structure, a termination region having a withstand voltage holding structure has been formed on the outer peripheral portion in plan view of the semiconductor substrate in order to ensure the off-withstand voltage of the device. Various types of breakdown voltage holding structures have been disclosed, and guard ring structures, RESURF (Reduced Surface Field) structures, and the like are well known.

  For example, a semiconductor device having an n-type drift layer in a semiconductor chip body includes a termination region having a p-type breakdown voltage holding structure for holding an off breakdown voltage in the drift layer.

  When a high voltage is applied to the semiconductor device, the depletion layer spreads from the pn junction between the n-type drift layer and the p-type withstand voltage holding structure, so that the electric field concentration at the edge of the active region is alleviated. The off-breakdown voltage of the device is maintained.

  For example, Patent Document 1 discloses a semiconductor device further including a p-type stopper region formed so as to surround the breakdown voltage holding structure in plan view, in addition to the breakdown voltage holding structure in which the guard ring structure and the low impurity concentration RESURF structure are combined. Is disclosed. Here, the p-type stopper region is formed in the drift layer at the end of the semiconductor chip body for the purpose of fixing the potential, and is formed in the same manner as the guard ring structure. Further, the p-type stopper region is not always necessary.

JP-A-8-306937

  The semiconductor device having the termination region as described above can reduce the electric field strength inside the device by the breakdown voltage holding structure in the termination region. However, a desired breakdown voltage may not be obtained due to electric field concentration outside the device including the end portion of the semiconductor chip body. Specific examples in which the semiconductor device cannot obtain a desired breakdown voltage include a case where a sealing material outside the device is destroyed by a high electric field, and a creeping discharge occurs during a chip test.

  In order to reduce the electric field strength at the end of the semiconductor chip body, the ineffective area that is the area from the outer periphery of the termination region to the end of the semiconductor chip body is formed as long as possible, that is, from the termination region to the end of the semiconductor chip body. One effective method is to make the distance as long as possible.

  However, if the ineffective area is formed long as described above, the area of the chip body used in the semiconductor device becomes excessively large, and the number of semiconductor devices that can be manufactured from one semiconductor wafer is reduced. Therefore, there is a problem that the cost of the semiconductor device is increased.

  The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device capable of realizing a high breakdown voltage without increasing the chip area.

A semiconductor device according to an aspect of the present invention includes an active region provided in a first conductivity type semiconductor chip body, and a second conductivity type breakdown voltage formed on the surface of the semiconductor chip body, surrounding the active region in plan view. The semiconductor chip body having a holding structure and a high resistance region formed on the surface of the end portion of the semiconductor chip body so as to be separated from the withstand voltage holding structure and to reach the end surface of the semiconductor chip body. surface, depleted when a voltage is applied, the high resistance region, characterized in semiconductor regions der Rukoto of the second conductivity type is a lower concentration than the breakdown voltage holding structure.

  According to the above aspect of the present invention, the first conductivity type layer and the second conductivity type are provided on the surface of the end portion of the semiconductor chip body by providing the high resistance region formed away from the breakdown voltage holding structure. A depletion layer spreads from the junction with the layer, and a depletion region including the range up to the end of the semiconductor chip body can be formed.

  Since a relatively gentle electric field is formed in the depletion region, an abrupt potential difference is unlikely to occur at the end of the chip body, and electric field concentration at the end of the chip body can be suppressed. By suppressing the electric field concentration at the end of the chip body, a high breakdown voltage semiconductor device can be obtained without increasing the chip area.

It is principal part sectional drawing which shows the structure of the semiconductor device (Schottky diode) regarding embodiment of this invention. It is principal part sectional drawing which shows the structure of the semiconductor device (MOSFET) regarding embodiment of this invention. It is principal part sectional drawing which shows the structure of the semiconductor device in which the n ⁺ area ^| region was formed. It is principal part sectional drawing which shows the structure of the semiconductor device regarding embodiment of this invention. It is principal part sectional drawing which shows a different structure of the semiconductor device of embodiment of this invention. It is principal part sectional drawing which shows the structure of the semiconductor device in which the n ⁺ area ^| region was formed. It is principal part sectional drawing which showed the structure of the semiconductor device regarding the premise technique of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

  First, the structure of a semiconductor device having an n-type drift layer will be described as a prerequisite technique of the present invention.

  FIG. 7 is a cross-sectional view of a principal part showing the structure of a semiconductor device having an n-type drift layer related to the prerequisite technology of the present invention.

As shown in FIG. 7, the semiconductor device having the n-type n ⁻ drift layer 1 includes a termination region having a p-type breakdown voltage holding structure 2 for holding an off breakdown voltage.

The termination region is formed surrounding the active region in plan view. The termination region is formed so as to be surrounded by the invalid region in plan view. A metal electrode 3 is formed on the n ⁻ drift layer 1 in the active region.

When a high voltage is applied to the semiconductor device, the depletion layer extending from the pn junction between the n ⁻ drift layer 1 and the breakdown voltage holding structure 2 reduces the electric field concentration at the end of the active region, and the semiconductor device is turned off. The breakdown voltage is maintained.

However, in the above semiconductor device may withstand is not obtained by the electric field concentration at the instrumentation置外unit. Although it is conceivable to form the ineffective region as long as possible as a method of reducing the electric field strength of the chip body end portion 9, there is a problem that the chip area becomes excessively large, resulting in high cost. .

  In the following embodiments of the present invention, a semiconductor device that realizes a high breakdown voltage without increasing the chip area that solves the above-described problems will be described.

<First Embodiment>
<Configuration>
Embodiments of the invention are described below. In the following description, the first conductivity type is n-type and the second conductivity type is p-type. 4H—SiC or the like is used for the semiconductor substrate. Examples of the impurity forming the n-type region include nitrogen and phosphorus, and examples of the impurity forming the p-type impurity include boron and aluminum.

  FIG. 1 is a cross-sectional view of the main part showing the configuration of the semiconductor device according to the first embodiment of the present invention. As an example of the high voltage semiconductor device, a vertical structure Schottky diode is cited.

In the Schottky diode shown in FIG. 1, a metal electrode 3 serving as a Schottky junction is formed in a region corresponding to an active region on the main surface of an n ⁻ drift layer 1 formed on a semiconductor substrate (not shown). .

  The Schottky diode is formed with a termination region having a p-type breakdown voltage holding structure 2 such as a guard ring surrounding the active region in plan view. The termination region is formed in advance before the metal electrode 3 is formed.

  By forming the metal electrode 3 so as to overlap the termination region, local electric field concentration is suppressed and the breakdown voltage of the device is maintained.

In the ineffective region formed so as to further surround the termination region in plan view of the semiconductor device shown in the present embodiment, the p ⁻ region 4 as a high resistance region is formed. The p ⁻ region 4 is formed on the surface of the end portion 9 of the chip body, and is formed away from the breakdown voltage holding structure 2 in the termination region. The p ⁻ region 4 is a p-type region having a lower concentration than the p-type region formed as the breakdown voltage holding structure 2 and has a higher resistance than the breakdown voltage holding structure 2.

When the p ⁻ region 4 is formed at the chip body end 9, a depletion layer extends from the pn junction between the breakdown voltage holding structure 2 and the n ⁻ drift layer 1 to the inside of the p ⁻ region 4. A depletion region including the range up to is formed.

At this time, since the p ⁻ region 4 has a lower concentration than the breakdown voltage holding structure 2, the depletion layer sufficiently extends to the chip body end portion 9, and the potential change at the chip body end portion 9 becomes comparatively gentle. Therefore, it is possible to suppress electric field concentration at the chip body end portion 9.

  In this way, by suppressing the concentration of the electric field on the end portion 9 of the chip body, it is possible to suppress the breakdown of the sealing material due to the high electric field and the decrease in breakdown voltage due to the occurrence of creeping discharge during the chip test. Can be obtained.

Furthermore, in the case of attempt to include in the depletion region to the surface of the chip body end portion 9, p of the chip body end portion 9 ^- concentration in the region 4 and p ^- relationship deep region 4 is formed of the following Can be requested.

When a pn junction is formed such that the p ⁻ region 4 formed at the chip body end portion 9 and the n ⁻ drift layer 1 form a step junction, the depletion layer width W extending from the pn junction is expressed by the following equation (1): It is represented by

The ratio of the width of the depletion layer spreading in the direction of the drift layer 1, epsilon _s is the semiconductor material ^- Here, x _p is p from the pn junction ^- region 4 inside the depletion layer width extending in a direction, x _n is n from the pn junction dielectric constant, q is the elementary charge, _{n a} p ^- density region 4, the _{n d} n ^- concentration of the drift layer _1, is _{V bi} is a built-in potential (built-in potential). Here, as shown in Equation (2),

Therefore, the depletion layer width (x _p , x _n ) extending from the pn junction to the p ⁻ region 4 and the n ⁻ drift layer 1 is expressed by the following equation (3):

It becomes. From equation (3), p ^- the lower the concentration _{N a} region 4, p from the pn junction ^- depletion width _{x p} spanning region 4 internal direction is can be seen that large.

When a silicon carbide semiconductor is used as a semiconductor material, V _bi is expected to be about several volts, and there is almost no potential difference in the vicinity of the chip body end 9 even when a voltage is applied. Regardless of the size, the depletion layer width W is substantially constant. Therefore, when the surface of the chip body end 9 is to be included in the depletion region, the depth of the pn junction, that is, the distance from the surface of the chip body end 9 to the pn junction is expressed by the equation (3). as will be less than the value of x _p, p ^- it may be adjusted and the density and form the depth of the region 4.

The depletion layer width x _p extending in the p ⁻ region 4 is 4 × H ¹⁶ , when the concentration of the n ⁻ drift layer 1 is 1 × 9 ¹⁶ cm ⁻³ and the concentration of the p ⁻ region 4 is 1 × 9 ¹⁶ cm ⁻³ . When the depletion region is formed up to the surface of the end portion 9 of the chip body, the pn between the p ⁻ region 4 and the n ⁻ drift layer 1 is about 0.6 μm at about 0.4 μm and 5 × 9 ¹⁵ cm ^−3. What is necessary is just to form the position of a junction part (boundary surface) shallower than these.

p ^- the density of the region 4 becomes lower, a pn junction p ^- from the pn junction instead larger depletion layer width x _p spread inside the area 4 n ^- depletion width x _n spreading drift layer 1 is small composed are similar, but the effect of electric field concentration inhibition by the depletion layer width x _p becomes large, larger than the effect due to the depletion layer width x _n increases, p ^- density of region 4 is as low as possible is better .

Further, the p ⁻ region 4 may be formed at least on the surface of the chip body end portion 9. However, in consideration of the dicing position accuracy when the semiconductor wafer is obtained by dicing the semiconductor wafer, the p ⁻ region 4 is scheduled to be diced. It is desirable that the film is formed on the position and about 20 μm inside of the regions to be the semiconductor chip bodies on both sides across the dicing planned position.

In the above description, the case where the p ⁻ region 4 and the n ⁻ drift layer 1 form a step junction has been described, but the present invention can be used regardless of the concentration profile of the p ⁻ region 4.

In the above description, the p ⁻ region 4 has a lower concentration than the breakdown voltage holding structure 2 such as a guard ring, but is preferably formed in a separate process from the breakdown voltage holding structure 2. However, the resist thickness is appropriately controlled, and at the same time as the step of forming the p-type region of the breakdown voltage holding structure 2, an impurity or the like for forming the p-type region is implanted through the resist, thereby reducing the effective implantation amount. May be.

  Further, the present invention has a particularly remarkable effect when the semiconductor substrate is silicon carbide, but the effect can also be obtained with other semiconductor substrates such as silicon.

<Effect>
According to the embodiment of the present invention, the semiconductor device includes an active region provided in the n ⁻ drift layer 1 of the first conductivity type semiconductor chip body, the active region surrounded in plan view, and on the surface of the n ⁻ drift layer 1. The formed second conductivity type withstand voltage holding structure 2 and the p ⁻ region 4 as a high resistance region formed on the surface of the chip main body end portion 9 so as to be separated from the withstand voltage holding structure 2 are provided. Here, the surface of the semiconductor chip body on which the p ⁻ region 4 as the high resistance region is formed is depleted when a voltage is applied.

According to such a semiconductor device, the depletion layer extends from the pn junction between the breakdown voltage holding structure 2 and the n ⁻ drift layer 1 to the inside of the p ⁻ region 4, including the range up to the end 9 of the chip body. It can be a depletion region.

  Since a relatively gentle electric field is formed in the depletion region, an abrupt potential difference is unlikely to occur at the chip body end 9, and electric field concentration at the chip body end 9 can be suppressed. By suppressing the electric field concentration at the end 9 of the chip main body, it is possible to suppress the breakdown of the sealing material due to the high electric field and the decrease in the breakdown voltage due to the occurrence of creeping discharge during the chip test. A semiconductor device can be obtained.

In addition, since the p ⁻ region 4 as the high resistance region is formed away from the breakdown voltage holding structure 2, the depletion layer extends to the end portion 9 of the chip body, and the electric field strength can be reduced. can get.

Second Embodiment
<Configuration>
FIG. 2 is a fragmentary cross-sectional view showing the configuration of the semiconductor device according to the second embodiment of the present invention. As an example of the high voltage semiconductor device, a MOSFET having a vertical structure is cited. The same components as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted.

In the MOSFET shown in FIG. 2, a plurality of p-type well regions 5 as p-type regions are separated from each other on the surface corresponding to the active region of the main surface of the n ⁻ drift layer 1 formed on a semiconductor substrate (not shown). Is formed. On the surface of the p-type well region 5, an n ⁺ source region 6 which is a high-concentration n-type region is selectively formed.

Further, a gate electrode 7 is formed on the n ⁻ drift layer 1 so as to straddle the separated p-type well region 5, and further covers the gate insulating film covering the gate electrode 7 and the p-type well region 5, and the metal electrode 3. Is formed.

  In addition, a termination region having a p-type breakdown voltage holding structure 2 such as a guard ring is formed in the MOSFET so as to surround the active region in plan view. The metal electrode 3 is formed so as to overlap with the termination region.

Further, a p ⁻ region 4 is formed in the invalid region surrounding the terminal region in plan view. The p ⁻ region 4 is formed on the surface of the end portion 9 of the chip body, and is formed away from the breakdown voltage holding structure 2 in the termination region. The p ⁻ region 4 is a p-type region having a lower concentration than the p-type region formed as the breakdown voltage holding structure 2 and has a higher resistance than the breakdown voltage holding structure 2.

When the MOSFET is turned on, carriers flow from the n ⁻ drift layer 1 to the n ⁺ source region 6 through the vicinity of the surface of the p-type well region 5.

When the MOSFET is turned off, a depletion layer extends from the p-type well region 5 to the n ⁻ drift layer 1 to maintain a breakdown voltage. When the surface of the chip body end portion 9 is to be included in the depletion region, the concentration and formation depth of the p ⁻ region 4 may be adjusted as in the first embodiment.

When a MOSFET is formed, a plurality of p-type regions such as a p-type well region 5 and ap ⁺ region (not shown) for making ohmic contact are often formed. The breakdown voltage holding structure 2 having the same or lower concentration is formed.

In the MOSFET, an n ⁺ region may be formed near the end 9 of the chip body at the same time as the source forming step as a channel stopper region.

FIG. 3 is a fragmentary cross-sectional view showing the configuration of the semiconductor device in which the n ⁺ region 8 as the channel stopper region is formed.

As shown in FIG. 3, n ⁺ region 8 of the first conductivity type is n corresponds to the invalid region so as not to tip body end portion 9 ^- by being formed in the drift layer 1 surface, n ⁺ region 8 Thus, it is possible to obtain a semiconductor device that has the effect of reducing the electric field strength at the end portion 9 of the chip body while serving as a channel stopper region.

  In the present embodiment, the MOSFET has been described. However, the same effect can be obtained with an IGBT or a pn diode.

In the above description, the p ⁻ region 4 has a lower concentration than the breakdown voltage holding structure 2 such as a guard ring, but is preferably formed in a separate process from the breakdown voltage holding structure 2. However, the resist thickness is appropriately controlled, and at the same time as the step of forming the p-type region of the breakdown voltage holding structure 2, an impurity or the like for forming the p-type region is implanted through the resist, thereby reducing the effective implantation amount. May be.

  Further, the present invention has a particularly remarkable effect when the semiconductor substrate is silicon carbide, but the effect can also be obtained with other semiconductor substrates such as silicon.

<Effect>
According to the embodiment of the present invention, the semiconductor device includes the n ⁺ region 8 as the first conductivity type channel stopper region formed on the surface other than the chip main body end portion 9 outside in the plan view from the breakdown voltage holding structure 2. Further prepare.

According to such a semiconductor device, it is possible to obtain a semiconductor device that exhibits the effect of reducing the electric field strength at the end portion 9 of the chip body while the n ⁺ region 8 serves as a channel stopper region.

<Third Embodiment>
<Configuration>
FIG. 4 is a cross-sectional view of the main part showing the configuration of the semiconductor device according to the third embodiment of the present invention. As an example of the high voltage semiconductor device, a vertical structure Schottky diode is cited. The same components as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted.

The Schottky diode shown in FIG. 4 includes an ion implantation region 10 as a high resistance region having a deep level, separated from the termination region having the breakdown voltage holding structure 2, instead of the p ⁻ region 4 of FIG. 1. . The ion implantation region 10 can be formed by ion implantation of argon, titanium, vanadium, chromium, or the like.

In the ion implantation region 10, electrons in the n ⁻ drift layer 1 are captured at a deep level, and charge compensation is performed by holes that are minority carriers. At this time, in equation (3), when considering N _a as the deep level density (density of trapped electrons) and x _p as the depth of the ion implantation region 10, the ion implantation region 10 is a p ⁻ region. 4 is obtained, a depletion layer spreads inside the ion implantation region 10, and a depletion region including a range up to the surface of the chip body end portion 9 is formed.

  At this time, since the ion-implanted region 10 is a region having a high resistance, a depletion layer sufficiently spreads to the surface of the chip body end portion 9, and the potential change at the chip body end portion 9 becomes comparatively gentle. Therefore, it is possible to suppress electric field concentration at the chip body end portion 9.

  In this way, by suppressing the concentration of the electric field on the end portion 9 of the chip body, it is possible to suppress the breakdown of the sealing material due to the high electric field and the decrease in breakdown voltage due to the occurrence of creeping discharge during the chip test. Can be obtained.

  FIG. 5 is a fragmentary cross-sectional view showing a different configuration of the semiconductor device according to the third embodiment of the present invention. As an example of the high voltage semiconductor device, a MOSFET having a vertical structure is cited. The same components as those in FIG. 2 are denoted by the same reference numerals, and detailed description thereof is omitted.

The MOSFET shown in FIG. 5 includes an ion implantation region 10 as a high resistance region having a deep level, separated from the termination region having the breakdown voltage holding structure 2, instead of the p ⁻ region 4 of FIG. 2. The ion implantation region 10 can be formed by ion implantation of argon, titanium, vanadium, chromium, or the like.

In the ion implantation region 10, electrons in the n ⁻ drift layer 1 are captured at a deep level, and charge compensation is performed by holes that are minority carriers. At this time, in equation (3), when considering N _a as the deep level density (density of trapped electrons) and x _p as the depth of the ion implantation region 10, the ion implantation region 10 is a p ⁻ region. 4 is obtained, a depletion layer spreads inside the ion implantation region 10, and a depletion region including a range up to the surface of the chip body end portion 9 is formed.

  At this time, since the ion-implanted region 10 is a region having a high resistance, a depletion layer sufficiently spreads to the surface of the chip body end portion 9, and the potential change at the chip body end portion 9 becomes comparatively gentle. Therefore, it is possible to suppress electric field concentration at the chip body end portion 9.

  In this way, by suppressing the concentration of the electric field on the end portion 9 of the chip body, it is possible to suppress the breakdown of the sealing material due to the high electric field and the decrease in breakdown voltage due to the occurrence of creeping discharge during the chip test. Can be obtained.

In the MOSFET, an n ⁺ region may be formed near the end 9 of the chip body at the same time as the source forming step as a channel stopper region.

FIG. 6 is a fragmentary cross-sectional view showing the configuration of the semiconductor device in which the n ⁺ region 8 as the channel stopper region is formed.

As shown in FIG. 6, the n ⁺ region 8 is formed on the surface of the n ⁻ drift layer 1 corresponding to the ineffective region so as not to reach the end 9 of the chip body, so that the n ⁺ region 8 serves as a channel stopper region. Thus, a semiconductor device having the effect of reducing the electric field strength at the end portion 9 of the chip body can be obtained.

  In the present embodiment, the MOSFET has been described. However, the same effect can be obtained with an IGBT or a pn diode.

  In addition, the present invention has a particularly remarkable effect when the semiconductor substrate is silicon carbide, but is effective even with a semiconductor substrate having other band gaps.

<Effect>
According to the embodiment of the present invention, the semiconductor device includes the ion implantation region 10 that forms a deep level as the high resistance region.

  According to such a semiconductor device, a depletion region is formed in the vicinity of the chip body end 9, and electric field concentration at the chip body end 9 can be reduced.

  In the embodiment of the present invention, the material of each component, material, conditions for implementation, and the like are also described, but these are examples and are not limited to those described.

  In addition, within the scope of the present invention, the present invention can be freely combined with each embodiment, modified with any component in each embodiment, or omitted with any component in each embodiment.

1 n ⁻ drift layer, 2 breakdown voltage holding structure, 3 metal electrode, 4 p ⁻ region, 5 p type well region, 6 n ⁺ source region, 7 gate electrode, 8 n ⁺ region, 9 chip body end, 10 ion implantation region.

Claims (4)

An active region provided in the semiconductor chip body of the first conductivity type;
A pressure-resistant holding structure of a second conductivity type that surrounds the active region in plan view and is formed on the surface of the semiconductor chip body;
On the surface of the end portion of the semiconductor chip main body, a high resistance region formed to reach the end surface of the semiconductor chip main body apart from the withstand voltage holding structure,
The semiconductor chip body surface on which the high resistance region is formed is depleted when a voltage is applied,
The high resistance region is a second conductivity type semiconductor region having a lower concentration than the breakdown voltage holding structure,
Semi conductor device. It further comprises a channel stopper region of a first conductivity type formed on a surface which is not an end portion of the semiconductor chip body outside in a plan view outside the pressure resistance holding structure.
The semiconductor device according to claim 1. The material of the semiconductor chip body is silicon carbide,
The semiconductor device according to claim 1. The elementary charge q, the dielectric constant of the semiconductor chip body epsilon _s, the impurity concentration N _d of the semiconductor chip _body, the impurity concentration of the high resistance region N _a, and the high resistance region and said semiconductor chip body When the built-in potential at the pn junction is V _bi ,
The distance x _p of the pn junction from the surface of the semiconductor chip body is:

It is characterized by
The semiconductor device according to claim 1 .

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