JP6126404B2 - Transmission / reception system and communication method - Google Patents

Description

  The present invention relates to a transmission / reception system and a communication method for performing synchronization and phase compensation of transmission / reception frames in optical communication.

  In recent years, a coherent transmission method using digital signal processing, which has been developed in wireless communication, has been actively studied in optical communication. As a modulation method, phase shift keying (PSK) using phase information or quadrature amplitude modulation (QAM) method is adopted. In such optical communication, detection of a predetermined pattern included in a transmission / reception frame is performed in order to establish synchronization of the transmission / reception frame (Patent Document 1). In addition, since phase information is used in coherent transmission, phase noise caused by nonlinear optical effects and vibration of the optical fiber significantly degrades transmission characteristics. Therefore, in order to compensate for phase noise, a pilot symbol is intermittently inserted into the transmission / reception frame on the time axis in the transmitter, and after transmission, the phase of the received pilot symbol and the reference pilot symbol are compared. A method of estimating the phase noise and compensating the phase of the received signal by using it is conceivable.

Japanese Patent No. 4487743

  In order to perform phase compensation using a pilot symbol in a transmission / reception frame, it is necessary to acquire phase difference information by comparing a pilot symbol in the transmission / reception frame with a reference symbol at a receiving end. Since the pilot symbols are intermittently inserted in the transmission / reception frame, it is necessary to specify the time positions of the pilot symbols in the transmission / reception frame obtained from the reception signal in order to obtain the phase difference. As a method of establishing synchronization with a transmission / reception frame obtained from a received signal, there is a method of acquiring a correlation between a transmitted / received frame and a predetermined reference pilot symbol. In order to specify the pilot symbol time position without error, it is necessary to check the match between the received signal and the reference pilot symbol with at least 10 symbols.

  However, pilot symbols are inserted intermittently in transmission / reception frames. When the insertion ratio of pilot symbols in a transmission / reception frame is low, it is necessary to obtain a correlation with a reference pilot symbol over a long section of the transmission / reception frame. For this reason, the lower the pilot symbol insertion ratio, the greater the amount of computation and circuit scale for establishing synchronization. Along with this, there is a problem that arithmetic delay and circuit delay also increase. In addition, phase noise and frequency offset may remain in the transmission / reception frame. To perform processing while reducing these effects, there is a problem that the amount of calculation and the circuit scale further increase.

  The present invention has been made to solve the above problems, and an object of the present invention is to provide a transmission / reception system and a communication method capable of reducing the amount of calculation and circuit scale required for synchronization of transmission / reception frames.

In order to solve the above-described problem, the present invention provides a transmission / reception system that transmits and receives an optical signal, which is a transmission / reception frame including a synchronization pattern composed of consecutive symbols and data to be transmitted, wherein the synchronization pattern is arranged at equal intervals. A transmission / reception frame generation unit that generates a transmission / reception frame, a transmission unit that converts the transmission / reception frame generated by the transmission / reception frame generation unit into an optical signal, and an optical signal transmitted by the transmission unit. A reception unit that converts a signal into an electrical signal to generate one received digital signal sequence ; a synchronization pattern synchronization unit that detects the synchronization pattern included in the received digital signal sequence; and a synchronization pattern synchronization unit that detects the synchronization pattern the received digital signal sequence based on the position of the synchronization pattern is divided into a plurality of parallel expansion lane, divided the receiving Comprising a signal processing unit for performing signal processing in parallel for each digital signal sequence, the reception frame generation unit, if there are three or more values of the amplitude level at modulation on the synchronization pattern, the maximum amplitude level and In the transmission / reception system, symbols other than the minimum amplitude level are allocated, and the transmission / reception frame having a symbol length which is an integral multiple of the number of the plurality of parallel development lanes is generated.

Further, the present invention is the above-described invention, wherein the transmission / reception frame generation unit generates the transmission / reception frame in which pilot symbols are arranged at intervals of a predetermined number of symbols from the synchronization pattern, and the signal processing unit in, for each of said plurality of said received digital signal sequence is divided into parallel explosion lane, the detecting the pilot symbols based on the detected position of the synchronization pattern, based on said pilot symbols detected is divided Further, phase compensation is performed on the received digital signal sequence .

  Further, the present invention is the above-described invention, wherein the transmission / reception frame generation unit divides the pilot symbol into two orthogonal components, and arranges the synchronization pattern in each of the two components, and the synchronization pattern synchronization unit Detects the synchronization pattern in each of the two components, and the signal processing unit synchronizes the two components based on the position of the synchronization pattern in each of the two components detected by the synchronization pattern synchronization unit. It is characterized by that.

  In the invention described above, the transmission / reception frame generation unit uses a pseudo-random bit string as the synchronization pattern.

Also, the present invention is characterized in that, in the above-described invention, the transmission / reception frame generation unit uses modulation for mapping the two symbols whose phases are different by 180 ° for the synchronization pattern.

Further, the present invention is the invention described in the above, wherein the synchronization pattern synchronization unit performs a hard decision result on a differential detection signal obtained by performing differential detection on the received digital signal sequence with the synchronization pattern. And detecting the synchronization pattern included in the received digital signal sequence .

The present invention is also a communication method in a transmission / reception system for transmitting / receiving an optical signal, which is a transmission / reception frame including a synchronization pattern composed of consecutive symbols and data to be transmitted, wherein the synchronization patterns are arranged at equal intervals. A transmission / reception frame generation step for generating a transmission / reception frame; a transmission step for converting the transmission / reception frame generated in the transmission / reception frame generation step into an optical signal; and an optical signal transmitted in the transmission step. A reception step of converting a signal into an electrical signal to generate one reception digital signal sequence ; a synchronization pattern synchronization step of detecting the synchronization pattern included in the reception digital signal sequence; and the detection of the synchronization pattern synchronization step the received digital signal based on the position of the synchronization pattern Dividing the column into a plurality of parallel expansion lane, and a signal processing step of performing signal processing in parallel to each divided the received digital signal sequence, in the transceiver frame generating step, the modulation for the synchronization pattern When there are three or more amplitude levels, symbols other than the maximum amplitude level and the minimum amplitude level are allocated, and the transmission / reception frame having a symbol length that is an integral multiple of the number of the plurality of parallel development lanes is generated. This is a communication method characterized by the above.

  According to the present invention, the frame length of a transmission / reception frame transmitted as an optical signal is set to an integral multiple of the number of parallel development lanes for signal processing on the reception side. Thereby, once the synchronization pattern is detected on the receiving side, the position where the synchronization pattern appears can be made constant when the received digital signal is assigned to each parallel development lane based on the position of the detected synchronization pattern. Thereby, it is possible to maintain the synchronization of the transmission / reception frame by the synchronization pattern without detecting the synchronization pattern at all locations in the parallel development lane. Further, by making the position where the synchronization pattern appears constant, it is possible to reduce operations and circuits for detecting the synchronization pattern, and it is possible to reduce the amount of operation and circuit scale in the receiving apparatus.

It is a block diagram which shows the structural example of the transmission / reception system in 1st Embodiment which concerns on this invention. It is a block diagram which shows the structural example of the transmission / reception frame production | generation circuit with which the transmission apparatus 1 of this embodiment is equipped. It is a figure which shows the structural example of the transmission / reception frame in this embodiment. It is a figure which shows the other structural example of the transmission / reception frame in this embodiment. It is a figure which shows the structural example with which the insertion interval of a pilot symbol is uniform in a transmission / reception frame. It is a figure which shows the structural example in which the insertion space | interval of a pilot symbol is non-uniform in a transmission / reception frame. It is a figure explaining the outline | summary of the digital signal processing performed in the receiver 3 of this embodiment. It is a figure which shows the structural example of the transmission / reception frame of the pilot symbol with which mapping was performed on the same complex plane. An example of mapping of pilot symbols on the complex plane in the symbol mapping circuit 13 is shown. It is a figure which shows the structural example of the transmission / reception frame of the synchronous pattern by which mapping was performed on the same complex plane. It is a block diagram which shows the structural example of the transmission / reception frame synchronizing circuit used in the receiver 3 of this embodiment. It is a block diagram which shows the structure of the pilot symbol extraction circuit 5 in this embodiment. It is a block diagram which shows the structural example of 4 A of synchronous pattern synchronizing circuits in 2nd Embodiment. It is a block diagram which shows the structural example of the differential detection circuit 41 in this embodiment. It is a figure showing the calculation required for acquisition of the synchronous position information in 1st Embodiment and 2nd Embodiment. It is a block diagram which shows the structural example of the synchronous pattern synchronizing circuit 4B as a modification of 2nd Embodiment. It is a figure which shows the example of a mapping of the synchronous pattern at the time of modulating a data signal by 32QAM and 64QAM.

  Hereinafter, a transmission / reception system and a communication method according to an embodiment of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a block diagram showing a configuration example of a transmission / reception system according to the first embodiment of the present invention. The transmission / reception system includes a transmission device 1, a transmission path 2, and a reception device 3. The transmission device 1 inserts a synchronization pattern or a pilot symbol into a data signal to be transmitted to the reception device 3, and converts the signal from an electric signal to an optical signal. The transmission device 1 transmits the optical signal obtained by the conversion to the reception device 3 via the transmission path 2. The transmission line 2 is, for example, an optical fiber. The receiving device 3 converts an optical signal received via the transmission path 2 into an electrical signal, and acquires a data signal from the electrical signal.

  When a single polarization signal is used for transmission / reception of a data signal, in the receiving device 3, a receiving unit (not shown) converts the received optical signal into an electric signal and performs analog / digital conversion on the electric signal. Thus, a received digital signal is generated. In addition, when a signal that is polarization-multiplexed so as to be orthogonal to the transmission / reception of the data signal is used, the receiving device 3 converts the received optical signal into an electrical signal, and performs analog / digital conversion on the electrical signal. Is done. Thereafter, adaptive equalization processing is performed on the digitized signal to separate the polarization into a single polarization to obtain a received digital signal. In addition, when a polarization-multiplexed signal is used so as to be orthogonal to the transmission / reception of the data signal, the receiving device 3 uses a polarization controller to separate the signal into a single polarization to obtain a received digital signal. May be.

  FIG. 2 is a block diagram illustrating a configuration example of a transmission / reception frame generation circuit provided in the transmission device 1 of the present embodiment. The transmission / reception frame generation circuit includes a pilot symbol insertion circuit 11, a synchronization pattern insertion circuit 12, and a symbol mapping circuit 13. A pilot symbol insertion circuit 11 receives a data signal to be transmitted. Pilot symbol insertion circuit 11 inserts pilot symbols into the data signal and outputs the result to synchronization pattern insertion circuit 12. The synchronization pattern insertion circuit 12 inserts a synchronization pattern into the signal output from the pilot symbol insertion circuit 11 and outputs it to the symbol mapping circuit 13. The symbol mapping circuit 13 applies a predetermined modulation method and maps the signal output from the synchronization pattern insertion circuit 12 to generate a transmission / reception frame. The transmission / reception frame generated by the transmission / reception frame generation circuit is subjected to electro-optic conversion in a transmission unit (not shown) and transmitted as an optical signal.

Note that pilot symbols may be inserted after the synchronization pattern is inserted into the data signal. That is, the connection order of pilot symbol insertion circuit 11 and synchronization pattern insertion circuit 12 may be reversed.
As the synchronization pattern, any pattern may be used as long as the receiving apparatus 3 can detect the correlation peak when detecting the synchronization pattern in the received digital signal. As an example of the pattern used as the synchronization pattern, PRBS (Pseudo Random Bit Sequence) having a correlation only when the delay becomes zero can be used. PRBS has a sharp correlation only when the delay becomes zero. Note that PRBS is the same as PN sequence and M sequence.

Hereinafter, a configuration example of the transmission / reception frame generated by the transmission / reception frame generation circuit will be described.
FIG. 3 is a diagram illustrating a configuration example of a transmission / reception frame in the present embodiment. In the transmission / reception frame configuration, pilot symbols (PS) having a length of N symbols are inserted into transmission data at symbol intervals determined for a sequence. A synchronization pattern continuous over a plurality of symbols is inserted at a predetermined position of the transmission / reception frame. FIG. 3A is a diagram illustrating a configuration example of a typical transmission / reception frame. In the configuration of the transmission / reception frame shown in the figure, a synchronization pattern is provided at the head of the transmission / reception frame, and a data signal is inserted immediately after the synchronization pattern. Also, pilot symbols are inserted at regular intervals with respect to the data signal. FIG. 3B shows a configuration in which pilot symbols are arranged immediately after the synchronization pattern. In the transmission / reception frame generated by the transmission / reception frame generation circuit, pilot symbols are arranged at intervals of a predetermined number of symbols from the synchronization pattern.

  FIG. 4 is a diagram illustrating another configuration example of the transmission / reception frame in the present embodiment. In the transmission / reception frame shown in the figure, a data signal of M (1 to data frame length) symbols is inserted immediately after the synchronization pattern, and a pilot symbol is inserted following this data signal. With this configuration, it is possible to give flexibility to the transmission / reception frame configuration, and it is not necessary to insert stuff bytes. This is because the number of symbols in the transmission / reception frame does not change, and therefore the necessity for inserting stuff bytes does not change. For this reason, there is an effect that the interval between pilot symbols after the data signal inserted immediately after the synchronization pattern is made constant.

  The number M of data signal symbols inserted immediately after the synchronization pattern is the length of the synchronization pattern, the insertion rate of pilot symbols, the transmission / reception frame length, and the parallel expansion when the reception apparatus 3 processes the transmission / reception frames in parallel. It is predetermined by the number of lanes. For example, when the length of the synchronization pattern is Ns, the insertion rate of pilot symbols is Np [%], the length of the transmission / reception frame is Nf, and the number of parallel development lanes is Nl, the length of the data signal is (Nf−Ns). expressed. Pilot symbols are inserted into the data signal at intervals of ((Nf−Ns) * Np / 100). When pilot symbols can be inserted at regular intervals with respect to the data signal, that is, when ((Nf−Ns) * Np / 100) is an integer, M = 0. When a remainder appears in ((Nf−Ns) * Np / 100), mod ((Nf−Ns) * Np, 100)) = M. The function mod (x, y) is a function for calculating a remainder when x is divided by y. Further, when k is an arbitrary natural number, Nf = k × Nl.

  FIG. 5 is a diagram illustrating a configuration example in which the pilot symbol insertion interval is uniform in the transmission / reception frame. As shown in the figure, a pilot symbol is inserted for each X symbol. Assuming that phase information obtained from a plurality of pilot symbols is averaged to reduce the phase error of the pilot symbols due to distortion received in the transmission path 2, if the pilot symbol insertion interval is uniform, a low-pass filter (LPF: There is an advantage that the configuration of the Low Pass Filter can be simplified. In addition, there is an advantage that a circuit for processing the process can be simplified in the process of generating a pilot symbol by complementing and generating a compensation phase of a symbol portion other than the pilot symbol. In addition, since a fixed clock can be used for pilot symbol extraction, there is an advantage that the circuit scale can be reduced.

  On the other hand, FIG. 6 shows a case where the pilot symbol insertion interval is not uniform. FIG. 6 is a diagram illustrating a configuration example in which pilot symbol insertion intervals are not uniform in a transmission / reception frame. As will be described later, when the transmission / reception frame length is set to k times (k: a positive integer) the number of parallel development lanes in the receiving apparatus 3, the pilot symbol insertion interval may not be uniform depending on the redundancy. . In this case, the above-mentioned merit cannot be obtained, and the circuit scale may be increased in the pilot symbol averaging process, the interpolation process, and the pilot symbol extraction process.

  FIG. 7 is a diagram illustrating an outline of digital signal processing performed in the receiving device 3 of the present embodiment. In the receiving device 3, the received digital signal obtained from the received optical signal is developed in parallel and processed by a plurality of parallel development lanes. Since optical communication requires high-speed signal processing of several tens of Gbit / s to several hundred Gbit / s, and more, the receiving device 3 develops the received digital signal in parallel development lanes and performs processing in parallel. Yes. As shown in the figure, the received digital signal is expanded to the number of parallel expansion lanes and processed in parallel. By making the length of the transmission / reception frame (symbol length) proportional to the number of parallel development lanes, the synchronization pattern included in the transmission / reception frame can appear at the head of the parallel development lane each time. Thereby, the circuit scale for detecting the synchronization pattern can be reduced.

  On the other hand, when there is no proportional relationship between the number of parallel development lanes and the length of transmission / reception frames, when transmission / reception frames sequentially obtained from received optical signals are expanded to parallel expansion lanes, the transmission / reception frame length is divided by the number of parallel expansion lanes. The position of the synchronization pattern is shifted by the surplus symbols at that time. For this reason, it is necessary to provide a circuit for detecting a synchronization pattern in each parallel development lane, and the circuit scale becomes enormous.

  When the number of parallel development lanes is not proportional to the transmission / reception frame length, that is, when the transmission / reception frame length is not divisible by the number of parallel development lanes, the transmission / reception frame generation circuit uses the synchronization pattern as shown in FIG. An M symbol data signal is inserted between the pilot symbols. As a result, the synchronization pattern appears at the head of the parallel development lane. Instead of inserting the M symbol data signal immediately after the synchronization pattern, the interval between the pilot symbol immediately before the synchronization pattern and the synchronization pattern may be set to M symbols. Further, instead of the data signal of M symbols, a signal other than the data signal may be inserted as a stuff signal.

  For example, when used as an OTU4 frame transmission / reception frame standardized in optical communication, the number of parallel development lanes is 128 when a circuit that performs digital signal processing of the receiving device 3 operates in synchronization with a clock signal having a frequency of 250 MHz. In this case, the number of symbols in the transmission / reception frame is a multiple of 128. Further, when the frequency of the clock signal is 500 MHz, the number of parallel development lanes in the receiving device 3 is 64, and therefore the number of symbols in the transmission / reception frame is a multiple of 64. In addition, the number of symbols of the synchronization pattern, pilot symbol, and data signal constituting the transmission / reception frame is a multiple of 128 or 64. The same relationship holds for the OTU4V frame.

  FIG. 8 is a diagram illustrating a configuration example of a transmission / reception frame of pilot symbols in which mapping is performed on the same complex plane. In the receiving device 3, the transmission / reception frame is developed in parallel in two lanes of an I signal component and a Q signal component. At that time, the I signal component and the Q signal component of the pilot symbols mapped on the same complex plane need to be at the same time position. This is because, as shown in the figure, a complex signal obtained by combining the I signal component and the Q signal component is used as a known pilot symbol. If the combined I signal component and Q signal component are shifted, the known pilot symbol is used. Cannot be detected. Further, synchronization cannot be achieved, and phase compensation cannot be performed, or erroneous phase compensation is performed. For this reason, the receiving apparatus 3 performs delay adjustment and the like so that the delays of the I signal component and the Q signal component are combined to the same time position. For example, in the transmission / reception frame generation circuit, a synchronization pattern is inserted into each of the I signal component and the Q signal component at the same time position, the synchronization pattern is detected in the I signal component and the Q signal component in the receiving device 3, and the detected synchronization pattern is detected. Adjust the delay to match the time position.

  FIG. 9 shows a mapping example of pilot symbols on the complex plane in the symbol mapping circuit 13. The symbols shown in the figure are for the case where 16QAM is adopted as the modulation method. When mapping the pilot symbols, the symbol mapping circuit 13 maps the symbols (•) filled in black among the 16 symbols shown in FIG. This is to prevent the pilot symbol from receiving excessive phase noise compared to the data signal due to noise during transmission and waveform distortion. The causes of phase noise that can occur during transmission are the non-linear optical effects of self phase modulation (SPM), cross phase modulation (XPM), and local oscillation (LO). There is a frequency offset caused by deviation from the carrier frequency of the signal.

  Note that, in place of the mapping example shown in FIG. 9, when a modulation scheme having three or more amplitude levels is used, it is preferable to use symbols other than the maximum amplitude or the minimum amplitude for pilot symbol mapping. This is because an error is likely to occur in the symbol having the smallest amplitude due to the influence of noise, and an error is likely to occur in the symbol having the largest amplitude due to the influence of the nonlinear optical effect. Further, when the amplitude value is binary, it is preferable to use a symbol having an amplitude value that is less likely to cause an error.

FIG. 10 is a diagram illustrating a configuration example of a transmission / reception frame of a synchronization pattern in which mapping is performed on the same complex plane. As a modulation method for the synchronization pattern, BPSK having a phase margin of 90 ° and less prone to error is used.
The symbol mapping circuit 13 grasps the position of the pilot symbol inserted by the pilot symbol insertion circuit 11 and the position of the synchronization pattern inserted by the synchronization pattern insertion circuit 12, and the mapping target is any one of the pilot symbol, the synchronization pattern, and the data signal. Depending on whether or not, the symbol to be mapped is selected. For example, when mapping a synchronization pattern when 64QAM is used as a modulation method, the symbol mapping circuit 13 selects two symbols from 64 symbols, and the mapping result to the selected symbol becomes a PRBS pattern. Like that. Further, the bit pattern obtained as PRBS may be multiplied by 6 and mapped using 64QAM.

  FIG. 11 is a block diagram illustrating a configuration example of a transmission / reception frame synchronization circuit used in the reception device 3 of the present embodiment. The reception digital signal obtained in the reception device 3 is input to the transmission / reception frame synchronization circuit. The transmission / reception frame synchronization circuit establishes synchronization of the transmission / reception frame included in the reception digital signal, and acquires synchronization position information indicating the synchronization timing. The transmission / reception frame synchronization circuit extracts pilot symbols after synchronizing transmission / reception frames using a synchronization pattern. The transmission / reception frame synchronization circuit acquires a phase difference between the extracted pilot symbol and the pilot symbol stored in advance as a reference signal in the reception device 3. The transmission / reception frame synchronization circuit performs pilot phase compensation by performing phase rotation on the transmission / reception frame by the acquired phase difference. In optical communication, a frequency offset of several GHz may occur, so phase compensation may not be possible at a general pilot symbol insertion ratio of 10% or less. In such a case, a circuit for compensating for the frequency offset is separately provided before the transmission / reception frame synchronization circuit.

  The transmission / reception frame synchronization circuit includes a synchronization pattern synchronization circuit 4, a pilot symbol extraction circuit 5, a reference signal storage circuit 6, a phase difference acquisition circuit 7, and a phase difference compensation circuit 8. The synchronization pattern synchronization circuit 4 detects a position where a synchronization pattern is inserted with respect to an input received digital signal. The synchronization pattern synchronization circuit 4 outputs synchronization position information indicating the detected position to the pilot symbol extraction circuit 5. The pilot symbol extraction circuit 5 extracts pilot symbols inserted in the received digital signal based on the synchronization position information output from the synchronization pattern synchronization circuit 4.

  The pilot symbol extraction circuit 5 outputs the extracted pilot symbols to the phase difference acquisition circuit. In the reference signal storage circuit 6, pilot symbols inserted in the data signal by the pilot symbol insertion circuit 11 provided in the transmission device 1 are stored in advance as reference signals. The phase difference acquisition circuit 7 calculates the phase difference between the pilot symbol output from the pilot symbol extraction circuit 5 and the reference signal (pilot symbol) stored in the reference signal storage circuit 6. The phase difference acquisition circuit 7 outputs the calculated phase difference to the phase difference compensation circuit 8.

  The phase difference compensation circuit 8 performs phase compensation on the received digital signal based on the phase difference output from the phase difference acquisition circuit 7. The phase difference compensation circuit 8 outputs the received digital signal subjected to phase difference compensation to a subsequent digital signal processing circuit or the like. The latter stage digital signal processing circuit is, for example, a circuit that performs demapping, error correction decoding, and the like.

  As shown in FIG. 7, the processing on the received digital signal in the receiving device 3 is performed in parallel by dividing the received digital signal into each parallel development lane. The received digital signal is distributed to each parallel development lane based on the synchronization position information detected by the synchronization pattern synchronization circuit 4. For example, the pilot symbol extraction circuit 5 extracts symbols for each parallel development lane.

  The detection of the position of the synchronization pattern by the synchronization pattern synchronization circuit 4 calculates the correlation between the input received digital signal and a predetermined synchronization pattern, and searches for a time position where a correlation equal to or greater than the detection threshold is obtained. Is done. The synchronization pattern synchronization circuit 4 determines that the synchronization pattern is arranged at the time position where the correlation equal to or higher than the detection threshold is obtained. The detection threshold value is a predetermined value and is stored in the synchronization pattern synchronization circuit 4.

  In addition, for example, a convolution circuit that performs a convolution operation can be used to calculate the correlation in the synchronization pattern synchronization circuit 4. At this time, the input to the convolution circuit is a received digital signal and a synchronization pattern. Alternatively, the time position may be detected by binary identification of the received digital signal and specifying the time position where the digital pattern and the synchronization pattern substantially match. As a result, the circuit scale of the synchronization pattern synchronization circuit 4 can be reduced.

  Once the time position of the synchronization pattern can be detected in the received digital signal, the synchronization pattern repeatedly arrives at the period of the symbol length of the transmission / reception frame, so the time position where the synchronization pattern arrives can be predicted in advance. is there. By confirming that the synchronization pattern arrives again at the predicted time position, the accuracy of detecting the time position of the synchronization pattern can be improved.

  Also, when the change in the carrier phase is large, such as when the frequency offset remaining in the received digital signal is large, it is difficult to individually synchronize the I signal component and the Q signal component. In this case, signals of the parallel development lane of the I signal component of the received digital signal and the parallel development lane of the Q signal component corresponding to the I signal component are treated as a combination of complex numbers, and the received digital signal and the synchronization pattern The correlation is calculated in the complex number domain.

  If the time until the carrier phase is rotated by π / 2 due to the frequency offset remaining in the received digital signal is sufficiently longer than the pilot symbol insertion time interval, the time interval between the received digital signal and the pilot symbol is The symbols may be extracted in step (b), and a pilot symbol sequence obtained by differential detection of the extracted symbols and pilot symbols may be synchronized as a synchronization pattern.

  As a compensation method in the phase difference compensation circuit 8, in addition to a method of obtaining a phase difference between a pilot symbol and a reference signal in a transmission / reception frame and performing phase rotation, the phase difference is calculated by calculating electric field information and multiplying the electric field vector. There is also a way to compensate for this. In the latter method, E (Δφ) is obtained in a pilot symbol for the data signal E (jwt + Δφ) (Δφ is phase noise), and the data signal is multiplied by the complex conjugate component conj (E (Δφ)). To compensate. As another method, (−Δφ) phase rotation may be performed on the data signal when compensation is performed.

  FIG. 12 is a block diagram showing a configuration of the pilot symbol extraction circuit 5 in the present embodiment. In the figure, the received digital signal input to the transmission / reception frame synchronization circuit is divided into an in-phase component (Inphase) and a quadrature component (Quadrature). The pilot symbol extraction circuit 5 includes a pilot symbol position calculation circuit 51 and selectors 52 and 53. The pilot symbol position calculation circuit 51 calculates the position of the pilot symbol in the transmission / reception frame based on the synchronization position information acquired by the synchronization pattern synchronization circuit 4. Based on the position of the pilot symbol detected by the pilot symbol position calculation circuit 51, the selectors 52 and 53 extract pilot symbols from the parallel development lanes developed so as to process the received digital signals in parallel.

  The pilot symbol position calculation circuit 51 uses the synchronization position information to calculate the pilot symbol time position based on the relative relationship between the pilot symbol insertion time position and the synchronization pattern insertion time position. The pilot symbol position calculation circuit 51 stores in advance the relative time positions of the pilot symbols and the synchronization pattern. For example, as shown in FIG. 3 or FIG. 4, the time position of the pilot symbol in the transmission / reception frame can be obtained by determining the time position of the synchronization pattern.

  The received digital signal is developed in parallel in a plurality of parallel development lanes according to the frequency of the clock signal used for signal processing in the receiving device 3. For example, when a received digital signal having a symbol rate of 32 GHz is processed by a circuit that operates in synchronization with a clock signal having a frequency of 500 MHz, it is necessary to process 64 symbols per clock. Therefore, in the receiving device 3, the received digital signal is developed in parallel in 64 parallel lanes. The time position of the pilot symbol and the synchronization pattern in the received digital signal is represented by a combination of a lane number that uniquely identifies the parallel development lane and a clock count. The pilot symbol position calculation circuit 51 controls the selectors 52 and 53 using the time position represented by the combination of the lane number and the clock count, so that the pilot symbol can be extracted from the received digital signal.

  With the above configuration, the reception device 3 is a transmission / reception frame having a length that is an integral multiple of the number of parallel development lanes, and includes a transmission / reception frame in which synchronization patterns are arranged at equal intervals at predetermined positions. Synchronization can be established by detecting the synchronization pattern. Further, in the modulation (mapping) of the synchronization pattern, if there are three or more amplitude levels in the modulation method, symbols other than the maximum amplitude and the minimum amplitude are assigned to the synchronization pattern, which is a problem peculiar to optical communication. Synchronization can be established while suppressing the influence of the nonlinear optical effect.

  Also, since the length of the transmission / reception frame (symbol length) is an integral multiple of the number of parallel development lanes, the time when the synchronization pattern appears when the received digital signal is distributed to each parallel development lane and processed in parallel in the receiver 3. The position is fixed. Thereby, once the synchronization pattern is detected, the time position at which the synchronization pattern appears can be fixed. As a result, in each parallel development lane, there is no need to detect a synchronization pattern for all the symbols to be processed or to detect a pilot symbol, and the amount of calculation and circuit for detecting the synchronization pattern and pilot symbol can be reduced. Can do.

  In addition, the receiving apparatus 3 can improve the accuracy of detecting the pilot symbols by improving the accuracy of detecting the time position of the synchronization pattern. By using pilot symbols detected with high accuracy, the phase difference detection accuracy can be improved, and the accuracy of phase difference compensation for the received digital signal can also be improved.

(Second Embodiment)
In the second embodiment, as a modification of the transmission / reception frame synchronization circuit (FIG. 11) in the first embodiment, a synchronization pattern synchronization circuit having a configuration different from that of the synchronization pattern synchronization circuit 4 in the first embodiment will be described. In the synchronization pattern synchronization circuit according to the present embodiment, differential detection and exclusive OR operation are used instead of convolution when calculating the correlation. The transmission / reception frame configuration is the same as in the first embodiment.

  By using differential detection, a steady frequency offset component can be removed. For example, when the phase of the synchronization pattern is {θ (1), θ (2),..., Θ (N)}, the differential detection component Δθ (n) is Δθ (n) = θ (n + 1) −θ ( n), n = 1, 2,..., N-1. If a frequency offset ΔθN (n), n = 1, 2,..., N occurs when synchronization is performed using the differential detection component of Δθ, phase rotation is added to the synchronization pattern.

The phase of the synchronization pattern when the frequency offset occurs is {(θ (1) + ΔθN (1)), (θ (2) + ΔθN (2)),..., (Θ (N) + ΔθN (N))} It can be expressed. The differential detection component Δθ (n) at this time is as follows.
Δθ (n) = (θ (n + 1) + ΔθN (n + 1)) − (θ (n) + ΔθN (n))
= Δθ (n) + (ΔθN (n + 1) −ΔθN (n)),
(N = 1, 2,..., N-1)

When the frequency offset component is sufficiently low compared to the sampling frequency of the received digital signal, it can be approximated as ΔθN (i) = ΔθN (i + 1), (i = 1, 2,..., N−1). Therefore, the differential detection component does not have the phase rotation component due to the frequency offset, and only the Δθ (1),..., Δθ (N−1) components can be extracted.
As a result, synchronization can be established while suppressing the influence of the frequency offset.

FIG. 13 is a block diagram illustrating a configuration example of the synchronization pattern synchronization circuit 4A according to the second embodiment. Here, a configuration will be described in which phase information is used as a synchronization pattern and a modulation scheme having information of two bits or more in one symbol is used. As a modulation method in this case, for example, there is QPSK modulation. The synchronization pattern synchronization circuit 4A includes a differential detection circuit 41, an identification circuit 42, a reference signal storage circuit 43, and a pattern synchronization circuit 44.

  The differential detection circuit 41 receives an I signal component and a Q signal component that are signals corresponding to the horizontal axis (in-phase component) and the vertical axis (orthogonal component) on the complex plane. The differential detection circuit 41 calculates the differential detection signal by synchronously detecting the I signal component and the Q signal component. The identification circuit 42 performs determination on the complex plane, maps and decodes the differential detection signal calculated by the differential detection circuit 41. The identification circuit 42 sequentially outputs signals obtained by encoding. The reference signal storage circuit 43 stores a reference signal generated based on the synchronization pattern in advance. Specifically, a signal obtained by differential detection with respect to the synchronous pattern is stored as a reference signal. The pattern synchronization circuit 44 obtains synchronization position information by performing position synchronization between the synchronization pattern code sequence sequentially output from the identification circuit 42 and the reference signal stored in the reference signal storage circuit 43.

  FIG. 14 is a block diagram illustrating a configuration example of the differential detection circuit 41 in the present embodiment. The differential detection circuit 41 includes delay circuits 411 and 412, a complex conjugate calculation circuit 413, and a complex multiplication circuit 414. The I signal component input to the differential detection circuit 41 is input to the delay circuit 411 and the complex multiplication circuit 414. The delay circuit 411 gives a 1-bit delay to the I signal component and then outputs it to the complex conjugate calculation circuit 413. The Q signal component input to the differential detection circuit 41 is input to the delay circuit 412 and the complex multiplication circuit 414. The delay circuit 412 gives a 1-bit delay to the Q signal component and then outputs it to the complex conjugate calculation circuit 413.

  The complex conjugate calculation circuit 413 calculates a complex conjugate signal with respect to a complex signal obtained by using the input from the delay circuit 411 as an in-phase component and the input from the delay circuit 412 as a quadrature component. The complex conjugate calculation circuit 413 outputs the calculated complex conjugate signal to the complex multiplication circuit 414. The complex multiplication circuit 414 multiplies the complex signal composed of the I signal component and the Q signal component by the complex signal calculated by the complex conjugate calculation circuit 413, and outputs the multiplication result as a differential detection signal. Multiplication in the complex multiplication circuit 414 is expressed by the following equation (1).

In Expression (1), E _I (t) corresponds to a complex signal input to the complex multiplier circuit 414 from the outside, and E _I (t−1) ^* is input from the complex conjugate calculation circuit 413 to the complex multiplier circuit 414. Corresponding to complex signals. When QPSK or BPSK is used as the synchronization pattern, the amplitude value | E _I (t) | is always 1, and the output of the complex multiplication circuit 414 is only the phase component. When amplitude noise occurs due to transmission and the amplitude value deviates from 1, only the phase information can be obtained by dividing the output of the complex multiplication circuit 414 by the amplitude value of the output and normalizing.

  Position synchronization with the reference signal in the pattern synchronization circuit 44 is performed by an exclusive OR operation with the reference signal for the synchronization pattern code sequence output from the identification circuit 42. When the target of exclusive OR operation with the reference signal in the synchronization pattern code sequence output from the identification circuit 42 is identical with the reference signal, the result of the exclusive OR operation is 0 for the synchronization pattern length. . In addition, by providing an inverting circuit in either one of the synchronization pattern code sequence or the reference signal, 1 is continued by the synchronization pattern length when the reference signal matches the target of the exclusive OR operation with the reference signal. You can also. The same can be achieved by providing an inverting circuit for the result of the exclusive OR operation.

  When the exclusive OR operation is used in the pattern synchronization circuit 44, synchronization can be achieved with the gradation of the hard decision result (1 bit) in the identification circuit 42, and therefore based on the result of the convolution operation with the amplitude information. Thus, the calculation amount and the circuit scale can be reduced as compared with the case where synchronization is acquired.

  FIG. 15 is a diagram illustrating a calculation required for acquisition of synchronization position information in the first embodiment and the second embodiment. FIG. 15A shows a calculation (convolution calculation) required for acquisition of synchronization position information and synchronization by an amplitude value in the first embodiment. The information for acquiring synchronization differs depending on the resolution of the amplitude value, but requires several bits. On the other hand, in the calculation required for acquiring the position information in the second embodiment shown in FIG. 15B, after performing a hard detection with differential detection, synchronization can be achieved with 1 bit. The circuit scale can be reduced. Note that the identification circuit 42 corresponds to “hard decision” in FIG. 15B, and the pattern synchronization circuit corresponds to XOR.

  FIG. 16 is a block diagram illustrating a configuration example of a synchronization pattern synchronization circuit 4B as a modification of the second embodiment. In the synchronization pattern synchronization circuit 4A shown in FIG. 13, the configuration in the case where a modulation scheme having information of 2 bits or more in one symbol is used for the synchronization pattern has been described. The synchronization pattern synchronization circuit 4B has a configuration in which a modulation method having 1-bit information per symbol is used for the synchronization pattern. In this case, the modulation method includes BPSK.

  The synchronization pattern synchronization circuit 4B includes a differential detection circuit 41, an identification circuit 42B, a reference signal storage circuit 43B, and a pattern synchronization circuit 44B. The differential detection circuit 41 has the same configuration as the differential detection circuit 41 shown in FIG. The I signal component of the differential detection signal calculated by the differential detection circuit 41 is input to the identification circuit 42B. The identification circuit 42B determines and maps the differential detection signal on the complex plane and decodes it. In the reference signal storage circuit 43B, a reference signal generated based on the synchronization pattern is stored in advance. The pattern synchronization circuit 44B acquires the synchronization position information by performing position synchronization between the synchronization pattern code sequence sequentially output from the identification circuit 42B and the reference signal stored in the reference signal storage circuit 43B.

In FIG. 16, the I signal component output from the differential detection circuit 41 is input to the discrimination circuit 42B. However, since the I signal component and the Q signal component are always the same value on the complex plane, the discrimination circuit 42B. Any output may be used.
As an advantage of using the configuration shown in the figure, since the output from the identification circuit 42B to the pattern synchronization circuit 44B is 1 bit, the circuit scale of the pattern synchronization circuit 44B and the reference signal storage circuit 43B can be reduced.

  On the other hand, the merit of using the configuration of the synchronization pattern synchronization circuit 4A shown in FIG. 13 is that the frequency offset tolerance is higher than that of the synchronization pattern synchronization circuit 4B shown in FIG. For example, let us consider a case where the phase rotation due to the frequency offset remaining in the received digital signal is large and π / 2 is rotated by one symbol. When BPSK is used as the synchronization pattern, the differential detection signal becomes 1 or -1, but when the phase rotation of π / 2 is received, the differential detection signal becomes i or -i. At this time, if detection based only on the I signal component is performed, 0 is output as a differential detection signal, and a correct value cannot be obtained. When the phase rotation due to the frequency offset is large as described above, it can be solved by providing a separate frequency offset compensation unit in the order of GHz in the previous stage of the synchronization pattern synchronization circuit 4B.

In the above description of each embodiment, BPSK and QPSK are exemplified as mapping of the synchronization pattern. However, BPSK or QPSK can be selected as the synchronization pattern regardless of the multilevel of the data signal. However, when the data signal is modulated by BPSK, the synchronization pattern is also modulated by BPSK.
FIG. 17 is a diagram illustrating a synchronization pattern mapping example when a data signal is modulated by 32QAM and 64QAM. In the drawing, symbols used for synchronization pattern mapping are painted black. In the figure, an example in which the synchronization pattern is mapped as QPSK is shown. As shown in the figure, symbols other than the symbol having the maximum amplitude value and the minimum amplitude value are assigned to the synchronization pattern so that errors are not easily generated. This is because an error is likely to occur in the symbol having the smallest amplitude value due to the influence of noise, and an error is likely to occur in the symbol having the largest amplitude value due to the influence of the nonlinear optical effect. Note that the mapping shown in FIG. 17 is an example, and mapping using symbols different from those in FIG. 17 may be performed. When mapping the synchronization pattern as BPSK, two symbols that are 180 ° out of phase are selected from the symbols (●) filled in black.

  A program for realizing the function of the transmission / reception frame synchronization circuit in the above embodiment is recorded on a computer-readable recording medium, and the program recorded on the recording medium is read into a computer system and executed. Transmission / reception frame synchronization establishment and phase compensation may be performed. Here, the “computer system” includes an OS and hardware such as peripheral devices. The “computer system” includes a WWW system having a homepage providing environment (or display environment). The “computer-readable recording medium” refers to a storage device such as a flexible medium, a magneto-optical disk, a portable medium such as a ROM and a CD-ROM, and a hard disk incorporated in a computer system. Further, the “computer-readable recording medium” refers to a volatile memory (RAM) in a computer system that becomes a server or a client when a program is transmitted via a network such as the Internet or a communication line such as a telephone line. In addition, those holding programs for a certain period of time are also included.

  The program may be transmitted from a computer system storing the program in a storage device or the like to another computer system via a transmission medium or by a transmission wave in the transmission medium. Here, the “transmission medium” for transmitting the program refers to a medium having a function of transmitting information, such as a network (communication network) such as the Internet or a communication line (communication line) such as a telephone line. The program may be for realizing a part of the functions described above. Furthermore, what can implement | achieve the function mentioned above in combination with the program already recorded on the computer system, and what is called a difference file (difference program) may be sufficient.

DESCRIPTION OF SYMBOLS 1 ... Transmission apparatus 2 ... Transmission path 3 ... Reception apparatus 4, 4A, 4B ... Synchronization pattern synchronization circuit 5 ... Pilot symbol extraction circuit 6 ... Reference signal storage circuit 7 ... Phase difference acquisition circuit 8 ... Phase difference compensation circuit 11 ... Pilot symbol Insertion circuit 12 ... Synchronization pattern insertion circuit 13 ... Symbol mapping circuit 41 ... Differential detection circuit 42, 42B ... Identification circuit 43, 43B ... Reference signal storage circuit 44, 44B ... Pattern synchronization circuit 411, 412 ... Delay circuit 413 ... Complex conjugate Calculation circuit 414 ... Complex multiplication circuit 51 ... Pilot symbol position calculation circuit 52, 53 ... Selector

Claims (7)

In a transmission / reception system for transmitting / receiving optical signals,
A transmission / reception frame generation unit that generates a transmission / reception frame that includes a synchronization pattern composed of consecutive symbols and data to be transmitted and in which the synchronization pattern is arranged at equal intervals;
A transmission unit that converts the transmission / reception frame generated by the transmission / reception frame generation unit into an optical signal and transmits the optical signal;
A receiving unit that receives the optical signal transmitted by the transmitting unit, converts the received optical signal into an electrical signal, and generates one received digital signal sequence ;
A synchronization pattern synchronization unit for detecting the synchronization pattern included in the received digital signal sequence ;
The received digital signal sequence is divided into a plurality of parallel development lanes based on the position of the synchronization pattern detected by the synchronization pattern synchronization unit, and signal processing is performed in parallel on each of the divided received digital signal sequences. And a signal processing unit,
The transmission / reception frame generation unit includes:
If there are more than three amplitude levels in the modulation for the synchronization pattern, assign symbols other than the maximum amplitude level and the minimum amplitude level;
The transmission / reception system characterized by generating the transmission / reception frame having a symbol length which is an integral multiple of the number of the plurality of parallel development lanes. The transmission / reception system according to claim 1,
The transmission / reception frame generation unit generates the transmission / reception frame in which pilot symbols are arranged at intervals of a predetermined number of symbols from the synchronization pattern,
In the signal processing unit,
For each of the plurality of the received digital signal sequence is divided into parallel explosion lane, based on the position of the detected the synchronization pattern detecting said pilot symbols, based on the pilot symbols detected, divided the A transmission / reception system that performs phase compensation on a received digital signal sequence . The transmission / reception system according to claim 2,
The transmission / reception frame generation unit includes:
The pilot symbol is divided into two orthogonal components, and the synchronization pattern is arranged in each of the two components,
The synchronization pattern synchronization unit includes:
Detecting the synchronization pattern in each of the two components;
The signal processing unit
The transmission / reception system characterized by synchronizing the two components based on the position of the synchronization pattern in each of the two components detected by the synchronization pattern synchronization unit. In the transmission / reception system according to any one of claims 1 to 3,
The transmission / reception frame generation unit uses a pseudo random number bit string as the synchronization pattern. In the transmission / reception system according to any one of claims 1 to 4,
The transmission / reception frame generation unit includes:
A transmission / reception system using modulation that maps two symbols having a phase difference of 180 ° for the synchronization pattern. The transmission / reception system according to any one of claims 1 to 5,
The synchronization pattern synchronization unit includes:
Based on the hard decision result for the differential detection signals obtained by performing the differential detection of the synchronization pattern with respect to the received digital signal sequence, detecting the synchronization pattern included in said received digital signal sequence A characteristic transmission / reception system. A communication method in a transmission / reception system for transmitting / receiving an optical signal,
A transmission / reception frame generation step of generating a transmission / reception frame including a synchronization pattern composed of consecutive symbols and data to be transmitted, wherein the synchronization pattern is arranged at equal intervals; and
A transmission step of converting the transmission / reception frame generated in the transmission / reception frame generation step into an optical signal and transmitting the optical signal;
Receiving the optical signal transmitted in the transmitting step, and converting the received optical signal into an electrical signal to generate one received digital signal sequence ;
A synchronization pattern synchronization step of detecting the synchronization pattern included in the received digital signal sequence ;
A signal that divides the received digital signal sequence into a plurality of parallel development lanes based on the position of the synchronization pattern detected in the synchronization pattern synchronization step, and performs signal processing in parallel on each of the divided received digital signal sequences Processing steps and
In the transmission / reception frame generation step,
If there are more than three amplitude levels in the modulation for the synchronization pattern, assign symbols other than the maximum amplitude level and the minimum amplitude level;
The transmission / reception frame having a symbol length that is an integer multiple of the number of the plurality of parallel development lanes is generated.

Images