JP6124440B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP6124440B2
JP6124440B2 JP2013007485A JP2013007485A JP6124440B2 JP 6124440 B2 JP6124440 B2 JP 6124440B2 JP 2013007485 A JP2013007485 A JP 2013007485A JP 2013007485 A JP2013007485 A JP 2013007485A JP 6124440 B2 JP6124440 B2 JP 6124440B2
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base substrate
insulating layer
heat sink
semiconductor device
wiring
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JP2014138165A (en
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秀明 小長谷
秀明 小長谷
幸史 有岡
幸史 有岡
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Shindengen Electric Manufacturing Co Ltd
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Shindengen Electric Manufacturing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Description

本発明は半導体装置に関し、詳しくは、電子部品のグランドラインの技術に関する。   The present invention relates to a semiconductor device, and more particularly to a technology for a ground line of an electronic component.

従来の半導体装置、例えば車載用の電装装置の概要構成を図４に示す。図４に示す従来の半導体装置１０は、導電性のヒートシンク１１上に、絶縁層１２を介して導電性のベース基板１３が形成されている。そして、ベース基板１３の一面１３ａに絶縁層１４が形成され、この絶縁層１４に重ねて複数の半導体素子１５，１５、および配線層１６が所定のパターンで形成されている。絶縁層１４には、ベース基板１３の一面１３ａを露呈させる開口１７が形成され、この開口１７から導電性のベース基板１３が露呈されている。   FIG. 4 shows a schematic configuration of a conventional semiconductor device, for example, a vehicle-mounted electrical device. In the conventional semiconductor device 10 shown in FIG. 4, a conductive base substrate 13 is formed on a conductive heat sink 11 via an insulating layer 12. An insulating layer 14 is formed on one surface 13a of the base substrate 13, and a plurality of semiconductor elements 15, 15 and a wiring layer 16 are formed in a predetermined pattern on the insulating layer 14. An opening 17 is formed in the insulating layer 14 to expose the one surface 13 a of the base substrate 13, and the conductive base substrate 13 is exposed from the opening 17.

そして、それぞれの半導体素子１５のグランド端子は、接続配線１８を介して導電性のベース基板１３に接続されている。こうした構成の半導体装置１０は、断面積の大きい導電性のベース基板１３をグランド配線として利用することで、絶縁層１４上に別途、専用のグランド配線パターンを形成する必要が無く、寄生インダクタンスや配線抵抗を低減し、かつ製造工程を簡略化することができる（例えば、特許文献１参照）。   The ground terminal of each semiconductor element 15 is connected to the conductive base substrate 13 via the connection wiring 18. The semiconductor device 10 having such a configuration uses a conductive base substrate 13 having a large cross-sectional area as a ground wiring, so that it is not necessary to separately form a dedicated ground wiring pattern on the insulating layer 14, and parasitic inductance and wiring Resistance can be reduced and a manufacturing process can be simplified (for example, refer patent document 1).

特開２０１１−１１９４８９号公報JP 2011-119589 A

しかしながら、上述したような従来の半導体装置では、グランド配線を兼ねているベース基板１３と導電性のヒートシンク１１との間の絶縁性の確保が、必ずしも充分であるとは言えず、ベース基板１３と導電性のヒートシンク１１との間の絶縁性を更に向上させる構成が望まれていた。   However, in the conventional semiconductor device as described above, it cannot be said that the insulation between the base substrate 13 also serving as the ground wiring and the conductive heat sink 11 is sufficient. A configuration that further improves the insulation between the conductive heat sink 11 is desired.

本発明は上記課題に鑑みてなされたものであり、導電性のベース基板をグランド配線として利用する半導体装置において、ベース基板と、このベース基板に絶縁層を介して配された導電性のヒートシンクとの間の絶縁性を、より一層向上させることが可能な半導体装置を提供することを目的とする。   The present invention has been made in view of the above problems, and in a semiconductor device using a conductive base substrate as a ground wiring, a base substrate, and a conductive heat sink disposed on the base substrate via an insulating layer, An object of the present invention is to provide a semiconductor device capable of further improving the insulation between the two.

上記課題を解決するために、本発明のいくつかの態様は次のような半導体装置を提供した。すなわち、本発明の半導体装置は、導電性材料からなるヒートシンクと、該ヒートシンクの一面に重ねて配された第一絶縁層と、該第一絶縁層に重ねて配され、導電性材料からなるベース基板と、該ベース基板の一面に重ねて配された第二絶縁層と、該第二絶縁層に重ねて配された配線層および半導体素子と、を備えた半導体装置であって、前記ベース基板の前記ヒートシンク側における周縁領域には、前記ヒートシンクと対向する他面および該他面に垂直な周面が交わる角部を面取りした形状を成す面取部と、前記第二絶縁層の一部を切り欠いて前記ベース基板の一面を露呈させる開口と、前記半導体素子のグランド端子を、前記開口によって露呈された前記ベース基板の一面に接続させる接続配線と、を備え、前記第一絶縁層は、前記面取部全体を覆うように形成され、かつ、前記半導体素子よりも上方の高さまで延長されており、前記ベース基板をグランド配線にしたことを特徴とする。 In order to solve the above problems, some embodiments of the present invention provide the following semiconductor device. That is, the semiconductor device of the present invention includes a heat sink made of a conductive material, a first insulating layer arranged on one surface of the heat sink, and a base made of a conductive material arranged on the first insulating layer. A semiconductor device comprising: a substrate; a second insulating layer disposed on one surface of the base substrate; and a wiring layer and a semiconductor element disposed on the second insulating layer, wherein the base substrate In the peripheral region on the heat sink side, a chamfered portion formed by chamfering a corner portion where the other surface facing the heat sink and a peripheral surface perpendicular to the other surface intersect, and a part of the second insulating layer are provided. An opening that exposes one surface of the base substrate by notching, and a connection wiring that connects a ground terminal of the semiconductor element to the one surface of the base substrate exposed by the opening, and the first insulating layer includes: Said surface It is formed so as to cover the whole part, and the being extended to above the height than the semiconductor element, and characterized in that said base substrate to the ground line.

前記第一絶縁層には、該第一絶縁層と前記ヒートシンクとを機械的に係合させる係合部材を挿入する係合穴が更に形成されていることを特徴とする。   The first insulating layer further includes an engagement hole into which an engagement member for mechanically engaging the first insulating layer and the heat sink is inserted.

前記半導体素子は、前記配線層に重ねて形成されていることを特徴とする。   The semiconductor element is formed so as to overlap the wiring layer.

前記面取部は、前記他面と前記周面との間で所定の角度で傾斜した傾斜面であることを特徴とする。   The chamfered portion is an inclined surface that is inclined at a predetermined angle between the other surface and the peripheral surface.

前記面取部は、前記他面と前記周面との間で断面円弧状に湾曲した湾曲面であることを特徴とする。   The chamfered portion is a curved surface curved in a circular arc shape between the other surface and the peripheral surface.

本発明の半導体装置によれば、導電性のベース基板の周縁領域に面取部を形成し、ベース基板がヒートシンクと対向する他面側の周縁領域を、導電性のヒートシンクの一面から遠ざかるように離間させた。これにより、ベース基板の周面とヒートシンクの一面との間には所定のギャップが形成されるため、ベース基板の周縁領域とヒートシンクの一面との間の絶縁性を、より一層向上させることが可能になる。よって、グランド配線（ベース基板）の絶縁性を高めた信頼性の高い半導体装置を実現することができる。   According to the semiconductor device of the present invention, the chamfered portion is formed in the peripheral region of the conductive base substrate, and the peripheral region on the other surface side where the base substrate faces the heat sink is moved away from one surface of the conductive heat sink. Separated. As a result, a predetermined gap is formed between the peripheral surface of the base substrate and one surface of the heat sink, so that the insulation between the peripheral region of the base substrate and one surface of the heat sink can be further improved. become. Therefore, a highly reliable semiconductor device with improved insulation of the ground wiring (base substrate) can be realized.

本発明の第一実施形態における半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device in 1st embodiment of this invention. 本発明の第二実施形態における半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device in 2nd embodiment of this invention. 本発明の第三実施形態における半導体装置を示す要部断面図である。It is principal part sectional drawing which shows the semiconductor device in 3rd embodiment of this invention. 従来の半導体装置の一例を示す断面図である。It is sectional drawing which shows an example of the conventional semiconductor device. 導電体の離間距離と絶縁耐圧との関係を示すグラフである。It is a graph which shows the relationship between the separation distance of a conductor, and a withstand voltage.

以下、図面を参照して、本発明に係る半導体装置の一実施形態について説明する。なお、本実施形態は、発明の趣旨をより良く理解させるために具体的に説明するものであり、特に指定のない限り、本発明を限定するものではない。また、以下の説明で用いる図面は、本発明の特徴をわかりやすくするために、便宜上、要部となる部分を拡大して示している場合があり、各構成要素の寸法比率などが実際と同じであるとは限らない。   Hereinafter, an embodiment of a semiconductor device according to the present invention will be described with reference to the drawings. The present embodiment is specifically described for better understanding of the gist of the invention, and does not limit the invention unless otherwise specified. In addition, in the drawings used in the following description, in order to make the features of the present invention easier to understand, there is a case where a main part is shown in an enlarged manner for convenience, and the dimensional ratio of each component is the same as the actual one. Not necessarily.

（第一実施形態）
本発明の半導体装置の一実施形態を図１に示す。半導体装置２０は、例えば、アルミニウムや銅などからなる導電性のヒートシンク２１と、このヒートシンク２１の一面２１ａ上に、第一絶縁層２２を介して配された導電性のベース基板２３とを備えている。第一絶縁層２２は、例えば、ヒートシンク２１とベース基板２３とを接合する接着性および絶縁性をもつ樹脂や、絶縁性セラミックスなどから構成されればよい。ベース基板２３は、例えば、アルミニウムや銅などの導電体から構成されればよい。 (First embodiment)
One embodiment of the semiconductor device of the present invention is shown in FIG. The semiconductor device 20 includes a conductive heat sink 21 made of, for example, aluminum or copper, and a conductive base substrate 23 disposed on one surface 21 a of the heat sink 21 via a first insulating layer 22. Yes. The first insulating layer 22 may be made of, for example, a resin having adhesiveness and insulating properties for joining the heat sink 21 and the base substrate 23, insulating ceramics, or the like. The base substrate 23 may be made of a conductor such as aluminum or copper.

ベース基板２３の一面２３ａには第二絶縁層２４が形成されている。第一絶縁層２２は、例えば、フォトリソグラフィーによって所定の形状に形成した絶縁性のレジスト層などであればよい。そして、この第二絶縁層２４に重ねて、複数の半導体素子２５，２５・・、および配線層２６が所定のパターンで形成されている。   A second insulating layer 24 is formed on one surface 23 a of the base substrate 23. The first insulating layer 22 may be an insulating resist layer formed in a predetermined shape by photolithography, for example. A plurality of semiconductor elements 25, 25... And a wiring layer 26 are formed in a predetermined pattern so as to overlap the second insulating layer 24.

第二絶縁層２４には、ベース基板２３の一面２３ａを露呈させる開口２７が形成され、この開口２７から導電性のベース基板２３の一面２３ａが露呈されている。それぞれの半導体素子２５のグランド端子は、接続配線２８を介して、開口２７によって露呈された導電性のベース基板２３に接続されている。これにより、導電性のベース基板２３は、複数の半導体素子２５，２５・・や、接続配線２８を支持する支持体としての機能に加えて、グランド配線としても作用する。よって、それぞれの半導体素子２５，２５・・のグランド端子を接続するためのグランド配線を、第二絶縁層２４上に形成する必要がない。   The second insulating layer 24 has an opening 27 that exposes one surface 23 a of the base substrate 23, and the one surface 23 a of the conductive base substrate 23 is exposed from the opening 27. The ground terminal of each semiconductor element 25 is connected to the conductive base substrate 23 exposed through the opening 27 via the connection wiring 28. Thus, the conductive base substrate 23 functions as a ground wiring in addition to the function as a support for supporting the plurality of semiconductor elements 25, 25... And the connection wiring 28. Therefore, it is not necessary to form ground wiring on the second insulating layer 24 for connecting the ground terminals of the respective semiconductor elements 25, 25.

ベース基板２３のヒートシンク２１側における周縁領域には、ヒートシンク２１と対向する他面２３ｂおよび他面２３ｂに垂直な周面２３ｃが交わる角部を面取りした形状を成す面取部２９が形成されている。こうした面取部２９は、本実施形態においては、ベース基板２３の他面２３ｂと周面２３ｃとの間で所定の角度で傾斜した傾斜面として形成されている。   In the peripheral region on the heat sink 21 side of the base substrate 23, a chamfered portion 29 having a chamfered shape at the corner where the other surface 23b facing the heat sink 21 and the peripheral surface 23c perpendicular to the other surface 23b intersect is formed. . In the present embodiment, the chamfered portion 29 is formed as an inclined surface that is inclined at a predetermined angle between the other surface 23b of the base substrate 23 and the peripheral surface 23c.

こうした傾斜面は、加工性を考慮して、ヒートシンク２１の一面２１ａに対して、例えば４０°〜５０°の傾斜範囲で一律に傾斜していればよい。第一絶縁層２２は、ベース基板２３がヒートシンク２１と対向する他面２３ｂ全体を少なくとも覆い、更にこうした面取部２９までを覆うように延在していることがより好ましい。   Such an inclined surface should just incline in the inclination range of 40 degrees-50 degrees, for example with respect to the one surface 21a of the heat sink 21 in consideration of workability. More preferably, the first insulating layer 22 extends so that the base substrate 23 covers at least the entire other surface 23 b facing the heat sink 21 and further covers such a chamfered portion 29.

以上のような構成の半導体装置２０の作用、効果を説明する。半導体装置２０は、第二絶縁層２４にベース基板２３の一面２３ａを露呈させる開口２７を形成して、接続配線２８を介してベース基板２３と半導体素子２５のグランド端子とを接続した。これにより、導電性のベース基板２３はグランド配線として作用する。   The operation and effect of the semiconductor device 20 configured as described above will be described. In the semiconductor device 20, an opening 27 that exposes one surface 23 a of the base substrate 23 is formed in the second insulating layer 24, and the base substrate 23 and the ground terminal of the semiconductor element 25 are connected via the connection wiring 28. Thereby, the conductive base substrate 23 acts as a ground wiring.

ベース基板２３をグランド配線として用いることで、複数の半導体素子２５，２５や配線層２６の間の狭い空間を縫うようにグランド配線層を第二絶縁層２４上に形成する必要がなく、半導体素子２５，２５や配線層２６のレイアウト上の制約を少なくすることができる。また、ベース基板２３は、従来のようなベース基板上にレイアウトされるグランド配線よりも、大幅にその断面積が大きいため、半導体装置のオン抵抗値や寄生インダクタンスの低減を実現することが可能になる。   By using the base substrate 23 as the ground wiring, it is not necessary to form a ground wiring layer on the second insulating layer 24 so as to sew a narrow space between the plurality of semiconductor elements 25, 25 and the wiring layer 26, and the semiconductor element 25, 25 and the layout restrictions of the wiring layer 26 can be reduced. Further, since the cross-sectional area of the base substrate 23 is significantly larger than that of the ground wiring laid out on the base substrate as in the prior art, it is possible to reduce the on-resistance value and the parasitic inductance of the semiconductor device. Become.

本発明では、このようにベース基板２３をグランド配線として作用させる際に、導電性のベース基板２３の周縁領域に面取部２９を形成することによって、ベース基板２３の周縁領域とヒートシンク２１の一面２１ａとの間での絶縁性をより一層向上させる。即ち、ベース基板２３をグランド配線として利用する場合、上述したように寄生インダクタンスの低減などの効果を得ることができるが、一方で、従来のように、ベース基板の端部まで絶縁層を介してヒートシンクと接していると、この端部（周縁領域）において、グランド配線として作用するベース基板と、導電性のヒートシンクとの間で、絶縁性が高く保たれない懸念がある。   In the present invention, when the base substrate 23 acts as a ground wiring in this way, the chamfered portion 29 is formed in the peripheral region of the conductive base substrate 23, so that the peripheral region of the base substrate 23 and one surface of the heat sink 21 Insulation with 21a is further improved. That is, when the base substrate 23 is used as the ground wiring, the effect of reducing the parasitic inductance can be obtained as described above. On the other hand, as in the conventional case, the end of the base substrate is interposed through the insulating layer. When in contact with the heat sink, there is a concern that in this end portion (peripheral region), the insulating property cannot be kept high between the base substrate acting as the ground wiring and the conductive heat sink.

そこで、本発明では、上述したように導電性のベース基板２３の周縁領域に面取部２９を形成し、ベース基板２３がヒートシンク２１と対向する他面２３ｂ側の周縁領域を、導電性のヒートシンク２１の一面２１ａから遠ざかるように離間させた。こうした構成とすることにより、例えば、第一絶縁層２２の厚みを薄く形成したとしても、ベース基板２３の周面２３ｃの下端とヒートシンク２１の一面２１ａとの間には所定のギャップが形成されるため、絶縁性が低くなる懸念があるベース基板２３の周縁領域とヒートシンク２１の一面２１ａとの間の絶縁性を、より一層向上させることが可能になる。これにより、グランド配線（ベース基板３０）の絶縁性を高めた信頼性の高い半導体装置２０を実現することができる。   Therefore, in the present invention, as described above, the chamfered portion 29 is formed in the peripheral region of the conductive base substrate 23, and the peripheral region on the other surface 23 b side where the base substrate 23 faces the heat sink 21 is defined as the conductive heat sink. 21 so as to be away from the one surface 21a. With this configuration, for example, even if the first insulating layer 22 is formed thin, a predetermined gap is formed between the lower end of the peripheral surface 23 c of the base substrate 23 and the one surface 21 a of the heat sink 21. Therefore, it is possible to further improve the insulation between the peripheral region of the base substrate 23 and the one surface 21a of the heat sink 21 where there is a concern that the insulation may be lowered. Thereby, the highly reliable semiconductor device 20 in which the insulation of the ground wiring (base substrate 30) is improved can be realized.

導電性のベース基板２３と、導電性のヒートシンク２１との離間距離に応じた、絶縁耐圧の変化を図５に示す。このグラフによれば、導電体どうしの離間距離を０．１ｍｍ広げていくだけで、絶縁耐圧は数百Ｖづつ大幅に増加することが分かる。よって、ベース基板２３がヒートシンク２１と対向する他面２３ｂ側の周縁領域を、導電性のヒートシンク２１の一面２１ａから遠ざかるように傾斜面を形成して離間させることで、ベース基板２３のエッジ部分の絶縁性が大幅に向上する。   FIG. 5 shows changes in the withstand voltage according to the separation distance between the conductive base substrate 23 and the conductive heat sink 21. According to this graph, it can be seen that the withstand voltage greatly increases by several hundred V only by increasing the distance between the conductors by 0.1 mm. Therefore, the peripheral region on the side of the other surface 23 b where the base substrate 23 faces the heat sink 21 is formed by forming an inclined surface away from the one surface 21 a of the conductive heat sink 21, so that the edge portion of the base substrate 23 is separated. Insulation is greatly improved.

なお、本実施形態においては、第一絶縁層２２は、ベース基板２３がヒートシンク２１と対向する他面２３ｂ全体から面取部２９までを覆うように形成されているが、更に、この面取部２９から周面２３ｃまで覆うようにすることも好ましい。また、第一絶縁層２２は、ベース基板２３がヒートシンク２１と対向する他面２３ｂ全体を覆いつつ、面取部２９を覆わない構成であってもよい。   In the present embodiment, the first insulating layer 22 is formed so that the base substrate 23 covers the entire other surface 23b facing the heat sink 21 to the chamfered portion 29. It is also preferable to cover from 29 to the peripheral surface 23c. The first insulating layer 22 may have a configuration in which the base substrate 23 covers the entire other surface 23 b facing the heat sink 21, but does not cover the chamfered portion 29.

（第二実施形態）
以下、本発明の第２実施形態について、図２を用いて説明する。図２は、第２実施形態の半導体装置を示す断面図である。なお、図２において、図１に示した第１実施形態の半導体装置２０と同一の構成要素には同一符号を付して、その説明を省略する。
本実施形態の半導体装置３０では、ベース基板２３のヒートシンク２１側における周縁領域に、ヒートシンク２１と対向する他面２３ｂおよび他面２３ｂに垂直な周面２３ｃが交わる角部を面取りした形状を成す面取部３９が形成されている。面取部３９は、断面円弧状に湾曲した湾曲面となるように形成されている。なお、この実施形態では、第一絶縁層３２は、ベース基板２３がヒートシンク２１と対向する他面２３ｂ全体を覆い、湾曲面を成す面取部３９は覆わない構成となっているが、第一絶縁層２２を更に延長してこの湾曲面を成す面取部３９まで覆う構成とすることも好ましい。 (Second embodiment)
Hereinafter, a second embodiment of the present invention will be described with reference to FIG. FIG. 2 is a cross-sectional view showing the semiconductor device of the second embodiment. In FIG. 2, the same components as those of the semiconductor device 20 according to the first embodiment shown in FIG.
In the semiconductor device 30 of the present embodiment, a surface formed by chamfering a corner portion where the other surface 23b facing the heat sink 21 and the peripheral surface 23c perpendicular to the other surface 23b intersect with the peripheral region on the heat sink 21 side of the base substrate 23. A take-up portion 39 is formed. The chamfered portion 39 is formed to be a curved surface curved in a circular arc shape in cross section. In this embodiment, the first insulating layer 32 has a configuration in which the base substrate 23 covers the entire other surface 23b facing the heat sink 21 and does not cover the chamfered portion 39 forming the curved surface. It is also preferable to further extend the insulating layer 22 to cover the chamfered portion 39 that forms this curved surface.

本実施形態のように、導電性のベース基板２３の周縁領域に、断面円弧状に湾曲した湾曲面からなる面取部３９を形成しても、ベース基板２３の周面２３ｃの下端とヒートシンク２１の一面２１ａとの間には所定のギャップが形成されるため、絶縁性が低くなる懸念があるベース基板２３の周縁領域とヒートシンク２１の一面２１ａとの間の絶縁性を、より一層向上させることが可能になる。   Even if the chamfered portion 39 formed of a curved surface curved in a circular arc shape is formed in the peripheral region of the conductive base substrate 23 as in the present embodiment, the lower end of the peripheral surface 23c of the base substrate 23 and the heat sink 21 are formed. Since a predetermined gap is formed between the first surface 21a and the first surface 21a, the insulating property between the peripheral region of the base substrate 23 and the first surface 21a of the heat sink 21 may be further improved. Is possible.

（第三実施形態）
以下、本発明の第３実施形態について、図３を用いて説明する。図３は、第３実施形態の半導体装置を示す要部断面図である。なお、図３において、図１に示した第１実施形態の半導体装置２０と同一の構成要素には同一符号を付して、その説明を省略する。半導体装置４０は、導電性のヒートシンク４１と、このヒートシンク４１の一面４１ａ上に、第一絶縁層４２を介して配された導電性のベース基板４３とを備えている。 (Third embodiment)
Hereinafter, a third embodiment of the present invention will be described with reference to FIG. FIG. 3 is a fragmentary cross-sectional view showing the semiconductor device of the third embodiment. In FIG. 3, the same components as those of the semiconductor device 20 according to the first embodiment shown in FIG. The semiconductor device 40 includes a conductive heat sink 41 and a conductive base substrate 43 disposed on one surface 41 a of the heat sink 41 via a first insulating layer 42.

ベース基板４３の一面４３ａには第二絶縁層４４が形成され、この第二絶縁層４４に重ねて、半導体素子２５および配線層２６が所定のパターンで形成されている。第二絶縁層４４には、ベース基板４３の一面４３ａを露呈させる開口４７が形成され、ベース基板４３の一面４３ａと半導体素子２５のグランド端子とが、接続配線２８を介して電気的に接続される。   A second insulating layer 44 is formed on one surface 43 a of the base substrate 43, and the semiconductor element 25 and the wiring layer 26 are formed in a predetermined pattern on the second insulating layer 44. The second insulating layer 44 is formed with an opening 47 that exposes one surface 43 a of the base substrate 43, and the one surface 43 a of the base substrate 43 and the ground terminal of the semiconductor element 25 are electrically connected via the connection wiring 28. The

ベース基板４３のヒートシンク４１側における周縁領域には、ヒートシンク４１と対向する他面４３ｂおよび他面４３ｂに垂直な周面４３ｃが交わる角部を面取りした傾斜面を成す面取部４９が形成されている。   In the peripheral region on the heat sink 41 side of the base substrate 43, a chamfered portion 49 that forms an inclined surface with chamfered corners where the other surface 43b facing the heat sink 41 and the peripheral surface 43c perpendicular to the other surface 43b intersect is formed. Yes.

本実施形態においては、第一絶縁層４２は、絶縁性ケースを構成している。即ち、第一絶縁層４２は、ベース基板４３がヒートシンク２１と対向する他面４３ｂ全体を覆い、更に周縁領域で肉厚に形成され、傾斜面を成す面取部４９から他面４３ｂに垂直な周面４３ｃまでを覆い、更に、半導体素子２５よりも上方の高さまで延長されている。これにより、ベース基板４３から半導体素子２５や配線層２６を封止する封止樹脂層５１が形成される。   In the present embodiment, the first insulating layer 42 constitutes an insulating case. In other words, the first insulating layer 42 covers the entire other surface 43b facing the heat sink 21 with the base substrate 43, and is formed thick in the peripheral region, and is perpendicular to the other surface 43b from the chamfered portion 49 forming the inclined surface. It covers up to the peripheral surface 43 c and further extends to a height above the semiconductor element 25. Thereby, a sealing resin layer 51 that seals the semiconductor element 25 and the wiring layer 26 from the base substrate 43 is formed.

また、絶縁性ケースとして肉厚に形成された第一絶縁層４２の周縁部には、ねじ穴５２が形成されている。また、ヒートシンク４１には、このねじ穴５２と合致する位置に、ねじ受け５３が形成されている。こうした構成によって、例えば、ボルト５４をねじ穴５２からねじ受け５３まで挿入して締め付けることにより、半導体素子２５や配線層２６が実装されたベース基板４３と、ヒートシンク４１とを機械的に締結することができる。こうした構成において、ねじ穴５２を絶縁性ケースである第一絶縁層４２の肉厚な周縁部に形成することによって、ボルト５４が金属など導電性材料であっても、ベース基板４３と、ヒートシンク４１との絶縁性を確実に確保することができる。   A screw hole 52 is formed in the peripheral edge portion of the first insulating layer 42 formed thick as an insulating case. The heat sink 41 is formed with a screw receiver 53 at a position matching the screw hole 52. With such a configuration, for example, the base board 43 on which the semiconductor element 25 and the wiring layer 26 are mounted and the heat sink 41 are mechanically fastened by inserting and tightening the bolt 54 from the screw hole 52 to the screw receiver 53. Can do. In such a configuration, the screw hole 52 is formed in the thick peripheral portion of the first insulating layer 42 that is an insulating case, so that the base substrate 43 and the heat sink 41 can be formed even if the bolt 54 is a conductive material such as metal. It is possible to reliably ensure insulation.

２０…半導体装置、２１…ヒートシンク、２２…第一絶縁層、２３…ベース基板、２４…第二絶縁層、２５…半導体素子、２６…配線層、２７…開口、２９…面取部。   DESCRIPTION OF SYMBOLS 20 ... Semiconductor device, 21 ... Heat sink, 22 ... 1st insulating layer, 23 ... Base substrate, 24 ... 2nd insulating layer, 25 ... Semiconductor element, 26 ... Wiring layer, 27 ... Opening, 29 ... Chamfering part.

Claims (5)

導電性材料からなるヒートシンクと、該ヒートシンクの一面に重ねて配された第一絶縁層と、該第一絶縁層に重ねて配され、導電性材料からなるベース基板と、該ベース基板の一面に重ねて配された第二絶縁層と、該第二絶縁層に重ねて配された配線層および半導体素子と、を備えた半導体装置であって、
前記ベース基板の前記ヒートシンク側における周縁領域には、前記ヒートシンクと対向する他面および該他面に垂直な周面が交わる角部を面取りした形状を成す面取部と、前記第二絶縁層の一部を切り欠いて前記ベース基板の一面を露呈させる開口と、前記半導体素子のグランド端子を、前記開口によって露呈された前記ベース基板の一面に接続させる接続配線と、を備え、
前記第一絶縁層は、前記面取部全体を覆うように形成され、かつ、前記半導体素子よりも上方の高さまで延長されており、
前記ベース基板をグランド配線にしたことを特徴とする半導体装置。 A heat sink made of a conductive material, a first insulating layer disposed on one surface of the heat sink, a base substrate disposed on the first insulating layer and made of a conductive material, and on one surface of the base substrate A semiconductor device comprising: a second insulating layer disposed to overlap; a wiring layer and a semiconductor element disposed to overlap the second insulating layer;
In the peripheral region on the heat sink side of the base substrate, a chamfered portion formed by chamfering a corner portion where the other surface facing the heat sink and a peripheral surface perpendicular to the other surface intersect, and the second insulating layer An opening that exposes one surface of the base substrate by cutting out a portion thereof, and a connection wiring that connects a ground terminal of the semiconductor element to the one surface of the base substrate exposed by the opening ,
The first insulating layer is formed so as to cover the entire chamfered portion, and is extended to a height above the semiconductor element,
A semiconductor device, wherein the base substrate is a ground wiring. 前記第一絶縁層には、該第一絶縁層と前記ヒートシンクとを機械的に係合させる係合部材を挿入する係合穴が更に形成されていることを特徴とする請求項１記載の半導体装置。   2. The semiconductor according to claim 1, wherein the first insulating layer is further formed with an engagement hole into which an engagement member for mechanically engaging the first insulating layer and the heat sink is inserted. apparatus. 前記半導体素子は、前記配線層に重ねて形成されていることを特徴とする請求項１または２記載の半導体装置。 The semiconductor device, the semiconductor device according to claim 1 or 2, wherein the formed overlaid on the wiring layer. 前記面取部は、前記他面と前記周面との間で所定の角度で傾斜した傾斜面であることを特徴とする請求項１ないし３いずれか１項記載の半導体装置。 The chamfered portion, the other surface of the semiconductor device of claims 1, wherein 3 wherein any one that is an inclined surface inclined at a predetermined angle between said circumferential surface. 前記面取部は、前記他面と前記周面との間で断面円弧状に湾曲した湾曲面であることを特徴とする請求項１ないし３いずれか１項記載の半導体装置。 The chamfered portion, the semiconductor device of claims 1, wherein 3 according any one to be a curved surface curved in an arc-shaped cross section between said other surface and the circumferential surface.
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