JP6119454B2 - Method for manufacturing semiconductor device and method for measuring semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device and a method for measuring a semiconductor device.

  Conventionally, a technique for measuring a channel region of a transistor has been proposed.

  For example, in a P-type MOS transistor, the carrier mobility is improved by applying a compressive stress to the channel region, while in the N-type MOS transistor, the carrier mobility is improved by applying a tensile stress to the channel region. It has been known.

  Therefore, there is a strained silicon technique as a method for intentionally applying stress to the channel region to improve the operation speed of the transistor. This is a technique for improving the current driving capability by applying a stress to the channel region to change the band structure, reduce the effective mass of the carrier, and improve the carrier mobility.

  The state of the channel region to which such stress is applied is measured as the amount of strain in the channel region using, for example, Raman scattering spectroscopy.

  In Raman scattering spectroscopy, the amount of distortion of the crystal lattice can be measured nondestructively by examining the amount of wave number shift of the scattered light scattered in the channel region with respect to the incident light. For example, the amount of crystal distortion can be measured with a spatial resolution of several hundreds of nanometers by using microscopic Raman scattering spectroscopy.

  In particular, the amount of strain in the channel region is also measured for transistors that do not use the strained silicon technology in order to measure carrier mobility.

Special table 2009-518869 JP 2009-32962 A

Phys. Rev. B, 15 February, 1972, Vol. 4,1440-1454 Journal of Surface Analysis, Vol. 8, no. 1,2001, 9-16

  Usually, an impurity element having P-type or N-type polarity is implanted into the channel region in order to adjust the threshold value.

  It is known that the impurity element injected into the crystal affects the wave number shift amount measured by Raman scattering spectroscopy.

  For example, even with crystals having the same lattice constant, if the concentration of the impurity element is different, the amount of wave number shift is different, so that the correct amount of distortion may not be measured.

  Therefore, an object of the present specification is to provide a method for manufacturing a semiconductor device that can measure the amount of strain without being affected by impurities.

  Another object of the present specification is to provide a method for measuring a semiconductor device that can measure the amount of strain without being affected by impurities.

  According to one embodiment of the method for manufacturing a semiconductor device disclosed in the present specification, a first channel formed on a silicon substrate and having a first source / drain disposed on both sides of the first channel. A method of manufacturing a semiconductor device, comprising: a second element having one element, a second channel, and a second source / drain disposed on both sides of the second channel, wherein the second element is formed. A first mask is formed on the second element formation region, and a first polarity is applied to the second element formation region covered with the first mask and the first channel formation region where the first channel is formed. A second step of implanting impurities, a first source / drain formation region where the first source / drain is formed, and a second source / drain formation region where the second source / drain is formed. polarity A second step of implanting impurities to form the first source / drain and the second source / drain, and forming a silicide layer on each of the first source / drain and the second source / drain. And a third step.

Further, according to one mode of the method for measuring a semiconductor device disclosed in the present specification, the first channel formed on the silicon substrate, and the first source / drain disposed on both sides of the first channel, A method of measuring a semiconductor device comprising: a first element having a first element; a second channel; and a second element having a second source / drain disposed on both sides of the second channel,
In the semiconductor device, a first mask is formed on a second element formation region in which the second element is formed, and the second element formation region and the first channel covered with the first mask are formed. A first step of implanting an impurity having a first polarity into the first channel formation region, a first source / drain formation region in which the first source / drain is formed, and a second source / drain are formed. A second step of implanting an impurity having a second polarity into each of the second source / drain formation regions to form the first source / drain and the second source / drain; and the first source / drain and the above It is manufactured using a third step of forming a silicide layer on each of the second source / drain, and the strain in the first channel is measured by measuring the strain in the second channel. To estimate.

  According to one embodiment of the method for manufacturing a semiconductor device disclosed in this specification, the strain amount of the manufactured semiconductor device can be measured without being affected by impurities.

  Further, according to one embodiment of the method for measuring a semiconductor device disclosed in this specification, the strain amount of the semiconductor device can be measured without being affected by impurities.

  The objects and advantages of the invention will be realized and obtained by means of the elements and combinations particularly pointed out in the appended claims.

  Both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention as claimed.

It is a figure showing one embodiment of a semiconductor device indicated to this specification. It is a figure which shows the silicon substrate with which the semiconductor device disclosed in this specification was formed. It is a figure which shows the process (the 1) of one Embodiment of the manufacturing method of the semiconductor device disclosed to this specification. It is a figure which shows the process (the 2) of one Embodiment of the manufacturing method of the semiconductor device disclosed to this specification. It is a figure which shows the process (the 3) of one Embodiment of the manufacturing method of the semiconductor device disclosed to this specification. It is a figure which shows the process (the 4) of one Embodiment of the manufacturing method of the semiconductor device disclosed to this specification. It is a figure which shows the process (the 5) of one Embodiment of the manufacturing method of the semiconductor device disclosed to this specification. It is a figure which shows the process (the 6) of one Embodiment of the manufacturing method of the semiconductor device disclosed to this specification. It is a figure which shows the process (the 7) of one Embodiment of the manufacturing method of the semiconductor device disclosed to this specification. It is a figure which shows the process (the 8) of one Embodiment of the manufacturing method of the semiconductor device disclosed to this specification. It is a figure which shows the process (the 9) of one Embodiment of the manufacturing method of the semiconductor device disclosed to this specification. It is a figure which shows the process (the 10) of one Embodiment of the manufacturing method of the semiconductor device disclosed to this specification. It is a figure which shows the process (the 11) of one Embodiment of the manufacturing method of the semiconductor device disclosed to this specification. It is a figure which shows the process (the 12) of one Embodiment of the manufacturing method of the semiconductor device disclosed to this specification. It is a figure which shows the process (the 13) of one Embodiment of the manufacturing method of the semiconductor device disclosed to this specification. It is a figure which shows the process (the 14) of one Embodiment of the manufacturing method of the semiconductor device disclosed to this specification. 3 is a flowchart of an embodiment of a method for measuring a semiconductor device disclosed in the specification.

  Hereinafter, a preferred embodiment of a semiconductor device disclosed in this specification will be described with reference to the drawings. However, the technical scope of the present invention is not limited to these embodiments, but extends to the invention described in the claims and equivalents thereof.

  FIG. 1 is a diagram illustrating an embodiment of a semiconductor device disclosed in this specification. FIG. 2 is a diagram illustrating a silicon substrate on which the semiconductor device disclosed in this specification is formed.

  The semiconductor device 10 includes a first device region T1 and a second device region T2 where transistors are formed, and a first monitor region M1 and a second monitor region M2 for measuring the amount of distortion. The first device region T1 and the second device region T2, and the first monitor region M1 and the second monitor region M2 are formed on the same silicon substrate 11.

  The first monitor region M1 is a region formed for estimating the amount of distortion in the first device region T1, and the second monitor region M2 is formed for estimating the amount of distortion in the second device region T2. It is an area.

  As shown in FIG. 2, the first device region T <b> 1 and the second device region T <b> 2 are disposed on a circuit formation region 30 where circuit elements and the like are formed on the silicon substrate 11. The first monitor region M1 and the second monitor region M2 are arranged in the monitor region 31 on the silicon substrate 11. The monitor region 31 is preferably disposed in the scribe region between the circuit formation region 30 and the circuit formation region 30 on the silicon substrate 11 from the viewpoint of not reducing the element density of the circuit formation region 30. The monitor area 31 may be disposed in the circuit formation area 30. The first monitor area M1 and the second monitor area M2 may not be arranged in the same monitor area 31.

  An N-type MOS transistor 1a is arranged in the first device region T1. N-type MOS transistor 1a has P-type channel region A1 implanted with P-type impurities and N-type source / drain regions B1 arranged on both sides of P-type channel region A1.

  A P-type MOS transistor 1b is disposed in the second device region T2. P-type MOS transistor 1b has an N-type channel region A2 into which an N-type impurity has been implanted, and a P-type source / drain region B2 disposed on both sides of N-type channel region A2.

  A CMOS transistor can be formed by the N-type MOS transistor 1a and the P-type MOS transistor 1b.

  An N-type MOS transistor 1c is arranged in the first monitor region M1. N-type MOS transistor 1c has a monitor channel region C1 into which no impurity is implanted, and N-type source / drain regions D1 arranged on both sides of monitor channel region C1. N-type MOS transistor 1c is formed such that the stress state of monitor channel region C1 is the same as that of P-type channel region A1 of N-type MOS transistor 1a. That is, the distortion amount of the monitor channel region C1 is the same as that of the P-type channel region A1.

  A P-type MOS transistor 1d is arranged in the second monitor region M2. P-type MOS transistor 1d has a monitor channel region C2 into which no impurity is implanted, and a P-type source / drain region D2 arranged on both sides of monitor channel region C2. The P-type MOS transistor 1d is formed so that the stress state of the monitor channel region C2 is the same as that of the N-type channel region A2 of the P-type MOS transistor 1b. That is, the distortion amount of the monitor channel region C2 is the same as that of the N-type channel region A2.

  Since impurities are not implanted into the monitor channel regions C1 and C2, the amount of crystal distortion can be accurately measured using Raman scattering spectroscopy.

  The strain amount of the P-type channel region A1 of the N-type MOS transistor 1a can be estimated based on the strain amount of the monitor channel region C1 of the N-type MOS transistor 1c into which no impurity is implanted. Specifically, the amount of distortion in the monitor channel region C1 of the N-type MOS transistor 1c is measured using Raman scattering spectroscopy, and the measured amount of distortion is estimated to be the amount of distortion in the monitor channel region C1. .

  As described above, by estimating the strain amount of the P-type channel region A1 into which the impurity is implanted based on the measured value of the monitor channel region C1, the strain amount of the P-type channel region A1 without being affected by the impurity. Can be obtained.

  Similarly, the strain amount of the N-type channel region A2 of the P-type MOS transistor 1b can be estimated based on the strain amount of the monitor channel region C2 of the P-type MOS transistor 1d into which no impurity is implanted. Specifically, the amount of distortion in the monitor channel region C2 of the P-type MOS transistor 1d is measured using Raman scattering spectroscopy, and the measured amount of distortion is estimated to be the amount of distortion in the N-type channel region A2. The

  As described above, by estimating the strain amount of the N-type channel region A2 into which the impurity is implanted based on the measured value of the monitor channel region C2, the strain amount of the N-type channel region A2 without being affected by the impurity. Can be obtained.

  Next, the structure of the transistor disposed in each region will be further described.

  First, the N-type MOS transistor 1a disposed in the first device region T1 will be described. The P-type MOS transistor 1b arranged in the second device region T2 has the same structure as the N-type MOS transistor 1a except that the polarity is different. The same applies to the case.

  As shown in FIG. 1, a first device region T <b> 1 defined by an element isolation layer 12 is disposed on a single crystal silicon substrate 11. The first device region T1 has a P-type well 13a having P-type polarity, and a P-type MOS transistor 1b is disposed in the P-type well 13a.

  On the silicon substrate 11, a gate insulating film 14a is arranged corresponding to the P-type channel region A1. The gate insulating film 14a is formed of, for example, a silicon oxide film or a silicon oxynitride film. The P-type channel region A1 is a region sandwiched between two N-type source / drain regions B1, and is a region where the flow of carriers is controlled by an electric field applied from the gate electrode 15a.

  A gate electrode 15a is disposed on the gate insulating film 14a. The gate electrode 15a is made of, for example, tungsten or polysilicon.

  First sidewalls 16a are disposed on both sides of the gate electrode 15a. A second sidewall 17a is disposed outside the first sidewall 16a. The first sidewall 16a and the second sidewall 17a are preferably formed using a material that transmits incident light irradiated on the sample by Raman scattering spectroscopy. Visible light to ultraviolet light is usually used as incident light in Raman scattering spectroscopy. In this case, for example, silicon nitride can be used as a material for forming the first sidewall 16a and the second sidewall 17a.

  In the silicon substrate 11, an N-type source / drain region B1 having an N-type polarity is disposed outside the second sidewall 17a.

  An extension region 19a having N-type polarity extends from the N-type source / drain region B1 toward a portion below the second sidewall 17a.

  Since the portions on both sides of the P-type channel region A1 overlap with the extension region 19a, the portion of the P-type channel region A1 that overlaps with the extension region 19a does not have electrical characteristics as a channel.

  An impurity diffusion suppression region 18a is arranged so as to surround the extension region 19a and the N-type source / drain region B1. The impurity diffusion suppression region 18a has a function of suppressing diffusion of impurity elements in the extension region 19a and the N-type source / drain region B1 into other regions.

  As the impurity diffusion suppression element that forms the impurity diffusion suppression region 18a, for example, carbon, nitrogen, or fluorine can be used.

  A silicide layer 20a is disposed on the N-type source / drain region B1.

  On the silicon substrate 11, an insulating layer 21 is formed so as to bury the N-type MOS transistor 1a. The insulating layer 21 is preferably formed using a material that transmits incident light irradiated on the sample by Raman scattering spectroscopy. As a material for forming the insulating layer 21, for example, silicon oxide can be used.

  A contact 22 penetrating the insulating layer 21 is disposed on the silicide layer 20a.

  The above is the description of the N-type MOS transistor 1a.

  The P-type MOS transistor 1b is disposed in the N-type well 13b having the N-type polarity in the second device region T2. The P-type MOS transistor 1b has a P-type source / drain region B2 having a P-type polarity and an extension region 19b having a P-type polarity. As described above, the description regarding the N-type MOS transistor 1a is also applied to the P-type MOS transistor 1b as appropriate.

  Next, the N-type MOS transistor 1c disposed in the first monitor region M1 will be described below. The P-type MOS transistor 1d arranged in the second monitor region M2 has the same structure as the N-type MOS transistor 1c except that the polarity is different. The same applies to the case.

  The N-type MOS transistor 1c is arranged in the first monitor region M1. The first monitor region M1 does not have a P-type well. The N-type MOS transistor 1c does not have an extension region. Further, no impurity is implanted into the monitor channel region C1. Except for these, the N-type MOS transistor 1c has the same structure as the N-type MOS transistor 1a described above. Each structure of the N-type MOS transistor 1c is formed in the same manner as each corresponding structure of the N-type MOS transistor 1a.

  The reason why the P-type well is not disposed in the first monitor region M1 and the N-type MOS transistor 1c has no extension region is to prevent impurities from being implanted or diffused into the monitor channel region C1. It is.

  On the other hand, the N-type MOS transistor 1c, like the N-type MOS transistor 1a, has an N-type source / drain region D1 having an N-type polarity and a silicide layer 20c.

  The reason why the N-type MOS transistor 1c has the silicide layer 20c is to reproduce the state of stress applied to the monitor channel region C1 by the silicide layer 20c in the same manner as the N-type MOS transistor 1a.

  Accordingly, the silicide layer 20c of the N-type MOS transistor 1c is formed in the same manner as the silicide layer 20a of the N-type MOS transistor 1a.

  The silicide layer 20c is formed on the N-type source / drain region D1, but it has been reported that the thickness of the silicide layer 20c is affected by the polarity of the N-type source / drain region D1 or the impurity concentration. (For example, refer nonpatent literature 2).

  Therefore, in the N-type MOS transistor 1c, the N-type source / drain region D1 is formed in the same manner as the N-type source / drain region B1 of the N-type MOS transistor 1a, and the silicide layer 20c is made the same as the silicide layer 20a. It is formed.

  In addition to the N-type source / drain region D1, the first sidewall 16c, the second sidewall 17c, the contact 22, and the like are components that give distortion to the monitor channel region C1. Therefore, these components in the first monitor region M1 are also formed in the same manner as in the first device region T1.

  An impurity diffusion suppression region 18c is arranged so as to surround the N-type source / drain region D1. The impurity diffusion suppression region 18c has a function of suppressing the impurity element of the N-type source / drain region D1 from diffusing into the monitor channel region C1.

  As described above, the first sidewall 16c and the second sidewall 17c of the N-type MOS transistor 1c are made of a material that transmits incident light applied to the sample by Raman scattering spectroscopy, as in the N-type MOS transistor 1a. It is preferable to form by using. This is so as not to affect the wave number shift of scattered light that enters and scatters into the monitor channel region C1.

  Specifically, the first sidewall 16c and the second sidewall 17c of the N-type MOS transistor 1c are the same using the same material as the first sidewall 16a and the second sidewall 17a of the N-type MOS transistor 1a. Formed.

  A gate electrode 15c is disposed on the monitor channel region C1. The gate electrode 15c is usually formed of metal or polysilicon. Metals do not transmit ultraviolet light from visible light. Polysilicon affects the wave number shift of scattered light.

  In the first monitor region M1, the amount of distortion in the channel measurement region E1, which is a portion of the monitor channel region C1 located below the first sidewall 16c and the second sidewall 17c, is measured.

  Therefore, the monitor channel region C1 is transmitted through the first sidewall 16c and the second sidewall 17c, is incident on the channel measurement region E1, and the light scattered in the channel measurement region E1 is transmitted to the first side wall 16c. Measurement is performed through the wall 16c and the second sidewall 17c.

  The monitor channel region A1 of the N-type MOS transistor 1a is normally not measured by Raman scattering spectroscopy. From this point of view, the first sidewall 16a and the second sidewall 17a of the N-type MOS transistor 1a are not required to be formed using a material that transmits incident light irradiated by Raman scattering spectroscopy. However, since the first sidewall 16a and the second sidewall 17a of the N-type MOS transistor 1a are formed simultaneously with the first sidewall 16c and the second sidewall 17c of the N-type MOS transistor 1c, they have the same characteristics. become.

  The above is the description of the N-type MOS transistor 1c.

  The P-type MOS transistor 1d is arranged in the second monitor region M2. N-type wells are not arranged in the second monitor region M2. The P-type MOS transistor 1d does not have an extension region. Further, no impurity is implanted into the monitor channel region C2 of the P-type MOS transistor 1d. On the other hand, the P-type MOS transistor 1d has a P-type source / drain region D2 having a P-type polarity and a silicide layer 20d. In the second monitor region M2, the amount of distortion in the channel measurement region E2, which is a portion of the monitor channel region C2 located below the first sidewall 16d and the second sidewall 17d, is measured. As described above, the description regarding the N-type MOS transistor 1c is also applied to the P-type MOS transistor 1d as appropriate.

  On the silicon substrate 11, at least one monitor region 31 having the first monitor region M1 and the second monitor region M2 described above is disposed. Further, by disposing a plurality of monitor regions 31 on the silicon substrate 11, it is possible to measure the strain distribution on the silicon substrate 11.

  When the monitor region 31 is disposed in the scribe region, it is preferable to measure the strain amount of the monitor region 31 before the silicon substrate 11 is cut for each circuit formation region 30.

  Next, a preferred embodiment of the semiconductor device manufacturing method of the present embodiment described above will be described below with reference to the drawings.

  The basic concept of the semiconductor device manufacturing method is as follows.

  1. Impurities are not implanted into the monitor channel region of the transistor in the monitor region. From this point of view, in the monitor region, no impurity is implanted except for the source / drain region for forming a strained silicide layer.

  2. The strain amount of the monitor channel region of the transistor in the monitor region is set to be the same as the strain amount of the channel region of the transistor in the device region. From this viewpoint, each component of the transistor in the monitor region is formed using the same material under the same conditions at the same time as each corresponding component of the transistor in the device region.

  In the present embodiment, the circuit region 30 and the monitor region 31 (see FIG. 2) are formed simultaneously on the silicon substrate 11. Since the processing of each step described below is performed on the entire surface of the silicon substrate 11 under the same conditions at the same time, the corresponding components of the circuit region 30 and the monitor region 31 that are separated on the silicon substrate 11 are: It is formed in the same way.

  First, as shown in FIG. 3, the element isolation layer 12 is formed on the silicon substrate 11, and the first device formation region S1 where the first device region T1 is formed and the second device region T2 is formed. A device formation region S2 is defined. Similarly, the element isolation layer 12 is formed on the silicon substrate 11, and the first monitor formation region N1 in which the first monitor region M1 is formed and the second monitor formation region N2 in which the second monitor region M2 is formed are defined. Is done.

  In the first device formation region S1, a P-type channel formation region F1 in which a P-type channel region A1 is formed and an N-type source / drain formation region G1 in which an N-type source / drain region B1 is formed are shown. Yes. In the second device formation region S2, an N-type channel formation region F2 in which an N-type channel region A2 is formed and a P-type source / drain formation region G2 in which a P-type source / drain region B2 is formed are shown.

  Similarly, in the first monitor formation region N1, a monitor channel formation region H1 in which the monitor channel region C1 is formed and an N type source / drain formation region I1 in which the N type source / drain region D1 is formed are shown. . In the second monitor formation region N2, a monitor channel formation region H2 where the monitor channel region C2 is formed and a P type source / drain formation region I2 where the P type source / drain region D2 is formed are shown.

  Next, as shown in FIG. 4, a mask 40 is formed on the second device formation region S2, and a mask 41 is formed on the first monitor formation region N1 and the second monitor formation region N2. The first device formation region S1, the second device formation region S2 covered with the mask 40, and the first monitor formation region N1 and the second monitor formation region N2 covered with the mask 41 are P. A type impurity is implanted to form a P-type well 13a in the first device formation region S1. Impurities are not implanted into the portion of the silicon substrate 11 covered with the mask. Then, the mask 40 is removed.

  Next, as shown in FIG. 5, a mask 42 is formed on the first device formation region S1. The first device formation region S1 and the second device formation region S2 covered with the mask 42, and the first monitor formation region N1 and the second monitor formation region N2 covered with the mask 41, N A type impurity is implanted to form an N type well 13b in the second device formation region S2. Impurities are not implanted into the portion of the silicon substrate 11 covered with the mask. Then, the mask 42 is removed.

Next, as shown in FIG. 6, a mask 43 is formed on the second device formation region S2. The first device formation region S1, the second device formation region S2 covered with the mask 43, and the first monitor formation region N1 and the second monitor formation region N2 covered with the mask 41 are P. A type impurity is implanted to form a P-type impurity region 44 in the first device formation region S1. The P-type impurity region 44 is a region including the P-type channel formation region F1. The P-type channel formation region F1 is a region that will become the P-type channel region A1 in the future. The implantation amount of the P-type impurity can be set, for example, in the range of 2 × 10 ¹² to 8 × 10 ¹² cm ⁻² . Then, the mask 43 is removed.

Next, as shown in FIG. 7, a mask 45 is formed on the first device formation region S1. The first device formation region S1 and the second device formation region S2 covered with the mask 45 and the first monitor formation region N1 and the second monitor formation region N2 covered with the mask 41 are N A type impurity is implanted to form an N-type impurity region 46 in the second device formation region S2. The N-type impurity region 46 is a region including the N-type channel formation region F2. The N-type channel formation region F2 is a region that will become the N-type channel region A2 in the future. The implantation amount of the N-type impurity can be, for example, in the range of 2 × 10 ¹² to 8 × 10 ¹² cm ⁻² . Then, the mask 45 and the mask 41 are removed.

  Next, as shown in FIG. 8, a gate insulating film is formed on the P-type channel formation region F1, the N-type channel formation region F2, and the monitor channel formation regions H1 and H2 by using a photolithography technique and an etching technique. 14a-14d and the gate electrode 15a are formed. The gate insulating films 14a to 14d are simultaneously formed in the same shape using the same material. Similarly, the gate electrode 15a is simultaneously formed in the same shape using the same material.

  Next, as shown in FIG. 9, impurities that suppress diffusion of impurities in the first device formation region S1, the second device formation region S2, the first monitor formation region N1, and the second monitor formation region N2, respectively. Diffusion suppression elements are implanted in the same manner to form impurity diffusion suppression regions 18a to 18d. The impurity diffusion suppression regions 18a to 18d are preferably formed so as to include future source / drain regions. The impurity diffusion suppression regions 18a and 18b are preferably formed so as to include extension regions that will be formed in the future.

The impurity diffusion suppressing element can be implanted using a carbon atom ion, a carbon cluster, a molecular ion such as C ₇ H ₇ , or a molecular ion such as a nitrogen atom ion or a nitrogen molecule (N ₂ ).

When carbon is implanted as the impurity diffusion suppressing element, the amount of carbon implanted can be in the range of 5 × 10 ¹⁴ to 5 × 10 ¹⁵ cm ⁻² .

  Next, as shown in FIG. 10, the first sidewall 16a is formed on both sides of the gate electrode 15a and the first sidewall 16c is formed on both sides of the gate electrode 15c by using a photolithography technique and an etching technique. It is formed in the same manner as the first sidewall 16a. The first sidewall 16b is formed on both sides of the gate electrode 15b, and the first sidewall 16d is formed on both sides of the gate electrode 15d in the same manner as the first sidewall 16b. In the present embodiment, the first sidewalls 16a to 16d are simultaneously formed in the same shape using the same material.

Next, as shown in FIG. 11, a mask 47 is formed on the first device formation region S1, and a mask 48 is formed on the first monitor formation region N1 and the second monitor formation region N2. The first device formation region S1 and the second device formation region S2 covered with the mask 47, and the first monitor formation region N1 and the second monitor formation region N2 covered with the mask 48, P Type impurities are implanted. An extension region 19b is formed outside the first sidewall 16b with the gate electrode 15b interposed therebetween. The implantation amount of the P-type impurity can be, for example, in the range of 2 × 10 ¹⁴ to 5 × 10 ¹⁴ cm ⁻² . Impurities are not implanted into the portion of the silicon substrate 11 covered with the mask. Then, the mask 47 is removed.

Next, as shown in FIG. 12, a mask 49 is formed on the second device formation region S2. The first device formation region S1, the second device formation region S2 covered with the mask 49, and the first monitor formation region N1 and the second monitor formation region N2 covered with the mask 48 are N Type impurities are implanted. Then, an extension region 19a is formed outside the first sidewall 16a sandwiching the gate electrode 15a. The implantation amount of the N-type impurity can be set, for example, in the range of 2 × 10 ¹⁴ to 5 × 10 ¹⁴ cm ⁻² . Impurities are not implanted into the portion of the silicon substrate 11 covered with the mask. Then, the mask 49 and the mask 48 are removed.

  Next, as shown in FIG. 13, a second sidewall 17a is formed outside the first sidewall 16a and a second sidewall is formed outside the first sidewall 16c by using a photolithography technique and an etching technique. The side wall 17c is formed in the same manner as the second side wall 17a. The second sidewall 17b is formed outside the first sidewall 16b, and the second sidewall 17d is formed outside the first sidewall 16d in the same manner as the second sidewall 17b. In the present embodiment, the second sidewalls 17a to 17d are simultaneously formed in the same shape using the same material.

  Next, as shown in FIG. 14, a mask 50 is formed on the first device formation region S1, and a mask 51 is formed on the first monitor formation region N1. Then, with respect to the first device formation region S1 and the second device formation region S2 covered with the mask 50, and the first monitor formation region N1 and the second monitor formation region N2 covered with the mask 51 P-type impurities are implanted.

  In the second device formation region S2, P-type impurities are implanted into the P-type source / drain formation region G2 using the gate electrode 15b, the first sidewall 16b, and the second sidewall 17b as a mask, and the P-type source / drain region B2 is formed. At the same time, in the second monitor formation region N2, P-type impurities are implanted into the P-type source / drain formation region I2 using the gate electrode 15d, the first sidewall 16d, and the second sidewall 17d as a mask. A drain region D2 is formed. Impurities are not implanted into the portion of the silicon substrate 11 covered with the mask.

  In the second device formation region S2, an N-type channel region A2 sandwiched between P-type source / drain regions B2 is formed. Similarly, in the second monitor formation region N2, a monitor channel region C2 sandwiched between the P-type source / drain regions D2 is formed.

The P-type impurity has the same amount of impurity addition and the region (width and depth) into which the impurity is implanted with respect to the P-type source / drain formation region G2 and the P-type source / drain formation region I2. Injected. Here, the amount of P-type impurities implanted into the P-type source / drain formation region G2 and the P-type source / drain formation region I2 is preferably 10 times or more larger than the amount implanted into the extension region 19b. . The implantation amount of the P-type impurity can be set to 5 × 10 ¹⁵ cm ⁻² , for example. Then, the mask 50 and the mask 51 are removed.

  Next, as shown in FIG. 15, a mask 52 is formed on the second device formation region S2, and a mask 53 is formed on the second monitor formation region N2. And with respect to 1st device formation area S1, 2nd device formation area S2 covered with the mask 52, 1st monitor formation area N1, and 2nd monitor formation area S2 covered with the mask 53 N-type impurities are implanted.

  In the first device formation region S1, an N-type impurity is implanted into the N-type source / drain formation region G1 using the gate electrode 15a, the first sidewall 16a, and the second sidewall 17a as a mask, and the N-type source / drain region B1 is formed. At the same time, in the first monitor formation region N1, N-type impurities are implanted into the N-type source / drain formation region I1 using the gate electrode 15c, the first sidewall 16c, and the second sidewall 17c as a mask. A drain region D1 is formed. Impurities are not implanted into the portion of the silicon substrate 11 covered with the mask.

  In the first device formation region S1, a P-type channel region A1 sandwiched between N-type source / drain regions B1 is formed. Similarly, in the first monitor formation region N1, a monitor channel region C1 sandwiched between N-type source / drain regions D1 is formed.

The N-type impurity has the same amount of impurity addition and the region (width and depth) into which the impurity is implanted with respect to the N-type source / drain formation region G1 and the N-type source / drain formation region I1. Injected. Here, the amount of N-type impurity implanted into the N-type source / drain formation region G1 and the N-type source / drain formation region I1 is preferably 10 times or more larger than the amount implanted into the extension region 19a. . The implantation amount of the N-type impurity can be set to 5 × 10 ¹⁵ cm ⁻² , for example. Then, the mask 52 and the mask 53 are removed.

  Then, the silicon substrate 11 is heat-treated to electrically activate the impurities. As heat processing, it can carry out at the temperature of 1100-1150 degreeC for the time for 1 second or less, for example. In this heat treatment, the diffusion of the N-type impurity in the N-type source / drain region D1 into the monitor channel region C1 is suppressed by the function of the impurity diffusion suppression region 18c. Similarly, the action of the impurity diffusion suppression region 18d suppresses the diffusion of the P-type impurity in the P-type source / drain region D2 into the monitor channel region C2.

  Next, as shown in FIG. 16, the silicide layer 20a and the silicide layer 20c are formed in the same manner on the N-type source / drain region B1 and the N-type source / drain region D1, respectively. Since the impurity polarity and impurity concentration of the N-type source / drain region D1 are the same as those of the N-type source / drain region B1, the thickness of the silicide layer 20c is the same as that of the silicide layer 20a.

  Therefore, the state of stress applied to the P-type channel region A1 by the silicide layer 20a is the same as the state of stress applied to the monitor channel region C1 by the silicide layer 20c.

  Similarly, the silicide layer 20b and the silicide layer 20d are formed in the same manner on the P-type source / drain region B2 and the P-type source / drain region D2, respectively. Since the impurity polarity and impurity concentration of the P-type source / drain region D2 are the same as those of the P-type source / drain region B2, the thickness of the silicide layer 20d is the same as that of the silicide layer 20b.

  Therefore, the state of stress applied to the N-type channel region A2 by the silicide layer 20b is the same as the state of stress applied to the monitor channel region C2 by the silicide layer 20d.

  As a method for forming the silicide layers 20a to 20d, for example, a salicide method can be used.

  In this way, the first device region T1 having the N-type MOS transistor 1a, the second device region T2 having the P-type MOS transistor 1b, the first monitor region M1 having the N-type MOS transistor 1c, and the P-type MOS A second monitor region M2 having the transistor 1d is formed.

  The impurity concentration of the N-type source / drain region B1 of the N-type MOS transistor 1a is higher than that of the N-type source / drain region D1 by the amount of P-type impurities implanted to form the extension region 19a. However, if the impurity concentration of the extension region 19a is 1/10 or less of the N-type source / drain region B1, the influence on the thickness of the silicide layer can be ignored.

  The same applies to the difference between the impurity concentration of the P-type source / drain region B2 of the P-type MOS transistor 1b and the concentration of the P-type source / drain region D2.

  Next, a method for measuring a semiconductor device disclosed in this specification will be described below with reference to a flowchart shown in FIG.

  First, in step S1, the distortion amounts of the monitor channel region C1 of the first monitor region M1 and the monitor channel region C2 of the second monitor region M2 on the silicon substrate 11 are measured using Raman scattering spectroscopy. As the Raman scattering spectroscopy, it is preferable to use micro Raman scattering spectroscopy.

  As shown in FIG. 1, in the first monitor region M1, the amount of distortion in the channel measurement region E1 is measured. Similarly, in the second monitor region M2, the amount of distortion in the channel measurement region E2 is measured.

  Next, in step S2, the distortion amount of the P-type channel region A1 of the first device region T1 is estimated based on the measured distortion amount of the monitor channel region C1 of the first monitor region M1. Similarly, based on the measured distortion amount of the monitor channel region C2 of the second monitor region M2, the distortion amount of the N-type channel region A2 of the second device region T2 is estimated.

  According to the method for measuring the semiconductor device of the present embodiment described above, the strain amount of the P-type channel region A1 into which the P-type impurity is implanted is determined by using the Raman scattering spectroscopy. It is obtained by measuring. Similarly, the strain amount of the N-type channel region A2 into which the N-type impurity is implanted can be obtained by measuring the strain amount of the monitor channel region C2 using Raman scattering spectroscopy.

  In the present invention, the method for manufacturing the semiconductor device and the method for measuring the semiconductor device according to the above-described embodiments can be appropriately changed without departing from the gist of the present invention.

  For example, in the embodiment described above, the impurity diffusion suppression region is formed. However, when the diffusion of impurities from the source / drain region or the extension region to the channel region can be ignored, the impurity diffusion suppression region is not formed. Also good.

  In the above-described embodiment, the extension region is formed. However, the extension region may not be formed.

  In the embodiment of the method for measuring a semiconductor device described above, the non-destructive measurement of the monitor channel region is performed using Raman scattering spectroscopy. However, the electron beam diffraction method is used to measure the broken monitor channel region. The amount of distortion may be measured.

  Further, the method for manufacturing a semiconductor device and the method for measuring a semiconductor device disclosed in this specification can also be applied to a semiconductor device in which a channel region is distorted using a silicon germanium mixed crystal or the like.

  All examples and conditional words mentioned herein are intended for educational purposes to help the reader deepen and understand the inventions and concepts contributed by the inventor. All examples and conditional words mentioned herein are to be construed without limitation to such specifically stated examples and conditions. Also, such exemplary mechanisms in the specification are not related to showing the superiority and inferiority of the present invention. While embodiments of the present invention have been described in detail, it should be understood that various changes, substitutions or modifications can be made without departing from the spirit and scope of the invention.

DESCRIPTION OF SYMBOLS 10 Semiconductor device 1a N-type MOS transistor 1b P-type MOS transistor 1c N-type MOS transistor 1d P-type MOS transistor 11 Silicon substrate 12 Element isolation layer 13a P-type well 13b N-type well 14a-14d Gate insulating film 15a-15d Gate electrode 16a -16d First side wall 17a-17d Second side wall 18a-18d Impurity diffusion suppression region 19a, 19b Extension region 20a-20d Silicide layer 21 Insulating layer 22 Contact 30 Circuit formation region 31 Monitor region 40 Mask 41 Mask 42 Mask 43 Mask 44 P-type impurity region 45 Mask 46 N-type impurity region 47 Mask 48 Mask 49 Mask 50 Mask 51 Mask 52 Mask 53 Mask T1 First device region (first) Element)
T2 Second device region (first element)
M1 first monitor region (second element)
M2 second monitor region (second element)
A1 P-type channel region (first channel)
A2 N-type channel region (first channel)
B1 N-type source / drain region (first source / drain)
B2 P-type source / drain region (first source / drain)
C1 Monitor channel area (second channel)
C2 Monitor channel area (second channel)
D1 N-type source / drain region (second source / drain)
D2 P-type source / drain region (second source / drain)
E1 channel measurement region E2 channel measurement region S1 first device formation region (first element formation region)
S2 Second device formation region (first element formation region)
N1 first monitor formation region (second element formation region)
N2 Second monitor formation region (second element formation region)
F1 P-type channel formation region (first channel formation region)
F2 N-type channel formation region (first channel formation region)
G1 N-type source / drain formation region (first source / drain formation region)
G2 P-type source / drain formation region (first source / drain formation region)
H1 monitor channel formation region (second channel formation region)
H2 monitor channel formation region (second channel formation region)
I1 N-type source / drain formation region (second source / drain formation region)
I2P type source / drain formation region (second source / drain formation region)

Claims (9)

A first element formed on a silicon substrate and having a first channel and a first source / drain disposed on both sides of the first channel, a second channel, and both sides of the second channel. A method of manufacturing a semiconductor device comprising a second element having a second source / drain.
The second element is an element used for measuring a distortion amount of the second channel and estimating a distortion amount of the first channel based on the measured distortion amount.
A first mask is formed on a second element formation region where the second element is formed, and a first channel formation in which the second element formation region and the first channel covered with the first mask are formed A first step of implanting an impurity having a first polarity into the region;
Impurities having a second polarity are implanted into the first source / drain formation region where the first source / drain is formed and the second source / drain formation region where the second source / drain is formed, A second step of forming a first source / drain and the second source / drain;
A third step of forming a silicide layer on each of the first source / drain and the second source / drain;
A method for manufacturing a semiconductor device comprising: In the second step,
2. The impurity having a second polarity is implanted into each of the first source / drain formation region and the second source / drain formation region so that the amount of impurity added and the region into which the impurity is implanted are the same. The manufacturing method of the semiconductor device as described in any one of Claims 1-3. In the third step,
3. The method of manufacturing a semiconductor device according to claim 1, wherein the silicide layer is formed to have the same thickness on each of the first source / drain region and the second source / drain region. Forming a first gate electrode on the first channel formation region, and forming a second gate electrode on the second channel formation region in which the second channel is formed;
Forming a first sidewall on both sides of the first gate electrode, and forming a second sidewall on both sides of the second gate electrode;
Forming a second mask on the second element formation region; and using the second mask, the first gate electrode, and the first sidewall as a mask, respectively in the second element formation region and the first element formation region. A fourth step of implanting an impurity having a second polarity to form an extension outside the first sidewall;
The method for manufacturing a semiconductor device according to claim 1, wherein the method is provided between the first step and the second step. In the second step,
Forming a third sidewall outside the first sidewall, and forming a fourth sidewall outside the second sidewall;
The first source / drain formation region using the first gate electrode, the first sidewall, and the third sidewall, and the second gate electrode, the second sidewall, and the fourth sidewall as a mask, and The method of manufacturing a semiconductor device according to claim 4, wherein an impurity having a second polarity is implanted into each of the second source / drain formation regions. Before the second step,
6. The method according to claim 1, further comprising a fifth step of implanting an impurity diffusion suppressing element that suppresses diffusion of impurities into each of the first source / drain formation region and the second source / drain formation region. Semiconductor device manufacturing method. Before the first step,
A sixth mask is formed on the second element formation region, and an impurity having a first polarity is implanted into the second element formation region and the first element formation region covered with the third mask. The manufacturing method of the semiconductor device as described in any one of Claims 1-6 provided with a process. A first element formed on a silicon substrate and having a first channel and a first source / drain disposed on both sides of the first channel, a second channel, and both sides of the second channel. A method of measuring a semiconductor device comprising a second element having a second source / drain.
In the semiconductor device, a first mask is formed on a second element formation region in which the second element is formed, and the second element formation region and the first channel covered with the first mask are formed. A first step of implanting an impurity having a first polarity into the first channel forming region;
Impurities having a second polarity are implanted into the first source / drain formation region where the first source / drain is formed and the second source / drain formation region where the second source / drain is formed, A second step of forming a first source / drain and the second source / drain;
Manufactured using a third step of forming a silicide layer on each of the first source / drain and the second source / drain;
A method of estimating a distortion amount of the first channel by measuring a distortion amount of the second channel.   The method according to claim 8, wherein the amount of distortion of the second channel is measured using Raman scattering spectroscopy.

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