JP2013105765A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technology to improve transistor performance of a semiconductor device having a field effect transistor.SOLUTION: A semiconductor device manufacturing method comprises: forming side walls 9 on a gate insulation film 5 and on lateral faces of gate electrodes 6n, 6p; subsequently forming an impurity region by ion implanting an impurity to a semiconductor substrate 1 on both sides of the sidewalls 9; subsequently, forming a first insulation film 14, a second insulation film 15 and a third insulation film 16 sequentially on a principal surface of the semiconductor substrate 1; and subsequently performing a thermal treatment for activating the ion-implanted impurity. In this case, the first insulation film 14 is a film having coatability more excellent than that of the second insulation film 15 and having an etching selection ratio different from that of the second insulation film 15. The second insulation film 15 is a film having a higher function of preventing hydrogen diffusion than the first insulation film 14. The third insulation film 16 is a film in which a change in an internal stress is larger than in the first insulation film 14 and in the second insulation film 15.

Description

  The present invention relates to a semiconductor device manufacturing technique, and more particularly to a technique effective when applied to the manufacture of a semiconductor device having a field effect transistor.

  For example, in Japanese Patent Application Laid-Open No. 2004-172389 (Patent Document 1), in an n-channel MOS transistor having a polysilicon gate electrode formed on a silicon substrate, compressive stress remains in the gate electrode, and the silicon substrate A technique in which a tensile stress is applied to is disclosed.

  Japanese Patent Laid-Open No. 2009-016407 (Patent Document 2) discloses that after an N-type transistor and a P-type transistor are formed on the same substrate, only the N-type transistor is covered with a cover film that generates stress by heating. A technique is disclosed in which a first characteristic improvement process is performed on a transistor and a second characteristic improvement process is performed on a P-type transistor.

  Japanese Unexamined Patent Application Publication No. 2009-290079 (Patent Document 3) discloses a step of forming a stressor film on the upper surface of a semiconductor substrate, and using a resist film as a mask, the stressor film in the pMOS region is etched away by a predetermined thickness. The step of separating the stressor film in the nMOS region from the stressor film in the pMOS region, the step of covering the stressor film exposed from the boundary between the nMOS region and the pMOS region with a protective film, and etching the stressor film remaining in the pMOS region A method for manufacturing a semiconductor device including a removing step is disclosed.

  Japanese Patent Laid-Open No. 2010-021300 (Patent Document 4) discloses that an insulating film is formed so as to cover the NMOS region after forming a relatively thin protective film on the NMOS region and a relatively thick protective film on the PMOS region. And a technique of applying a tensile stress to the NMOS region by heat-treating the insulating film.

  Japanese Unexamined Patent Publication No. 2007-005527 (Patent Document 5) discloses a semiconductor element having an insulated gate transistor, a first insulating film formed on the semiconductor element, and a metal formed on the first insulating film. In a semiconductor device having a wiring and a second insulating film formed so as to cover the first insulating film and the metal wiring, the first insulating film includes an oxynitride having a nitrogen content in the range of 1 atom% to 15 atom%. It is described that it is a silicon film.

  Japanese Patent Application Publication No. 2010-508672 (Patent Document 6) discloses a step of providing a semiconductor substrate having a first transistor element including a first amorphous region and a second transistor element including a second amorphous region; Forming a stress generating layer on the first transistor element without covering the transistor element; performing a first annealing process to recrystallize the first amorphous region and the second amorphous region; A method of forming a semiconductor structure including a step of performing a second annealing process while leaving a stress generating layer on one transistor element.

JP 2004-172389 A JP 2009-016407 A JP 2009-290079 A JP 2010-021300 A JP 2007-005527 A Special table 2010-508672 gazette

  One means for further increasing the speed of field effect transistors is strained silicon technology. This is a technique for improving carrier mobility by causing strain in the silicon layer. That is, when the silicon crystal lattice of the channel is distorted by applying stress, the symmetry of the band structure of the isotropic silicon crystal is lost, and energy level splitting occurs. As a result, carrier scattering or effective mass is reduced due to lattice vibration, and the mobility of electrons and holes can be improved.

  In addition, as a background of the above strained silicon technology, initially, biaxial stress was mainly generated in the channel region. Biaxial stress is stress generated in the gate length direction and the gate width direction. However, when this biaxial stress is used, it has become clear from experiments that the drive current does not increase as much as expected. In particular, the increase in current was small in the p-channel field effect transistor. This is because the stress generated in the gate length direction increases the current, but the stress generated in the gate width direction decreases the current. Therefore, a uniaxial stress that generates a stress only in the gate length direction is required.

  Further, in order to increase the current of the field effect transistor due to such stress, the stress must be generated in the entire channel region located between the source region and the drain region and below the gate electrode. is there. That is, in the n-channel field effect transistor, a uniaxial tensile stress (stress that widens the distance between Si atoms) is applied to the entire channel region in the gate length direction, and in the p-channel field effect transistor, 1 in the gate length direction. Axial compressive stress (stress that reduces the distance between Si atoms) needs to be applied to the entire channel region.

  One strained silicon technique is SMT (Stress Memorization Technique). SMT is a technique for improving carrier mobility by applying tensile stress to the channel of a field effect transistor. The specific process of SMT is as follows, for example. First, after covering the whole field effect transistor with a cover film, heat treatment at 1000 ° C. or higher is performed. As a result, strain is generated in the polycrystalline silicon constituting the gate electrode, and the strain is quenched. Thereafter, a tensile stress is applied to the channel by removing the cover film that has suppressed the expansion of the polycrystalline silicon.

  As a cover film used for SMT, a silicon nitride film formed by plasma CVD rather than thermal CVD (Chemical Vapor Deposition) is applied in order to apply higher stress. The reason is that the silicon nitride film formed by the plasma CVD method has an internal stress of 0.66 GPa before the heat treatment, whereas the internal stress after the heat treatment is 1.8 GPa. This is because the internal stress changes.

  However, a silicon nitride film formed by a plasma CVD method contains more hydrogen and moisture than a silicon nitride film formed by a thermal CVD method. Therefore, when heat treatment at 1000 ° C. or higher is performed on the silicon nitride film formed by the plasma CVD method, hydrogen and moisture contained in the silicon nitride film diffuse into the semiconductor substrate, causing crystal defects in the semiconductor substrate. There is a problem of causing it. The crystal defect causes abnormal growth of a silicide film formed in a subsequent process, and causes a decrease in manufacturing yield. In addition, since a leakage current easily flows through the crystal defect, the crystal defect also hinders low power consumption.

  An object of the present invention is to provide a technique capable of improving the transistor performance of a semiconductor device having a field effect transistor.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in this application, an embodiment of a representative one will be briefly described as follows.

  This embodiment is a method of manufacturing a semiconductor device having a field effect transistor. After sidewalls are formed on the side surfaces of the gate insulating film and gate electrode formed on the main surface of the semiconductor substrate, impurities are ion-implanted into the semiconductor substrate on both sides of the sidewalls to form impurity regions. Subsequently, a first insulating film, a second insulating film, and a third insulating film are sequentially formed on the main surface of the semiconductor substrate, and then a heat treatment for activating the ion-implanted impurities is performed. Here, the first insulating film is a film having better coverage than the second insulating film, and is a film having an etching selectivity different from that of the second insulating film. The second insulating film is a film having a higher function of preventing hydrogen diffusion than the first insulating film. The third insulating film is a film having a larger change in internal stress than the first insulating film and the second insulating film.

  Among the inventions disclosed in the present application, effects obtained by one embodiment of a representative one will be briefly described as follows.

  A technique capable of improving the transistor performance of a semiconductor device including a field effect transistor can be provided.

It is principal part sectional drawing of the CMIS device and resistance element which show the manufacturing process of the semiconductor device by one embodiment of this invention. FIG. 2 is a principal part cross-sectional view of the same place as in FIG. 1 in the process of manufacturing the semiconductor device, following FIG. 1; FIG. 3 is a principal part cross-sectional view of the same place as in FIG. 1 in the process of manufacturing the semiconductor device, following FIG. 2; FIG. 4 is a principal part cross-sectional view of the same place as in FIG. 1 in the process of manufacturing the semiconductor device, following FIG. 3; FIG. 5 is a principal part cross-sectional view of the same place as in FIG. 1 in the process of manufacturing the semiconductor device, following FIG. 4; FIG. 6 is a principal part cross-sectional view of the same place as in FIG. 1 in the process of manufacturing the semiconductor device, following FIG. 5; FIG. 7 is an essential part cross-sectional view of the same place as in FIG. 1 in the process of manufacturing the semiconductor device, following FIG. 6; FIG. 8 is a principal part cross-sectional view of the same place as in FIG. 1 in the process of manufacturing the semiconductor device, following FIG. 7; FIG. 9 is a principal part cross-sectional view of the same place as in FIG. 1 in the process of manufacturing the semiconductor device, following FIG. 8; FIG. 10 is an essential part cross-sectional view of the same place as in FIG. 1 in the process of manufacturing the semiconductor device, following FIG. 9; FIG. 11 is a principal part cross-sectional view of the same place as in FIG. 1 in the process of manufacturing the semiconductor device, following FIG. 10; FIG. 12 is a principal part cross-sectional view of the same place as in FIG. 1 in the process of manufacturing the semiconductor device, following FIG. 11; FIG. 13 is a principal part cross-sectional view of the same place as in FIG. 1 in the process of manufacturing the semiconductor device, following FIG. 12; FIG. 14 is an essential part cross-sectional view of the same place as in FIG. 1 in the process of manufacturing the semiconductor device, following FIG. 13; FIG. 15 is a principal part cross-sectional view of the same place as in FIG. 1 in the process of manufacturing the semiconductor device, following FIG. 14; FIG. 16 is a principal part cross-sectional view of the same place as in FIG. 1 in the process of manufacturing the semiconductor device, following FIG. 15; FIG. 17 is an essential part cross-sectional view of the same place as in FIG. 1 in the process of manufacturing the semiconductor device, following FIG. 16; FIG. 18 is a principal part cross-sectional view of the same place as in FIG. 1 in the process of manufacturing the semiconductor device, following FIG. 17; It is process drawing explaining a part of flow of the manufacturing process by one embodiment of this invention.

  In the following embodiments, when necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other, and one is the other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

In the following embodiments, a MISFET (Metal Insulator Semiconductor Field Effect Transistor) representing a field effect transistor is abbreviated as MIS, a p-channel type MISFET is abbreviated as pMIS, and an n-channel type MISFET is abbreviated as nMIS. In the following embodiments, when referring to silicon nitride, silicon nitride, or silicon nitride, not only Si ₃ N ₄ but also silicon nitride is used and includes an insulating film having a similar composition. . In addition, when it is referred to as silicon oxide or silicon oxide, not only SiO ₂ but also an oxide film of silicon and an insulating film having a similar composition is included. In the following embodiments, the term “wafer” mainly refers to a wafer made of single crystal silicon. However, not only that, but also an SOI (Silicon On Insulator) wafer and an integrated circuit are formed thereon. It refers to an insulating film substrate or the like. The shape includes not only a circle or a substantially circle but also a square, a rectangle and the like.

  In all the drawings for explaining the following embodiments, components having the same function are denoted by the same reference numerals in principle, and repeated description thereof is omitted. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment)
A method for manufacturing a CMIS (Complementary Metal Insulator Semiconductor) device and a resistance element according to an embodiment of the present invention will be described in the order of steps with reference to FIGS. 1 to 18 are cross-sectional views of the principal parts of the CMIS device and the resistance element, and FIG. 19 is a process diagram illustrating a part of the flow of the manufacturing process. 1 to 18, nMIS (nMIS region (silicide region)) for forming a silicide film on the upper surface of the gate electrode and the upper surface of the source / drain, and a silicide film on the upper surface of the gate electrode and the upper surface of the source / drain. An nMIS not formed (nMIS region (non-silicide region)), a resistance element region, a pMIS (pMIS region (silicide region)) in which a silicide film is formed on the upper surface of the gate electrode and the upper surface of the source / drain are shown.

  First, as shown in FIG. 1, a semiconductor substrate (semiconductor plate having a substantially planar shape called a semiconductor wafer) 1 made of, for example, p-type single crystal silicon is prepared. Next, a trench having a depth of, for example, about 0.3 μm is formed in the element isolation region of the semiconductor substrate 1, and an element isolation 2 is formed by embedding an insulating film such as a silicon oxide film in the trench.

  Next, the p-type well 3 is formed by ion-implanting a p-type impurity such as boron (B) into the nMIS region and the resistance element region of the semiconductor substrate 1. Similarly, an n-type well 4 is formed by ion-implanting an n-type impurity such as phosphorus (P) or arsenic (As) into the pMIS region of the semiconductor substrate 1.

  Next, as shown in FIG. 2, a gate insulating film 5 made of silicon oxide is formed on the main surface of the semiconductor substrate 1. Next, after depositing a polycrystalline silicon film on the gate insulating film 5 by a CVD method, the polycrystalline silicon film is etched using the resist pattern as a mask to form the gate electrodes 6n and 6p of nMIS and pMIS, respectively. The gate length of the gate electrodes 6n and 6p is, for example, about 40 nm.

Next, as shown in FIG. 3, the pMIS region is covered with a resist pattern (not shown), and n-type impurities such as phosphorus (P) or arsenic (As) are ionized in the nMIS region and the resistance element region of the semiconductor substrate 1. Implantation is performed to form a first n-type impurity region 7g above the gate electrode 6n, and a pair of first n-type impurity regions 7 are formed in the semiconductor substrate 1 (p-type well 3) on both sides of the gate electrode 6n. At the same time, a first n-type impurity region (resistance impurity region) 7r is formed in the resistance element region. For example, the implantation amount and implantation energy in arsenic (As) ion implantation are 1 to ² keV and 0.5 to 1 × 10 ¹⁵ / cm ² , respectively.

  Here, the polycrystalline silicon constituting the upper portion (first n-type impurity region 7g) of the gate electrode 6n into which the n-type impurity is ion-implanted and the semiconductor substrate 1 (first n-type impurity region 7, The single crystal silicon constituting 7r) is made amorphous.

Similarly, the nMIS region is covered with a resist pattern (not shown), and a p-type impurity such as boron (B) or boron fluoride (BF ₂ ) is ion-implanted into the pMIS region of the semiconductor substrate 1 to form the gate electrode 6p. A first p-type impurity region 8g is formed in the upper portion, and a pair of first p-type impurity regions 8 are formed in the semiconductor substrate 1 (n-type well 4) on both sides of the gate electrode 6p. For example, the implantation amount and implantation energy in the ion implantation of boron (B) are 0.1 to 0.5 keV and 0.5 to 1 × 10 ¹⁵ / cm ² , respectively.

  Here, the polycrystalline silicon constituting the upper part (first p-type impurity region 8g) of the gate electrode 6p into which the p-type impurity is ion-implanted and the semiconductor substrate 1 into which the p-type impurity is ion-implanted (first p-type impurity region 8). The single crystal silicon constituting the film is made amorphous.

  Next, as shown in FIG. 4, after a silicon oxide film 9a having a thickness of, for example, about 10 nm is deposited on the main surface of the semiconductor substrate 1, a nitride film having a thickness of, for example, about 50 nm is further formed on the silicon oxide film 9a. A silicon film 9b is deposited. Subsequently, the silicon nitride film 9b and the silicon oxide film 9a are sequentially etched by the RIE (Reactive Ion Etching) method to form the side walls 9 on the side surfaces of the gate electrodes 6n and 6p of nMIS and pMIS. The length of the sidewall 9 (sidewall length) is, for example, about 20 to 40 nm.

Next, as shown in FIG. 5, the pMIS region is covered with a resist pattern 10, and n-type impurities such as phosphorus (P) or arsenic (As) are ion-implanted into the nMIS region and the resistive element region of the semiconductor substrate 1. A second n-type impurity region 11g is formed on the gate electrode 6n, and a pair of second n-type impurity regions 11 are formed on the semiconductor substrate 1 (p-type well 3) on both sides of the sidewall 9. At the same time, a second n-type impurity region (resistance impurity region) 11r is formed in the resistance element region. For example, the implantation amount and implantation energy in arsenic (As) ion implantation are 5 to 10 keV and 1 to 5 × 10 ¹⁵ / cm ² , respectively.

  Here, the polycrystalline silicon constituting the upper part (second n-type impurity region 11g) of the gate electrode 6n into which the n-type impurity is ion-implanted and the semiconductor substrate 1 into which the n-type impurity is ion-implanted (the second n-type impurity region 11, The single crystal silicon constituting 11r) is made amorphous.

Next, as shown in FIG. 6, after removing the resist pattern 10, the nMIS region is covered with the resist pattern 12, and a p-type impurity such as boron (B) or boron fluoride (BF ₂ ) is added to the pMIS region of the semiconductor substrate 1. ) Is implanted to form a second p-type impurity region 13g above the gate electrode 6p, and a pair of second p-type impurity regions 13 are formed in the semiconductor substrate 1 (n-type well 4) on both sides of the sidewall 9. . For example, the implantation amount and implantation energy for boron (B) ion implantation are 1.4 to ² keV and 1 to 5 × 10 ¹⁵ / cm ² , respectively.

  Here, the polycrystalline silicon above the gate electrode 6p into which the p-type impurity is ion-implanted (second p-type impurity region 13g) and the semiconductor substrate 1 into which the p-type impurity is ion-implanted (second p-type impurity region 13) Crystalline silicon is made amorphous.

  Next, as shown in FIG. 7, after removing the resist pattern 12, a first insulating film 14 is deposited on the main surface of the semiconductor substrate 1. Further, as shown in FIG. 8, a second insulating film 15 is deposited on the first insulating film 14, and a third insulating film 16 is deposited on the second insulating film 15 as shown in FIG. The thickness of the first insulating film 14 is, for example, about 2 to 5 nm, the thickness of the second insulating film 15 is, for example, about 2 to 5 nm, and the thickness of the third insulating film 16 is, for example, about 20 to 50 nm.

  The first insulating film 14 is a film having a better covering property than the second insulating film 15 and has a different etching selectivity from the second insulating film 15 (under the same etching conditions, the first insulating film 14 The etching rate is slower than the etching rate of the second insulating film 15). Furthermore, the insulating film 14 is a film having an etching selectivity different from that of the sidewall 9 (the etching rate of the first insulating film 14 is faster than the etching rate of the sidewall 9 under the same etching conditions).

The first insulating film 14 is formed by a CVD method using TEOS (Tetra Ethyl Ortho Silicate; Si (OC ₂ H ₅ ) ₄ ) and ozone (O ₃ ) as source gases at a temperature of about 300 to 500 ° C., for example. A TEOS film (hereinafter referred to as an O ₃ -TEOS film).

The second insulating film 15 is a film having a higher function of preventing the diffusion of hydrogen and moisture entering from the outside into the semiconductor substrate 1 than the first insulating film 14, and is formed by using, for example, plasma. It is a silicon film (hereinafter referred to as a p-SiON film) (see JP 2007-005527 A (Patent Publication 5)). Since the hydrogen trap density of the p-SiON film is 2.5 × 10 ¹⁹ cm ⁻³ or more, the p-SiON film having a thickness of ^{2 to} 5 nm has hydrogen of 5 to 12 × 10 ¹² cm ⁻² or more. It can be trapped.

As a method for forming the p-SiON film, the following three methods can be exemplified. The first method is a method of forming a p-SiON film by plasma CVD using monosilane (SiH ₄ ) and nitrogen oxide (N ₂ O). The second method is to use monosilane (SiH ₄ ), nitrogen oxide (N ₂ O), and the like before forming the third insulating film 16 in the apparatus for forming the third insulating film 16 (for example, a plasma CVD apparatus). This is a method (in situ method) for forming a p-SiON film by the plasma CVD method. In the third method, in the apparatus for forming the third insulating film 16 (for example, a plasma CVD apparatus), the surface of the first insulating film 14 is subjected to nitrogen (N ₂ ) plasma before the third insulating film 16 is formed. Alternatively, a p-SiON film is formed by nitriding with ammonia (NH ₃ ) plasma (in situ method).

  The first insulating film 14 is a film having a lower function of preventing the diffusion of hydrogen and moisture that have entered from the outside into the semiconductor substrate 1 compared to the second insulating film 15. The function of the laminated film with the film 15 overlapped is improved from the function of the single layer of the second insulating film 15.

The third insulating film 16 is a film having a large change in internal stress before and after the heat treatment, and is, for example, a silicon nitride film (hereinafter referred to as a p-SiN film) formed by a plasma CVD method. The p-SiN film is formed by plasma CVD using, for example, monosilane (SiH ₄ ) and nitrogen (N ₂ ) or ammonia (NH ₃ ).

  The silicon nitride film formed by the thermal CVD method hardly changes its internal stress (for example, tensile 1.33 GPa) before and after the heat treatment at 1000 ° C. or higher, whereas the p-SiN film formed by the plasma CVD method is The internal stress changes from tensile 0.66 GPa to tensile 1.8 GPa before and after heat treatment at 1000 ° C. or higher.

  Next, as shown in FIG. 10, the semiconductor substrate 1 is subjected to a heat treatment, for example, about 1000 to 1100 ° C., for example, spike annealing. As a result, the n-type impurities in the first n-type impurity region 7 and the second n-type impurity region 11 formed in the nMIS region are activated to form the nMIS first n-type impurity region 7 and second n-type impurity region 11. Source / drain is formed. Similarly, the p-type impurity in the first p-type impurity region 8 and the second p-type impurity region 13 formed in the pMIS region is activated to form the pMIS first p-type impurity region 8 and the second p-type impurity region 13. Source / drain is formed. In addition, the n-type impurity in the second n-type impurity region 11r formed in the resistance element region is activated to form a resistance portion.

  At the same time, the amorphous silicon and the semiconductor substrate 1 (second n-type impurity regions 11 and 11r) constituting the upper portion (second n-type impurity region 11g) of the nMIS gate electrode 6n that has been amorphousized by ion implantation of n-type impurities are formed. Amorphous silicon is recrystallized. Similarly, the amorphous silicon constituting the upper part (second p-type impurity region 13g) of the gate electrode 6p of the pMIS that has been amorphized by ion implantation of p-type impurities and the amorphous material constituting the semiconductor substrate 1 (second p-type impurity region 13). Silicon is recrystallized.

  Furthermore, in this heat treatment, the internal stress of the third insulating film 16 changes. For example, when a p-SiN film is applied to the third insulating film 16, the internal stress of the p-SiN film changes from a tension of 0.66 GPa to a tension of 1.8 GPa before and after the heat treatment. As a result, stress is applied to the gate electrodes 6n and 6p of the nMIS and pMIS covered by the third insulating film 16, and strain is generated in the polycrystalline silicon constituting the gate electrodes 6n and 6p, and the strain is quenched ( Freeze memory).

  Further, when a p-SiN film is applied to the third insulating film 16, the p-SiN film contains a large amount of hydrogen and moisture, and the hydrogen and moisture contained in the p-SiN film can be easily applied to the semiconductor substrate 1 by heat treatment. Will spread. However, diffusion of hydrogen and moisture into the semiconductor substrate 1 can be prevented by the second insulating film 15 (or the first insulating film 14 and the second insulating film 15) formed under the p-SiN film. As a result, crystal defects are less likely to occur in the semiconductor substrate 1. In the present embodiment, neither nMIS nor pMIS causes characteristic deterioration due to crystal defects, such as an increase in junction leakage current.

  Next, as shown in FIG. 11, the third insulating film 16 is removed by hot phosphoric acid to expose the second insulating film 15. By removing the third insulating film 16, the polycrystalline silicon constituting the gate electrodes 6n and 6p of the nMIS and pMIS expands, and distortion occurs in the channels of the nMIS and pMIS. In the present embodiment, in the case of nMIS, the on-current of the nMIS in which the channel is distorted is increased by about 7% from the on-current of the nMIS in which the channel is not distorted. On the other hand, in the case of pMIS, no significant increase in on-current was observed as in nMIS, but other operating characteristics were not deteriorated.

  Next, as shown in FIG. 12, a fourth insulating film (silicide protection film) 17 is deposited on the second insulating film 15. The fourth insulating film is a TEOS film formed by a CVD method using TEOS and ozone as source gases at a temperature of about 300 to 500 ° C., for example. The thickness of the fourth insulating film 17 is, for example, about 10 to 20 nm.

  Next, as shown in FIG. 13, an nMIS region (non-silicide region) and a resistance element region where a silicide film is not formed in a later step are covered with a resist pattern (not shown), and dry etching or masking using the resist pattern as a mask is performed. The fourth insulating film 17, the second insulating film 15, and the first insulating film 14 exposed from the resist pattern are sequentially removed by wet etching. As a result, the upper surface of the nMIS gate electrode 6n and the upper surface of the source / drain (second n-type impurity region 11) on which the silicide film is formed in a later step, and the upper surface of the pMIS gate electrode 6p on which the silicide film is formed and The upper surface of the source / drain (second p-type impurity region 13) is exposed.

Next, as shown in FIG. 14, a nickel (Ni) film (not shown) is formed on the main surface of the semiconductor substrate 1, and then heat treatment is performed. By this heat treatment, the single crystal silicon and nickel constituting the semiconductor substrate 1 and the polycrystalline silicon constituting the gate electrodes 6n and 6p of nMIS and pMIS and nickel are solid-phase reacted to form nickel silicide (NiSi). To do. Subsequently, unreacted nickel is removed using a mixed solution of sulfuric acid (H ₂ SO ₄ ) and hydrogen peroxide water (H ₂ O ₂ ), whereby the upper surface of the nMIS gate electrode 6 n and the source / drain ( A silicide film 18 is formed on the upper surface of the second n-type impurity region 11). Similarly, a silicide film 18 is formed on the upper surface of the gate electrode 6p of pMIS and the upper surface of the source / drain (second p-type impurity region 13). Instead of nickel silicide, for example, nickel alloy silicide obtained by adding platinum (Pt) or the like to nickel, platinum silicide (PtSi), cobalt silicide (CoSi ₂ ), or the like may be applied. By forming the silicide film, the connection resistance with a plug or the like formed in a later process can be reduced. Further, it is possible to reduce the resistance of the gate electrodes 6n and 6p of nMIS and pMIS and the resistance of the source / drain itself.

  As described above, the diffusion of hydrogen and moisture contained in the third insulating film 16 into the semiconductor substrate 1 is blocked by the second insulating film 15 (or the first insulating film 14 and the second insulating film 15), and the semiconductor substrate. 1 is reduced, the abnormal growth of the silicide film 18 can be prevented.

  Next, as shown in FIG. 15, a fifth insulating film 19 is deposited on the main surface of the semiconductor substrate 1. The fifth insulating film 19 is, for example, a silicon nitride film.

  Next, as shown in FIG. 16, an interlayer insulating film 20 is deposited on the fifth insulating film 19. The interlayer insulating film 20 is a TEOS film formed by plasma CVD using, for example, TEOS and ozone as source gases. Subsequently, the interlayer insulating film 20 is polished by a CMP (Chemical Vapor Deposition) method to flatten the surface.

  Next, as shown in FIG. 17, in the nMIS region (silicide region) and the pMIS region (silicide region) where the silicide film 18 is formed by dry etching using the resist pattern as a mask, the interlayer insulating film 20 and the fifth insulating film are formed. The film 19 is etched to form connection holes (first connection holes) 21 at predetermined locations. Thus, in the nMIS region (silicide region) where the silicide film 18 is formed, the silicide film 18 formed on the upper surface of the gate electrode 6n of the nMIS and the upper surface of the source / drain (second n-type impurity region 11) are formed. Connection holes 21 reaching the silicide films 18 are formed. Similarly, in the pMIS region (silicide region) in which the silicide film 18 is formed, the silicide film 18 formed on the upper surface of the gate electrode 6p of the pMIS and the upper surface of the source / drain (second p-type impurity region 13) are formed. Connection holes 21 reaching the silicide films 18 are formed. Note that the connection hole 21 formed in the upper part of the gate electrodes 6n and 6p in the silicide region is not shown in FIG.

  On the other hand, in the nMIS region (non-silicide region) and the resistance element region where the silicide film 18 is not formed, the fourth insulating film 17, the second insulating film 15, and the first insulating film 14 are located under the fifth insulating film 19. Since it is formed, the interlayer insulating film 20, the fifth insulating film 19, the fourth insulating film 17, the second insulating film 15, and the first insulating film 14 are etched by the dry etching, and a connection hole is formed at a predetermined position. (Second connection hole) 21 is formed. Thereby, in the nMIS region (non-silicide region) where the silicide film 18 is not formed, the connection holes 21 reaching the gate electrode 6n of the nMIS and the source / drain (second n-type impurity region 11) are formed. In the resistance element region, a connection hole 21 reaching the second n-type impurity region 11r is formed. Note that the connection hole 21 formed in the upper part of the gate electrode 6n in the non-silicide region is not shown in FIG.

  Here, the fourth insulating film 17 and the second insulating film 15 are made of different materials, and the second insulating film 15 and the first insulating film 14 are made of different materials. The first insulating film 14 and the fourth insulating film 17 are, for example, TEOS films, and the second insulating film 15 is, for example, a p-SiON film. Thereby, after the fourth insulating film 17 is processed by dry etching, once the change of the etching rate can be confirmed by the second insulating film 15, and further, the change of the etching rate can be confirmed by the first insulating film 14, Over-etching of the connection hole 21 can be prevented.

  Next, as shown in FIG. 18, a barrier metal film (for example, titanium nitride (TiN) film) and a metal film (for example, tungsten (W) film) are sequentially formed on the main surface of the semiconductor substrate 1 including the inside of the connection hole 21. After the deposition, the barrier metal film and the metal film are polished by the CMP method, and the barrier metal film and the metal film are embedded in the connection hole 21 to form the plug 22. The barrier metal film has a function of preventing the metal film from diffusing into the semiconductor substrate 1.

  Thereafter, after depositing a metal film (for example, an aluminum (Al) film or a copper (Cu) film) on the main surface of the semiconductor substrate 1, the metal film is processed by dry etching using the resist pattern as a mask to form the wiring 23. Form.

  Through the manufacturing process described above, the CMIS device and the resistance element according to the present embodiment are substantially completed. Thereafter, the semiconductor device is manufactured by forming a further upper layer wiring through a normal manufacturing process of the semiconductor device.

  As described above, according to the present embodiment, by using the third insulating film 16 whose internal stress greatly changes by the heat treatment, distortion is generated in each channel of nMIS and pMIS, thereby improving operating characteristics, for example, It is possible to increase the on-current of the nMIS. In nMIS, tensile stress is generated in the entire channel region mainly in the gate length direction. That is, uniaxial tensile stress is generated. In pMIS, compressive stress is generated in the entire channel region mainly in the gate length direction. That is, uniaxial compressive stress is generated.

  However, the third insulating film 16 contains a lot of hydrogen and moisture, and the hydrogen and moisture contained in the third insulating film 16 are easily diffused by the heat treatment. However, since the second insulating film 15 (or the first insulating film 14 and the second insulating film 15) formed under the third insulating film 16 prevents hydrogen and moisture from diffusing into the semiconductor substrate 1, Generation of crystal defects in the semiconductor substrate 1 can be suppressed. Thereby, for example, it is possible to prevent a decrease in manufacturing yield due to abnormal growth of the silicide film 18 due to crystal defects. In addition, an increase in junction leakage current through crystal defects can be prevented, and power consumption can be reduced.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention can be applied to the manufacture of a semiconductor device having a field-effect transistor that realizes high speed using channel distortion.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Element isolation | separation 3 P-type well 4 N-type well 5 Gate insulating film 6n, 6p Gate electrode 7, 7g 1n type impurity region 7r 1st n-type impurity region (impurity region for resistance)
8, 8g First p-type impurity region 9 Side wall 9a Silicon oxide film 9b Silicon nitride film 10 Resist pattern 11, 11g Second n-type impurity region 11r Second n-type impurity region (resistance impurity region)
12 resist patterns 13, 13g second p-type impurity region 14 first insulating film 15 second insulating film 16 third insulating film 17 fourth insulating film (silicide protection film)
18 Silicide film 19 Fifth insulating film 20 Interlayer insulating film 21 Connection hole 22 Plug 23 Wiring

Claims (11)

A method for manufacturing a semiconductor device comprising the following steps:
(A) a step of sequentially forming a gate insulating film and a gate electrode on the main surface of the first region of the first conductivity type semiconductor substrate;
(B) forming a sidewall on a side surface of the gate electrode;
(C) forming an impurity region by ion-implanting a second conductivity type impurity different from the first conductivity type into the semiconductor substrate on both sides of the sidewall;
(D) a step of forming a first insulating film on the main surface of the semiconductor substrate after the step (c);
(E) a step of forming a second insulating film on the first insulating film after the step (d);
(F) After the step (e), forming a third insulating film on the second insulating film;
(G) a step of performing a heat treatment after the step (f),
Here, the first insulating film is a film having better coverage than the second insulating film, and is a film having an etching selectivity different from that of the second insulating film,
The second insulating film is a film having a higher function of preventing hydrogen diffusion than the first insulating film,
The third insulating film is a film having a larger change in internal stress than the first insulating film and the second insulating film.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the third insulating film is a silicon nitride film formed by a film forming method using plasma.   3. The method of manufacturing a semiconductor device according to claim 2, wherein the second insulating film is a silicon oxynitride film formed by a film forming method using plasma.   4. The method of manufacturing a semiconductor device according to claim 3, wherein the first insulating film is a TEOS film formed by a CVD method using TEOS and ozone as source gases.   4. The method of manufacturing a semiconductor device according to claim 3, wherein the silicon oxynitride film is formed by a plasma CVD method using monosilane and nitrogen oxide.   4. The method of manufacturing a semiconductor device according to claim 3, wherein the silicon oxynitride film is formed by nitriding the surface of the first insulating film with nitrogen plasma or ammonia plasma. .   2. The method of manufacturing a semiconductor device according to claim 1, wherein the first insulating film has a thickness of 2 to 5 nm, the second insulating film has a thickness of 2 to 5 nm, and the third insulating film has a thickness of A method for manufacturing a semiconductor device, wherein the thickness is 20 to 50 nm.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the heat treatment in the step (g) is spike annealing, and the temperature is 1000 to 1100.degree. In the manufacturing method of the semiconductor device according to claim 1,
Furthermore, the step (c)
(C1) forming a resistance impurity region by ion-implanting a second conductivity type impurity into a second region different from the first region of the semiconductor substrate;
Including
Further, after the step (g), the method includes the following steps:
(H) removing the third insulating film in the first region and the second region;
(I) After the step (h), a step of forming a fourth insulating film on the second insulating film;
(J) After the step (i), removing the fourth insulating film, the second insulating film, and the first insulating film in the first region;
(K) After the step (j), a step of forming a silicide film on each upper surface of the gate electrode and the impurity region in the first region;
(L) A step of forming a fifth insulating film on the main surface of the semiconductor substrate after the step (k);
(M) forming an interlayer insulating film on the fifth insulating film;
(N) forming a first connection hole reaching the silicide film in the interlayer insulating film, the fifth insulating film, and the fourth insulating film in the first region; and the interlayer insulating film in the second region; Forming a second connection hole reaching the resistance impurity region in the fifth insulating film, the fourth insulating film, the second insulating film, and the first insulating film;
(O) forming an electrode inside the first connection hole and the second connection hole;   10. The method of manufacturing a semiconductor device according to claim 9, wherein the fourth insulating film is a TEOS film formed by a CVD method using TEOS and ozone as source gases.   10. The method of manufacturing a semiconductor device according to claim 9, wherein the fifth insulating film is a silicon nitride film.

Images