JP6094243B2 - Composite substrate and method for manufacturing semiconductor wafer using the same - Google Patents

Composite substrate and method for manufacturing semiconductor wafer using the same Download PDF

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JP6094243B2
JP6094243B2 JP2013022222A JP2013022222A JP6094243B2 JP 6094243 B2 JP6094243 B2 JP 6094243B2 JP 2013022222 A JP2013022222 A JP 2013022222A JP 2013022222 A JP2013022222 A JP 2013022222A JP 6094243 B2 JP6094243 B2 JP 6094243B2
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substrate
film
semiconductor
semiconductor layer
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JP2014154668A (en
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裕紀 関
裕紀 関
一成 佐藤
一成 佐藤
喜之 山本
喜之 山本
松原 秀樹
秀樹 松原
浩一 曽我部
浩一 曽我部
長谷川 幹人
幹人 長谷川
裕 辻
裕 辻
明人 藤井
明人 藤井
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Sumitomo Electric Industries Ltd
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    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02Epitaxial-layer growth
    • C30B25/18Epitaxial-layer growth characterised by the substrate
    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10Inorganic compounds or compositions
    • C30B29/40AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
    • C30B29/403AIII-nitrides
    • C30B29/406Gallium nitride
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/0242Crystalline insulating materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials

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Description

本発明は、高品質の半導体ウエハを高収率で効率よく製造するために好適な複合基板およびそれを用いた半導体ウエハの製造方法に関する。   The present invention relates to a composite substrate suitable for efficiently producing a high-quality semiconductor wafer with high yield and a method for producing a semiconductor wafer using the same.

GaNウエハなどのIII族窒化物の半導体ウエハは、発光デバイス、電子デバイスなどの半導体デバイスの基板および半導体層として好適に用いられる。かかる半導体ウエハを製造するための下地基板としては、その下地基板と半導体ウエハとの間で、格子定数および熱膨張係数を一致させるまたは一致に近づける観点から、半導体ウエハと化学組成が同じまたは近似しているものが優れている。ところが、半導体ウエハがGaNウエハなどの場合は、下地基板として最も優れるGaN基板は非常に高価であり、また、主面の直径が2インチを超える大口径のGaN基板の入手は困難である。   Group III nitride semiconductor wafers such as GaN wafers are suitably used as substrates and semiconductor layers of semiconductor devices such as light-emitting devices and electronic devices. As a base substrate for manufacturing such a semiconductor wafer, the chemical composition is the same as or close to that of the semiconductor wafer from the viewpoint of making the lattice constant and the thermal expansion coefficient match or close to match between the base substrate and the semiconductor wafer. What you have is excellent. However, when the semiconductor wafer is a GaN wafer or the like, the most excellent GaN substrate as the base substrate is very expensive, and it is difficult to obtain a large-diameter GaN substrate having a main surface diameter exceeding 2 inches.

このため、GaNウエハを形成するための下地基板として、一般に、サファイア基板が用いられている。しかしながら、サファイア結晶とGaN結晶とでは、それらの格子定数および熱膨張係数が大きく異なる。   For this reason, a sapphire substrate is generally used as a base substrate for forming a GaN wafer. However, sapphire crystals and GaN crystals have greatly different lattice constants and thermal expansion coefficients.

このため、サファイア結晶とGaN結晶との間の格子定数の不整合を緩和して結晶性が良好なGaNウエハを形成するために、たとえば、特開平04−297023号公報(特許文献1)は、サファイア基板にGaN結晶を成長させる際に、サファイア基板上にGaNバッファ層を形成し、そのGaNバッファ層上にGaN結晶層を成長させることを開示する。   For this reason, in order to relax the mismatch of the lattice constant between the sapphire crystal and the GaN crystal and form a GaN wafer with good crystallinity, for example, Japanese Patent Laid-Open No. 04-297023 (Patent Document 1) It is disclosed that when a GaN crystal is grown on a sapphire substrate, a GaN buffer layer is formed on the sapphire substrate and the GaN crystal layer is grown on the GaN buffer layer.

また、GaN結晶の熱膨張係数に近い熱膨張係数の支持基板とGaN単結晶膜との複合基板を用いて結晶性が高く反りの小さいGaN系膜を得るために、たとえば、特開2012−121788号公報(特許文献2)は、主面内の熱膨張係数がGaN結晶の熱膨張係数に比べて0.8倍より大きく1.2倍より小さい酸化物焼結体支持基板と、支持基板の主面側に配置されているGaN単結晶膜とを含む複合基板のGaN単結晶膜上に、GaN系膜を成長させることを開示する。   In order to obtain a GaN-based film having a high crystallinity and a small warpage using a composite substrate of a support substrate having a thermal expansion coefficient close to that of the GaN crystal and a GaN single crystal film, for example, JP 2012-121788 A (Patent Document 2) discloses that an oxide sintered body supporting substrate having a thermal expansion coefficient in the main surface larger than 0.8 times and smaller than 1.2 times the thermal expansion coefficient of the GaN crystal, Disclosed is a growth of a GaN-based film on a GaN single crystal film of a composite substrate including a GaN single crystal film disposed on the main surface side.

特開平04−297023号公報Japanese Patent Laid-Open No. 04-297023 特開2012−121788号公報JP 2012-121788 A

上記の特開平04−297023号公報(特許文献1)においては、サファイア結晶の熱膨張係数がGaN結晶の熱膨張係数に比べて非常に大きいため、主面の直径が大きくなるほど、反りの小さいGaN膜を得ることは困難である。   In the above Japanese Patent Laid-Open No. 04-297023 (Patent Document 1), since the thermal expansion coefficient of a sapphire crystal is much larger than the thermal expansion coefficient of a GaN crystal, the larger the main surface diameter, the smaller the warpage of GaN. It is difficult to obtain a film.

一方、上記の特開2012−121788号公報(特許文献2)においては、用いられる複合基板には、酸化物焼結体支持基板の研磨後の平坦化度が低く、酸化物焼結体支持基板とGaN単結晶膜との間の接合が不十分な領域があり、かかる領域上においてGaN系膜の均一な成長が阻害され、GaN系膜の収率向上を阻害するという問題点があった。   On the other hand, in the above-mentioned Japanese Patent Application Laid-Open No. 2012-121788 (Patent Document 2), the composite substrate used has a low flatness after polishing of the oxide sintered body supporting substrate, and the oxide sintered body supporting substrate. There is a region where the bonding between the GaN-based film and the GaN single crystal film is insufficient, and the uniform growth of the GaN-based film is inhibited on the region, which hinders the improvement of the yield of the GaN-based film.

本発明は、上記の問題点を解決して、高品質の半導体ウエハを高収率で効率よく製造するために好適な複合基板およびそれを用いた半導体ウエハの製造方法を提供することを目的とする。   An object of the present invention is to solve the above problems and provide a composite substrate suitable for efficiently producing a high-quality semiconductor wafer with high yield and a method for producing a semiconductor wafer using the same. To do.

本発明は、結晶相として35質量%以上65質量%以下のムライト相および35質量%以上65質量%以下のアルミナ相を含み、非結晶相として10質量%以下のシリカ相を含む支持基板と、支持基板の主面側に配置されている半導体膜と、を含む複合基板である。 The present invention, viewed contains 35 mass% or more 65 wt% or less of mullite phase and 35 wt% or more 65 wt% or less of the alumina phase as a crystal phase, including the support substrate 10 mass% or less of the silica phase as the amorphous phase And a semiconductor film disposed on the main surface side of the support substrate.

また、本発明は、結晶相として35質量%以上65質量%以下のムライト相および35質量%以上65質量%以下のアルミナ相を含み、非結晶相として10質量%以下のシリカ相を含む支持基板と、支持基板の主面側に配置されている半導体膜と、を含む複合基板を準備する工程と、複合基板の半導体膜上に少なくとも1層の半導体層を成長させて半導体層付複合基板を形成する工程と、半導体層付複合基板から支持基板を除去して半導体ウエハを形成する工程と、を含む半導体ウエハの製造方法である。 The present invention also viewed contains 35 mass% or more 65 wt% or less of mullite phase and 35 wt% or more 65 wt% or less of the alumina phase as a crystal phase, including 10 mass% or less of the silica phase as the amorphous phase A step of preparing a composite substrate including a support substrate and a semiconductor film disposed on a main surface side of the support substrate; and a composite with a semiconductor layer by growing at least one semiconductor layer on the semiconductor film of the composite substrate A method for manufacturing a semiconductor wafer, comprising: a step of forming a substrate; and a step of forming a semiconductor wafer by removing a support substrate from the composite substrate with a semiconductor layer.

本発明によれば、高品質の半導体ウエハを高収率で効率よく製造するために好適な複合基板およびそれを用いた半導体ウエハの製造方法を提供できる。   ADVANTAGE OF THE INVENTION According to this invention, in order to manufacture a high quality semiconductor wafer efficiently with a high yield, the suitable composite substrate and the manufacturing method of a semiconductor wafer using the same can be provided.

本発明にかかる複合基板の一例を示す概略断面図である。It is a schematic sectional drawing which shows an example of the composite substrate concerning this invention. 本発明にかかる複合基板を準備する工程の一例を示す概略断面図である。It is a schematic sectional drawing which shows an example of the process of preparing the composite substrate concerning this invention. 本発明にかかる複合基板を準備する工程の別の例を示す概略断面図である。It is a schematic sectional drawing which shows another example of the process of preparing the composite substrate concerning this invention. 本発明にかかる半導体ウエハの製造方法を示す概略断面図である。It is a schematic sectional drawing which shows the manufacturing method of the semiconductor wafer concerning this invention.

[実施形態1:複合基板]
図1を参照して、本発明の一実施形態である複合基板1は、結晶相として35質量%以上65質量%以下のムライト相および35質量%以上65質量%以下のアルミナ相を含む支持基板11と、支持基板11の主面11m側に配置されている半導体膜13と、を含む。本実施形態の複合基板1は、その支持基板11が結晶相としてムライト相およびアルミナ相を含み、ムライト相の含有量が35質量%以上65質量%以下でかつアルミナ相の含有量が35質量%以上65質量%以下であることから、支持基板11の研磨後の主面の平坦化度が高くなるとともに半導体膜13の熱膨張係数αFに対する支持基板11の熱膨張係数αSの比αF/αSが1に近くなる。これにより、複合基板1は、支持基板11と半導体膜13との接合性が高くなるとともに反りおよび割れの発生が抑制されるため、半導体膜13上に高品質の半導体ウエハを高収率で効率よく形成することができる。
[Embodiment 1: Composite substrate]
Referring to FIG. 1, a composite substrate 1 according to an embodiment of the present invention includes a support substrate including a mullite phase of 35% to 65% by mass and an alumina phase of 35% to 65% by mass as crystal phases. 11 and a semiconductor film 13 disposed on the main surface 11m side of the support substrate 11. In the composite substrate 1 of this embodiment, the support substrate 11 includes a mullite phase and an alumina phase as crystal phases, the mullite phase content is 35 mass% to 65 mass%, and the alumina phase content is 35 mass%. Since the amount is 65% by mass or less, the planarization degree of the main surface after polishing of the support substrate 11 is increased, and the ratio α F of the thermal expansion coefficient α S of the support substrate 11 to the thermal expansion coefficient α F of the semiconductor film 13 is increased. / Α S is close to 1. Thereby, since the composite substrate 1 has high bonding properties between the support substrate 11 and the semiconductor film 13 and the occurrence of warping and cracking is suppressed, a high-quality semiconductor wafer can be efficiently produced on the semiconductor film 13 with high yield. Can be well formed.

(支持基板)
図1を参照して、本実施形態の複合基板1に含まれる支持基板11は、支持基板11の研磨後の主面の平坦化度を高くする観点から、結晶相として35質量%以上65質量%以下のムライト相および35質量%以上65質量%以下のアルミナ相を含むことが必要である。さらに、支持基板11は、研磨後の主面の平坦化度がより高くする観点から、ムライト相の含有量は、40質量%以上63質量%以下が好ましく、45質量%以上61質量%以下がより好ましい。また、支持基板11のアルミナ相の含有量は、37質量%以上55質量%以下が好ましく、39質量%以上49質量%以下がより好ましい。
(Support substrate)
With reference to FIG. 1, the support substrate 11 included in the composite substrate 1 of the present embodiment has a crystal phase of 35% by mass or more and 65% by mass from the viewpoint of increasing the flatness of the main surface after polishing of the support substrate 11. % Of mullite phase and 35% by mass or more and 65% by mass or less of alumina phase are necessary. Furthermore, the support substrate 11 has a mullite phase content of preferably 40% by mass or more and 63% by mass or less, and 45% by mass or more and 61% by mass or less from the viewpoint of further increasing the flatness of the main surface after polishing. More preferred. In addition, the content of the alumina phase of the support substrate 11 is preferably 37% by mass or more and 55% by mass or less, and more preferably 39% by mass or more and 49% by mass or less.

支持基板11において、ムライト相の化学組成はAl6Si213(3Al23・2SiO2)またはその近傍の組成であり、アルミナ相の化学組成はAl23である。結晶相であるムライト相およびアルミナ相の含有量は、X線回折により測定することができる。また、支持基板11の研磨後の主面の平坦化度は、研磨後の主面のJIS B0601に規定する算術平均粗さRaを測定することにより評価することができる。算術平均粗さRaが小さいほど平坦化度が高く、算術平均粗さRaが大きいほど平坦化度が低い。 In the support substrate 11, the chemical composition of the mullite phase is Al 6 Si 2 O 13 (3Al 2 O 3 .2SiO 2 ) or a composition in the vicinity thereof, and the chemical composition of the alumina phase is Al 2 O 3 . The contents of the mullite phase and the alumina phase which are crystal phases can be measured by X-ray diffraction. Further, the flatness of the main surface after polishing of the support substrate 11 can be evaluated by measuring the arithmetic average roughness Ra defined in JIS B0601 of the main surface after polishing. The smaller the arithmetic average roughness Ra, the higher the flatness degree, and the higher the arithmetic average roughness Ra, the lower the flatness degree.

支持基板11は、研磨後の主面の平坦化度を高く維持したまま、フッ化水素酸などのエッチャントに対する被エッチング性を高めることにより複合基板1からの除去性を高める観点から、非結晶相として10質量%以下のシリカ相をさらに含むことが好ましい。支持基板11中のシリカ相の含有量が10質量%を超えると、支持基板11の研磨後の主面の平坦化度が低下する傾向がある。また、複合基板1からの支持基板11の除去性を高める観点から、支持基板11中のシリカ相の含有量は0.02質量%以上が好ましい。また、支持基板11において、シリカ相の化学組成はSiO2である。非結晶相であるシリカ相の含有量は、支持基板11を十分にエッチングした後のエッチャント中のSi濃度をICP−OES(誘導結合プラズマ−発光)分析により測定することにより算出できる。 From the viewpoint of improving the removability from the composite substrate 1 by increasing the etchability with respect to an etchant such as hydrofluoric acid while maintaining the flatness of the main surface after polishing high, the support substrate 11 is an amorphous phase. It is preferable to further contain 10 mass% or less of silica phase. When the content of the silica phase in the support substrate 11 exceeds 10% by mass, the degree of planarization of the main surface after polishing of the support substrate 11 tends to decrease. Further, from the viewpoint of enhancing the removability of the support substrate 11 from the composite substrate 1, the content of the silica phase in the support substrate 11 is preferably 0.02% by mass or more. Further, the support substrate 11, the chemical composition of the silica phase is SiO 2. The content of the silica phase that is an amorphous phase can be calculated by measuring the Si concentration in the etchant after sufficiently etching the support substrate 11 by ICP-OES (inductively coupled plasma-luminescence) analysis.

支持基板11は、上記の特徴を有するものであればその製造方法および形態に特に制限はないが、各化学組成分の含有量の調整による物性の調節が容易な観点から、原料として、アルミナ粉末およびシリカ粉末の混合粉末、あるいはムライト粉末、アルミナ粉末およびシリカ粉末の混合粉末を用いて、これらの原料を焼結することにより得られた焼結体で形成することが好ましい。   The supporting substrate 11 is not particularly limited in its production method and form as long as it has the above-mentioned characteristics, but from the viewpoint of easy physical property adjustment by adjusting the content of each chemical composition, alumina powder is used as a raw material. It is preferable to form a sintered body obtained by sintering these raw materials using a mixed powder of silica powder and a mixed powder of mullite powder, alumina powder and silica powder.

(半導体膜)
図1を参照して、本実施形態の複合基板1に含まれる半導体膜13の厚さは、その半導体膜13上に結晶性の高い少なくとも1層の半導体層を成長させる観点から、その厚さが、10μm以上が必要であり、20μm以上が好ましく、50μm以上がより好ましい。また、半導体膜13の厚さは、安価な複合基板を得る観点から、その厚さが、250μm以下が好ましく、200μm以下がより好ましい。
(Semiconductor film)
Referring to FIG. 1, the thickness of the semiconductor film 13 included in the composite substrate 1 of the present embodiment is the thickness from the viewpoint of growing at least one semiconductor layer having high crystallinity on the semiconductor film 13. However, 10 micrometers or more are required, 20 micrometers or more are preferable and 50 micrometers or more are more preferable. In addition, the thickness of the semiconductor film 13 is preferably 250 μm or less, and more preferably 200 μm or less, from the viewpoint of obtaining an inexpensive composite substrate.

本実施形態の複合基板1に含まれる半導体膜13は、特に制限はないが、その半導体膜13上に結晶性の高い少なくとも1層の半導体層を成長させる観点から、成長させようとする半導体層と化学組成が同一または近似していることが好ましい。たとえば、成長させようとする半導体層がGaN系(Gaを含むIII族窒化物)層の場合は、半導体膜13はGaN膜が好ましい。   The semiconductor film 13 included in the composite substrate 1 of the present embodiment is not particularly limited, but from the viewpoint of growing at least one semiconductor layer having high crystallinity on the semiconductor film 13, a semiconductor layer to be grown. And the chemical composition is preferably the same or similar. For example, when the semiconductor layer to be grown is a GaN-based (Group III nitride containing Ga) layer, the semiconductor film 13 is preferably a GaN film.

(接合膜)
図1を参照して、本実施形態の複合基板1は、支持基板11と半導体膜13との接合強度を高める観点から、支持基板11と半導体膜13との間に接合膜12が形成されていることが好ましい。接合膜12は、特に制限はないが、支持基板11と半導体膜13との接合強度を高める効果が高い観点から、SiO2層、TiO2層などが好ましい。さらに、フッ化水素酸によりエッチング除去できる観点から、SiO2層がより好ましい。
(Bonding film)
With reference to FIG. 1, in the composite substrate 1 of this embodiment, a bonding film 12 is formed between the support substrate 11 and the semiconductor film 13 from the viewpoint of increasing the bonding strength between the support substrate 11 and the semiconductor film 13. Preferably it is. The bonding film 12 is not particularly limited, but an SiO 2 layer, a TiO 2 layer, or the like is preferable from the viewpoint that the effect of increasing the bonding strength between the support substrate 11 and the semiconductor film 13 is high. Furthermore, a SiO 2 layer is more preferable from the viewpoint that it can be removed by etching with hydrofluoric acid.

[実施形態2:半導体ウエハの製造方法]
図2、図3および図4を参照して、本発明の別の実施形態である半導体ウエハの製造方法は、結晶相として35質量%以上65質量%以下のムライト相および35質量%以上65質量%以下のアルミナ相とを含む支持基板11と、支持基板11の主面11m側に配置されている半導体膜13と、を含む複合基板1を準備する工程(図2(A)〜(D)、図3(A)〜(D)および図4(A))と、複合基板1の半導体膜13上に少なくとも1層の半導体層20を成長させて半導体層付複合基板2を形成する工程(図4(B))と、半導体層付複合基板2から支持基板11を除去して半導体ウエハを形成する工程(図4(C))と、を含む。本実施形態の半導体ウエハ3の製造方法は、結晶相として35質量%以上65質量%以下のムライト相および35質量%以上65質量%以下のアルミナ相を含む支持基板11とその主面11m側に配置されている半導体膜13とを含む複合基板1の半導体膜13上に、少なくとも1層の半導体層20を成長させた後、支持基板を除去することにより、高品質の半導体ウエハ3を高収率で効率よく製造することができる。
[Embodiment 2: Manufacturing Method of Semiconductor Wafer]
2, 3, and 4, a method for manufacturing a semiconductor wafer according to another embodiment of the present invention includes a mullite phase of 35 mass% or more and 65 mass% or less and a crystal phase of 35 mass% or more and 65 mass% or more. Step of preparing a composite substrate 1 including a support substrate 11 including an alumina phase of not more than% and a semiconductor film 13 disposed on the main surface 11m side of the support substrate 11 (FIGS. 2A to 2D). 3 (A) to 3 (D) and FIG. 4 (A)), and a step of growing at least one semiconductor layer 20 on the semiconductor film 13 of the composite substrate 1 to form the composite substrate 2 with a semiconductor layer ( 4B) and a step of removing the support substrate 11 from the composite substrate with semiconductor layer 2 to form a semiconductor wafer (FIG. 4C). The manufacturing method of the semiconductor wafer 3 of the present embodiment includes a support substrate 11 including a mullite phase of 35 mass% to 65 mass% and an alumina phase of 35 mass% to 65 mass% as crystal phases on the main surface 11 m side. After growing at least one semiconductor layer 20 on the semiconductor film 13 of the composite substrate 1 including the semiconductor film 13 disposed, the support substrate is removed to obtain a high-quality semiconductor wafer 3 with high yield. It can be manufactured efficiently at a high rate.

(複合基板の準備工程)
図4(A)を参照して、複合基板1を準備する工程において、複合基板1の支持基板11の主面11m側に半導体膜13を配置する方法には、特に制限はなく、支持基板11の主面11m上に半導体膜13を成長させる方法(第1の方法)、支持基板11の主面11mに、下地基板の主面上に成膜させた半導体膜13を貼り合わせた後下地基板を除去する方法(第2の方法)、支持基板11の主面11mに半導体膜ドナー基板(図示せず)を貼り合わせた後その半導体膜ドナー基板を貼り合わせ面から所定の深さの面で切断することにより支持基板11の主面11m上に半導体膜13を形成する方法(第3の方法)などが挙げられる。支持基板11が酸化物の焼結体で形成されている場合には、上記の第1の方法が困難であるため、上記の第2および第3のいずれかの方法が好ましく用いられる。上記の第2の方法において、支持基板11に半導体膜13を貼り合わせる方法には、特に制限はなく、支持基板11の主面11mに直接半導体膜13を貼り合わせる方法、支持基板11の主面11mに接合膜12を介在させて半導体膜13を貼り合わせる方法などが挙げられる。上記の第3の方法において、支持基板11に半導体膜ドナー基板を貼り合わせる方法には、特に制限はなく、支持基板11の主面11mに直接半導体膜ドナー基板を貼り合わせる方法、支持基板11の主面11mに接合膜12を介在させて半導体膜ドナー基板を貼り合わせる方法などが挙げられる。
(Preparation process of composite substrate)
With reference to FIG. 4A, in the step of preparing the composite substrate 1, the method for disposing the semiconductor film 13 on the main surface 11 m side of the support substrate 11 of the composite substrate 1 is not particularly limited. A method of growing the semiconductor film 13 on the main surface 11m (first method), and bonding the semiconductor film 13 formed on the main surface of the base substrate to the main surface 11m of the support substrate 11 and then the base substrate (Second method), a semiconductor film donor substrate (not shown) is bonded to the main surface 11m of the support substrate 11, and then the semiconductor film donor substrate is bonded at a predetermined depth from the bonding surface. For example, a method (third method) of forming the semiconductor film 13 on the main surface 11m of the support substrate 11 by cutting. When the support substrate 11 is formed of an oxide sintered body, the first method is difficult, and therefore any one of the second and third methods is preferably used. In the second method, the method for bonding the semiconductor film 13 to the support substrate 11 is not particularly limited, and the method for bonding the semiconductor film 13 directly to the main surface 11m of the support substrate 11 or the main surface of the support substrate 11 is not limited. For example, a method of bonding the semiconductor film 13 with the bonding film 12 interposed in 11 m may be used. In the third method, the method for bonding the semiconductor film donor substrate to the support substrate 11 is not particularly limited. The method for bonding the semiconductor film donor substrate directly to the main surface 11m of the support substrate 11, For example, a method may be used in which the semiconductor film donor substrate is bonded to the main surface 11m with the bonding film 12 interposed therebetween.

上記の複合基板1を準備する工程は、特に制限はないが、効率的に品質の高い複合基板1を準備する観点から、たとえば、図2を参照して、上記の第2の方法においては、支持基板11を準備するサブ工程(図2(A))と、下地基板30の主面30n上に半導体膜13を成膜するサブ工程(図2(B))と、支持基板11と半導体膜13とを貼り合わせるサブ工程(図2(C))と、下地基板30を除去するサブ工程(図2(D))と、含むことができる。   The step of preparing the composite substrate 1 is not particularly limited, but from the viewpoint of efficiently preparing a composite substrate 1 with high quality, for example, referring to FIG. A sub-process for preparing the support substrate 11 (FIG. 2A), a sub-process for forming the semiconductor film 13 on the main surface 30n of the base substrate 30 (FIG. 2B), the support substrate 11 and the semiconductor film 13 can be included, and a sub-process for removing the base substrate 30 (FIG. 2D).

図2(C)では、支持基板11と半導体膜13とを貼り合わせるサブ工程において、支持基板11の主面11m上に接合膜12aに形成し(図2(C1))、下地基板30の主面30n上に成長させられた半導体膜13の主面13n上に接合膜12bを形成した(図2(C2))後、支持基板11上に形成された接合膜12aの主面12amと下地基板30上に成膜された半導体膜13上に形成された接合膜12bの主面12bnとを貼り合わせることにより、接合膜12aと接合膜12bとが接合して形成された接合膜12を介在させて支持基板11と半導体膜13とが貼り合わされる(図2(C3))。しかし、支持基板11と半導体膜13とが互いに接合可能なものであれば、支持基板11と半導体膜13とを、接合膜12を介在させることなく直接貼り合わせることができる。   In FIG. 2C, in a sub-process for bonding the support substrate 11 and the semiconductor film 13, a bonding film 12a is formed on the main surface 11m of the support substrate 11 (FIG. 2C1). After forming the bonding film 12b on the main surface 13n of the semiconductor film 13 grown on the surface 30n (FIG. 2 (C2)), the main surface 12am of the bonding film 12a formed on the support substrate 11 and the base substrate By bonding the main surface 12bn of the bonding film 12b formed on the semiconductor film 13 formed on the semiconductor film 13, the bonding film 12a formed by bonding the bonding film 12a and the bonding film 12b is interposed. Then, the support substrate 11 and the semiconductor film 13 are bonded together (FIG. 2 (C3)). However, as long as the support substrate 11 and the semiconductor film 13 can be bonded to each other, the support substrate 11 and the semiconductor film 13 can be directly bonded together without the bonding film 12 interposed.

支持基板11と半導体膜13とを貼り合わせる具体的な手法としては、特に制限はないが、貼り合わせ後高温でも接合強度を保持できる観点から、貼り合わせ面を洗浄しそのまま貼り合わせた後600℃〜1200℃程度に昇温して接合する直接接合法、貼り合わせ面を洗浄しプラズマやイオンなどで活性化させた後に室温(たとえば25℃)〜400℃程度の低温で接合する表面活性化法などが好ましく用いられる。   A specific method for bonding the support substrate 11 and the semiconductor film 13 is not particularly limited, but from the viewpoint of maintaining the bonding strength even at a high temperature after bonding, the bonded surfaces are washed and bonded as they are, and then, 600 ° C. A direct bonding method in which bonding is performed by raising the temperature to about 1200 ° C., and a surface activation method in which bonding is performed at a low temperature of about room temperature (for example, 25 ° C.) to about 400 ° C. after the bonded surface is cleaned and activated with plasma or ions. Etc. are preferably used.

また、上記の複合基板1を準備する工程は、たとえば、図3を参照して、上記の第3の方法においては、支持基板11を準備するサブ工程(図3(A))と、半導体膜ドナー基板13Dを準備するサブ工程(図3(B))と、支持基板11と半導体膜ドナー基板13Dとを貼り合わせるサブ工程(図3(C))と、半導体膜ドナー基板13Dの貼り合わせ主面13nから内部に所定の距離に位置する面で半導体膜ドナー基板13Dを切断するサブ工程(図3(D))と、含むことができる。   The step of preparing the composite substrate 1 includes, for example, referring to FIG. 3, in the third method, the sub-step of preparing the support substrate 11 (FIG. 3A), the semiconductor film Sub-step for preparing donor substrate 13D (FIG. 3B), sub-step for bonding support substrate 11 and semiconductor film donor substrate 13D (FIG. 3C), and bonding of semiconductor film donor substrate 13D A sub-process (FIG. 3D) for cutting the semiconductor film donor substrate 13D along a surface located at a predetermined distance from the surface 13n.

図3(B)に示す半導体膜ドナー基板13Dとは、III族窒化物複合基板1を形成するために支持基板11に半導体膜13を提供する基板をいう。図3(B)を参照して、半導体膜ドナー基板13Dを準備する工程において、半導体膜ドナー基板13Dを製造する方法は、特に制限なく、半導体膜ドナー基板13DがIII−V族化合物半導体膜ドナー基板のときはHVPE(ハイドライド気相成長)法、MOCVD(有機金属化学気相堆積)法、MBE(分子線成長)法、昇華法、フラックス法、高窒素圧溶液法などにより好適に行なうことができ、半導体膜ドナー基板13DがIV族元素半導体膜ドナー基板またはIV族化合物半導体膜ドナー基板のときはLPE(液相成長)法、MOCVD法、MBE法、昇華法などにより好適に行なうことができる。   The semiconductor film donor substrate 13D shown in FIG. 3B refers to a substrate that provides the support substrate 11 with the semiconductor film 13 in order to form the group III nitride composite substrate 1. Referring to FIG. 3B, in the step of preparing the semiconductor film donor substrate 13D, the method of manufacturing the semiconductor film donor substrate 13D is not particularly limited, and the semiconductor film donor substrate 13D is a group III-V compound semiconductor film donor. In the case of a substrate, HVPE (hydride vapor deposition) method, MOCVD (metal organic chemical vapor deposition) method, MBE (molecular beam growth) method, sublimation method, flux method, high nitrogen pressure solution method, etc. are preferably used. In addition, when the semiconductor film donor substrate 13D is a group IV element semiconductor film donor substrate or a group IV compound semiconductor film donor substrate, it can be suitably performed by an LPE (liquid phase growth) method, an MOCVD method, an MBE method, a sublimation method, or the like. .

図3(C)では、支持基板11と半導体膜13とを貼り合わせるサブ工程において、支持基板11の主面11m上に接合膜12aに形成し(図3(C1))、III族窒化物膜ドナー基板13Dの主面13n上に接合膜12bを形成した(図3(C2))後、支持基板11上に形成された接合膜12aの主面12amとIII族窒化物膜ドナー基板13D上に形成された接合膜12bの主面12bnとを貼り合わせることにより、接合膜12aと接合膜12bとが接合して形成された接合膜12を介在させて支持基板11と半導体膜13とが貼り合わされる(図3(C3))。しかし、支持基板11と半導体膜13とが互いに接合可能なものであれば、支持基板11と半導体膜13とを、接合膜12を介在させることなく直接貼り合わせることができる。ここで、支持基板11と半導体膜13とを貼り合わせる具体的な手法としては、上記の図2(C)で説明したように、直接接合法、表面活性化法などが好ましく用いられる。こうして支持基板11と半導体膜ドナー基板13Dとが貼り合わされた接合基板1Lが得られる。   In FIG. 3C, in a sub-process for bonding the support substrate 11 and the semiconductor film 13, the bonding film 12a is formed on the main surface 11m of the support substrate 11 (FIG. 3C1), and the group III nitride film is formed. After the bonding film 12b is formed on the main surface 13n of the donor substrate 13D (FIG. 3 (C2)), the main surface 12am of the bonding film 12a formed on the support substrate 11 and the group III nitride film donor substrate 13D are formed. By bonding the principal surface 12bn of the formed bonding film 12b, the support substrate 11 and the semiconductor film 13 are bonded together with the bonding film 12 formed by bonding the bonding film 12a and the bonding film 12b interposed therebetween. (FIG. 3 (C3)). However, as long as the support substrate 11 and the semiconductor film 13 can be bonded to each other, the support substrate 11 and the semiconductor film 13 can be directly bonded together without the bonding film 12 interposed. Here, as described in FIG. 2C above, a direct bonding method, a surface activation method, or the like is preferably used as a specific method for bonding the supporting substrate 11 and the semiconductor film 13 together. Thus, a bonded substrate 1L in which the support substrate 11 and the semiconductor film donor substrate 13D are bonded together is obtained.

図3(D)を参照して、半導体膜ドナー基板13Dを切断するサブ工程においては、接合基板1Lの半導体膜ドナー基板13Dの貼り合わせ主面13nから内部に所定の距離に位置する面で半導体膜ドナー基板13Dを切断することにより、複合基板1が形成される。   Referring to FIG. 3D, in the sub-process for cutting the semiconductor film donor substrate 13D, the semiconductor is a surface located at a predetermined distance from the bonding main surface 13n of the semiconductor film donor substrate 13D of the bonding substrate 1L. The composite substrate 1 is formed by cutting the film donor substrate 13D.

半導体膜ドナー基板13Dを切断する方法は、特に制限はなく、ワイヤーソー、ブレードソー、レーザ加工、放電加工、ウォータージェットなどの方法が挙げられる。III族窒化物膜ドナー基板13Dをワイヤーソーで切断する場合、大口径のIII族窒化物膜ドナー基板13Dを平坦に切断するためには固定砥粒ワイヤーを用いることが好ましく、切断代(せつだんしろ)を低減するためには細線ワイヤーを用いることが好ましい。切断代を低減するためには遊離砥粒方式が好ましい。また、III族窒化物膜ドナー基板13Dをワイヤーソーで切断する際には、切断抵抗によるワイヤーの曲がりを低減して厚さの精度および平坦性を高めるために、ワイヤーの張力を増加し、線速を増加させることが好ましい。そのためには、高剛性のワイヤーソー装置が好ましい。   A method for cutting the semiconductor film donor substrate 13D is not particularly limited, and examples thereof include a wire saw, a blade saw, laser processing, electric discharge processing, and a water jet. When the group III nitride film donor substrate 13D is cut with a wire saw, it is preferable to use a fixed abrasive wire in order to cut the group III nitride film donor substrate 13D with a large diameter flatly. In order to reduce the margin, it is preferable to use a fine wire. In order to reduce the cutting allowance, the loose abrasive method is preferred. Further, when the group III nitride film donor substrate 13D is cut with a wire saw, the wire tension is increased in order to reduce the bending of the wire due to the cutting resistance and increase the accuracy and flatness of the thickness. It is preferable to increase the speed. For this purpose, a highly rigid wire saw device is preferable.

また、切断抵抗を低減して厚さの精度および平坦性を高めるために、ワイヤーを揺動させ、それに同期して半導体膜ドナー基板13Dを振動させることが好ましい。具体的には、半導体膜ドナー基板13Dの切断の進行方向に対して垂直またはそれに近い角度にワイヤーソーが位置しているときは半導体膜ドナー基板13Dが切断の進行方向に動き、半導体膜ドナー基板13Dの切断の進行方向に対して垂直から遠い角度にワイヤーソーが位置しているときは半導体膜ドナー基板13Dが切断の進行方向と反対方向に動くことにより、切断抵抗を低減することができる。   In order to reduce the cutting resistance and increase the accuracy and flatness of the thickness, it is preferable to vibrate the wire and vibrate the semiconductor film donor substrate 13D in synchronization therewith. Specifically, when the wire saw is positioned at an angle perpendicular to or close to the cutting progress direction of the semiconductor film donor substrate 13D, the semiconductor film donor substrate 13D moves in the cutting progress direction, and the semiconductor film donor substrate When the wire saw is positioned at an angle far from perpendicular to the cutting progress direction of 13D, the semiconductor film donor substrate 13D moves in the direction opposite to the cutting progress direction, thereby reducing the cutting resistance.

なお、半導体膜ドナー基板13Dが、GaN膜ドナー基板などのIII族窒化物膜ドナー基板の場合は、サファイア基板およびSiC基板などに比べて脆くて割れ易いため、サファイア基板およびSiC基板と同様の切断方法では良好に切断することができない。III族窒化物膜ドナー基板の切断においてはその切断抵抗をさらに低減することが必要である。切断抵抗を低減して厚さの精度および平坦性を高めるためには、スライス用加工液の粘度η(単位:Pa・s)、加工液の流量Q(単位:m3/s)、ワイヤー線速度V(単位:m/s)、最大切断長さL(単位:m)、切断速度P(単位:m/s)、および同時切断数nを用いて、R=(η×Q×V)/(L×P×n)で表される抵抗係数R(単位:N)が、適切な範囲にあること、具体的には4000以上5000以下であることが好ましい。 When the semiconductor film donor substrate 13D is a group III nitride film donor substrate such as a GaN film donor substrate, it is more brittle and easier to break than a sapphire substrate and an SiC substrate. The method cannot be cut well. In cutting the group III nitride film donor substrate, it is necessary to further reduce the cutting resistance. In order to reduce cutting resistance and increase thickness accuracy and flatness, viscosity η (unit: Pa · s) of machining fluid for slicing, flow rate Q (unit: m 3 / s) of machining fluid, wire wire Using speed V (unit: m / s), maximum cutting length L (unit: m), cutting speed P (unit: m / s), and simultaneous cutting number n, R = (η × Q × V) It is preferable that the resistance coefficient R (unit: N) represented by / (L × P × n) is in an appropriate range, specifically 4000 or more and 5000 or less.

切断により得られた複合基板1は、その半導体膜13および支持基板11の主面を研磨することにより、所望の厚さおよびその均一性を得ることができる。具体的には、研磨時の研磨装置への複合基板1の貼付には、吸着固定、バックパッドによる固定を行うことができる。また、保持プレートへ複合基板1を貼り付けた後に研磨装置に貼り付けることもできる。真空チャック、エアバッグ加圧、重りなどの機械的加圧により、傾きを抑制し、反りを矯正して貼り付けることができる。複合基板1を吸着固定することもできる。複合基板1を研磨装置に均一に貼り付けることで、研磨後の厚さ分布を低減することができる。   The composite substrate 1 obtained by cutting can obtain a desired thickness and uniformity thereof by polishing the main surface of the semiconductor film 13 and the support substrate 11. Specifically, the composite substrate 1 can be affixed to the polishing apparatus during polishing by suction fixation or back pad fixation. Alternatively, the composite substrate 1 can be attached to the holding plate and then attached to the polishing apparatus. By mechanical pressurization such as vacuum chuck, air bag pressurization, weight, etc., the tilt can be suppressed and the warp can be corrected and pasted. The composite substrate 1 can also be adsorbed and fixed. By uniformly bonding the composite substrate 1 to the polishing apparatus, the thickness distribution after polishing can be reduced.

上記のように、複合基板を準備する工程においては、複合基板1の半導体膜13の厚さ分布を低減するとともに半導体膜13の切断によるダメージ層を除去して結晶品質を高く維持し、主面を平滑化する観点から、切断により得られた複合基板1の半導体膜13の主面を研磨することが好ましい。   As described above, in the step of preparing the composite substrate, the thickness distribution of the semiconductor film 13 of the composite substrate 1 is reduced, the damaged layer due to the cutting of the semiconductor film 13 is removed, and the crystal quality is maintained high. From the viewpoint of smoothing, it is preferable to polish the main surface of the semiconductor film 13 of the composite substrate 1 obtained by cutting.

このため、複合基板を準備する工程においては、接合基板1Lの半導体膜ドナー基板13Dを切断する面である半導体膜ドナー基板13Dの貼り合わせ主面から内部に所定の距離に位置する面における所定の距離とは、製造の目的とする複合基板1の半導体膜13の厚さに研磨代(けんましろ)の厚さを加えた距離とすることが好ましい。ここで、研磨代は、特に制限はないが、厚さ分布およびオフ角分布を低減しかつダメージ層を除去する観点から、10μm以上が好ましく、20μm以上がより好ましく、30μm以上がさらに好ましい。また、研磨代は、半導体膜ドナー基板13Dの材料ロスを低減する観点から、100μm以下が好ましく、80μm以下がより好ましく、60μm以下がさらに好ましい。   For this reason, in the step of preparing the composite substrate, a predetermined value on a surface located at a predetermined distance from the main bonding surface of the semiconductor film donor substrate 13D, which is a surface for cutting the semiconductor film donor substrate 13D of the bonding substrate 1L. The distance is preferably a distance obtained by adding the thickness of the polishing margin to the thickness of the semiconductor film 13 of the composite substrate 1 to be manufactured. Here, the polishing allowance is not particularly limited, but is preferably 10 μm or more, more preferably 20 μm or more, and even more preferably 30 μm or more from the viewpoint of reducing the thickness distribution and off-angle distribution and removing the damaged layer. The polishing allowance is preferably 100 μm or less, more preferably 80 μm or less, and further preferably 60 μm or less from the viewpoint of reducing material loss of the semiconductor film donor substrate 13D.

また、図3(D)および(B)を参照して、残りの半導体膜ドナー基板13Drは、その主面を研磨することにより、繰り返し用いることができる。   In addition, referring to FIGS. 3D and 3B, the remaining semiconductor film donor substrate 13Dr can be repeatedly used by polishing its main surface.

こうして得られる複合基板1において、支持基板11、半導体膜13および接合膜12の材料などについては、上述の通りであるため、ここでは繰り返さない。   In the composite substrate 1 obtained in this way, the materials of the support substrate 11, the semiconductor film 13, and the bonding film 12 are as described above, and thus are not repeated here.

(半導体層付複合基板の形成工程)
図4(B)を参照して、半導体層付複合基板2を得る工程は、複合基板1の半導体膜13上に、少なくとも1層の半導体層20を成長させることにより行なわれる。少なくとも1層の半導体層20を成長させる方法は、特に制限はなく、半導体層20がIII−V族化合物半導体層のときはHVPE(ハイドライド気相成長)法、MOCVD(有機金属化学気相堆積)法、MBE(分子線成長)法、昇華法、フラックス法、高窒素圧溶液法、PLE(位相制御成長)法などにより好適に行なうことができ、半導体層20がIV族元素半導体層のときはCVD(化学気相堆積)法、MBE法、溶液成長法などにより好適に行なうことができ、半導体層20がIV族化合物半導体層のときはCVD法、MBE法、昇華法、LPE(液相成長)法などにより好適に行なうことができる。
(Process for forming a composite substrate with a semiconductor layer)
Referring to FIG. 4B, the step of obtaining composite substrate 2 with a semiconductor layer is performed by growing at least one semiconductor layer 20 on semiconductor film 13 of composite substrate 1. The method for growing at least one semiconductor layer 20 is not particularly limited. When the semiconductor layer 20 is a III-V group compound semiconductor layer, the HVPE (hydride vapor phase epitaxy) method, MOCVD (metal organic chemical vapor deposition) is used. And MBE (molecular beam growth) method, sublimation method, flux method, high nitrogen pressure solution method, PLE (phase control growth) method, etc., and when the semiconductor layer 20 is a group IV element semiconductor layer It can be suitably performed by CVD (chemical vapor deposition), MBE, solution growth, etc. When the semiconductor layer 20 is a group IV compound semiconductor layer, CVD, MBE, sublimation, LPE (liquid phase growth) ) Method or the like.

複合基板1の半導体膜13上に成長させる少なくとも1層の半導体層20は、品質のよい半導体層20を成長させる観点から、半導体層20は、半導体膜13に比べて、化学組成が近似することが好ましく、同一であることがより好ましい。ここで、化学組成が近似するとは、同一ではないが、いずれもIII−V族化合物、IV族元素、またはIV族化合物であることをいう。化学組成が同一とは、構成元素が同一であることをいう。   At least one semiconductor layer 20 grown on the semiconductor film 13 of the composite substrate 1 is similar in chemical composition to the semiconductor layer 20 compared to the semiconductor film 13 from the viewpoint of growing the semiconductor layer 20 with good quality. Are preferable, and the same is more preferable. Here, that the chemical compositions are approximate is not the same, but all are III-V group compounds, IV group elements, or IV group compounds. The same chemical composition means that the constituent elements are the same.

また、成長させる半導体層20の結晶性を向上させる観点から、複合基板1の半導体膜13の主面13m上に少なくとも半導体層20を成長させる工程は、半導体膜13の主面13m上に半導体バッファ層21を成長させるサブ工程と、半導体バッファ層21の主面21m上に半導体結晶層23を成長させるサブ工程と、を含むことが好ましい。ここで、半導体バッファ層21とは、半導体結晶層23に比べて低い温度で成長される結晶性が低いまたは非結晶(アモルファス)の層をいう。   From the viewpoint of improving the crystallinity of the semiconductor layer 20 to be grown, the step of growing at least the semiconductor layer 20 on the main surface 13m of the semiconductor film 13 of the composite substrate 1 includes a semiconductor buffer on the main surface 13m of the semiconductor film 13. It is preferable to include a sub-process for growing the layer 21 and a sub-process for growing the semiconductor crystal layer 23 on the main surface 21 m of the semiconductor buffer layer 21. Here, the semiconductor buffer layer 21 refers to a layer of low crystallinity or non-crystalline (amorphous) grown at a lower temperature than the semiconductor crystal layer 23.

このようにして、複合基板1の半導体膜13上に少なくとも1層の半導体層20が配置された半導体層付複合基板2が得られる。   In this way, the composite substrate with semiconductor layer 2 in which at least one semiconductor layer 20 is disposed on the semiconductor film 13 of the composite substrate 1 is obtained.

(半導体ウエハを得る工程)
図4(C)を参照して、半導体層20を含む半導体ウエハ3を得る工程は、半導体層付複合基板2から支持基板11を除去することにより行なわれる。支持基板11を除去する方法は、特に制限はないが、支持基板11を効率的に除去する観点から、支持基板11をエッチングにより溶解させて除去する方法、支持基板11を研削または研磨により除去する方法が好ましい。支持基板11に含まれる非結晶相のシリカ相が0.05質量%以上の場合は、支持基板11をフッ化水素酸によってエッチング除去する方法が好ましい。支持基板11に含まれる非結晶相のシリカ相が0.05質量未満または非結晶相のシリカ相が含まれない場合は、支持基板11を研削または研磨により除去する方法が好ましい。
(Process for obtaining a semiconductor wafer)
Referring to FIG. 4C, the step of obtaining semiconductor wafer 3 including semiconductor layer 20 is performed by removing support substrate 11 from composite substrate 2 with a semiconductor layer. The method for removing the support substrate 11 is not particularly limited, but from the viewpoint of efficiently removing the support substrate 11, a method for removing the support substrate 11 by etching, or removing the support substrate 11 by grinding or polishing. The method is preferred. When the silica phase of the amorphous phase contained in the support substrate 11 is 0.05 mass% or more, a method of removing the support substrate 11 by etching with hydrofluoric acid is preferable. When the amorphous silica phase contained in the support substrate 11 is less than 0.05 mass or no amorphous silica phase is contained, a method of removing the support substrate 11 by grinding or polishing is preferable.

(実施例1)
1.複合基板の半導体膜を形成するGaN結晶の熱膨張係数の測定
複合基板の半導体膜を形成するGaN結晶の熱膨張係数を測定するために、基板HVPE法により成長させた、転位密度が1×106cm-2、シリコン(Si)濃度が1×1018cm-2、酸素(O)濃度が1×1017cm-2、炭素(C)濃度が1×1016cm-2のGaN単結晶から、サイズが2×2×20mm(長手方向がa軸、長手方向に平行な面がc面およびm面のいずれかで構成され、面方位の精度は±0.1°以内)の評価用サンプルを切り出した。
Example 1
1. Measurement of thermal expansion coefficient of GaN crystal forming semiconductor film of composite substrate In order to measure the thermal expansion coefficient of GaN crystal forming semiconductor film of composite substrate, the dislocation density grown by the substrate HVPE method is 1 × 10 GaN single crystal with 6 cm -2 , silicon (Si) concentration of 1 x 10 18 cm -2 , oxygen (O) concentration of 1 x 10 17 cm -2 and carbon (C) concentration of 1 x 10 16 cm -2 To 2 × 2 × 20 mm in size (the longitudinal direction is a-axis, the plane parallel to the longitudinal direction is either c-plane or m-plane, and the accuracy of the plane orientation is within ± 0.1 °) A sample was cut out.

上記の評価用サンプルについて、室温(25℃)から800℃ まで昇温したときの平均熱膨張係数をTMA(熱機械分析)により測定した。具体的には、(株)リガク製TMA8310を用いて示差膨張方式により窒素ガス流通雰囲気下で評価サンプルの熱膨張係数を測定した。かかる測定により得られた複合基板の半導体膜を形成するGaN結晶のa軸方向の25℃から800℃までにおける平均熱膨張係数αF(GaN)は、5.84×10-6/℃であった。 About said sample for evaluation, the average thermal expansion coefficient when it heated up from room temperature (25 degreeC) to 800 degreeC was measured by TMA (thermomechanical analysis). Specifically, the thermal expansion coefficient of the evaluation sample was measured in a nitrogen gas circulation atmosphere by a differential expansion method using TMA8310 manufactured by Rigaku Corporation. The average thermal expansion coefficient α F (GaN) in the a-axis direction from 25 ° C. to 800 ° C. of the GaN crystal forming the semiconductor film of the composite substrate obtained by such measurement was 5.84 × 10 −6 / ° C. It was.

2.複合基板の準備工程
(1)支持基板を準備するサブ工程
図2(A)を参照して、支持基板11の材料として、アルミナ(Al23)粉末とシリカ(SiO2)粉末とを、以下の質量比で混合した13種類の原料1A〜1Mを、大気雰囲気下、1700℃で20時間焼結させることにより、13種類の焼結体1A〜1Mを準備した。ここで、Al23粉末とSiO2粉末との質量比Al23:SiO2は、原料1Aが65:35、原料1Bが70:30、原料1Cが73:27、原料1Dが77:23、原料1Eが79:21、原料1Fが81:19、原料1Gが83:17、原料1Hが85:15、原料1Iが87:13、原料1Jが89:11、原料1Kが92:8、原料1Lが95:5、原料1Mが98:2であった。
2. Preparation Step of Composite Substrate (1) Sub-Step of Preparing Support Substrate With reference to FIG. 2 (A), alumina (Al 2 O 3 ) powder and silica (SiO 2 ) powder are used as materials for the support substrate 11. Thirteen types of sintered bodies 1A to 1M were prepared by sintering 13 types of raw materials 1A to 1M mixed at the following mass ratios in an air atmosphere at 1700 ° C. for 20 hours. Here, the mass ratio Al 2 O 3 : SiO 2 between the Al 2 O 3 powder and the SiO 2 powder is 65:35 for the raw material 1A, 70:30 for the raw material 1B, 73:27 for the raw material 1C, and 77 for the raw material 1D. : 23, Raw material 1E is 79:21, Raw material 1F is 81:19, Raw material 1G is 83:17, Raw material 1H is 85:15, Raw material 1I is 87:13, Raw material 1J is 89:11, Raw material 1K is 92: 8. Raw material 1L was 95: 5, and raw material 1M was 98: 2.

準備した13種類の焼結体1A〜1Mには、X線回折により確認したところ、いずれについても結晶相としてムライト(Al6Si213)相およびアルミナ(Al23)相が存在していた。非結晶相であるシリカ(SiO2)相は、X線回折では検出されないが、焼結体を20mm×10mm×厚さ0.15mmの大きさに加工し、45質量%のフッ化水素酸水溶液200mlに20時間溶解させて得られた溶液を、ICP−OES(誘導結合プラズマ−発光)分析により評価し、検出されたSi量から焼結体中のシリカ含有量を算出した。この結果と、X線回折の結果を併せて支持基板11の組成比とした。 The prepared 13 types of sintered bodies 1A to 1M were confirmed by X-ray diffraction. As a result, a mullite (Al 6 Si 2 O 13 ) phase and an alumina (Al 2 O 3 ) phase existed as crystal phases. It was. The silica (SiO 2 ) phase, which is an amorphous phase, is not detected by X-ray diffraction, but the sintered body is processed into a size of 20 mm × 10 mm × thickness 0.15 mm, and a 45 mass% hydrofluoric acid aqueous solution The solution obtained by dissolving in 200 ml for 20 hours was evaluated by ICP-OES (inductively coupled plasma-luminescence) analysis, and the silica content in the sintered body was calculated from the detected amount of Si. This result and the result of X-ray diffraction were combined to determine the composition ratio of the support substrate 11.

また、上記13種類の焼結体1A〜1Mのそれぞれからサイズが2×2×20mm(長手方向は焼結体から切り出される支持基板の主面に実質的に平行な方向)の測定用サンプルを切り出した。ここで、焼結体1A〜1Mは方向特異性がないため、切り出し方向は任意とした。それらの測定用サンプルについて、上記と同様にして、室温(25℃)から800℃まで昇温した時の平均熱膨張係数αSを測定した。 Further, a sample for measurement having a size of 2 × 2 × 20 mm (longitudinal direction is a direction substantially parallel to the main surface of the support substrate cut out from the sintered body) from each of the 13 types of sintered bodies 1A to 1M. Cut out. Here, since the sintered bodies 1A to 1M have no direction specificity, the cutting direction is arbitrary. For these measurement samples, the average thermal expansion coefficient α S when the temperature was raised from room temperature (25 ° C.) to 800 ° C. was measured in the same manner as described above.

焼結体1Aは、結晶相であるムライト相およびアルミナ相と非結晶相シリカ相との質量比Al6Si213:Al23:SiO2が89:1:10であり、25℃から800℃までにおける平均熱膨張係数αS(以下、単に平均熱膨張係数αSという)が4.0×10-6/℃であり、GaN結晶のa軸方向の平均熱膨張係数αF(GaN)に対する焼結体の熱膨張係数αSの比(以下、αS/αF(GaN)比という)が0.683であった。焼結体1Bは、質量比Al6Si213:Al23:SiO2が96:1:3であり、平均熱膨張係数αSが4.5×10-6/℃であり、αS/αF(GaN)比が0.768であった。焼結体1Cは、質量比Al6Si213:Al23:SiO2が95:4:1であり、平均熱膨張係数αSが4.8×10-6/℃であり、αS/αF(GaN)比が0.819であった。焼結体1Dは、質量比Al6Si213:Al23:SiO2が79:19:1であり、平均熱膨張係数αSが5.1×10-6/℃であり、αS/αF(GaN)比が0.870であった。焼結体1Eは、質量比Al6Si213:Al23:SiO2が73.9:26:0.1であり、平均熱膨張係数αSが5.4×10-6/℃であり、αS/αF(GaN)比が0.922であった。焼結体1Fは、質量比Al6Si213:Al23:SiO2が67.02:32:0.08であり、平均熱膨張係数αSが5.6×10-6/℃であり、αS/αF(GaN)比が0.956であった。焼結体1Gは、質量比Al6Si213:Al23:SiO2が60.94:39:0.06であり、平均熱膨張係数αSが5.8×10-6/℃であり、αS/αF(GaN)比が0.990であった。焼結体1Hは、質量比Al6Si213:Al23:SiO2が52.94:47:0.06であり、平均熱膨張係数αSが6.0×10-6/℃であり、αS/αF(GaN)比が1.024であった。焼結体1Iは、質量比Al6Si213:Al23:SiO2が45:54.95:0.05であり、平均熱膨張係数αSが6.2×10-6/℃であり、αS/αF(GaN)比が1.058であった。焼結体1Jは、質量比Al6Si213:Al23:SiO2が38:61.95:0.05であり、平均熱膨張係数αSが6.5×10-6/℃であり、αS/αF(GaN)比が1.109であった。焼結体1Kは、質量比Al6Si213:Al23:SiO2が28:71.96:0.04であり、平均熱膨張係数αSが6.9×10-6/℃であり、αS/αF(GaN)比が1.177であった。焼結体1Lは、質量比Al6Si213:Al23:SiO2が17:82.97:0.03であり、平均熱膨張係数αSが7.3×10-6/℃であり、αS/αF(GaN)比が1.246であった。焼結体1Mは、質量比Al6Si213:Al23:SiO2が7:92.99:0.01であり、平均熱膨張係数αSが7.9×10-6/℃であり、αS/αF(GaN)比が1.348であった。 The sintered body 1A has a mass ratio Al 6 Si 2 O 13 : Al 2 O 3 : SiO 2 of 89: 1: 10 between the mullite phase, which is a crystalline phase, and the alumina phase and the amorphous silica phase, and 25 ° C. The average thermal expansion coefficient α S (hereinafter, simply referred to as the average thermal expansion coefficient αS) from 4.0 to 800 ° C. is 4.0 × 10 −6 / ° C., and the average thermal expansion coefficient α F (GaN The ratio of the thermal expansion coefficient α S of the sintered body to ) (hereinafter referred to as α S / α F (GaN) ratio) was 0.683. The sintered body 1B has a mass ratio of Al 6 Si 2 O 13 : Al 2 O 3 : SiO 2 of 96: 1: 3, an average thermal expansion coefficient α S of 4.5 × 10 −6 / ° C., The α S / α F (GaN) ratio was 0.768. The sintered body 1C has a mass ratio of Al 6 Si 2 O 13 : Al 2 O 3 : SiO 2 of 95: 4: 1 and an average thermal expansion coefficient α S of 4.8 × 10 −6 / ° C. The α S / α F (GaN) ratio was 0.819. The sintered body 1D has a mass ratio of Al 6 Si 2 O 13 : Al 2 O 3 : SiO 2 of 79: 19: 1, an average thermal expansion coefficient α S of 5.1 × 10 −6 / ° C., The α S / α F (GaN) ratio was 0.870. The sintered body 1E has a mass ratio of Al 6 Si 2 O 13 : Al 2 O 3 : SiO 2 of 73.9: 26: 0.1 and an average thermal expansion coefficient α S of 5.4 × 10 −6 / ° C and the α S / α F (GaN) ratio was 0.922. The sintered body 1F has a mass ratio of Al 6 Si 2 O 13 : Al 2 O 3 : SiO 2 of 67.02: 32: 0.08 and an average thermal expansion coefficient α S of 5.6 × 10 −6 / ° C and the α S / α F (GaN) ratio was 0.956. The sintered body 1G has a mass ratio of Al 6 Si 2 O 13 : Al 2 O 3 : SiO 2 of 60.94: 39: 0.06 and an average thermal expansion coefficient α S of 5.8 × 10 −6 / ° C and the α S / α F (GaN) ratio was 0.990. The sintered body 1H has a mass ratio of Al 6 Si 2 O 13 : Al 2 O 3 : SiO 2 of 52.94: 47: 0.06 and an average thermal expansion coefficient α S of 6.0 × 10 −6 / And the α S / α F (GaN) ratio was 1.024. The sintered body 1I has a mass ratio of Al 6 Si 2 O 13 : Al 2 O 3 : SiO 2 of 45: 54.95: 0.05 and an average thermal expansion coefficient α S of 6.2 × 10 −6 / And the α S / α F (GaN) ratio was 1.058. The sintered body 1J has a mass ratio of Al 6 Si 2 O 13 : Al 2 O 3 : SiO 2 of 38: 61.95: 0.05, and an average thermal expansion coefficient α S of 6.5 × 10 −6 / And the α S / α F (GaN) ratio was 1.109. The sintered body 1K has a mass ratio of Al 6 Si 2 O 13 : Al 2 O 3 : SiO 2 of 28: 71.96: 0.04 and an average thermal expansion coefficient α S of 6.9 × 10 −6 / And the α S / α F (GaN) ratio was 1.177. The sintered body 1L has a mass ratio of Al 6 Si 2 O 13 : Al 2 O 3 : SiO 2 of 17: 82.97: 0.03 and an average thermal expansion coefficient α S of 7.3 × 10 −6 / And the α S / α F (GaN) ratio was 1.246. The sintered body 1M has a mass ratio of Al 6 Si 2 O 13 : Al 2 O 3 : SiO 2 of 7: 92.99: 0.01 and an average thermal expansion coefficient α S of 7.9 × 10 −6 / The α S / α F (GaN) ratio was 1.348.

上記13種類の焼結体1A〜1Mから、直径4インチ(101.6mm)で厚さ0.40mmの支持基板をそれぞれ切り出して、それぞれの支持基板の両主面を鏡面に研磨して、13種類の支持基板1A〜1Mを作製した。研磨後の支持基板1A〜1Mの主面の平坦化度は、AFM(電子間力顕微鏡)を用いて20μm×20μmの範囲で測定したJIS B0601に規定する算術平均粗さRaの値により評価した。主面の平坦化度の評価は、算術平均粗さRaが10nm以下のものを高、算術平均粗さRaが10nmより大きく20nm以下のものを中、算術平均粗さRaが20nmより大きいものを低、とした。主面の平坦化度は、支持基板1Aが低、支持基板1B〜1Dが中、支持基板1E〜1Mが高であった。   A support substrate having a diameter of 4 inches (101.6 mm) and a thickness of 0.40 mm was cut out from each of the 13 types of sintered bodies 1A to 1M, and both main surfaces of each support substrate were polished into mirror surfaces. Various types of support substrates 1A to 1M were prepared. The flatness of the main surfaces of the support substrates 1A to 1M after polishing was evaluated based on the value of the arithmetic average roughness Ra defined in JIS B0601 measured in a range of 20 μm × 20 μm using an AFM (electron force microscope). . The evaluation of the flatness of the main surface is such that the arithmetic average roughness Ra is 10 nm or less, the arithmetic average roughness Ra is greater than 10 nm and less than 20 nm, and the arithmetic average roughness Ra is greater than 20 nm. Low. The flatness of the main surface was low for the support substrate 1A, medium for the support substrates 1B to 1D, and high for the support substrates 1E to 1M.

(2)下地基板上に半導体膜を成膜するサブ工程
図2(B)を参照して、下地基板30として、鏡面に研磨された(111)面の主面30nを有する直径5インチ(127mm)で厚さ0.5mmのSi基板を準備した。
(2) Sub-Process for Forming Semiconductor Film on Base Substrate With reference to FIG. 2B, the base substrate 30 has a diameter of 5 inches (127 mm) having a (111) principal surface 30n polished to a mirror surface. ) To prepare a Si substrate having a thickness of 0.5 mm.

上記の下地基板30の主面30n上に、半導体膜13 として厚さ0.4μm のGaN膜をMOCVD法により成膜した。成膜条件は、原料ガスとしてTMGガスおよびNH3ガスを使用し、キャリアガスとしてH2ガスを使用し、成膜温度1000℃、成膜圧力は1気圧とした。なお、こうして得られた半導体膜13の主面13mは、(0001)面からのオフ角が±1°以内の面方位を有していた。 A GaN film having a thickness of 0.4 μm was formed as the semiconductor film 13 on the main surface 30n of the base substrate 30 by MOCVD. The film formation conditions were as follows: TMG gas and NH 3 gas were used as the source gas, H 2 gas was used as the carrier gas, the film formation temperature was 1000 ° C., and the film formation pressure was 1 atm. The main surface 13m of the semiconductor film 13 obtained in this way had a plane orientation with an off angle of ± 1 ° from the (0001) plane.

(3)支持基板と半導体膜とを貼り合わせるサブ工程
図2(C)中の(C1)を参照して、図2(A)の支持基板11である支持基板1A〜1Mのそれぞれの主面11m上に厚さ2μmのSiO2膜をCVD(化学気相堆積)法により成膜した。次いで、かかる支持基板1A〜1Mのそれぞれの主面11m上の厚さ2μmのSiO2膜を、CeO2スラリーを用いて研磨することにより、厚さ0.2μm のSiO2膜だけ残存させて、接合膜12aとした。これにより、支持基板1A〜1Mのそれぞれの主面11mの空隙が埋められ、接合膜12aである平坦な主面12amを有する厚さ0.2μmのSiO2膜が得られた。
(3) Sub-process for bonding support substrate and semiconductor film Referring to (C1) in FIG. 2 (C), main surfaces of support substrates 1A to 1M which are support substrate 11 in FIG. 2 (A) A SiO 2 film having a thickness of 2 μm was formed on 11 m by a CVD (chemical vapor deposition) method. Next, the SiO 2 film having a thickness of 2 μm on each main surface 11 m of each of the support substrates 1A to 1M is polished using a CeO 2 slurry, so that only the SiO 2 film having a thickness of 0.2 μm is left. The bonding film 12a was obtained. Thus, the gap is filled in each of the main surfaces 11m of the supporting substrate 1A~1M, SiO 2 film having a thickness of 0.2μm having a flat main surface 12am is bonding film 12a is obtained.

また、図2(C)中の(C2)を参照して、図2(B)の下地基板30であるSi基板上に成膜された半導体膜13であるGaN膜の主面13n上に厚さ2μmのSiO2膜をCVD法により成膜した。次いで、この厚さ2μmのSiO2膜を、CeO2スラリーを用いて研磨することにより、厚さ0.2μmのSiO2膜だけ残存させて、接合膜12bとした。 Further, referring to (C2) in FIG. 2 (C), a thickness is formed on the main surface 13n of the GaN film which is the semiconductor film 13 formed on the Si substrate which is the base substrate 30 in FIG. 2 (B). A 2 μm thick SiO 2 film was formed by CVD. Next, the SiO 2 film having a thickness of 2 μm was polished using a CeO 2 slurry, so that only the SiO 2 film having a thickness of 0.2 μm was left to form the bonding film 12b.

次いで、図2(C)中の(C3)を参照して、支持基板11である支持基板1A〜1Mのそれぞれに形成された接合膜12aの主面12amおよび下地基板30であるSi基板上に成膜された半導体膜13上に形成された接合膜12bの主面12bnをアルゴンプラズマにより清浄化および活性化させた後、接合膜12aの主面12amと接合膜12bの主面12bnとを貼り合わせて、窒素雰囲気下300℃で2時間熱処理した。   2C, the main surface 12am of the bonding film 12a formed on each of the support substrates 1A to 1M as the support substrate 11 and the Si substrate as the base substrate 30 are referred to. The main surface 12bn of the bonding film 12b formed on the formed semiconductor film 13 is cleaned and activated by argon plasma, and then the main surface 12am of the bonding film 12a and the main surface 12bn of the bonding film 12b are pasted. In addition, heat treatment was performed at 300 ° C. for 2 hours in a nitrogen atmosphere.

(4)下地基板を除去するサブ工程
図2(D)を参照して、支持基板11である支持基板1A〜1Mのそれぞれの裏側(半導体膜13が貼り合わされていない側)の主面および側面をワックス40で覆って保護した後、10質量%のフッ化水素酸および5質量%の硝酸を含む混酸水溶液を用いて、エッチングにより下地基板30であるSi基板を除去した。こうして、図4(A)に示すような支持基板11である支持基板1A〜1Mのそれぞれの主面11m側に半導体膜13であるGaN膜が配置された複合基板1である複合基板1A〜1Mが得られた。
(4) Sub-step of removing base substrate Referring to FIG. 2D, the main surface and side surfaces of the back side (side where semiconductor film 13 is not bonded) of support substrates 1A to 1M which are support substrate 11 Then, the Si substrate as the base substrate 30 was removed by etching using a mixed acid aqueous solution containing 10% by mass of hydrofluoric acid and 5% by mass of nitric acid. Thus, the composite substrates 1A to 1M, which are the composite substrates 1 in which the GaN film that is the semiconductor film 13 is arranged on the main surface 11m side of the support substrates 1A to 1M that are the support substrates 11 as shown in FIG. was gotten.

3.半導体層の形成工程
図4(B)を参照して、複合基板1である複合基板1A〜1Mの半導体膜13であるGaN膜の主面13m(かかる主面は(0001)面である。)上および直径4インチ(101.6mm)で厚さ1mmのサファイア基板の主面(かかる主面は(0001)面である。)上に、それぞれMOCVD法により半導体層20としてGaN層を成長させた。かかる半導体層20の成長においては、原料ガスとしてTMG(トリメチルガリウム)ガスおよびNH3ガスを使用し、キャリアガスとしてH2ガスを使用して、まず、500℃で、半導体バッファ層21として厚さ0.1μmのGaNバッファ層を成長させ、次いで、1050℃で、半導体結晶層23として厚さ5μmのGaN結晶層を成長させた。ここで、GaN結晶層の成長速度は1μm/hrであった。その後、複合基板1A〜1Mのそれぞれに半導体層30であるGaN層が形成された半導体層付複合基板1A〜1Mを10℃/minの速度で室温(25℃)まで冷却した。
3. Step of Forming Semiconductor Layer Referring to FIG. 4B, the main surface 13m of the GaN film that is the semiconductor film 13 of the composite substrate 1A to 1M that is the composite substrate 1 (the main surface is the (0001) plane). A GaN layer was grown as a semiconductor layer 20 by MOCVD on the top and the main surface of a sapphire substrate having a diameter of 4 inches (101.6 mm) and a thickness of 1 mm (the main surface is the (0001) plane). . In the growth of the semiconductor layer 20, TMG (trimethylgallium) gas and NH 3 gas are used as source gases, and H 2 gas is used as a carrier gas. A GaN buffer layer having a thickness of 0.1 μm was grown, and then a GaN crystal layer having a thickness of 5 μm was grown as the semiconductor crystal layer 23 at 1050 ° C. Here, the growth rate of the GaN crystal layer was 1 μm / hr. Thereafter, the composite substrates 1A to 1M with a semiconductor layer in which the GaN layer as the semiconductor layer 30 was formed on each of the composite substrates 1A to 1M were cooled to room temperature (25 ° C.) at a rate of 10 ° C./min.

室温まで冷却後に成膜装置から取り出された半導体層付複合基板1A〜1Mにの反り形状および反り量を、半導体層20であるGaN層側の主面をCorning Tropel社のFM200EWaferを用いて観察される光干渉縞により測定した。   The warpage shape and amount of warpage of the composite substrate with semiconductor layers 1A to 1M taken out from the film forming apparatus after cooling to room temperature were observed using the Corning Tropel FM200EWafer on the main surface of the semiconductor layer 20 on the GaN layer side. Measured by optical interference fringes.

半導体層付複合基板1Aは、半導体層側が凹状に反り、反り量が700μmであった。半導体層付複合基板1Bは、半導体層側が凹状に反り、反り量が650μmであった。半導体層付複合基板1Cは、半導体層側が凹状に反り、反り量が630μmであった。半導体層付複合基板1Dは、半導体層側が凹状に反り、反り量が450μmであった。半導体層付複合基板1Eは、半導体層側が凹状に反り、反り量が350μmであった。半導体層付複合基板1Fは、半導体層側が凹状に反り、反り量が230μmであった。半導体層付複合基板1Gは、半導体層側が凹状に反り、反り量が150μmであった。半導体層付複合基板1Hは、半導体層側が凹状に反り、反り量が10μmであった。半導体層付複合基板1Iは、半導体層側が凸状に反り、反り量が13μmであった。半導体層付複合基板1Jは、半導体層側が凸状に反り、反り量が100μmであった。半導体層付複合基板1Kは、半導体層側が凸状に反り、反り量が220μmであった。半導体層付複合基板1Lは、半導体層側が凸状に反り、反り量が750μmであった。半導体層付複合基板1Mは、半導体層側が凸状に反り、支持基板が割れたため、反り量の測定が困難であった。これらの結果を表1にまとめた。表1において、「−」は、その物性値が未測定であることを示す。   In the composite substrate with a semiconductor layer 1A, the semiconductor layer side warped in a concave shape, and the amount of warpage was 700 μm. In the composite substrate with a semiconductor layer 1B, the semiconductor layer side warped in a concave shape, and the amount of warpage was 650 μm. In the composite substrate with a semiconductor layer 1C, the semiconductor layer side warped in a concave shape, and the amount of warpage was 630 μm. The composite substrate 1D with a semiconductor layer warped in a concave shape on the semiconductor layer side, and the amount of warpage was 450 μm. In the composite substrate 1E with a semiconductor layer, the semiconductor layer side warped in a concave shape, and the amount of warpage was 350 μm. The composite substrate 1F with a semiconductor layer warped in a concave shape on the semiconductor layer side, and the amount of warpage was 230 μm. In the composite substrate with a semiconductor layer 1G, the semiconductor layer side warped in a concave shape, and the amount of warpage was 150 μm. The composite substrate with a semiconductor layer 1H warped in a concave shape on the semiconductor layer side, and the amount of warpage was 10 μm. In the composite substrate with a semiconductor layer 1I, the semiconductor layer side warped in a convex shape, and the amount of warpage was 13 μm. In the composite substrate with a semiconductor layer 1J, the semiconductor layer side warped convexly, and the amount of warpage was 100 μm. In the composite substrate with a semiconductor layer 1K, the semiconductor layer side warped in a convex shape, and the amount of warpage was 220 μm. In the composite substrate with a semiconductor layer 1L, the semiconductor layer side warped in a convex shape, and the amount of warpage was 750 μm. In the composite substrate 1M with a semiconductor layer, the semiconductor layer side warped in a convex shape and the support substrate was cracked, so that it was difficult to measure the amount of warpage. These results are summarized in Table 1. In Table 1, “-” indicates that the physical property value is not measured.

4.支持基板の除去工程
図4(C)を参照して、上記で得られた半導体層付複合基板1A〜1Mを、45質量%のフッ化水素酸水溶液に浸漬することにより、支持基板11である支持基板1A〜1Mおよび接合膜12であるSiO2膜を溶解させることにより除去して、半導体膜13であるGaN膜の主面13m上に成長された半導体層20である半導体ウエハ1A〜1Mが得られた。下地基板の除去時間は、表1に示すように、半導体層付複合基板1A〜1Lについて500時間未満であり、半導体層付複合基板1Mについては500時間以上であった。
4). Step of removing support substrate Referring to FIG. 4C, the composite substrate with semiconductor layer 1A to 1M obtained above is immersed in a 45% by mass hydrofluoric acid aqueous solution to form support substrate 11. was removed by dissolving the supporting substrate 1A~1M and the bonding film 12 a is SiO 2 film, a semiconductor wafer 1A~1M is a semiconductor layer 20 grown on the main surface 13m of the GaN film is a semiconductor film 13 Obtained. As shown in Table 1, the removal time of the base substrate was less than 500 hours for the composite substrates with semiconductor layers 1A to 1L, and 500 hours or more for the composite substrate with semiconductor layers 1M.

なお、半導体ウエハ1A〜1Mにおいても反りがCorning Tropel社のFM200EWaferを用いて観察される光干渉縞による測定により認められ、半導体ウエハ1A〜1Mの反りの大小関係には、半導体層付複合基板1A〜1Mにおける反りの大小関係が維持されていた。   It should be noted that the warpage of the semiconductor wafers 1A to 1M is also recognized by the measurement by optical interference fringes observed using the Corning Tropel FM200EWafer, and the magnitude relation of the warpage of the semiconductor wafers 1A to 1M is shown in FIG. The magnitude relation of the warp at ˜1M was maintained.

Figure 0006094243
Figure 0006094243

(実施例2)
1.複合基板の半導体膜を形成するGaN結晶の熱膨張係数の測定
複合基板の半導体膜を形成するGaN結晶の熱膨張係数を実施例1と同様にして測定したところ、複合基板の半導体膜を形成するGaN結晶のa軸方向の25℃から800℃までにおける平均熱膨張係数αF(GaN)は、5.84×10-6/℃であった。
(Example 2)
1. Measurement of thermal expansion coefficient of GaN crystal forming semiconductor film of composite substrate When the thermal expansion coefficient of GaN crystal forming semiconductor film of composite substrate was measured in the same manner as in Example 1, the semiconductor film of composite substrate was formed. The average coefficient of thermal expansion α F (GaN) from 25 ° C. to 800 ° C. in the a-axis direction of the GaN crystal was 5.84 × 10 −6 / ° C.

2.複合基板の準備工程
(1)支持基板を準備するサブ工程
図2(A)を参照して、支持基板11の材料として、ムライト(Al6Si213)粉末とアルミナ(Al23)粉末とシリカ(SiO2)粉末とを、以下の質量比で混合した10種類の原料2A〜2Jを、アルゴンガス雰囲気下一軸方向に50MPaの圧力をかけて1700℃で2時間焼結させることにより、10種類の焼結体2A〜2Jを準備した。ここで、Al6Si213粉末とAl23粉末とSiO2粉末との質量比Al6Si213:Al23:SiO2は、原料2Aが50:22:28、原料2Bが50:30:20、原料2Cが50:32:18、原料2Dが50:35:15、原料2Eが50:39:11、原料2Fが50:42:8、原料2Gが50:44:6、原料2Hが50:46:4、原料2Iが50:48:2、原料2Jが50:50:0であった。
2. Preparation Step of Composite Substrate (1) Sub-Step of Preparing Support Substrate Referring to FIG. 2 (A), as materials for the support substrate 11, mullite (Al 6 Si 2 O 13 ) powder and alumina (Al 2 O 3 ) By sintering 10 kinds of raw materials 2A to 2J obtained by mixing powder and silica (SiO 2 ) powder in the following mass ratio at 1700 ° C. for 2 hours under a pressure of 50 MPa in a uniaxial direction under an argon gas atmosphere. Ten types of sintered bodies 2A to 2J were prepared. Here, the mass ratio between the Al 6 Si 2 O 13 powder, the Al 2 O 3 powder, and the SiO 2 powder is Al 6 Si 2 O 13 : Al 2 O 3 : SiO 2 , and the raw material 2A is 50:22:28. 2B is 50:30:20, Raw material 2C is 50:32:18, Raw material 2D is 50:35:15, Raw material 2E is 50:39:11, Raw material 2F is 50: 42: 8, and Raw material 2G is 50:44. : 6, raw material 2H was 50: 46: 4, raw material 2I was 50: 48: 2, and raw material 2J was 50: 50: 0.

準備した10種類の焼結体2A〜2Jには、X線回折により確認したところ、いずれについても結晶相としてムライト(Al6Si213)相およびアルミナ(Al23)相が存在していた。非結晶相であるシリカ(SiO2)相は、X線回折では検出されないが、焼結体を20mm×10mm×厚さ0.15mmの大きさに加工し、45質量%のフッ化水素酸水溶液200mlに20時間溶解させて得られた溶液を、ICP−OES(誘導結合プラズマ−発光)分析により評価し、検出されたSi量から焼結体中のシリカ含有量を算出した。この結果と、X線回折の結果を併せて支持基板11の組成比とした。 The 10 types of sintered bodies 2A to 2J prepared were confirmed by X-ray diffraction. As a result, a mullite (Al 6 Si 2 O 13 ) phase and an alumina (Al 2 O 3 ) phase existed as crystal phases. It was. The silica (SiO 2 ) phase, which is an amorphous phase, is not detected by X-ray diffraction, but the sintered body is processed into a size of 20 mm × 10 mm × thickness 0.15 mm, and a 45 mass% hydrofluoric acid aqueous solution The solution obtained by dissolving in 200 ml for 20 hours was evaluated by ICP-OES (inductively coupled plasma-luminescence) analysis, and the silica content in the sintered body was calculated from the detected amount of Si. This result and the result of X-ray diffraction were combined to determine the composition ratio of the support substrate 11.

また、上記10種類の焼結体2A〜2Jのそれぞれからサイズが2×2×20mm(長手方向は焼結体から切り出される支持基板の主面に実質的に平行な方向)の測定用サンプルを切り出した。ここで、焼結体2A〜2Jは方向特異性がないため、切り出し方向は任意とした。それらの測定用サンプルについて、上記と同様にして、室温(25℃)から800℃まで昇温した時の平均熱膨張係数αSを測定した。 In addition, a measurement sample having a size of 2 × 2 × 20 mm (longitudinal direction is a direction substantially parallel to the main surface of the support substrate cut out from the sintered body) from each of the 10 types of sintered bodies 2A to 2J. Cut out. Here, since the sintered bodies 2A to 2J have no direction specificity, the cutting direction is arbitrary. For these measurement samples, the average thermal expansion coefficient α S when the temperature was raised from room temperature (25 ° C.) to 800 ° C. was measured in the same manner as described above.

焼結体2Aは、結晶相であるムライト相およびアルミナ相と非結晶相シリカ相との質量比Al6Si213:Al23:SiO2が79:1:19であり、25℃から800℃までにおける平均熱膨張係数αS(以下、単に平均熱膨張係数αSという)が3.5×10-6/℃であり、GaN結晶のa軸方向の平均熱膨張係数αF(GaN)に対する焼結体の熱膨張係数αSの比(以下、αS/αF(GaN)比という)が0.597であった。焼結体2Bは、質量比Al6Si213:Al23:SiO2が90:1:9であり、平均熱膨張係数αSが3.9×10-6/℃であり、αS/αF(GaN)比が0.666であった。焼結体2Cは、質量比Al6Si213:Al23:SiO2が93:1:6であり、平均熱膨張係数αSが4.3×10-6/℃であり、αS/αF(GaN)比が0.734であった。焼結体2Dは、質量比Al6Si213:Al23:SiO2が97:1:2であり、平均熱膨張係数αSが4.8×10-6/℃であり、αS/αF(GaN)比が0.819であった。焼結体2Eは、質量比Al6Si213:Al23:SiO2が88.5:11:0.5であり、平均熱膨張係数αSが5.0×10-6/℃であり、αS/αF(GaN)比が0.853であった。焼結体2Fは、質量比Al6Si213:Al23:SiO2が78.9:21:0.1であり、平均熱膨張係数αSが5.2×10-6/℃であり、αS/αF(GaN)比が0.887であった。焼結体2Gは、質量比Al6Si213:Al23:SiO2が71.92:28:0.08であり、平均熱膨張係数αSが5.6×10-6/℃であり、αS/αF(GaN)比が0.956であった。焼結体2Hは、質量比Al6Si213:Al23:SiO2が64.94:35:0.06であり、平均熱膨張係数αSが5.8×10-6/℃であり、αS/αF(GaN)比が0.990であった。焼結体2Iは、質量比Al6Si213:Al23:SiO2が55.96:44:0.04であり、平均熱膨張係数αSが6.1×10-6/℃であり、αS/αF(GaN)比が1.041であった。焼結体2Jは、質量比Al6Si213:Al23:SiO2が50:50:0であり、平均熱膨張係数αSが6.2×10-6/℃であり、αS/αF(GaN)比が1.058であった。 The sintered body 2A has a mass ratio Al 6 Si 2 O 13 : Al 2 O 3 : SiO 2 of 79: 1: 19 between the mullite phase and the alumina phase, which is a crystalline phase, and the amorphous phase, and 25 ° C. To 800 ° C., the average thermal expansion coefficient α S (hereinafter simply referred to as the average thermal expansion coefficient α S ) is 3.5 × 10 −6 / ° C., and the average thermal expansion coefficient α F ( The ratio of the thermal expansion coefficient α S of the sintered body to GaN) (hereinafter referred to as α S / α F (GaN) ratio) was 0.597. The sintered body 2B has a mass ratio of Al 6 Si 2 O 13 : Al 2 O 3 : SiO 2 of 90: 1: 9, an average thermal expansion coefficient α S of 3.9 × 10 −6 / ° C., The α S / α F (GaN) ratio was 0.666. The sintered body 2C has a mass ratio of Al 6 Si 2 O 13 : Al 2 O 3 : SiO 2 of 93: 1: 6, an average thermal expansion coefficient α S of 4.3 × 10 −6 / ° C., The α S / α F (GaN) ratio was 0.734. The sintered body 2D has a mass ratio of Al 6 Si 2 O 13 : Al 2 O 3 : SiO 2 of 97: 1: 2, an average thermal expansion coefficient α S of 4.8 × 10 −6 / ° C., The α S / α F (GaN) ratio was 0.819. The sintered body 2E has a mass ratio of Al 6 Si 2 O 13 : Al 2 O 3 : SiO 2 of 88.5: 11: 0.5 and an average coefficient of thermal expansion α S of 5.0 × 10 −6 / ° C and the α S / α F (GaN) ratio was 0.853. The sintered body 2F has a mass ratio of Al 6 Si 2 O 13 : Al 2 O 3 : SiO 2 of 78.9: 21: 0.1 and an average thermal expansion coefficient α S of 5.2 × 10 −6 / ° C and the α S / α F (GaN) ratio was 0.887. The sintered body 2G has a mass ratio of Al 6 Si 2 O 13 : Al 2 O 3 : SiO 2 of 71.92: 28: 0.08 and an average thermal expansion coefficient α S of 5.6 × 10 −6 / ° C and the α S / α F (GaN) ratio was 0.956. The sintered body 2H has a mass ratio of Al 6 Si 2 O 13 : Al 2 O 3 : SiO 2 of 64.94: 35: 0.06 and an average thermal expansion coefficient α S of 5.8 × 10 −6 / ° C and the α S / α F (GaN) ratio was 0.990. The sintered body 2I has a mass ratio of Al 6 Si 2 O 13 : Al 2 O 3 : SiO 2 of 55.96: 44: 0.04 and an average thermal expansion coefficient α S of 6.1 × 10 −6 / ° C and the α S / α F (GaN) ratio was 1.041. The sintered body 2J has a mass ratio of Al 6 Si 2 O 13 : Al 2 O 3 : SiO 2 of 50: 50: 0, an average thermal expansion coefficient α S of 6.2 × 10 −6 / ° C., The α S / α F (GaN) ratio was 1.058.

上記10種類の焼結体2A〜2Jから、直径4インチ(101.6mm)で厚さ0.40mmの支持基板をそれぞれ切り出して、それぞれの支持基板の両主面を鏡面に研磨して、10種類の支持基板2A〜2Jを作製した。研磨後の支持基板2A〜2Jの主面の平坦化度は、実施例1と同様にして評価した。主面の平坦化度は、支持基板2Aが低、支持基板2B〜2Dが中、支持基板2E〜2Jが高であった。   From the 10 types of sintered bodies 2A to 2J, a support substrate having a diameter of 4 inches (101.6 mm) and a thickness of 0.40 mm was cut out, and both main surfaces of each support substrate were polished into mirror surfaces. Various types of support substrates 2A to 2J were prepared. The flatness of the main surfaces of the support substrates 2A to 2J after polishing was evaluated in the same manner as in Example 1. The flatness of the main surface was low for the support substrate 2A, medium for the support substrates 2B to 2D, and high for the support substrates 2E to 2J.

(2)下地基板上に半導体膜を成膜するサブ工程
図2(B)を参照して、下地基板30として、実施例1と同様にして、鏡面に研磨された(111)面の主面30nを有する直径5インチ(127mm)で厚さ0.5mmのSi基板を準備した。
(2) Sub-Process for Forming Semiconductor Film on Base Substrate Referring to FIG. 2 (B), as the base substrate 30, the main surface of the (111) surface polished to a mirror surface in the same manner as in Example 1 A Si substrate having a diameter of 5 inches (127 mm) and a thickness of 0.5 mm having 30n was prepared.

上記の下地基板30の主面30n上に、実施例1と同様にして、半導体膜13として厚さ0.4μmのGaN膜をMOCVD法により成膜した。得られた半導体膜13の主面13mは、(0001)面からのオフ角が±1°以内の面方位を有していた。   A GaN film having a thickness of 0.4 μm was formed as the semiconductor film 13 on the main surface 30n of the base substrate 30 by the MOCVD method in the same manner as in Example 1. The main surface 13m of the obtained semiconductor film 13 had a plane orientation whose off angle from the (0001) plane was within ± 1 °.

(3)支持基板と半導体膜とを貼り合わせるサブ工程
図2(C)を参照して、実施例1と同様にして、支持基板11と半導体膜13とを接合膜12を介在させて貼り合わせた。
(3) Sub-step of bonding support substrate and semiconductor film Referring to FIG. 2C, the support substrate 11 and the semiconductor film 13 are bonded together with the bonding film 12 interposed in the same manner as in the first embodiment. It was.

(4)下地基板を除去するサブ工程
図2(D)を参照して、実施例1と同様にして、下地基板30であるSi基板を除去した。こうして、図4(A)に示すような支持基板11である支持基板2A〜2Jのそれぞれの主面11m側に半導体膜13であるGaN膜が配置された複合基板1である複合基板2A〜2Jが得られた。
(4) Sub-Process for Removing the Base Substrate With reference to FIG. 2D, the Si substrate as the base substrate 30 was removed in the same manner as in Example 1. Thus, the composite substrates 2A to 2J, which are the composite substrates 1 in which the GaN film that is the semiconductor film 13 is arranged on the main surface 11m side of each of the support substrates 2A to 2J that are the support substrates 11 as shown in FIG. was gotten.

3.半導体層の形成工程
図4(B)を参照して、実施例1と同様にして、複合基板1である複合基板2A〜2Jの半導体膜13であるGaN膜の主面13m(かかる主面は(0001)面である。)上に、それぞれMOCVD法により半導体層20としてGaN層を成長させた。こうして、複合基板2A〜2Jのそれぞれに半導体層30であるGaN層が形成された半導体層付複合基板2A〜2Jを得た。
3. Step of Forming Semiconductor Layer Referring to FIG. 4B, in the same manner as in Example 1, the main surface 13m of the GaN film that is the semiconductor film 13 of the composite substrate 2A to 2J that is the composite substrate 1 (the main surface is A GaN layer was grown as the semiconductor layer 20 by the MOCVD method. Thus, composite substrates with semiconductor layers 2A to 2J in which the GaN layers as the semiconductor layers 30 were formed on the composite substrates 2A to 2J were obtained.

室温まで冷却後に成膜装置から取り出された半導体層付複合基板2A〜2Jにの反り形状および反り量を、実施例1と同様にして測定した。   The warpage shape and the warpage amount of the composite substrates 2A to 2J with semiconductor layers taken out from the film forming apparatus after cooling to room temperature were measured in the same manner as in Example 1.

半導体層付複合基板2Aは、半導体層側が凹状に反り、支持基板が割れたため、反り量の測定が困難であった。半導体層付複合基板2Bは、半導体層側が凹状に反り、反り量が690μmであった。半導体層付複合基板2Cは、半導体層側が凹状に反り、反り量が670μmであった。半導体層付複合基板2Dは、半導体層側が凹状に反り、反り量が620μmであった。半導体層付複合基板2Eは、半導体層側が凹状に反り、反り量が500μmであった。半導体層付複合基板2Fは、半導体層側が凹状に反り、反り量が400μmであった。半導体層付複合基板2Gは、半導体層側が凹状に反り、反り量が230μmであった。半導体層付複合基板1Hは、半導体層側が凹状に反り、反り量が150μmであった。半導体層付複合基板2Iは、半導体層側が凸状に反り、反り量が12μmであった。半導体層付複合基板2Jは、半導体層側が凸状に反り、反り量が13μmであった。これらの結果を表2にまとめた。   In the composite substrate 2A with a semiconductor layer, the semiconductor layer side warped in a concave shape and the support substrate was cracked, so that it was difficult to measure the amount of warpage. In the composite substrate 2B with a semiconductor layer, the semiconductor layer side warped in a concave shape, and the amount of warpage was 690 μm. In the composite substrate with a semiconductor layer 2C, the semiconductor layer side warped in a concave shape, and the amount of warpage was 670 μm. The composite substrate 2D with a semiconductor layer warped in a concave shape on the semiconductor layer side, and the amount of warpage was 620 μm. The composite substrate 2E with a semiconductor layer warped in a concave shape on the semiconductor layer side, and the amount of warpage was 500 μm. The composite substrate 2F with a semiconductor layer warped in a concave shape on the semiconductor layer side, and the amount of warpage was 400 μm. The semiconductor substrate with a semiconductor layer 2G warped in a concave shape on the semiconductor layer side, and the amount of warpage was 230 μm. The composite substrate with a semiconductor layer 1H warped in a concave shape on the semiconductor layer side, and the amount of warpage was 150 μm. In the composite substrate with semiconductor layer 2I, the semiconductor layer side warped convexly, and the amount of warpage was 12 μm. In the composite substrate 2J with a semiconductor layer, the semiconductor layer side warped convexly, and the amount of warpage was 13 μm. These results are summarized in Table 2.

4.支持基板の除去工程
図4(C)を参照して、上記で得られた半導体層付複合基板2A〜2Jを、45質量%のフッ化水素酸水溶液に浸漬することにより、支持基板11である支持基板2A〜2Jおよび接合膜12であるSiO2膜を研削および研磨することにより除去して、半導体膜13であるGaN膜の主面13m上に成長された半導体層20である半導体ウエハ2A〜2Jが得られた。
4). Step of removing support substrate Referring to FIG. 4C, the composite substrate 2A to 2J with the semiconductor layer obtained above is immersed in a 45% by mass hydrofluoric acid aqueous solution to form the support substrate 11. the supporting substrate 2A~2J and the bonding film 12 a is SiO 2 film is removed by grinding and polishing, the semiconductor wafer 2A~ a semiconductor layer 20 grown on the main surface 13m of the GaN film is a semiconductor film 13 2J was obtained.

なお、半導体ウエハ2A〜2Jにおいても反りがCorning Tropel社のFM200EWaferを用いて観察される光干渉縞による測定により認められ、半導体ウエハ1A〜1Mの反りの大小関係には、半導体層付複合基板1A〜1Mにおける反りの大小関係が維持されていた。   It should be noted that warpage in the semiconductor wafers 2A to 2J is also recognized by measurement by optical interference fringes observed using the Corning Tropel FM200EWafer, and the magnitude relation of the warpage of the semiconductor wafers 1A to 1M is related to the composite substrate with semiconductor layer 1A. The magnitude relation of the warp at ˜1M was maintained.

Figure 0006094243
Figure 0006094243

(実施例3)
1.複合基板の半導体膜を形成するGaN結晶の熱膨張係数の測定
複合基板の半導体膜を形成するGaN結晶の熱膨張係数を実施例1と同様にして測定したところ、複合基板の半導体膜を形成するGaN結晶のa軸方向の25℃から800℃までにおける平均熱膨張係数αF(GaN)は、5.84×10-6/℃であった。
(Example 3)
1. Measurement of thermal expansion coefficient of GaN crystal forming semiconductor film of composite substrate When the thermal expansion coefficient of GaN crystal forming semiconductor film of composite substrate was measured in the same manner as in Example 1, the semiconductor film of composite substrate was formed. The average coefficient of thermal expansion α F (GaN) from 25 ° C. to 800 ° C. in the a-axis direction of the GaN crystal was 5.84 × 10 −6 / ° C.

2.複合基板の準備工程
(1)支持基板を準備するサブ工程
図3(A)を参照して、支持基板11の材料として、アルミナ(Al23)粉末とシリカ(SiO2)粉末とを、以下の質量比で混合した13種類の原料3A〜3Mを、大気雰囲気下、1700℃で20時間焼結させることにより、13種類の焼結体3A〜3Mを準備した。ここで、Al23粉末とSiO2粉末との質量比Al23:SiO2は、原料3Aが65:35、原料3Bが70:30、原料3Cが73:27、原料3Dが77:23、原料3Eが79:21、原料3Fが81:19、原料3Gが83:17、原料3Hが85:15、原料3Iが87:13、原料3Jが89:11、原料3Kが92:8、原料3Lが95:5、原料3Mが98:2であった。
2. Preparation Step of Composite Substrate (1) Sub-Step of Preparing Support Substrate With reference to FIG. 3 (A), alumina (Al 2 O 3 ) powder and silica (SiO 2 ) powder are used as materials for the support substrate 11. Thirteen types of sintered bodies 3A to 3M were prepared by sintering 13 types of raw materials 3A to 3M mixed at the following mass ratios in an air atmosphere at 1700 ° C. for 20 hours. Here, the mass ratio Al 2 O 3 : SiO 2 between the Al 2 O 3 powder and the SiO 2 powder is 65:35 for the raw material 3A, 70:30 for the raw material 3B, 73:27 for the raw material 3C, and 77 for the raw material 3D. : 23, Raw material 3E 79:21, Raw material 3F 81:19, Raw material 3G 83:17, Raw material 3H 85:15, Raw material 3I 87:13, Raw material 3J 89:11, Raw material 3K 92: 8. Raw material 3L was 95: 5, and raw material 3M was 98: 2.

準備した13種類の焼結体3A〜3Mには、X線回折により確認したところ、いずれについても結晶相としてムライト(Al6Si213)相およびアルミナ(Al23)相が存在していた。非結晶相であるシリカ(SiO2)相は、X線回折では検出されないが、焼結体を20mm×10mm×厚さ0.15mmの大きさに加工し、45質量%のフッ化水素酸水溶液200mlに20時間溶解させて得られた溶液を、ICP−OES(誘導結合プラズマ−発光)分析により評価し、検出されたSi量から焼結体中のシリカ含有量を算出した。この結果と、X線回折の結果を併せて支持基板11の組成比とした。 The prepared 13 types of sintered bodies 3A to 3M were confirmed by X-ray diffraction. As a result, a mullite (Al 6 Si 2 O 13 ) phase and an alumina (Al 2 O 3 ) phase existed as crystal phases. It was. The silica (SiO 2 ) phase, which is an amorphous phase, is not detected by X-ray diffraction, but the sintered body is processed into a size of 20 mm × 10 mm × thickness 0.15 mm, and a 45 mass% hydrofluoric acid aqueous solution The solution obtained by dissolving in 200 ml for 20 hours was evaluated by ICP-OES (inductively coupled plasma-luminescence) analysis, and the silica content in the sintered body was calculated from the detected amount of Si. This result and the result of X-ray diffraction were combined to determine the composition ratio of the support substrate 11.

また、上記13種類の焼結体3A〜3Mのそれぞれからサイズが2×2×20mm(長手方向は焼結体から切り出される支持基板の主面に実質的に平行な方向)の測定用サンプルを切り出した。ここで、焼結体3A〜3Mは方向特異性がないため、切り出し方向は任意とした。それらの測定用サンプルについて、上記と同様にして、室温(25℃)から800℃まで昇温した時の平均熱膨張係数αSを測定した。 Further, a sample for measurement having a size of 2 × 2 × 20 mm (longitudinal direction is a direction substantially parallel to the main surface of the support substrate cut out from the sintered body) from each of the 13 types of sintered bodies 3A to 3M. Cut out. Here, since the sintered bodies 3A to 3M have no direction specificity, the cutting direction was arbitrary. For these measurement samples, the average thermal expansion coefficient α S when the temperature was raised from room temperature (25 ° C.) to 800 ° C. was measured in the same manner as described above.

焼結体3Aは、結晶相であるムライト相およびアルミナ相と非結晶相シリカ相との質量比Al6Si213:Al23:SiO2が89:1:10であり、25℃から800℃までにおける平均熱膨張係数αS(以下、単に平均熱膨張係数αSという)が4.0×10-6/℃であり、GaN結晶のa軸方向の平均熱膨張係数αF(GaN)に対する焼結体の熱膨張係数αSの比(以下、αS/αF(GaN)比という)が0.683であった。焼結体3Bは、質量比Al6Si213:Al23:SiO2が96:1:3であり、平均熱膨張係数αSが4.5×10-6/℃であり、αS/αF(GaN)比が0.768であった。焼結体3Cは、質量比Al6Si213:Al23:SiO2が95:4:1であり、平均熱膨張係数αSが4.8×10-6/℃であり、αS/αF(GaN)比が0.819であった。焼結体3Dは、質量比Al6Si213:Al23:SiO2が79:19:1であり、平均熱膨張係数αSが5.1×10-6/℃であり、αS/αF(GaN)比が0.870であった。焼結体3Eは、質量比Al6Si213:Al23:SiO2が73.9:26:0.1であり、平均熱膨張係数αSが5.4×10-6/℃であり、αS/αF(GaN)比が0.922であった。焼結体3Fは、質量比Al6Si213:Al23:SiO2が67.02:32:0.08であり、平均熱膨張係数αSが5.6×10-6/℃であり、αS/αF(GaN)比が0.956であった。焼結体3Gは、質量比Al6Si213:Al23:SiO2が60.94:39:0.06であり、平均熱膨張係数αSが5.8×10-6/℃であり、αS/αF(GaN)比が0.990であった。焼結体3Hは、質量比Al6Si213:Al23:SiO2が52.94:47:0.06であり、平均熱膨張係数αSが6.0×10-6/℃であり、αS/αF(GaN)比が1.024であった。焼結体3Iは、質量比Al6Si213:Al23:SiO2が45:54.95:0.05であり、平均熱膨張係数αSが6.2×10-6/℃であり、αS/αF(GaN)比が1.058であった。焼結体3Jは、質量比Al6Si213:Al23:SiO2が38:61.95:0.05であり、平均熱膨張係数αSが6.5×10-6/℃であり、αS/αF(GaN)比が1.109であった。焼結体3Kは、質量比Al6Si213:Al23:SiO2が28:71.96:0.04であり、平均熱膨張係数αSが6.9×10-6/℃であり、αS/αF(GaN)比が1.177であった。焼結体3Lは、質量比Al6Si213:Al23:SiO2が17:82.97:0.03であり、平均熱膨張係数αSが7.3×10-6/℃であり、αS/αF(GaN)比が1.246であった。焼結体3Mは、質量比Al6Si213:Al23:SiO2が7:92.99:0.01であり、平均熱膨張係数αSが7.9×10-6/℃であり、αS/αF(GaN)比が1.348であった。 The sintered body 3A has a mass ratio Al 6 Si 2 O 13 : Al 2 O 3 : SiO 2 of 89: 1: 10 between the mullite phase, which is a crystalline phase, and the alumina phase and the amorphous silica phase, and 25 ° C. The average thermal expansion coefficient α S (hereinafter simply referred to as the average thermal expansion coefficient α S ) from 4.0 to 800 ° C. is 4.0 × 10 −6 / ° C., and the average thermal expansion coefficient α F ( The ratio of the thermal expansion coefficient α S of the sintered body to GaN) (hereinafter referred to as α S / α F (GaN) ratio) was 0.683. The sintered body 3B has a mass ratio of Al 6 Si 2 O 13 : Al 2 O 3 : SiO 2 of 96: 1: 3, an average thermal expansion coefficient α S of 4.5 × 10 −6 / ° C., The α S / α F (GaN) ratio was 0.768. The sintered body 3C has a mass ratio of Al 6 Si 2 O 13 : Al 2 O 3 : SiO 2 of 95: 4: 1, an average thermal expansion coefficient α S of 4.8 × 10 −6 / ° C., The α S / α F (GaN) ratio was 0.819. The sintered body 3D has a mass ratio of Al 6 Si 2 O 13 : Al 2 O 3 : SiO 2 of 79: 19: 1, an average thermal expansion coefficient α S of 5.1 × 10 −6 / ° C., The α S / α F (GaN) ratio was 0.870. The sintered body 3E has a mass ratio of Al 6 Si 2 O 13 : Al 2 O 3 : SiO 2 of 73.9: 26: 0.1 and an average thermal expansion coefficient α S of 5.4 × 10 −6 / ° C and the α S / α F (GaN) ratio was 0.922. The sintered body 3F has a mass ratio of Al 6 Si 2 O 13 : Al 2 O 3 : SiO 2 of 67.02: 32: 0.08 and an average thermal expansion coefficient α S of 5.6 × 10 −6 / ° C and the α S / α F (GaN) ratio was 0.956. The sintered body 3G has a mass ratio of Al 6 Si 2 O 13 : Al 2 O 3 : SiO 2 of 60.94: 39: 0.06 and an average thermal expansion coefficient α S of 5.8 × 10 −6 / ° C and the α S / α F (GaN) ratio was 0.990. The sintered body 3H has a mass ratio of Al 6 Si 2 O 13 : Al 2 O 3 : SiO 2 of 52.94: 47: 0.06 and an average thermal expansion coefficient α S of 6.0 × 10 −6 / And the α S / α F (GaN) ratio was 1.024. The sintered body 3I has a mass ratio of Al 6 Si 2 O 13 : Al 2 O 3 : SiO 2 of 45: 54.95: 0.05 and an average thermal expansion coefficient α S of 6.2 × 10 −6 / And the α S / α F (GaN) ratio was 1.058. The sintered body 3J had a mass ratio of Al 6 Si 2 O 13 : Al 2 O 3 : SiO 2 of 38: 61.95: 0.05 and an average thermal expansion coefficient α S of 6.5 × 10 −6 / And the α S / α F (GaN) ratio was 1.109. The sintered body 3K has a mass ratio of Al 6 Si 2 O 13 : Al 2 O 3 : SiO 2 of 28: 71.96: 0.04 and an average thermal expansion coefficient α S of 6.9 × 10 −6 / And the α S / α F (GaN) ratio was 1.177. The sintered body 3L has a mass ratio of Al 6 Si 2 O 13 : Al 2 O 3 : SiO 2 of 17: 82.97: 0.03 and an average thermal expansion coefficient α S of 7.3 × 10 −6 / And the α S / α F (GaN) ratio was 1.246. The sintered body 3M has a mass ratio of Al 6 Si 2 O 13 : Al 2 O 3 : SiO 2 of 7: 92.99: 0.01 and an average thermal expansion coefficient α S of 7.9 × 10 −6 / The α S / α F (GaN) ratio was 1.348.

上記13種類の焼結体3A〜3Mから、直径4インチ(101.6mm)で厚さ0.40mmの支持基板をそれぞれ切り出して、それぞれの支持基板の両主面を鏡面に研磨して、13種類の支持基板3A〜3Mを作製した。研磨後の支持基板3A〜3Mの主面の平坦化度は、AFM(電子間力顕微鏡)を用いて20μm×20μmの範囲で測定したJIS B0601に規定する算術平均粗さRaの値により評価した。主面の平坦化度の評価は、算術平均粗さRaが10nm以下のものを高、算術平均粗さRaが10nmより大きく20nm以下のものを中、算術平均粗さRaが20nmより大きいものを低、とした。主面の平坦化度は、支持基板3Aが低、支持基板3B〜3Dが中、支持基板3E〜3Mが高であった。   A support substrate having a diameter of 4 inches (101.6 mm) and a thickness of 0.40 mm was cut out from each of the 13 types of sintered bodies 3A to 3M, and both main surfaces of each support substrate were polished into mirror surfaces. Various types of support substrates 3A to 3M were prepared. The flatness of the main surfaces of the support substrates 3A to 3M after polishing was evaluated by the value of the arithmetic average roughness Ra defined in JIS B0601 measured in the range of 20 μm × 20 μm using an AFM (electron force microscope). . The evaluation of the flatness of the main surface is such that the arithmetic average roughness Ra is 10 nm or less, the arithmetic average roughness Ra is greater than 10 nm and less than 20 nm, and the arithmetic average roughness Ra is greater than 20 nm. Low. The flatness of the main surface was low for the support substrate 3A, medium for the support substrates 3B to 3D, and high for the support substrates 3E to 3M.

(2)半導体膜ドナー基板を準備する工程
図3(B)を参照して、III族窒化物膜ドナー基板13Dとして直径4インチ(101.6mm)で厚さ8mmのGaN結晶体を準備し、III族窒化物膜ドナー基板13Dの貼り合わせ面を機械研磨および好ましくはCMPにより算術平均粗さRaが10nm以下に鏡面化した。ここで、III族窒化物膜ドナー基板13Dは、下地基板としてGaAs基板を用いて、HVPE法により成長させたものであった。
(2) Step of Preparing Semiconductor Film Donor Substrate Referring to FIG. 3B, a GaN crystal body having a diameter of 4 inches (101.6 mm) and a thickness of 8 mm is prepared as a group III nitride film donor substrate 13D. The bonded surface of the group III nitride film donor substrate 13D was mirror-polished to an arithmetic average roughness Ra of 10 nm or less by mechanical polishing and preferably by CMP. Here, the group III nitride film donor substrate 13D was grown by HVPE using a GaAs substrate as a base substrate.

(3)支持基板と半導体膜ドナー基板とを貼り合わせるサブ工程
図3(C)中の(C1)を参照して、図3(A)の支持基板11である支持基板3A〜3Mのそれぞれの主面11m上に厚さ2μmのSiO2膜をCVD(化学気相堆積)法により成膜した。次いで、かかる支持基板3A〜3Mのそれぞれの主面11m上の厚さ2μmのSiO2膜を、CeO2スラリーを用いて研磨することにより、厚さ0.2μmのSiO2膜だけ残存させて、接合膜12aとした。これにより、支持基板3A〜3Mのそれぞれの主面11mの空隙が埋められ、接合膜12aである平坦な主面12amを有する厚さ0.2μmのSiO2膜が得られた。
(3) Sub-process for bonding support substrate and semiconductor film donor substrate Referring to (C1) in FIG. 3 (C), each of support substrates 3A to 3M which are support substrate 11 in FIG. 3 (A) A SiO 2 film having a thickness of 2 μm was formed on the main surface 11 m by a CVD (chemical vapor deposition) method. Next, the SiO 2 film having a thickness of 2 μm on each main surface 11 m of the supporting substrates 3 </ b> A to 3 </ b> M is polished using a CeO 2 slurry to leave only the SiO 2 film having a thickness of 0.2 μm. The bonding film 12a was obtained. Thus, the gap is filled in each of the main surfaces 11m of the supporting substrate 3A~3M, SiO 2 film having a thickness of 0.2μm having a flat main surface 12am is bonding film 12a is obtained.

また、図3(C)中の(C2)を参照して、図3(B)の半導体膜ドナー基板13DであるGaN結晶体の主面13n上に厚さ2μmのSiO2膜をCVD法により成膜した。次いで、この厚さ2μmのSiO2膜を、CeO2スラリーを用いて研磨することにより、厚さ0.2μmのSiO2膜だけ残存させて、接合膜12bとした。 Further, referring to (C2) in FIG. 3 (C), an SiO 2 film having a thickness of 2 μm is formed by CVD on the main surface 13n of the GaN crystal body which is the semiconductor film donor substrate 13D in FIG. 3 (B). A film was formed. Next, the SiO 2 film having a thickness of 2 μm was polished using a CeO 2 slurry, so that only the SiO 2 film having a thickness of 0.2 μm was left to form the bonding film 12b.

次いで、図3(C)中の(C3)を参照して、支持基板11である支持基板3A〜3Mのそれぞれに形成された接合膜12aの主面12amおよび半導体膜ドナー基板13D上に形成された接合膜12bの主面12bnをアルゴンプラズマにより清浄化および活性化させた後、接合膜12aの主面12amと接合膜12bの主面12bnとを貼り合わせて、窒素雰囲気下300℃で2時間熱処理した。   Next, referring to (C3) in FIG. 3 (C), formed on the main surface 12am of the bonding film 12a and the semiconductor film donor substrate 13D formed on each of the support substrates 3A to 3M as the support substrate 11. After cleaning and activating the main surface 12bn of the bonding film 12b with argon plasma, the main surface 12am of the bonding film 12a and the main surface 12bn of the bonding film 12b are bonded together, and then at 300 ° C. for 2 hours in a nitrogen atmosphere. Heat treated.

こうして、支持基板11に接合膜12を介在させて半導体膜ドナー基板13Dが貼り合わされた接合基板1Lが得られた。   Thus, the bonded substrate 1L was obtained in which the semiconductor film donor substrate 13D was bonded to the support substrate 11 with the bonding film 12 interposed.

3.半導体膜ドナー基板を切断するサブ工程
図3(D)を参照して、接合基板1LのIII族窒化物膜ドナー基板13Dを接合膜12との貼り合わせ面から内部に400μmの距離の深さに位置する面でワイヤーソーにより切断することにより、図4(A)に示すような支持基板11と半導体膜13であるGaN膜とが接合膜12を介在させて貼り合わされた複合基板1を得た。ワイヤーは、ダイヤモンド砥粒を電着した固定砥粒ワイヤーを用いた。切断抵抗を低減して厚さの精度および平坦性を高めるために、切断方式としてはワイヤーを揺動させ、それに同期して半導体膜ドナー基板13Dを振動させる方式とした。ワイヤーソー切断の抵抗係数は、4200Nとした。切断後に、III族窒化物複合基板1の半導体膜13を機械研磨およびCMPを行なった。半導体膜13の厚さの均一化のため、CMPでの複合基板の装置への取り付けには、予備的に真空チャック吸着で基板形状を矯正した後に、装置に吸着固定する方式とした。
3. Sub-Process for Cutting Semiconductor Film Donor Substrate Referring to FIG. 3D, the group III nitride film donor substrate 13D of bonding substrate 1L is formed at a depth of 400 μm from the bonding surface with bonding film 12 to the inside. By cutting with a wire saw at the surface to be located, a composite substrate 1 was obtained in which a supporting substrate 11 and a GaN film as a semiconductor film 13 were bonded together with a bonding film 12 interposed therebetween as shown in FIG. . The wire used was a fixed abrasive wire electrodeposited with diamond abrasive grains. In order to reduce the cutting resistance and increase the accuracy and flatness of the thickness, the cutting method is a method in which the wire is swung and the semiconductor film donor substrate 13D is vibrated in synchronization therewith. The resistance coefficient of wire saw cutting was 4200N. After cutting, the semiconductor film 13 of the group III nitride composite substrate 1 was subjected to mechanical polishing and CMP. In order to make the thickness of the semiconductor film 13 uniform, the composite substrate is attached to the apparatus by CMP by preliminarily correcting the substrate shape by vacuum chuck adsorption and then adsorbing and fixing to the apparatus.

4.半導体層の形成工程
図4(B)を参照して、実施例1と同様にして、複合基板1である複合基板3A〜3Mの半導体膜13であるGaN膜の主面13m(かかる主面は(0001)面である。)上に、それぞれMOCVD法により半導体層20としてGaN層を成長させた。こうして、複合基板3A〜3Mのそれぞれに半導体層20であるGaN層が形成された半導体層付複合基板3A〜3Mを得た。
4). Step of Forming Semiconductor Layer Referring to FIG. 4B, in the same manner as in Example 1, the main surface 13m of the GaN film that is the semiconductor film 13 of the composite substrates 3A to 3M that are the composite substrate 1 (the main surface is A GaN layer was grown as the semiconductor layer 20 by the MOCVD method. Thus, composite substrates with semiconductor layers 3A to 3M in which the GaN layers as the semiconductor layers 20 were formed on the composite substrates 3A to 3M were obtained.

室温まで冷却後に成膜装置から取り出された半導体層付複合基板2A〜2Jにの反り形状および反り量を、実施例1と同様にして測定した。   The warpage shape and the warpage amount of the composite substrates 2A to 2J with semiconductor layers taken out from the film forming apparatus after cooling to room temperature were measured in the same manner as in Example 1.

半導体層付複合基板3Aは、半導体層側が凹状に反り、反り量が700μmであった。半導体層付複合基板3Bは、半導体層側が凹状に反り、反り量が650μmであった。半導体層付複合基板3Cは、半導体層側が凹状に反り、反り量が630μmであった。半導体層付複合基板3Dは、半導体層側が凹状に反り、反り量が450μmであった。半導体層付複合基板3Eは、半導体層側が凹状に反り、反り量が350μmであった。半導体層付複合基板3Fは、半導体層側が凹状に反り、反り量が230μmであった。半導体層付複合基板3Gは、半導体層側が凹状に反り、反り量が150μmであった。半導体層付複合基板3Hは、半導体層側が凹状に反り、反り量が10μmであった。半導体層付複合基板3Iは、半導体層側が凸状に反り、反り量が13μmであった。半導体層付複合基板3Jは、半導体層側が凸状に反り、反り量が100μmであった。半導体層付複合基板3Kは、半導体層側が凸状に反り、反り量が220μmであった。半導体層付複合基板3Lは、半導体層側が凸状に反り、反り量が750μmであった。半導体層付複合基板3Mは、半導体層側が凸状に反り、支持基板が割れたため、反り量の測定が困難であった。これらの結果を表3にまとめた。表3において、「−」は、その物性値が未測定であることを示す。   In the composite substrate with semiconductor layer 3A, the semiconductor layer side warped in a concave shape, and the amount of warpage was 700 μm. In the composite substrate 3B with a semiconductor layer, the semiconductor layer side warped in a concave shape, and the amount of warpage was 650 μm. In the composite substrate with a semiconductor layer 3C, the semiconductor layer side warped in a concave shape, and the amount of warpage was 630 μm. In the composite substrate 3D with a semiconductor layer, the semiconductor layer side warped in a concave shape, and the amount of warpage was 450 μm. In the composite substrate 3E with a semiconductor layer, the semiconductor layer side warped in a concave shape, and the amount of warpage was 350 μm. The composite substrate 3F with a semiconductor layer warped in a concave shape on the semiconductor layer side, and the amount of warpage was 230 μm. In the composite substrate 3G with a semiconductor layer, the semiconductor layer side warped in a concave shape, and the amount of warpage was 150 μm. In the composite substrate 3H with a semiconductor layer, the semiconductor layer side warped in a concave shape, and the amount of warpage was 10 μm. In the composite substrate with semiconductor layer 3I, the semiconductor layer side warped in a convex shape, and the amount of warpage was 13 μm. The composite substrate 3J with a semiconductor layer warped in a convex shape on the semiconductor layer side, and the amount of warpage was 100 μm. The composite substrate 3K with a semiconductor layer warped in a convex shape on the semiconductor layer side, and the warpage amount was 220 μm. In the composite substrate with a semiconductor layer 3L, the semiconductor layer side warped in a convex shape, and the amount of warpage was 750 μm. In the composite substrate 3M with a semiconductor layer, the semiconductor layer side warped in a convex shape and the support substrate was cracked, so that it was difficult to measure the amount of warpage. These results are summarized in Table 3. In Table 3, “-” indicates that the physical property value is not measured.

5.支持基板の除去工程
図4(C)を参照して、上記で得られた半導体層付複合基板3A〜3Mを、45質量%のフッ化水素酸水溶液に浸漬することにより、支持基板11である支持基板3A〜3Mおよび接合膜12であるSiO2膜を溶解させることにより除去して、半導体膜13であるGaN膜の主面13m上に成長された半導体層20である半導体ウエハ3A〜3Mが得られた。下地基板の除去時間は、表3に示すように、半導体層付複合基板3A〜3Lについて500時間未満であり、半導体層付複合基板3Mについては500時間以上であった。
5. Step of removing support substrate Referring to FIG. 4C, the composite substrate 3A to 3M with a semiconductor layer obtained above is immersed in a 45% by mass hydrofluoric acid aqueous solution to form the support substrate 11. The semiconductor wafers 3A to 3M, which are the semiconductor layers 20 grown on the main surface 13m of the GaN film that is the semiconductor film 13, are removed by dissolving the support substrates 3A to 3M and the SiO 2 film that is the bonding film 12. Obtained. As shown in Table 3, the removal time of the base substrate was less than 500 hours for the composite substrates with semiconductor layers 3A to 3L, and 500 hours or more for the composite substrate with semiconductor layers 3M.

なお、半導体ウエハ3A〜3Mにおいても反りがCorning Tropel社のFM200EWaferを用いて観察される光干渉縞による測定により認められ、半導体ウエハ3A〜3Mの反りの大小関係には、半導体層付複合基板3A〜3Mにおける反りの大小関係が維持されていた。   It should be noted that the warpage of the semiconductor wafers 3A to 3M is also recognized by measurement by optical interference fringes observed using the Corning Tropel FM200EWafer, and the magnitude relation of the warpage of the semiconductor wafers 3A to 3M is related to the composite substrate 3A with semiconductor layer. The magnitude relation of warpage at ˜3M was maintained.

Figure 0006094243
Figure 0006094243

表1〜表3を参照して、結晶相として35質量%以上65質量%以下のムライト相および35質量%以上65質量%以下のアルミナ相を含む支持基板と、支持基板の主面側に配置されている厚さ10μm以上の半導体膜と、を含む複合基板は、支持基板の研磨後の平坦度が高くかつ半導体膜の熱膨張係数αFに対する支持基板の熱膨張係数αSの比αS/αFが0.99以上1.11以下と1に近く、かかる複合基板を用いることにより、反りの小さい半導体層付複合基板および反りの小さい半導体ウエハが得られた。また、複合基板において研磨後の支持基板の主面の平坦化度を高く維持しつつ支持基板のエッチングによる除去性を高める観点から、支持基板は非結晶相として10質量%以下のシリカ相をさらに含むことが好ましかった。 Referring to Tables 1 to 3, a support substrate including a mullite phase of 35% to 65% by mass and an alumina phase of 35% to 65% by mass as a crystal phase, and disposed on the main surface side of the support substrate The composite substrate including a semiconductor film having a thickness of 10 μm or more has high flatness after polishing of the support substrate, and the ratio α S of the thermal expansion coefficient α S of the support substrate to the thermal expansion coefficient α F of the semiconductor film By using such a composite substrate, / α F is 0.99 or more and 1.11 or less close to 1, a composite substrate with a semiconductor layer with small warpage and a semiconductor wafer with small warpage were obtained. Further, from the viewpoint of improving the removability by etching of the support substrate while maintaining a high degree of flatness of the main surface of the support substrate after polishing in the composite substrate, the support substrate further includes a silica phase of 10% by mass or less as an amorphous phase. It was preferable to include.

今回開示された実施形態および実施例はすべての点で例示であって制限的なものではないと考えられるべきである。本発明の範囲は、上記した説明でなくて特許請求の範囲によって示され、特許請求の範囲と均等の意味および範囲内のすべての変更が含まれることが意図される。   It should be understood that the embodiments and examples disclosed herein are illustrative and non-restrictive in every respect. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 複合基板、1L 接合基板、2 半導体膜付複合基板、3 半導体ウエハ、11 支持基板、1m,11m,12am,12bn,13m,13n,20m,21m,23m,30n 主面、12,12a,12b 接合膜、13 半導体膜、13D 半導体膜ドナー基板、20 半導体層、21 半導体バッファ層、23 半導体結晶層、30 下地基板。   DESCRIPTION OF SYMBOLS 1 Composite substrate, 1L bonded substrate, 2 Composite substrate with semiconductor film, 3 Semiconductor wafer, 11 Support substrate, 1m, 11m, 12am, 12bn, 13m, 13n, 20m, 21m, 23m, 30n Main surface, 12, 12a, 12b Bonding film, 13 semiconductor film, 13D semiconductor film donor substrate, 20 semiconductor layer, 21 semiconductor buffer layer, 23 semiconductor crystal layer, 30 base substrate.

Claims (2)

結晶相として35質量%以上65質量%以下のムライト相および35質量%以上65質量%以下のアルミナ相を含み、非結晶相として10質量%以下のシリカ相を含む支持基板と、前記支持基板の主面側に配置されている厚さ10μm以上の半導体膜と、を含む複合基板。 See contains 35 mass% or more 65 wt% or less of mullite phase and 35 wt% or more 65 wt% or less of the alumina phase as a crystal phase, and including a supporting substrate 10 mass% or less of the silica phase as the amorphous phase, the support A composite substrate comprising: a semiconductor film having a thickness of 10 μm or more disposed on a main surface side of the substrate. 結晶相として35質量%以上65質量%以下のムライト相および35質量%以上65質量%以下のアルミナ相をみ、非結晶相として10質量%以下のシリカ相を含む支持基板と、前記支持基板の主面側に配置されている厚さ10μm以上の半導体膜と、を含む複合基板を準備する工程と、
前記複合基板の前記半導体膜上に少なくとも1層の半導体層を成長させて半導体層付複合基板を形成する工程と、
前記半導体層付複合基板から前記支持基板を除去して半導体ウエハを形成する工程と、を含む半導体ウエハの製造方法。
See contains 35 mass% or more 65 wt% or less of mullite phase and 35 wt% or more 65 wt% or less of the alumina phase as a crystal phase, and including a supporting substrate 10 mass% or less of the silica phase as the amorphous phase, the support Preparing a composite substrate including a semiconductor film having a thickness of 10 μm or more disposed on the main surface side of the substrate;
Growing at least one semiconductor layer on the semiconductor film of the composite substrate to form a composite substrate with a semiconductor layer;
Removing the support substrate from the composite substrate with a semiconductor layer to form a semiconductor wafer.
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