JP6094011B2 - Semiconductor light receiving element and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor light receiving element and a method for manufacturing the same.

  A semiconductor light receiving element is known in which an electrode pad electrically connected to a semiconductor layer constituting a mesa-shaped light receiving portion is provided on a dummy mesa different from the mesa of the light receiving portion (for example, Patent Document 1).

JP-A-4-290477

  The semiconductor layer constituting the mesa-shaped light receiving portion has a structure in which a first conductivity type semiconductor layer and a second conductivity type semiconductor layer opposite to the first conductivity type are sequentially stacked on a substrate. Each of the first conductivity type semiconductor layer and the second conductivity type semiconductor layer is electrically connected to an electrode pad on the electrode connection portion by wiring extending on the dummy mesa (hereinafter referred to as an electrode connection portion). In such a configuration, since a parasitic capacitance is generated between the wiring electrically connected to the second conductivity type semiconductor layer and the first conductivity type semiconductor layer, the first conductivity type semiconductor layer around the electrode connection portion is generated. Is made to be removed. However, in this case, disconnection is likely to occur in the wiring due to a step formed by the groove formed by removing the first conductive type semiconductor layer.

  In view of the above-described problems, an object of the present invention is to provide a semiconductor light-receiving element that can reduce parasitic capacitance and suppress the disconnection of wiring, and a method for manufacturing the same.

  A semiconductor light receiving element according to the present invention is provided on a semi-insulating substrate, and includes a stacked structure including a first conductive semiconductor layer and a second conductive semiconductor layer having a conductivity type opposite to the first conductive semiconductor layer. A mesa-shaped light receiving portion, a mesa-shaped first electrode connecting portion and a mesa-shaped second electrode connecting portion provided on the semi-insulating substrate and including the same laminated structure as the light receiving portion, and the first electrode A resin film embedded between the connection portion and the light receiving portion; and an electrode pad on the first electrode connection portion and the second conductive semiconductor in the light receiving portion provided to extend on the resin film A first wiring for electrically connecting the layers; the first conductive semiconductor layer extending under the resin film in the light receiving portion; and an electrode pad on the second electrode connecting portion. And a first conductive semiconductor layer in the first electrode connection portion. A groove for electrically separating the first conductive type semiconductor layer in the light receiving portion, and the first conductive layer is formed under the second wiring over the entire extension region of the second wiring. A type semiconductor layer is provided. According to the semiconductor light receiving element of the present invention, parasitic capacitance can be reduced and disconnection of wiring can be suppressed.

  The resin film may have a structure in which the groove is embedded. The groove may be configured to surround the first electrode connecting portion.

  According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor light-receiving element having a laminated structure including a first conductive semiconductor layer and a second conductive semiconductor layer opposite to the first conductive semiconductor layer on a semi-insulating substrate. Forming a mesa-shaped light receiving portion, a mesa-shaped first electrode connecting portion, and a mesa-shaped second electrode connecting portion, and etching the multilayer structure; and the first electrode connection An opening having a pattern for electrically separating the first conductive semiconductor layer in the light receiving portion from the first conductive semiconductor layer in the light receiving portion, and a region between the second electrode connecting portion and the light receiving portion Forming a mask layer having a pattern covering the first conductive type semiconductor layer, forming a groove by etching the first conductive type semiconductor layer exposed from the mask layer, In the receiver Connected to the first conductive type semiconductor layer, extends on the first conductive type semiconductor layer between the light receiving portion and the second electrode connecting portion, and is drawn onto the second electrode connecting portion. A step of forming a second wiring, a step of embedding a resin film between the first electrode connection portion and the light receiving portion, and one end connected to the second conductive semiconductor layer in the light receiving portion, A step of forming a first wiring extending on the resin film and drawn on the first electrode connection portion; and an electrode pad connected to the first wiring on the first electrode connection portion. And forming an electrode pad connected to the second wiring on the second electrode connection portion. According to the method for manufacturing a semiconductor light receiving element according to the present invention, parasitic capacitance can be reduced and disconnection of wiring can be suppressed.

  ADVANTAGE OF THE INVENTION According to this invention, a parasitic capacitance can be reduced and the semiconductor light receiving element which can suppress the disconnection of wiring, and its manufacturing method can be provided.

FIG. 1A is an example of a top view of a semiconductor light receiving element according to a comparative example, and FIG. 1B is an example of a bottom view of a semiconductor light receiving element according to a comparative example. FIG. 2 is an example of an AA cross-sectional view of FIG. FIG. 3 is an example of a top view showing a region where a groove is provided in the semiconductor light receiving element according to the comparative example. FIG. 4 is an example of a cross-sectional view of the semiconductor light receiving element according to the first embodiment. FIG. 5 is an example of a top view illustrating a region in which a groove is provided in the semiconductor light receiving element according to the first embodiment. FIG. 6A to FIG. 6C are examples of cross-sectional views (part 1) illustrating the method for manufacturing the semiconductor light receiving element according to the first embodiment. FIG. 7A to FIG. 7C are examples of cross-sectional views (No. 2) illustrating the method for manufacturing the semiconductor light receiving element according to the first embodiment. FIG. 8 is an example of a top view illustrating a region in which a groove is provided in the semiconductor light receiving element according to the first modification of the first embodiment.

  First, a semiconductor light receiving element according to a comparative example will be described. The comparative example is an example of a back-illuminated semiconductor light receiving element. FIG. 1A is an example of a top view of a semiconductor light receiving element according to a comparative example, and FIG. 1B is an example of a bottom view of a semiconductor light receiving element according to a comparative example. FIG. 2 is an example of an AA cross-sectional view of FIG. As shown in FIG. 1A to FIG. 2, in the semiconductor light receiving element according to the comparative example, a mesa-shaped light receiving unit 20 is provided on, for example, an InP substrate 10. The light receiving unit 20 is provided, for example, in the central portion of the InP substrate 10 having a substantially square shape when viewed from above. The light receiving unit 20 has a stacked structure in which an n-type InP layer 22, a non-doped InGaAs layer 24, and a p-type InP layer 26 are stacked on the InP substrate 10 in this order. The non-doped InGaAs layer 24 functions as a light absorption layer.

  Four mesa electrode connection portions 30 a to 30 d are provided adjacent to the light receiving portion 20 on the InP substrate 10. The four electrode connection portions 30a to 30d are provided at the positions of the apexes of a substantially square centered on the light receiving portion 20, for example. The electrode connection portions 30a to 30d have a stacked structure in which an n-type InP layer 32, a non-doped InGaAs layer 34, and a p-type InP layer 36 are stacked on the InP substrate 10 in this order. That is, the electrode connection portions 30a to 30d and the light receiving portion 20 have a stacked structure made of the same material. In addition, although the electrode connection parts 30a-30d have the same laminated structure as the light-receiving part 20, they do not have a function as a light-receiving part which receives incident light.

  A lens 12 is provided on the lower surface of the InP substrate 10 at a position facing the light receiving unit 20. Thereby, light incident from the lower surface side of the InP substrate 10 and condensed by the lens 12 enters the light receiving unit 20. The non-doped InGaAs layer 24 absorbs incident light. The absorption of light by the non-doped InGaAs layer 24 not only absorbs light from the InP substrate 10 side toward the non-doped InGaAs layer 24 but also passes through the non-doped InGaAs layer 24 and is reflected by a p-side wiring 44 described later. Absorb. For this reason, the light absorption efficiency is high.

  A groove 38 dug up to a part of the InP substrate 10 is provided around the light receiving unit 20 and the electrode connection units 30a to 30d. FIG. 3 is an example of a top view showing a region where the groove 38 is provided in the comparative example. In FIG. 3, the area | region in which the groove | channel 38 was provided is represented by mesh shape. By this groove 38, the n-type InP layer 22 in the light receiving unit 20 and the n-type InP layer 32 in the electrode connection units 30a to 30d are separated from each other.

  Between the light receiving unit 20 and the electrode connecting unit 30a, from the side surface of the light receiving unit 20 to the side surface of the electrode connecting unit 30a along the bottom surface of the groove 38 (that is, the upper surface of the InP substrate 10), for example, from a silicon nitride film A first insulating film 14 is provided. The thickness of the first insulating film 14 is, for example, 0.2 μm. A resin film 16 made of, for example, a polymer is provided so as to be buried in the groove 38 between the light receiving unit 20 and the electrode connecting unit 30a. The width of the first insulating film 14 is 20 μm, for example. The width of the resin film 16 is, for example, 10 μm.

  A second insulating film 18 made of, for example, a silicon nitride film is provided on the entire InP substrate 10 such as the upper surface and side surfaces of the light receiving unit 20 and the electrode connection units 30a to 30d and the upper surface of the resin film 16. The thickness of the second insulating film 18 is, for example, 0.2 μm. Thereby, since the upper and lower sides of the resin film 16 are covered with the first insulating film 14 and the second insulating film 18, moisture resistance and adhesion are improved.

  In the second insulating film 18, a ring-shaped opening is formed on the upper surface of the light receiving unit 20. In this ring-shaped opening, a p-electrode wiring 42 is embedded in contact with the upper surface of the p-type InP layer 26. The inner diameter of the ring-shaped p electrode wiring 42 is, for example, 34 μm, and the ring width is, for example, 5 μm. The p-electrode wiring 42 is provided so as to extend on the second insulating film 18 from the light receiving unit 20 to the electrode connecting unit 30 a via the resin film 16. For example, the p-electrode wiring 42 is a stacked body in which Ti, Pt, and Au are sequentially stacked from the second insulating film 18 side. The thickness of Ti is, for example, 0.1 μm. The thickness of Pt and Au is, for example, 0.2 μm.

  A p-side wiring 44 is provided which covers the second insulating film 18 in the inner region of the ring-shaped p-electrode wiring 42 on the light-receiving portion 20 and extends to the electrode connection portion 30 a in contact with the upper surface of the p-electrode wiring 42. ing. As described above, the p-side wiring 44 functions as a reflection film that reflects light incident from the lower surface side of the InP substrate 10. The p-side wiring 44 is made of, for example, Au and has a thickness of 0.4 μm.

  A p-electrode pad 40 is provided on the electrode connection portion 30 a and in contact with the upper surface of the p-side wiring 44. The p electrode pad 40 is made of, for example, Au plating and has a thickness of 3 μm. The p-electrode pad 40 is electrically connected to the p-type InP layer 26 via the p-side wiring 44 and the p-electrode wiring 42.

  An arc-shaped opening centered on the light receiving portion 20 is provided in the second insulating film 18 so as to include between the light receiving portion 20 and the electrode connection portions 30b to 30d. An ohmic electrode 52 in contact with the n-type InP layer 22 is buried in this opening. The ohmic electrode 52 is made of AuGe as an example. The thickness of the ohmic electrode 52 is, for example, 0.2 μm. An n-electrode wiring 54 is provided in contact with the upper surface of the ohmic electrode 52. The n-electrode wiring 54 is provided so as to cover the ohmic electrode 52 and has the same arc shape as that of the ohmic electrode 52. For example, the n-electrode wiring 54 is a stacked body made of the same material as the p-electrode wiring 42. The n-electrode wiring 54 is provided so as to extend on the second insulating film 18 from the ohmic electrode 52 to the electrode connection portions 30b to 30d.

  An n-side wiring 56 is provided in contact with the upper surface of the n-electrode wiring 54. Similarly to the n-electrode wiring 54, the n-side wiring 56 has the same arc shape as that of the ohmic electrode 52, and is provided to extend from the ohmic electrode 52 to the electrode connection portions 30 b to 30 d. As an example, the n-side wiring 56 is made of the same material as the p-side wiring 44.

  An n electrode pad 50 is provided on the electrode connection portions 30 b to 30 d and in contact with the upper surface of the n-side wiring 56. For example, the n-electrode pad 50 is made of the same material as the p-electrode pad 40. The n-electrode pad 50 is electrically connected to the n-type InP layer 22 through the n-side wiring 56, the n-electrode wiring 54, and the ohmic electrode 52.

  According to the comparative example, as shown in FIGS. 2 and 3, the groove 38 from which the n-type InP layer is removed is formed around the electrode connection portion 30 a, and the n-type InP layer 32 and the light receiving portion 20 in the electrode connection portion 30 a are formed. The n-type InP layer 22 is electrically separated. Thereby, the parasitic capacitance between the p-electrode wiring 42 and the n-type InP layer can be reduced. In forming the groove 38, in consideration of in-plane uniformity, the periphery of the light receiving portion 20 and the electrode connecting portions 30a to 30d is etched. In this case, the groove 38 is also formed between the light receiving unit 20 and the electrode connection units 30b to 30d. If the groove 38 is formed between the light receiving unit 20 and the electrode connection units 30 b to 30 d, the n electrode wiring 54 and the n side wiring 56 are likely to be disconnected due to the step of the groove 38. An embodiment that can reduce the parasitic capacitance and suppress the disconnection of the wiring will be described below.

  FIG. 4 is an example of a cross-sectional view of the semiconductor light receiving element according to the first embodiment. In addition, Example 1 is also an example of a back-illuminated type semiconductor light receiving element as in the comparative example, and the top view and the bottom view are the same as FIGS. 1A and 1B of the comparative example. Illustration is omitted. As illustrated in FIG. 4, in the semiconductor light receiving element according to the first embodiment, the n-type InP layer 22 a in the light receiving unit 20 extends from the light receiving unit 20 to the electrode connection units 30 b to 30 d. That is, no groove is formed in the n-type InP layer 22a between the light receiving unit 20 and the electrode connection units 30b to 30d, and the upper surface of the n-type InP layer 22a is flat. The n-electrode wiring 54 and the n-side wiring 56 are provided so as to extend on the n-type InP layer 22a extending from the light receiving unit 20 to the electrode connection units 30b to 30d.

  On the other hand, the n-type InP layer 22a in the light receiving unit 20 and the n-type InP layer 32 in the electrode connecting unit 30a are separated by a groove 38a between the light receiving unit 20 and the electrode connecting unit 30a. Are also separated. Note that the n-type InP layer 22a in the light receiving portion 20 extends under the resin film 16 embedded between the light receiving portion 20 and the electrode connection portion 30a. Here, the area | region in which the groove | channel 38a was provided is demonstrated using FIG. FIG. 5 is an example of a top view showing a region where the groove 38a is provided in the first embodiment. As shown in FIG. 5, the groove 38a is only provided so as to surround the electrode connection portion 30a, and is not provided around the electrode connection portions 30b to 30d.

  Since the other configuration of the semiconductor light receiving element according to the first embodiment is the same as that of FIG. 2 of the comparative example, the description thereof is omitted.

  Next, a method for manufacturing the semiconductor light receiving element according to the first embodiment will be described. FIG. 6A to FIG. 7C are examples of cross-sectional views illustrating the method for manufacturing the semiconductor light receiving element according to the first embodiment. As shown in FIG. 6A, an n-type InP layer, a non-doped InGaAs layer, and a p-type InP layer are formed in this order on the InP substrate 10 to form a stacked structure. For example, MOCVD (metal organic chemical vapor deposition) can be used to form each semiconductor layer. Etching is performed on the p-type InP layer, the non-doped InGaAs layer, and a part of the n-type InP layer using the mask layer formed on the p-type InP layer. For the etching process, for example, a dry etching method such as an RIE (reactive ion etching) method can be used. Alternatively, a wet etching method may be used. As a result, the mesa-shaped light receiving portion 20 having the n-type InP layer 22a, the non-doped InGaAs layer 24, and the p-type InP layer 26 is formed. Mesa-shaped electrode connection portions 30a to 30d having an n-type InP layer 22a, a non-doped InGaAs layer 34, and a p-type InP layer 36 are formed. At this stage, the n-type InP layer 22a extends from the light receiving portion 20 to the electrode connection portions 30a to 30d, and the n-type InP layers 22a of the light receiving portion 20 and the electrode connection portions 30a to 30d are connected to each other. That is, the n-type InP layer 22a remains around the light receiving unit 20 and the electrode connection units 30a to 30d.

  As shown in FIG. 6B, an opening having a pattern for electrically separating the n-type InP layer 22a in the electrode connecting portion 30a from the n-type InP layer 22a in the light receiving portion 20 is provided, and the electrode connecting portions 30b to 30d. A mask layer 60 having a pattern covering the n-type InP 22a in a region between the light receiving unit 20 and the light receiving unit 20 is formed. The mask layer 60 is made of a resist layer, for example. Using the mask layer 60 as a mask, the n-type InP layer 22a exposed from the mask layer 60 and a part of the InP substrate 10 are etched. For the etching process, for example, a dry etching method such as an RIE method can be used. Alternatively, a wet etching method may be used. Thereby, the groove 38a dug up to the InP substrate 10 is formed so as to surround the electrode connection portion 30a. By this groove 38 a, the n-type InP layer in the electrode connection part 30 a is separated from the n-type InP layer 22 a in the light receiving part 20 to become the n-type InP layer 32.

  As shown in FIG. 6C, a first insulating film 14 is deposited on the entire InP substrate 10. For the deposition of the first insulating film 14, for example, a plasma CVD method can be used. Thereafter, the resin film 16 is embedded between the light receiving unit 20 and the electrode connecting unit 30a. After embedding the resin film 16, the first insulating film 14 is etched using a mask layer formed on the resin film 16 and the first insulating film 14. For the etching treatment, a dry etching method or a wet etching method can be used. Thereby, the first insulating film 14 deposited in the region other than the region where the resin film 16 is formed and the region in the vicinity thereof is removed.

  As shown in FIG. 7A, the second insulating film 18 is deposited on the entire InP substrate 10. For the deposition of the second insulating film 18, for example, a plasma CVD method can be used. Thereafter, using the mask layer formed on the second insulating film 18, the second insulating film 18 deposited between the light receiving portion 20 and the electrode connecting portions 30b to 30d is etched to form an opening. To do. For the etching treatment, a dry etching method or a wet etching method can be used. An ohmic electrode 52 in contact with the n-type InP layer 22a is formed in this opening by using, for example, a vapor deposition method and a lift-off method.

  As shown in FIG. 7B, a mask layer formed on the second insulating film 18 is used to etch the second insulating film 18 deposited on the upper surface of the light receiving unit 20 to form a ring-shaped opening. Form. For the etching treatment, a dry etching method or a wet etching method can be used. Thereafter, for example, using a vapor deposition method and a lift-off method, the ring-shaped opening is embedded, one end is connected to the p-type InP layer 26 in the light receiving unit 20, and the electrode connection unit 30 a is passed through the resin film 16. A p-electrode wiring 42 to be drawn is formed. At the same time, one end is in contact with the upper surface of the ohmic electrode 52 so that it is connected to the n-type InP layer 22a in the light-receiving unit 20 and extends on the n-type InP layer 22a between the light-receiving unit 20 and the electrode connection units 30b to 30d. Thus, the n-electrode wiring 54 drawn out on the electrode connection portions 30b to 30d is formed.

  As shown in FIG. 7C, the second insulating film 18 in the inner region of the ring-shaped p electrode wiring 42 on the light receiving unit 20 is covered by, for example, sputtering, and is in contact with the upper surface of the p electrode wiring 42. However, the p-side wiring 44 is formed on the electrode connection portion 30a. At the same time, an n-side wiring 56 is formed to be drawn on the electrode connection portions 30b to 30d while being in contact with the upper surface of the n-electrode wiring 54. Thereafter, using, for example, an electrolytic plating method, the p electrode pad 40 in contact with the upper surface of the p side wiring 44 on the electrode connection portion 30a and the n electrode pad 50 in contact with the upper surface of the n side wiring 56 on the electrode connection portions 30b to 30d. And at the same time. Finally, the lens 12 is formed on the lower surface of the InP substrate 10 facing the light receiving unit 20 to complete the semiconductor light receiving element according to the first embodiment shown in FIG.

  According to the first embodiment, as illustrated in FIG. 4, the n-type InP layer 22 a (first conductive semiconductor layer) in the light receiving unit 20 is connected to the electrode connecting units 30 b to 30 d (second electrode connecting unit) from the light receiving unit 20. It extends over to. An n electrode wiring 54 and an n-side wiring 56 (second wiring) that electrically connect the n electrode pad 50 and the n-type InP layer 22a in the light receiving unit 20 extend from the light receiving unit 20 to the electrode connection units 30b to 30d. It extends over the extending n-type InP layer 22a. That is, the n-type InP layer 22a is provided under the n-electrode wiring 54 and the n-side wiring 56 over the entire region where these wirings extend. According to this, since the n-type InP layer 22a between the light receiving unit 20 and the electrode connection units 30b to 30d is not removed, it is possible to prevent the n electrode wiring 54 and the n side wiring 56 from being disconnected. Note that since the n-electrode wiring 54 and the n-type InP layer 22a have the same potential, there is no problem even if parasitic capacitance occurs.

  4 and 5, the n-type InP layer 22a in the light receiving unit 20 is separated from the light receiving unit 20 to the electrode connection unit 30a (first electrode connection unit) by a groove 38a. That is, a groove 38a for electrically separating the n-type InP layer 32 (first conductive type semiconductor layer) in the electrode connection portion 30a and the n-type InP layer 22a in the light receiving portion 20 is provided. Thereby, the parasitic capacitance between the p-electrode wiring 42 and the n-type InP layer can be reduced. Further, the p-electrode wiring 42 and the p-side wiring 44 (first wiring) for electrically connecting the p-electrode pad 40 and the p-type InP layer 26 (second conductivity type semiconductor layer) in the light-receiving unit 20 are provided in the light-receiving unit 20. On the resin film 16 embedded between the electrode connecting portion 30a and the electrode connecting portion 30a. Thereby, since the step of the groove 38a can be absorbed by the resin film 16, it is possible to suppress disconnection of the p-electrode wiring 42 and the p-side wiring 44.

  The upper surface of the n-type InP layer 22a extending from the light receiving unit 20 to the electrode connection units 30b to 30d is preferably a flat surface. Thereby, disconnection of the n-electrode wiring 54 and the n-side wiring 56 can be further suppressed. In addition, the resin film 16 is provided so as to bury the groove 38a in order to absorb the level difference of the groove 38a between the light receiving portion 20 and the electrode connecting portion 30a and suppress the disconnection of the p-electrode wiring 42 and the p-side wiring 44. It is preferable that

  The region where the groove 38a is formed is not limited to the region shown in FIG. For example, the case of the modification 1 of Example 1 shown in FIG. 8 may be sufficient. FIG. 8 is an example of a top view showing a region where the groove 38b is provided in the first modification of the first embodiment. As shown in FIG. 8, the groove 38b may have a ring shape surrounding the electrode connecting portion 30a. As shown in FIGS. 5 and 8, it is preferable that the groove surrounds the periphery of the electrode connecting portion 30a. This is because, if the n-type InP layer 32 in the electrode connection portion 30a and the n-type InP layer 22a in the light receiving portion 20 are partially connected, there is a parasitic capacitance between the p-electrode wiring 42 and the n-type InP layer. This is because it occurs.

  The resin film 16 embedded between the light receiving unit 20 and the electrode connection unit 30a reduces the parasitic capacitance through the resin film 16 between the p-electrode wiring 42 and the n-type InP layer. The case where it consists of resin which has is preferable.

  The light receiving unit 20 is illustrated as an example of a pin photodiode in which an n-type InP layer 22a, a non-doped InGaAs layer 24, and a p-type InP layer 26 are sequentially stacked, but is not limited thereto. A pn junction diode type photodiode in which an n-type semiconductor layer and a p-type semiconductor layer are stacked may be used. Moreover, the material of each semiconductor layer which comprises the light-receiving part 20 is not limited to said material, You may use another material. Further, a semi-insulating substrate other than the InP substrate 10 may be used.

  In the first embodiment, the case where the first conductivity type is n-type and the second conductivity type is p-type is shown as an example, but in the opposite case, the first conductivity type is p-type and the second conductivity type is second-conductivity. The type may be n-type. In the first embodiment, the case of a back-illuminated semiconductor light receiving element has been described as an example. However, a front-illuminated semiconductor light receiving element may be used.

  Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. It can be changed.

DESCRIPTION OF SYMBOLS 10 InP board | substrate 12 Lens 14 1st insulating film 16 Resin film 18 2nd insulating film 20 Light-receiving part 22, 22a n-type InP layer 24 Non-doped InGaAs layer 26 p-type InP layer 30a-30d Electrode connection part 32 n-type InP layer 34 Non-doped InGaAs layer 36 p-type InP layer 38, 38a, 38b groove 40 p electrode pad 42 p electrode wiring 44 p side wiring 50 n electrode pad 52 ohmic electrode 54 n electrode wiring 56 n side wiring 60 mask layer

Claims (4)

A mesa-shaped light receiving portion provided on a semi-insulating substrate and having a stacked structure including a first conductive semiconductor layer and a second conductive semiconductor layer opposite to the first conductive semiconductor layer;
A mesa-shaped first electrode connecting portion and a mesa-shaped second electrode connecting portion provided on the semi-insulating substrate and including the same laminated structure as the light receiving portion;
A resin film embedded between the first electrode connection portion and the light receiving portion;
A first wiring that extends over the resin film and electrically connects the electrode pad on the first electrode connecting portion and the second conductive semiconductor layer in the light receiving portion;
A second wiring for electrically connecting the first conductive semiconductor layer in the light receiving portion and the electrode pad on the second electrode connecting portion;
A groove for electrically separating the first conductive semiconductor layer in the first electrode connection portion and the first conductive semiconductor layer in the light receiving portion;
The first conductive type semiconductor layer is provided under the second wiring over the entire extension region of the second wiring,
The resin film is provided to extend between the light receiving portion and the first electrode connecting portion under the first wiring extending between the light receiving portion and the first electrode connecting portion, A semiconductor light receiving element having a width narrower than a mesa diameter of the first electrode connecting portion .   2. The semiconductor light receiving element according to claim 1, wherein the resin film fills the groove.   The semiconductor light receiving element according to claim 1, wherein the groove surrounds the periphery of the first electrode connecting portion. Forming a laminated structure including a first conductive semiconductor layer and a second conductive semiconductor layer opposite to the first conductive semiconductor layer on a semi-insulating substrate;
Etching the laminated structure to form a mesa-shaped light receiving portion, a mesa-shaped first electrode connection portion, and a mesa-shaped second electrode connection portion;
An opening having a pattern for electrically separating the first conductive semiconductor layer in the first electrode connection portion from the first conductive semiconductor layer in the light receiving portion; and the second electrode connection portion and the light receiving portion. Forming a mask layer having a pattern covering the first conductive type semiconductor layer in a region between
Forming a groove by etching the first conductive semiconductor layer exposed from the mask layer;
One end is connected to the first conductive type semiconductor layer in the light receiving part, and extends on the first conductive type semiconductor layer between the light receiving part and the second electrode connecting part, and the second electrode connection Forming a second wiring drawn on the part;
Embedding a resin film between the first electrode connecting portion and the light receiving portion;
Forming a first wiring having one end connected to the second conductive type semiconductor layer in the light receiving portion, extending on the resin film, and drawn on the first electrode connecting portion;
Forming an electrode pad connected to the first wiring on the first electrode connection portion, and forming an electrode pad connected to the second wiring on the second electrode connection portion,
The resin film is provided to extend between the light receiving portion and the first electrode connecting portion under the first wiring extending between the light receiving portion and the first electrode connecting portion, A method of manufacturing a semiconductor light receiving element, wherein the width is narrower than a mesa diameter of the first electrode connection portion .

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