JP6068805B2 - プロトタイプシステムにおける汎用的な可制御性及び可観測性のための方法及び装置 - Google Patents
プロトタイプシステムにおける汎用的な可制御性及び可観測性のための方法及び装置 Download PDFInfo
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- JP6068805B2 JP6068805B2 JP2012026121A JP2012026121A JP6068805B2 JP 6068805 B2 JP6068805 B2 JP 6068805B2 JP 2012026121 A JP2012026121 A JP 2012026121A JP 2012026121 A JP2012026121 A JP 2012026121A JP 6068805 B2 JP6068805 B2 JP 6068805B2
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/025,809 | 2011-02-11 | ||
| US13/025,809 US8281280B2 (en) | 2010-02-12 | 2011-02-11 | Method and apparatus for versatile controllability and observability in prototype system |
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| Publication Number | Publication Date |
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| JP2012168946A JP2012168946A (ja) | 2012-09-06 |
| JP2012168946A5 JP2012168946A5 (https=) | 2016-09-08 |
| JP6068805B2 true JP6068805B2 (ja) | 2017-01-25 |
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| JP2012026121A Active JP6068805B2 (ja) | 2011-02-11 | 2012-02-09 | プロトタイプシステムにおける汎用的な可制御性及び可観測性のための方法及び装置 |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9935638B1 (en) * | 2017-06-21 | 2018-04-03 | Intel Corporation | Validating an image for a reconfigurable device |
| CN115618773B (zh) * | 2022-09-21 | 2024-10-01 | 芯启源(上海)半导体科技有限公司 | 可SerDes接口信号识别的FPGA原型验证平台 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2000163456A (ja) * | 1998-11-25 | 2000-06-16 | Hitachi Ltd | 論理検証方法 |
| US8099273B2 (en) * | 2003-06-05 | 2012-01-17 | Mentor Graphics Corporation | Compression of emulation trace data |
| JP4890086B2 (ja) * | 2006-04-21 | 2012-03-07 | アオイ電子株式会社 | 回路検証装置及び回路検証方法 |
| US8412990B2 (en) * | 2007-06-27 | 2013-04-02 | Tabula, Inc. | Dynamically tracking data values in a configurable IC |
| JP2009031933A (ja) * | 2007-07-25 | 2009-02-12 | S2C Inc | スケーラブル再構成可能型プロトタイプシステムと方法 |
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| JP2012168946A (ja) | 2012-09-06 |
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