JP2012168946A5 - - Google Patents
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- JP2012168946A5 JP2012168946A5 JP2012026121A JP2012026121A JP2012168946A5 JP 2012168946 A5 JP2012168946 A5 JP 2012168946A5 JP 2012026121 A JP2012026121 A JP 2012026121A JP 2012026121 A JP2012026121 A JP 2012026121A JP 2012168946 A5 JP2012168946 A5 JP 2012168946A5
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- 238000012795 verification Methods 0.000 description 58
- 238000013461 design Methods 0.000 description 38
- 238000012360 testing method Methods 0.000 description 26
- 238000000034 method Methods 0.000 description 19
- 238000004891 communication Methods 0.000 description 18
- 238000012942 design verification Methods 0.000 description 12
- 238000010586 diagram Methods 0.000 description 10
- 239000000523 sample Substances 0.000 description 10
- 230000008859 change Effects 0.000 description 9
- 230000008569 process Effects 0.000 description 8
- 238000012545 processing Methods 0.000 description 8
- 238000004088 simulation Methods 0.000 description 6
- 230000001419 dependent effect Effects 0.000 description 4
- 230000018109 developmental process Effects 0.000 description 4
- 230000006870 function Effects 0.000 description 4
- 230000014509 gene expression Effects 0.000 description 4
- 230000004044 response Effects 0.000 description 4
- 238000005070 sampling Methods 0.000 description 4
- 238000013459 approach Methods 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 238000010998 test method Methods 0.000 description 3
- 238000010200 validation analysis Methods 0.000 description 3
- 238000004590 computer program Methods 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000011218 segmentation Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000012805 post-processing Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 238000003786 synthesis reaction Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/025,809 | 2011-02-11 | ||
| US13/025,809 US8281280B2 (en) | 2010-02-12 | 2011-02-11 | Method and apparatus for versatile controllability and observability in prototype system |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2012168946A JP2012168946A (ja) | 2012-09-06 |
| JP2012168946A5 true JP2012168946A5 (https=) | 2016-09-08 |
| JP6068805B2 JP6068805B2 (ja) | 2017-01-25 |
Family
ID=46981168
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2012026121A Active JP6068805B2 (ja) | 2011-02-11 | 2012-02-09 | プロトタイプシステムにおける汎用的な可制御性及び可観測性のための方法及び装置 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP6068805B2 (https=) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9935638B1 (en) * | 2017-06-21 | 2018-04-03 | Intel Corporation | Validating an image for a reconfigurable device |
| CN115618773B (zh) * | 2022-09-21 | 2024-10-01 | 芯启源(上海)半导体科技有限公司 | 可SerDes接口信号识别的FPGA原型验证平台 |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000163456A (ja) * | 1998-11-25 | 2000-06-16 | Hitachi Ltd | 論理検証方法 |
| US8099273B2 (en) * | 2003-06-05 | 2012-01-17 | Mentor Graphics Corporation | Compression of emulation trace data |
| JP4890086B2 (ja) * | 2006-04-21 | 2012-03-07 | アオイ電子株式会社 | 回路検証装置及び回路検証方法 |
| US8412990B2 (en) * | 2007-06-27 | 2013-04-02 | Tabula, Inc. | Dynamically tracking data values in a configurable IC |
| JP2009031933A (ja) * | 2007-07-25 | 2009-02-12 | S2C Inc | スケーラブル再構成可能型プロトタイプシステムと方法 |
-
2012
- 2012-02-09 JP JP2012026121A patent/JP6068805B2/ja active Active
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