JP6064977B2 - Silicon carbide semiconductor device - Google Patents

Description

  The present invention relates to a silicon carbide semiconductor device.

  Conventionally, switching elements such as IGBTs (Insulated Gate Bipolar Transistors) and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) formed of silicon (Si) have been used in power electronics equipment, but they have superior physical properties compared to silicon. Development of switching elements formed of silicon carbide (SiC) having a high concentration has been actively conducted.

  Examples of MOSFETs formed of silicon carbide include planar MOSFETs and trench gate MOSFETs that are vertical MOSFETs. In a planar MOSFET, a gate insulating film is formed on a drift layer, a base region, and a source region exposed between source regions (see, for example, Patent Document 1).

  On the other hand, a trench gate type MOSFET is formed by forming a trench as a recess in a silicon carbide layer and forming a gate in the trench. Here, the trench is formed such that the side surface of the trench is substantially perpendicular to the surface of the silicon carbide layer, and a gate insulating film is formed on the side surface and the bottom surface of the trench. Therefore, the source region and the gate insulating film are in contact with each other on the side surface of the trench (see, for example, Patent Document 2).

  In these MOSFETs, when a silicon carbide substrate in which the surface orientation of one surface is the (0001) plane is used as the silicon carbide substrate, in the planar MOSFET, the (0001) plane of the drift layer, the base region, and the source region And the gate insulating film are in contact with each other. In the trench gate type MOSFET, the side surface of the trench is substantially (11-20) plane because it is substantially perpendicular to the surface of the silicon carbide substrate, and the (11-20) plane of the source region is in contact with the gate insulating film. To do.

  Further, when a silicon carbide substrate in which the surface orientation of one surface is the (11-20) surface is used, in the planar MOSFET, the (11-20) surface of the drift layer, the base region and the source region, and the gate insulating film And contact.

  Here, the “(0001) plane” is a general term for planes perpendicular to the c-axis of silicon carbide. The (0001) plane (also referred to as “Si plane”) and the (000-1) plane (“c plane”). Is also called). The “(11-20) plane” is a general term for a plane (also referred to as “a plane”) perpendicular to the a-axis (axis perpendicular to the c-axis) of silicon carbide (parallel to the c-axis) (2 -1-10) plane, (11-20) plane, (-12-10) plane, (-2110) plane, (-1-120) plane, (1-210) plane, and the like.

Japanese Patent Laying-Open No. 2005-116893 (page 4, FIG. 1) JP-A-10-98188 (pages 4-5, FIG. 1)

  In such silicon carbide semiconductor devices, is there a difference between the gate insulating film on the (0001) plane and the gate insulating film on the (11-20) plane in terms of leakage characteristics related to the reliability life of the gate insulating film? How has not been investigated in detail so far. In addition, it has not been examined in detail whether there is a difference in leakage characteristics between a gate insulating film on a high impurity concentration region such as a source region and a gate insulating film on a low impurity concentration region such as a drift layer. It was.

Therefore, a sample (hereinafter referred to as “sample A”) in which a gate insulating film is formed on the (11-20) plane of a silicon carbide layer having an n-type impurity concentration of 10 ¹⁹ cm ⁻³ , and an n-type impurity concentration is A sample (hereinafter referred to as “sample B”) in which a gate insulating film is formed on the (0001) plane of a silicon carbide layer having 10 ¹⁹ cm ⁻³ units, and silicon carbide having an n-type impurity concentration of 10 ¹⁶ cm ⁻³ units For a sample in which a gate insulating film was formed on the (0001) plane of the layer (hereinafter referred to as “sample C”), the leakage characteristics of the gate insulating film were examined. Here, nitrogen is used as the n-type impurity, and the gate insulating film is formed by depositing a silicon dioxide (SiO ₂ ) film by a CVD (Chemical Vapor Deposition) method. Further, nitriding was performed after the gate insulating film was formed.

  FIG. 1 is a graph showing the results of examining the leakage characteristics of the above three samples, and is a graph showing the relationship between the electric field strength applied to the gate insulating film and the leakage current density. In FIG. 1, the horizontal axis indicates the electric field strength applied to the gate insulating film, and the vertical axis indicates the leakage current density. In FIG. 1, A indicates the leak characteristics of sample A, B indicates the leak characteristics of sample B, and C indicates the leak characteristics of sample C.

As can be seen from FIG. 1, in the gate insulating film (sample A) on the (11-20) plane of the silicon carbide layer having an n-type impurity concentration of 10 ¹⁹ cm ⁻³ , an electric field of 2 to 3 MV / cm is applied. Leakage current began to flow when it was applied. In addition, the gate insulating film (sample A) on the (11-20) plane has a leakage current density higher by about two to three digits than the gate insulating film (sample B) on the (0001) plane. It was. Since an electric field of about 3 MV or more is applied to the gate insulating film during the normal ON operation of the gate, the gate insulation on the (11-20) plane of the silicon carbide layer having an n-type impurity concentration of 10 ¹⁹ cm ⁻³ There is a concern that the reliability life of the film may be shortened. Further, from comparison between sample B and sample C, even when the plane orientation of the silicon carbide layer is the same (0001) plane, the leakage current density is higher in the gate insulating film on the silicon carbide layer having a high impurity concentration. I understood that. Here, the gate insulating film is a deposited film formed by a CVD method, but the same result can be obtained even if the gate insulating film is formed of a thermal oxide film.

  From the above results, the gate insulating film on the (11-20) plane has poorer leakage characteristics than the gate insulating film on the (0001) plane of the silicon carbide layer, and on the silicon carbide layer having a higher impurity concentration. It was found that the leakage characteristics of the gate insulating film was worse. In other words, the reliability life of the gate insulating film is limited by the reliability life of the portion formed on the (11-20) plane of the source region where the impurity concentration is set higher than that of the drift layer or the like. I found out.

  The present invention has been made to solve the above-described problem, and a silicon carbide semiconductor capable of further reducing the leakage current density of a gate insulating film formed on the (11-20) plane of a source layer. An object is to provide an apparatus and a method for manufacturing the same.

  A silicon carbide semiconductor device according to the present invention includes a silicon carbide substrate in which the surface orientation of one surface is a (0001) surface, a silicon carbide drift layer of a first conductivity type formed on one surface of the silicon carbide substrate, A second conductivity type silicon carbide base layer formed at a location including the surface of the silicon carbide drift layer; a first conductivity type silicon carbide source layer formed at a location including the surface of the silicon carbide base layer; Formed from the surface of the silicon source layer through the silicon carbide base layer, with a recess having the (11-20) plane as side surfaces, gate insulating films formed on the side and bottom surfaces of the recess, and filling the interior of the recess In addition, the gate electrode formed through the gate insulating film, the source electrode formed in contact with the silicon carbide source layer, and the gate insulating film formed on the bottom surface of the recess are in contact with the silicon carbide drift layer. Formed second conductivity type A gate insulating film protective layer, and the silicon carbide source layer is formed in contact with the first source region formed in contact with the gate insulating film, in contact with the source electrode and apart from the gate insulating film, and has an impurity concentration of A second source region set higher than the impurity concentration of the first source region, and the gate insulating film protective layer includes a first protective region formed in contact with the gate insulating film, and a first protective region. And a second protection region formed in a deep part and having an impurity concentration set higher than the impurity concentration of the first protection region.

  According to the silicon carbide semiconductor device of the present invention, the leakage current density of the gate insulating film formed on the (11-20) plane of the source layer can be further reduced, and the (11-20) plane is defined as the side surface. The reliability of the gate insulating film formed in the recess to be improved can be improved.

It is a graph which shows the relationship between the electric field strength applied to the gate insulating film, and leakage current density. It is sectional drawing which shows the silicon carbide semiconductor device in Embodiment 1 of this invention. It is sectional drawing which shows a part of manufacturing method of the silicon carbide semiconductor device in Embodiment 1 of this invention. It is sectional drawing which shows a part of manufacturing method of the silicon carbide semiconductor device in Embodiment 1 of this invention. It is sectional drawing which shows a part of manufacturing method of the silicon carbide semiconductor device in Embodiment 1 of this invention. It is sectional drawing which shows a part of manufacturing method of the silicon carbide semiconductor device in Embodiment 1 of this invention. It is sectional drawing which shows a part of manufacturing method of the silicon carbide semiconductor device in Embodiment 1 of this invention. It is sectional drawing which shows a part of manufacturing method of the silicon carbide semiconductor device in Embodiment 1 of this invention. It is sectional drawing which shows a part of manufacturing method of the silicon carbide semiconductor device in Embodiment 1 of this invention. It is sectional drawing which shows a part of manufacturing method of the silicon carbide semiconductor device in Embodiment 2 of this invention. It is sectional drawing which shows a part of manufacturing method of the silicon carbide semiconductor device in Embodiment 2 of this invention. It is sectional drawing which shows a part of manufacturing method of the silicon carbide semiconductor device in Embodiment 2 of this invention. It is a graph which shows the relationship between the electric field strength applied to the gate insulating film in Embodiment 2 of this invention, and leakage current density. It is sectional drawing which shows a part of manufacturing method of the silicon carbide semiconductor device in Embodiment 3 of this invention. It is sectional drawing which shows a part of manufacturing method of the silicon carbide semiconductor device in Embodiment 3 of this invention. It is sectional drawing which shows the silicon carbide semiconductor device in Embodiment 4 of this invention. It is sectional drawing which shows a part of manufacturing method of the silicon carbide semiconductor device in Embodiment 4 of this invention. It is the impurity concentration profile of the depth direction of the gate insulating-film protective layer in Embodiment 4 of this invention. It is sectional drawing which shows the silicon carbide semiconductor device in Embodiment 5 of this invention. It is sectional drawing which shows a part of manufacturing method of the silicon carbide semiconductor device in Embodiment 5 of this invention. It is sectional drawing which shows a part of manufacturing method of the silicon carbide semiconductor device in Embodiment 5 of this invention. It is sectional drawing which shows the silicon carbide semiconductor device in Embodiment 5 of this invention.

Embodiment 1 FIG.
First, the structure of silicon carbide semiconductor device 1a in the first embodiment of the present invention will be described. FIG. 2 is a cross sectional view showing silicon carbide semiconductor device 1a according to the first embodiment of the present invention. Here, a trench gate type MOSFET will be described as an example of silicon carbide semiconductor device 1a. In the following description, the n-type is assumed to be the first conductivity type and the p-type is assumed to be the second conductivity type.

  In FIG. 1, n-type silicon carbide drift layer 6 is formed on one surface 3 of n-type silicon carbide substrate 2. Here, the plane orientation of one surface 3 of silicon carbide substrate 2 is the (0001) plane. The “(0001) plane” is a general term for planes of silicon carbide in the c-axis direction, and the (0001) plane (also referred to as “Si plane”) and the (000-1) plane (also referred to as “c plane”). Including.

  A p-type silicon carbide base layer 7 is formed on the surface side of silicon carbide drift layer 6 so as to include the surface of silicon carbide drift layer 6. An n-type silicon carbide source layer 8 is formed on the surface side of silicon carbide base layer 7 so as to include the surface of silicon carbide base layer 7. Silicon carbide source layer 8 includes first source region 11 and second source region 12, and the impurity concentration of first source region 11 is set lower than the impurity concentration of second source region 12.

  Trench 13 that is a recess is formed so as to penetrate silicon carbide base layer 7 and reach silicon carbide drift layer 6 from the surface of silicon carbide source layer 8.

  Since side surface 16 of trench 13 is formed to be perpendicular to one surface 3 of silicon carbide substrate 2, that is, to be perpendicular to the surface of silicon carbide source layer 8, it is a (11-20) surface. Therefore, side surface 16 of trench 13 is formed by (11-20) plane of first source region 11 of silicon carbide source layer 8, silicon carbide base layer 7 and silicon carbide drift layer 6.

  The “(11-20) plane” is a general term for a plane (also referred to as “a plane”) perpendicular to the a-axis (axis perpendicular to the c-axis) of silicon carbide (parallel to the c-axis) (2 -1-10) plane, (11-20) plane, (-12-10) plane, (-2110) plane, (-1-120) plane, (1-210) plane, and the like.

  Bottom surface 17 of trench 13 is a (0001) plane because it is formed in parallel with one surface 3 of silicon carbide substrate 2, that is, in parallel with the surface of silicon carbide drift layer 6. Therefore, bottom surface 17 of trench 13 is formed by the (0001) plane of silicon carbide drift layer 6.

  A gate insulating film 18 is formed on the inner surface of the trench 13, that is, on the side surface 16 and the bottom surface 17. Therefore, the (11-20) plane of first source region 11, silicon carbide base layer 7 and silicon carbide drift layer 6 of silicon carbide source layer 8 is in contact with gate insulating film 18, and (0001) of silicon carbide drift layer 6 is (0001). ) Surface and the gate insulating film 18 come into contact with each other.

  A gate electrode 21 is formed on the gate insulating film 18 so as to fill the inside of the trench 13, and an interlayer insulating film 22 is formed so as to cover the gate electrode 21 from above. On the second source region 12 of the silicon carbide source layer 8, a source electrode 23 is formed in contact with the second source region 12. A drain electrode 27 is formed on the other surface 26 of the silicon carbide substrate 2.

  Next, a method for manufacturing silicon carbide semiconductor device 1a in the first embodiment of the present invention will be described. 3 to 9 are cross sectional views showing a part of the method for manufacturing silicon carbide semiconductor device 1a in the first embodiment of the present invention.

First, a silicon carbide substrate 2 having a plane orientation of one surface 3 of (0001), a 4H polytype, an n-type, and a low resistance is prepared. Then, as shown in FIG. 3, the n-type impurity concentration is, for example, 1 × 10 ¹⁵ to 1 × 10 ¹⁷ cm ⁻³ and 5 to 50 μm on one surface 3 of the silicon carbide substrate 2 by CVD. A thick silicon carbide drift layer 6 is epitaxially grown. The polytype of silicon carbide substrate 2 is not limited to 4H, but may be other types such as 6H and 3C.

  Hereinafter, a process of performing ion implantation will be described. For example, nitrogen, phosphorus, arsenic, or the like is used as an n-type impurity to be ion-implanted, and aluminum, boron, gallium, or the like is used as a p-type impurity.

  Next, as shown in FIG. 4, p-type impurities are ion-implanted from the surface side of silicon carbide drift layer 6 to form p-type silicon carbide base layer 7 at a location including the surface of silicon carbide drift layer 6. To do.

The p-type impurity concentration for ion implantation is 1 × 10 ¹⁷ to 1 × 10 ¹⁹ in order to prevent punch-through in the silicon carbide drift layer 6, the silicon carbide base layer 7, and the silicon carbide source layer 8 when the MOSFET is off. It is assumed that the n-type impurity concentration of silicon carbide drift layer 6 is exceeded in the range of cm ⁻³ . The depth of ion implantation is about 0.5 to 3 μm and does not exceed the thickness of silicon carbide drift layer 6.

  Next, a process of forming silicon carbide source layer 8 at a location including the surface of silicon carbide base layer 7 will be described. First, a mask is formed on the surface of the silicon carbide base layer 7 with a resist, and n-type impurities are ion-implanted from the surface side of the silicon carbide base layer 7. Thereby, first source region 11 of silicon carbide source layer 8 is formed at a location including the surface of silicon carbide base layer 7. FIG. 5 shows a cross-sectional view after removing the resist.

  Next, a mask is formed with a resist on the surface of first source region 11 and silicon carbide base layer 7 of silicon carbide source layer 8, and n-type impurities are ion-implanted. Thereby, second source region 12 of silicon carbide source layer 8 is formed at a location including the surface of silicon carbide base layer 7. That is, as a result, silicon carbide source layer 8 is formed at a location including the surface of silicon carbide base layer 7. A cross-sectional view after removing the resist is shown in FIG.

Here, the n-type impurity concentration for ion implantation exceeds the p-type impurity concentration of the silicon carbide base layer 7 in the range of 1 × 10 ¹⁸ to 1 × 10 ²¹ cm ⁻³ in the second source region 12. To do. Thereby, a good contact with the source electrode 23 is obtained. The impurity concentration of first source region 11 is set to be lower than the impurity concentration of second source region 12 and to exceed the p-type impurity concentration of silicon carbide base layer 7, but the impurity concentration should be as low as possible. It is preferable to set. In addition, the depth of ion implantation of first source region 11 and second source region 12 to be silicon carbide source layer 8 does not exceed the thickness of silicon carbide base layer 7.

  Next, silicon dioxide is deposited by CVD on the surfaces of silicon carbide source layer 8 and silicon carbide base layer 7 to form a mask. Then, by using this mask, the silicon carbide source layer 8, the silicon carbide base layer 7, and the silicon carbide drift layer 6 are anisotropically etched to form a trench 13 that is a recess. A cross-sectional view after removing the silicon dioxide mask is shown in FIG. Note that the etching mask is not limited to silicon dioxide, and a metal film may be formed by vapor deposition or the like, for example.

  The depth of trench 13 is about 0.5 to 3 μm, and is formed so as to penetrate through silicon carbide base layer 7 to the silicon carbide drift layer 6 from the surface of silicon carbide source layer 8. Side surface 16 of trench 13 is perpendicular to one surface 3 of silicon carbide substrate 2, that is, perpendicular to the surface of silicon carbide source layer 8, and bottom surface 17 of the trench is one surface of silicon carbide substrate 2. 3, that is, in parallel with the surface of the silicon carbide drift layer 6. Thereby, side surface 16 of trench 13 is formed by (11-20) plane of first source region 11 of silicon carbide source layer 8, silicon carbide base layer 7 and silicon carbide drift layer 6, and bottom surface 17 of trench 13 is The silicon carbide drift layer 6 is formed of the (0001) plane.

  Next, annealing is performed for 30 seconds to 1 hour in the range of 1300 to 1900 ° C. in an inert gas atmosphere such as argon using a heat treatment apparatus. By this annealing, impurity ions such as aluminum and nitrogen implanted are electrically activated.

  Next, as shown in FIG. 8, the gate insulating film 18 having a desired thickness is formed on the inner surface of the trench 13, that is, the side surface 16 and the bottom surface 17, the silicon carbide source layer 8, and the silicon carbide base layer 7. Form. Since gate insulating film 18 is formed on side surface 16 of trench 13, (11-20) plane of first source region 11 of silicon carbide source layer 8, silicon carbide base layer 7 and silicon carbide drift layer 6, and the gate insulating film 18 will come into contact.

Here, the gate insulating film 18 is formed by depositing a silicon dioxide (SiO ₂ ) film by a CVD method or the like, or by forming a silicon dioxide film by thermally oxidizing the surface of silicon carbide. Note that if nitriding is performed thereafter, SiO ₂ becomes SiON. Therefore, instead of the SiO ₂ film, a SiON film may be directly formed. Further, a multilayer film in which the side in contact with silicon carbide is SiO ₂ or SiON may be used, or a metal oxide film such as Al ₂ O ₃ or SiN may be laminated. That is, the gate insulating film 18 only needs to have silicon oxide as a main component.

Next, using a heat treatment apparatus, heat treatment is performed in an atmosphere containing nitric oxide (NO), dinitrogen monoxide (N ₂ O), or ammonia (NH ₃ ) to perform nitriding treatment. Thereafter, heat treatment may be further performed in an H ₂ O or H ₂ atmosphere.

  Next, as shown in FIG. 9, the gate electrode 21 is formed so as to contact the gate insulating film 18 and fill the inside of the trench 13. The gate electrode 21 is formed by forming and patterning a conductive polycrystalline silicon film by the CVD method.

  Next, an interlayer insulating film 22 is formed by a CVD method so as to cover the gate electrode 21 from above. Then, the interlayer insulating film 22 and the gate insulating film 18 in the region where the source electrode 23 is formed are removed. Then, source electrode 23 is formed so as to be in contact with second source region 12 of silicon carbide source layer 8, and drain electrode 27 is formed on the other surface 26 of silicon carbide substrate 2. The source electrode 23 and the drain electrode 27 are formed by a sputtering method, an evaporation method, or the like, and an aluminum alloy or the like is used as a material. Thus, silicon carbide semiconductor device 1a in the first embodiment of the present invention shown in FIG. 2 is completed.

  In the first embodiment of the present invention, the configuration as described above can suppress the leakage current density of gate insulating film 18 formed on the (11-20) plane of silicon carbide source layer 8 to a lower level. it can. Thereby, there is an effect that the reliability life of the gate insulating film 18 can be extended. Further, the first source region 11 having a low impurity concentration is provided to suppress the leakage current density of the gate insulating film 18 while the second source region 12 having a high impurity concentration is provided. Therefore, the source electrode 23 and the silicon carbide source layer 8 are provided. Good contact can be obtained between the two.

  In manufacturing silicon carbide semiconductor device 1a, silicon carbide substrate 2 in which the plane orientation of one surface 3 is the (0001) plane is often used, and therefore silicon carbide source layer 8 and silicon carbide base layer 7 are used. A trench gate having a trench 13 having a (11-20) plane as a side surface 16 and a (0001) plane of the silicon carbide drift layer 6 as a bottom surface 17 and a gate insulating film 18 formed on the side surface 16 and the bottom surface 17 of the trench 13. This is particularly effective in the type of silicon carbide semiconductor device.

  Further, the gate insulating film 18 can be easily formed by forming the gate insulating film 18 from a thermal oxide film or a deposited film containing silicon oxide as a main component.

  Moreover, the first source region 11 can be easily formed by forming the first source region 11 by ion implantation into the silicon carbide base layer 7. Further, secondly, by forming the source region 12 by ion implantation into the first source region 11, the second source region can be easily formed.

  In the first embodiment of the present invention, the silicon carbide substrate 2 in which the surface orientation of one surface 3 is the (0001) surface is used. However, even if it is not exactly coincident with the (0001) plane, it may be substantially parallel to the (0001) plane.

  Further, side surface 16 of trench 13 was formed to be perpendicular to one surface 3 of silicon carbide substrate 2, that is, perpendicular to the surface of silicon carbide source layer 8. However, it does not have to be strictly vertical, and may be almost vertical. That is, even if the side surface 16 of the trench 13 does not exactly coincide with the (11-20) plane, the effect can be obtained if it is a plane substantially parallel to the (11-20) plane.

  Bottom surface 17 of trench 13 was formed to be parallel to one surface 3 of silicon carbide substrate 2, that is, to be parallel to the surface of silicon carbide drift layer 6, and bottom surface 17 was a (0001) surface. However, the bottom surface 17 of the trench 13 does not need to be strictly parallel or substantially parallel to the one surface 3 of the silicon carbide substrate 2. That is, the bottom surface 17 of the trench 13 does not have to coincide with the (0001) plane and does not need to be a plane. For example, it may be formed with a curved surface.

  Furthermore, in Embodiment 1 of the present invention, the depth of trench 13 is set to a depth at which etching is performed up to a part of silicon carbide drift layer 6, but silicon carbide base layer 7 is removed and just a silicon carbide drift layer is formed. It is good also to the depth to which the surface of 6 is exposed. Therefore, the bottom surface 17 of the trench 13 only needs to be formed by the surface of the n-type silicon carbide drift layer 6, and the side surface 16 of the trench 13 does not include the surface of the silicon carbide drift layer 6 and the first source region 11. Alternatively, it may be formed only on the surface of silicon carbide base layer 7.

  In the first embodiment of the present invention, two regions of the first source region 11 and the second source region 12 having different impurity concentrations are provided in the silicon carbide source layer 8. However, three or more regions having different impurity concentrations may be used. In this case, the impurity concentration in the region in contact with the gate insulating film 18 is made as low as possible, and the impurity concentration in the region in contact with the source electrode 23 is set to a concentration at which a good contact can be obtained.

  In the first embodiment of the present invention, two regions of the first source region 11 and the second source region 12 having clearly different impurity concentrations are provided in the silicon carbide source layer 8. For example, the source electrode is separated from the gate insulating film 18. The impurity concentration may be continuously increased as the value approaches 23.

  In the first embodiment of the present invention, in order to make contact between source electrode 23 and silicon carbide base layer 7, source electrode 23 has both second source region 12 of silicon carbide source layer 8 and silicon carbide base layer 7. It was formed so as to be in contact with. In order to improve the contact between source electrode 23 and silicon carbide base layer 7, a higher concentration p-type base contact region can be provided in a region in contact with source electrode 23 of silicon carbide base layer 7. That's fine. Further, since the device operates as a device even if the source electrode 23 contacts only the second source region 12 and does not contact the silicon carbide base layer 7, it may be so.

  In Embodiment 1 of the present invention, in the step of forming silicon carbide source layer 8 at a location including the surface of silicon carbide base layer 7, a mask is formed on the surface of silicon carbide base layer 7 with a resist to perform ion implantation. Then, the first source region 11 was formed. However, ion implantation may be performed on the entire surface of silicon carbide base layer 7 without forming a mask here. By doing so, the steps for forming the mask can be reduced, and the cost can be reduced.

  In Embodiment 1 of the present invention, in the step of forming silicon carbide source layer 8, first source region 11 is formed first, and then second source region 12 is formed. However, this order may be reversed, and a mask is formed on the surface of the silicon carbide base layer 7. First, ion implantation is performed in a region to be the second source region 12, and then ion implantation is performed in the region to be the first source region 11. It may be injected.

  Further, the first source region 11 may be formed by implanting ions obliquely from the side surface 16 side of the trench 13 after forming the trench 13 and before removing the mask used for forming the trench 13. Good.

  In Embodiment 1 of the present invention, p-type silicon carbide base layer 7 is formed at a location including the surface of silicon carbide drift layer 6 by ion implantation of p-type impurities. However, instead of ion implantation, silicon carbide base layer 7 may be formed by epitaxial growth on the surface of silicon carbide drift layer 6, that is, at a location including the surface of silicon carbide drift layer 6 by the CVD method. . Also in this case, the impurity concentration and thickness of the silicon carbide base layer 7 may be the same as those formed by ion implantation.

  In the first embodiment of the present invention, the n-type is the first conductivity type and the p-type is the second conductivity type. However, conversely, p-type is the first conductivity type and n-type is the second conductivity type.

  In the first embodiment of the present invention, a trench gate type MOSFET using silicon carbide substrate 2 in which the surface orientation of one surface 3 is the (0001) plane has been described as an example of silicon carbide semiconductor device 1a. However, also in the planar MOSFET using the silicon carbide substrate 2 in which the plane orientation of one surface 3 is the (11-20) plane, the gate insulating film 18 is in contact with the (11-20) plane of the silicon carbide source layer 8. Therefore, if the region of the silicon carbide source layer 8 in contact with the gate insulating film 18 is the first source region 11 and the region of the silicon carbide source layer 8 in contact with the source electrode 23 is the second source region 12, the same effect is obtained. Is obtained.

  In the first embodiment of the present invention, the vertical MOSFET has been described. However, the formation of the first source region 11 and the second source region 12 in the silicon carbide source layer 8 can also be applied to the lateral MOSFET, and the same effect. Is obtained. Further, the present invention can be applied not only to MOSFET but also to IGBT, for example.

Embodiment 2. FIG.
10 to 12 are cross sectional views showing a part of the method for manufacturing silicon carbide semiconductor device 1a in the second embodiment of the present invention. 10 with the same reference numerals as in FIG. 5 and those with the same reference numerals as in FIG. 6 in FIG. 11 indicate the same or corresponding components, and the description thereof is omitted. The first embodiment of the present invention is different from the first embodiment in that a portion to be a silicon carbide source layer 8 is formed by epitaxial growth.

  A method for manufacturing silicon carbide semiconductor device 1a in the second embodiment of the present invention will be described. In addition, description is abbreviate | omitted here about the part similar to Embodiment 1 of this invention.

  First, the process up to the step of forming p-type silicon carbide base layer 7 at a location including the surface of silicon carbide drift layer 6 shown in FIG. 4 is the same as in the first embodiment of the present invention. Silicon carbide base layer 7 may be formed by epitaxial growth.

  Next, as shown in FIG. 10, the first source of silicon carbide source layer 8 is epitaxially grown on the surface of silicon carbide base layer 7, that is, at a location including the surface of silicon carbide base layer 7 by the CVD method. Region 11 is formed.

When silicon carbide source layer 8 is formed by ion implantation into silicon carbide base layer 7 as in the first embodiment of the present invention, the lower limit of the impurity concentration of silicon carbide source layer 8 is that of silicon carbide base layer 7. Limited by impurity concentration. However, in Embodiment 2 of the present invention, silicon carbide source layer 8 is formed by epitaxial growth, so that the impurity concentration of first source region 11 of silicon carbide source layer 8 is limited to the impurity concentration of silicon carbide base layer 7. A lower value can be achieved without doing so. For example, it is easy to set to 1 × 10 ¹⁶ cm ⁻³ or less, and it is also possible to set to 10 ¹⁴ cm ⁻³ units.

  Next, a mask is formed on the surface of the first source region 11 of the silicon carbide source layer 8 with a resist, and n-type impurities are ion-implanted. Thereby, second source region 12 of silicon carbide source layer 8 is formed. FIG. 11 shows a cross-sectional view after removing the resist.

  Next, a mask is formed on the surfaces of the first source region 11 and the second source region 12 with a resist, and p-type impurities are ion-implanted. Thereby, base contact region 28 for making contact between source electrode 23 and silicon carbide base layer 7 is formed. A cross-sectional view after removing the resist is shown in FIG.

Here, the p-type impurity concentration for ion implantation exceeds the n-type impurity concentration of the first source region 11 in the range of 1 × 10 ²⁰ to 1 × 10 ²² cm ⁻³ . The depth of ion implantation is set to a depth that exceeds the thickness of the silicon carbide source layer 8 and reaches the silicon carbide base layer 7.

  Next, a step of forming trench 13 is performed, and the subsequent steps are the same as in the first embodiment of the present invention. In the step of forming the source electrode 23, the source electrode 23 is formed on the surfaces of the second source region 12 and the base contact region 28.

  In Embodiment 2 of the present invention, since silicon carbide source layer 8 is formed by epitaxial growth as described above, the impurity concentration of first source region 11 of silicon carbide source layer 8 is changed to the impurity concentration of silicon carbide base layer 7. Without being limited to, it can be set to a lower value. By setting the impurity concentration of first source region 11 to be lower, the leakage current density of gate insulating film 18 formed on the (11-20) plane of silicon carbide source layer 8 can be kept lower. Thereby, there is an effect that the reliability life of the gate insulating film 18 can be further extended.

Next, a sample (hereinafter, “sample D”) in which a gate insulating film is formed on the (11-20) plane of the silicon carbide layer having an n-type impurity concentration of 10 ¹⁶ cm ⁻³ , and an n-type impurity concentration The experimental results of examining the leakage characteristics of the gate insulating film for the sample (sample A) in which the gate insulating film is formed on the (11-20) plane of the silicon carbide layer of 10 ¹⁹ cm ⁻³ are described.

  FIG. 13 is a graph showing the relationship between the electric field strength applied to the gate insulating film and the leakage current density in the second embodiment of the present invention. In FIG. 13, the horizontal axis indicates the electric field strength applied to the gate insulating film, and the vertical axis indicates the leakage current density. In FIG. 13, D indicates the leak characteristics of sample D, and A indicates the leak characteristics of sample A. Note that A in FIG. 13 and A in FIG.

  Here, in each sample, nitrogen is used as an n-type impurity, and the gate insulating film is formed by depositing a silicon dioxide film by a CVD method. Further, nitriding was performed after the gate insulating film was formed.

As can be seen from FIG. 13, in the sample D in which the impurity concentration of the silicon carbide layer is on the order of 10 ¹⁹ cm ⁻³ , the leakage current density is on the order of digits compared to the sample A in which the impurity concentration is on the order of 10 ¹⁶ cm ^−3. It became low. Therefore, it has been further clarified that the lower the impurity concentration of the silicon carbide layer, the lower the leakage current density, that is, the longer the reliability life of the gate insulating film.

  In the second embodiment of the present invention, portions different from the first embodiment of the present invention are described, and descriptions of the same or corresponding portions are omitted.

Embodiment 3 FIG.
14 and 15 are cross sectional views showing a part of a method for manufacturing silicon carbide semiconductor device 1a in the third embodiment of the present invention. 14 and 15, the same reference numerals as those in FIG. 12 denote the same or corresponding components, and the description thereof is omitted. The method of providing the base contact region 28 is different from the second embodiment of the present invention.

  A method for manufacturing silicon carbide semiconductor device 1a in the third embodiment of the present invention will be described. Here, the description of the same parts as in the first and second embodiments of the present invention will be omitted.

  First, the process up to the step of forming second source region 12 of silicon carbide source layer 8 shown in FIG. 11 is the same as in the first and second embodiments of the present invention. That is, here, silicon carbide base layer 7 is formed by epitaxial growth.

  Next, a mask is formed on the surfaces of first source region 11 and second source region 12, and as shown in FIG. 14, the n-type silicon carbide layer is etched so that silicon carbide base layer 7 is exposed. To.

  Next, as shown in FIG. 15, p-type impurities are ion-implanted into the portion where silicon carbide base layer 7 is exposed in the previous step. Thereby, base contact region 28 for making contact between source electrode 23 and silicon carbide base layer 7 is formed.

Here, the p-type impurity concentration for ion implantation exceeds the impurity concentration of silicon carbide base layer 7 in the range of 1 × 10 ²⁰ to 1 × 10 ²² cm ⁻³ . The depth of ion implantation is set to a depth not exceeding the thickness of the silicon carbide base layer 7.

  Next, a step of forming trench 13 is performed, and the subsequent steps are the same as in the first embodiment of the present invention. In the step of forming the source electrode 23, the source electrode 23 is formed on the surfaces of the second source region 12 and the base contact region 28.

  In the third embodiment of the present invention, the same effects as in the second embodiment of the present invention can be obtained by adopting the configuration as described above.

  In the third embodiment of the present invention, portions different from the first and second embodiments of the present invention are described, and descriptions of the same or corresponding portions are omitted.

Embodiment 4 FIG.
FIG. 16 is a cross sectional view showing a silicon carbide semiconductor device 1b according to the fourth embodiment of the present invention. In FIG. 16, the same reference numerals as those in FIG. 2 denote the same or corresponding components, and the description thereof is omitted. In the first embodiment of the present invention, p-type gate insulating film protective layer 31 is formed on silicon carbide drift layer 6 so as to be in contact with the portion formed on bottom surface 17 of trench 13 of gate insulating film 18. The configuration is different.

  The gate insulating film protection layer 31 has a first protection region 32 and a second protection region 33, and the impurity concentration of the first protection region 32 is set lower than the impurity concentration of the second protection region 33. The first protection region 32 is formed so as to be in contact with the gate insulating film 18, and the second protection region 33 is formed in a portion deeper than the first protection region 32.

  In FIG. 16, the gate insulating film protective layer 31 is provided with two regions of the first protective region 32 and the second protective region 33 that are clearly different in impurity concentration. As the process proceeds, the impurity concentration may be continuously increased.

  Next, a method for manufacturing silicon carbide semiconductor device 1b in the fourth embodiment of the present invention will be described. FIG. 17 is a cross sectional view showing a part of the method for manufacturing silicon carbide semiconductor device 1b in the fourth embodiment of the present invention. In addition, description is abbreviate | omitted here about the part similar to Embodiment 1 of this invention.

  First, the process up to forming the trench 13 shown in FIG. 7 is the same as that of the first embodiment of the present invention.

  Next, as shown in FIG. 17, a p-type gate insulating film protective layer 31 is formed. Specifically, the mask used for forming the trench 13 is used without being removed, and p-type impurities are ion-implanted.

  FIG. 18 is an impurity concentration profile in the depth direction of the gate insulating film protective layer 31 according to the fourth embodiment of the present invention. In FIG. 18, the horizontal axis indicates the depth from the surface of silicon carbide drift layer 6, and the vertical axis indicates the impurity concentration. As shown in FIG. 18, by ion implantation, the impurity concentration continuously increases as it proceeds in the depth direction, reaches a peak at a certain point, and has a profile that continuously decreases as it proceeds further in the depth direction. Can do.

  Here, a low impurity concentration region near the surface of the silicon carbide drift layer 6 corresponds to the first protection region 32, and a region near the peak impurity concentration corresponds to the second protection region 33. Therefore, by forming the gate insulating film protection layer 31 by ion implantation, the first protection region 32 and the second protection region 33 can be formed by a single ion implantation process. Here, although the first protection region 32 and the second protection region are formed by a single ion implantation step, they may be formed by separate ion implantation steps.

The impurity concentration for ion implantation is such that the second protective region 33 exceeds the n-type impurity concentration of the silicon carbide drift layer 6 within the range of 1 × 10 ¹⁷ to 1 × 10 ¹⁹ cm ⁻³ . The thickness of the second protection region 33 may be about 0.5 to 1 μm. The impurity concentration of the first protective region 32 can be lowered to 1 × 10 ¹⁷ cm ⁻³ or less, depending on the implantation conditions.

  Next, as in the first embodiment of the present invention, annealing is performed to electrically activate impurity ions such as ion-implanted aluminum and nitrogen.

  Next, thermal oxidation is performed to remove the region that has been ion-implanted into the side surface 16 of the trench 13 by ion implantation when forming the gate insulating film protective layer 31, and then the inner surface of the trench 13 is wetted. Etch. Depending on the ion implantation conditions at the time of forming the gate insulating film protective layer 31, it may be removed by about 50 to 100 nm.

  Next, a step of forming the gate insulating film 18 is performed, and the subsequent steps are the same as in the first embodiment of the present invention.

  In the fourth embodiment of the present invention, the p-type gate insulating film protective layer 31 is formed on the silicon carbide drift layer 6 in contact with the gate insulating film 18 formed on the bottom surface 17 of the trench 13 as described above. As a result, the electric field concentration on the gate insulating film 18 formed on the bottom surface 17 of the trench 13 can be relaxed, and the breakdown voltage can be improved.

  As can be seen from the comparison between sample B and sample C shown in FIG. 1, the gate insulating film 18 formed on the silicon carbide layer having a high impurity concentration has a high leakage current density. Therefore, when the impurity concentration of the gate insulating film protective layer 31 is increased, the leakage current density is increased at the portion of the gate insulating film 18 in contact with the gate insulating film protective layer 31.

  In the fourth embodiment of the present invention, the gate insulating film protective layer 31 includes a first protective region 32 formed in contact with the gate insulating film 18 and a second portion formed deeper than the first protective region 32. A region of the gate insulating film 18 in contact with the gate insulating film protective layer 31 because the impurity concentration of the first protective region 32 is set lower than the impurity concentration of the second protective region 33. The leakage current density can be kept low. Thereby, the reliability life of gate insulating film 18 can be extended, and silicon carbide semiconductor device 1b having a high breakdown voltage and a long life can be obtained.

  Furthermore, the first protection region 32 and the second protection region 33 can be formed by a single ion implantation step, and the number of steps can be reduced.

  In the fourth embodiment of the present invention, portions different from the first embodiment of the present invention are described, and descriptions of the same or corresponding portions are omitted.

Embodiment 5. FIG.
FIG. 19 is a cross sectional view showing a silicon carbide semiconductor device 1c according to the fifth embodiment of the present invention. 19, the same reference numerals as those in FIG. 2 denote the same or corresponding components, and the description thereof is omitted. The first embodiment of the present invention is that the silicon carbide base layer 7 is formed so that the first base region 36 formed in contact with the gate insulating film 18 and the second base formed so as not to contact the gate insulating film 18. And the structure in which the impurity concentration of the first base region 36 is set lower than the impurity concentration of the second base region 37 is different.

  In FIG. 19, two regions of a first base region 36 and a second base region 37 having clearly different impurity concentrations are provided in the silicon carbide base layer 7, but for example, impurities are continuously generated as the distance from the gate insulating film 18 increases. The concentration may be increased.

  Next, a method for manufacturing silicon carbide semiconductor device 1c in the fifth embodiment of the present invention will be described. 20 and 21 are cross sectional views showing a part of the method for manufacturing silicon carbide semiconductor device 1c in the fifth embodiment of the present invention. In addition, description is abbreviate | omitted here about the part similar to Embodiment 1 of this invention.

  First, the process up to the step of forming silicon carbide drift layer 6 shown in FIG. 3 is the same as in the first embodiment of the present invention.

Next, as shown in FIG. 20, p-type impurities are ion-implanted from the surface side of silicon carbide drift layer 6, and the first of p-type silicon carbide base layer 7 is formed at a location including the surface of silicon carbide drift layer 6. Base region 36 is formed. Instead of ion implantation, the first base region 36 of the silicon carbide base layer 7 is epitaxially grown on the surface of the silicon carbide drift layer 6, that is, at a location including the surface of the silicon carbide drift layer 6 by the CVD method. May be formed. Here, the p-type impurity concentration of the first base region 36 is set lower than, for example, 1 × 10 ¹⁷ cm ⁻³ .

Next, a mask is formed on the surface of first base region 36 of silicon carbide base layer 7 with a resist, and p-type impurities are ion-implanted. Thereby, second base region 37 of silicon carbide base layer 7 is formed. FIG. 21 shows a cross-sectional view after removing the resist. The p-type impurity concentration for ion implantation is in the range of 1 × 10 ¹⁷ to 1 × 10 ¹⁹ cm ⁻³ , and the n-type impurity concentration of the silicon carbide drift layer 6 and the p-type impurity concentration of the first base region 36 are set. Exceed.

  Next, a step of forming silicon carbide source layer 8 is performed, and the subsequent steps are the same as in the first and second embodiments of the present invention.

  In the fifth embodiment of the present invention, as described above, the first base region 36 formed in contact with the gate insulating film 18 is formed in the silicon carbide base layer 7 so as not to contact the gate insulating film 18. The second base region 37 is formed, and the impurity concentration of the first base region 36 is set to be lower than the impurity concentration of the second base region 37, so that (11− 20) The leakage current density of the gate insulating film 18 formed on the surface can be further reduced. Thereby, there is an effect that the reliability life of the gate insulating film 18 can be extended.

For example, as shown in the second embodiment of the present invention, when silicon carbide source layer 8 is formed by epitaxial growth, the impurity concentration of silicon carbide source layer 8 is set to a low value without being limited by the impurity concentration of silicon carbide base layer 7. It becomes possible to do. Here, for example, the impurity concentration of the silicon carbide base layer 7 is set to about 1 × 10 ^{17 to} 5 × 10 ¹⁷ cm ⁻³ , and the impurity concentration of the silicon carbide source layer 8 is set to about 1 × 10 ¹⁷ cm ⁻³ . As is the case, when the impurity concentration values of the silicon carbide base layer 7 and the silicon carbide source layer 8 are close, leakage current in the gate insulating film 18 in contact with the silicon carbide base layer 7 becomes a problem. Therefore, the first base region 36 formed in contact with the gate insulating film 18 and the second base region 37 formed not in contact with the gate insulating film 18 are formed in the silicon carbide base layer 7. Is particularly effective when the impurity concentration values of the silicon carbide base layer 7 and the silicon carbide source layer 8 are close.

  In the fifth embodiment of the present invention, portions different from the first embodiment of the present invention are described, and descriptions of the same or corresponding portions are omitted.

Embodiment 6 FIG.
FIG. 22 is a cross sectional view showing a silicon carbide semiconductor device 1d according to the fifth embodiment of the present invention. 22, the same reference numerals as those in FIGS. 2, 16, and 19 denote the same or corresponding components, and the description thereof is omitted. In the first, fourth and fifth embodiments of the present invention, a gate insulating film protective layer 31 having a first protective region 32 and a second protective region 33 is provided, and the first base region 36 and the silicon carbide base layer 7 are provided. The configuration in which the second base region 37 is provided is different.

  Since the method for manufacturing silicon carbide semiconductor device 1d in the sixth embodiment of the present invention is a combination of the first, fourth and fifth embodiments, description thereof will be omitted.

  In the sixth embodiment of the present invention, the effects described in the first, fourth, and fifth embodiments can be obtained by adopting the above-described configuration. Therefore, the lifetime of the gate insulating film 18 can be further extended.

  The first to sixth embodiments of the present invention have been described above. These configurations described in the first to sixth embodiments of the present invention can be combined with each other.

1a to 1d Silicon carbide semiconductor device 2 Silicon carbide substrate 3 One surface of silicon carbide substrate 6 Silicon carbide drift layer 7 Silicon carbide base layer 8 Silicon carbide source layer 11 First source region 12 Second source region 13 Trench 16 Side surface of trench 17 Bottom surface of trench 18 Gate insulating film 23 Source electrode 31 Gate insulating film protective layer 32 First protective region 33 Second protective region 36 First base region 37 Second base region

Claims (9)

A silicon carbide substrate in which the plane orientation of one surface is a (0001) plane;
A silicon carbide drift layer of a first conductivity type formed on the one surface of the silicon carbide substrate;
A second conductivity type silicon carbide base layer formed at a location including the surface of the silicon carbide drift layer;
A silicon carbide source layer of a first conductivity type formed at a location including the surface of the silicon carbide base layer;
A recess formed by penetrating the silicon carbide base layer from the surface of the silicon carbide source layer, and having a (11-20) plane as a side surface;
A gate insulating film formed on the side and bottom of the recess;
A gate electrode formed through the gate insulating film so as to fill the inside of the recess,
A source electrode formed in contact with the silicon carbide source layer;
A gate insulating film protective layer of a second conductivity type formed on the silicon carbide drift layer in contact with the gate insulating film formed on the bottom surface of the recess,
The silicon carbide source layer is
A first source region formed in contact with the gate insulating film;
A second source region that is in contact with the source electrode and is formed away from the gate insulating film and has an impurity concentration set higher than the impurity concentration of the first source region;
The gate insulating film protective layer is
A first protection region formed in contact with the gate insulating film;
A silicon carbide semiconductor device, comprising: a second protection region formed at a deeper position than the first protection region and having an impurity concentration set higher than the impurity concentration of the first protection region.   2. The silicon carbide semiconductor device according to claim 1, wherein an impurity concentration of the first source region is set lower than an impurity concentration of the silicon carbide base layer. The silicon carbide base layer is
A first base region formed in contact with the gate insulating layer and located under the first source region;
A second base region formed apart from the gate insulating film and positioned below the second source region and having an impurity concentration set higher than the impurity concentration of the first base region. The silicon carbide semiconductor device according to claim 1 or 2.   The silicon carbide semiconductor device according to claim 3, wherein a depth of a bottom surface of the first base region is the same as a depth of a bottom surface of the second base region. 5. The second protection region according to claim 1, wherein the second protection region has an impurity concentration of a second conductivity type of 1 × 10 ¹⁷ cm ⁻³ or more and 1 × 10 ¹⁹ cm ⁻³ or less. Silicon carbide semiconductor device.   6. The silicon carbide semiconductor device according to claim 1, wherein a depth of a bottom surface of the first source region is the same as a depth of a bottom surface of the second source region. 7. The first source region according to claim 1, wherein the second source region has a first conductivity type impurity concentration of 1 × 10 ¹⁸ cm ⁻³ or more and 1 × 10 ²¹ cm ⁻³ or less. The silicon carbide semiconductor device described in 1. The silicon carbide semiconductor device according to any one of claims 1 to 7, wherein the silicon carbide source layer includes three or more regions having different impurity concentrations.   The silicon carbide semiconductor device according to claim 1, wherein the gate insulating film contains silicon oxide as a main component.

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