JP6062185B2 - Solid-state imaging device - Google Patents

Description

  The present invention relates to a solid-state imaging device.

  Semiconductor image sensors such as CCD image sensors and MOS image sensors are currently applied to most image input device devices.

  In recent years, MOS type image sensors have become mainstream, taking advantage of low power consumption and the ability to manufacture with the same CMOS technology as peripheral circuits.

  On the other hand, in terms of image quality, there is a wide field of application of image input device devices for high image quality because CCD image sensors have low dark current and fixed pattern noise.

  Patent Documents 1 to 3 disclose solid-state imaging devices to which a multistage source follower circuit is applied.

  A conventional CCD image sensor will be described with reference to FIG.

FIG. 10 is a circuit diagram showing the vicinity of a charge detection unit of a conventional CCD image sensor. As shown in FIG. 10, the charge detection unit 100 of the CCD image sensor, the horizontal CCD101 for transferring photoelectrically converted signal charge, and a detector diode FD to voltage conversion by the transferred signal charge detection capacitance C _FD , A plurality of stages of source follower circuits 102, 103, and 104 having the detection diode FD as an input, and amplification transistors Tr 102, Tr 103, and Tr 104 and constant current load transistors Tr 105, Tr 106, and 104 constituting each source follower circuit 102, 103, and 104 Tr107 and a reset transistor Tr108 for discharging the transfer charge to the reset drain RD are provided.

  As a CCD image sensor, an output circuit generally has a multi-stage source follower amplifier configuration for output impedance conversion.

  Here, it is assumed that the charge detection unit 100 of the CCD type image sensor includes three stages of source follower circuits 102, 103, and 104, and the amplification transistors Tr102 and 102 of the source follower circuits 102, 103, and 104, respectively. The drains of Tr103 and Tr104 are connected to the power supply voltage VOD.

  In each of the source follower circuits 102, 103, and 104, the constant current load transistors Tr105, Tr106, and Tr107 are connected to the source side of each of the amplification transistors Tr102, Tr103, and Tr104.

  The output VOUT100 as the output of the charge detection unit 100 is output from the output unit OUT100 connected to the source of the amplification transistor Tr104 of the third-stage source follower circuit 104.

  Horizontal transfer clock pulses φH1 and φH2 are input to the gates H1 and H2 connected to the horizontal CCD 101, respectively.

  The drain of the reset transistor Tr108 serves as the reset drain RD, and the power supply voltage VRD is applied. A reset pulse φR is input to the gate of the reset transistor Tr108.

  FIG. 11 is a diagram illustrating signal timing of the charge detection unit 100 of the conventional CCD image sensor.

  At time T1, since the horizontal transfer clock pulse φH1 is at a high level, charges are not transferred from the horizontal CCD 101 to the detection diode FD, but transfer charges are accumulated below the horizontal transfer clock pulse φH1. On the other hand, the reset pulse φR becomes high level, and the potential of the detection diode FD is fixed at the same potential as the power supply voltage VRD.

  Next, at time T2, the reset pulse φR becomes low level, the potential of the detection diode FD is lowered by the amount of feedthrough, and is in a floating state.

At time T3, the horizontal transfer clock pulse φH1 becomes a low level, and the charge accumulated under the gate H1 is transferred to the detection diode FD through the output gate OG. In the detection diode FD, the transfer charge is converted into a signal voltage by the detection capacitor C _FD . When the transfer charge is Qsig, the output voltage Vsig at this time is expressed by the following (formula 1).

Vsig = G · Qsig / C _FD (Formula 1)
C _FD is a detection capacity. G is the gain of the source follower circuits 102, 103, and 104, and has a value of about 0.8 to 0.9. For example, when C _FD = 2 (fF), the charge to voltage conversion rate is about 64 uV / el. The output gate OG is about 1V, the voltage VRD of the reset drain RD and the voltages VOD of the output drains of the source follower circuits 102 and 103 are about 12V, and the DC voltage of about 0.8V as the voltage VBias to the bias terminal Bs. Is generally applied.

  Here, the reason why a plurality of source follower amplifiers (three in the conventional example) are provided as in the source follower circuits 102, 103, and 104 shown in FIG. 10 is as follows.

  First, when the gate width of the amplification transistor of the source follower amplifier is W, the gate length is L, and the flowing current is I, the output impedance Rout of the source follower amplifier can be expressed as (Equation 2) below.

  Therefore, in order to reduce the output impedance Rout, (W / L) is increased and I is increased.

  However, increasing W increases the input capacity. Further, if L is reduced, noise increases. Furthermore, when I is increased, the current consumption directly increases.

  For this reason, in consideration of these, it is designed that (W / L) · I increases in the later stage, and it is necessary to gradually reduce the output impedance. At this time, a large current of 5 mA or more is required for the source follower amplifier in the final stage.

  Patent Document 4 discloses a technique for lowering the current consumption by lowering the power supply voltage as it becomes the latter stage of a plurality of source follower amplifiers.

  FIG. 12 is an enlarged view of the output VOUT100 which is the output waveform shown in FIG.

In general, when the switch transistor transitions from on to off, kTC noise is generated. In particular, when the capacitance C is the detection capacitance C _FD , the capacitance value is very small. Therefore, as the reset transistor Tr108 transitions from the high level to the low level, kTC noise that cannot be ignored in the period T2 is generated.

  Therefore, analog signal processing for reading the difference signal between time T2 and time T3 by the subsequent analog clamp circuit, differential amplifier or CDS (correlated double sampling) circuit of the solid-state imaging device is performed in the subsequent chip. Is required.

Japanese Patent Laid-Open No. 3-274811 (released on December 5, 1991) Japanese Patent Laid-Open No. 5-251677 (published September 28, 1993) Japanese Patent Laid-Open No. 6-70239 (published on March 11, 1994) Japanese Patent Laid-Open No. 10-117306 (published May 6, 1998) JP 2000-152090 A (published on May 30, 2000) Japanese Patent Laying-Open No. 2006-49986 (released on February 16, 2006)

  However, in the prior art, the following problems occur in configuration and operation.

  As described above, after the signal is output from the solid-state imaging device, the subsequent chip must read the difference signal between the time T2 and the time T3 by a CDS circuit or the like.

  However, the output VOUT100, which is an analog waveform shown in FIG. 12, is very complicated, and includes harmonics while having a frequency component twice that of the basic clock. For this reason, a very wide frequency band is required for transmission of the output waveform VOUT.

  That is, the output impedance of the solid-state imaging device needs to be sufficiently low, and the substrate wiring between the solid-state imaging device and the subsequent stage chip including the CDS circuit must be sufficiently considered such as stray capacitance, additional resistance, and interference noise.

  Further, the CDS circuit of the subsequent stage chip requires an accurate analog processing timing for performing clamping during the period T2, which is a particularly short period.

  These problems are very complicated in the design of a camera system including a solid-state imaging device, and in reality, the clamp timing is a CDS circuit of a subsequent chip, and for example, the phase of the clamp pulse is finely monitored while watching signal noise. In some cases, it may be necessary to make individual adjustments such as adjustments.

  A solid-state imaging device for preventing this is proposed in Patent Document 5.

  However, in the technique of Patent Document 5, in this example, the clamping is performed by the same pulse as the reset pulse φR, so that the clamping is not performed but the level shift of the output signal is merely limited.

  Further, Patent Document 6 discloses a solid-state imaging device having an analog CDS circuit in each column of a two-dimensional pixel array.

  However, in the solid-state imaging device of Patent Document 6, the detection capacity and the gain of the source follower circuit vary for each column, and as a result, signal sensitivity variation occurs for each column. Due to this variation in signal sensitivity, a vertical line defect occurs, resulting in image quality degradation.

  It is also conceivable to provide a CDS circuit in the source follower circuits 102, 103 and 104 in a plurality of stages after the horizontal CCD 101 by the conventional technique shown in FIG. However, in this case, as shown in FIGS. 11 and 12, the period T2 becomes very short, and the output VOUT100 of the output VOUT100 is not made to correspond individually, such as adjusting the phase of the clamping pulse generated in the subsequent CDS circuit. It is difficult to perform an accurate clamping operation during the period T2.

  The present invention has been made to solve the above-described problems, and an object thereof is to perform a clamping operation accurately without variation.

  In order to solve the above-described problems, a solid-state imaging device according to the present invention includes a charge transfer element that transfers charges from a plurality of photoelectric conversion elements by input of a transfer pulse, and a charge transferred from the charge transfer element. Is converted into a signal voltage, and a multi-stage source follower circuit that amplifies the signal voltage converted by the charge conversion section, and the output of the previous source follower circuit is connected between the multi-stage source follower circuits. A clamp circuit for clamping is arranged, and the clamp circuit is characterized in that the transfer pulse is driven as a clamp pulse.

  According to the above configuration, since the clamp circuit drives the transfer pulse as a clamp pulse, the signal output obtained by amplifying the signal voltage by the multi-stage source follower circuit and the drive of the clamp circuit are synchronized. be able to. For this reason, it is possible to accurately perform the clamping operation without variation.

  A first power supply voltage is applied to the source follower circuit disposed in the preceding stage of the clamp circuit among the multi-stage source follower circuits, and the source follower circuit disposed in the subsequent stage of the clamp circuit is applied to the source follower circuit. Preferably, a second power supply voltage lower than the first power supply voltage is applied, and the second power supply voltage is applied to the clamp circuit.

  According to the above configuration, the second power supply voltage applied to the subsequent source follower circuit with high power consumption is lower than the first power supply voltage applied to the previous source follower circuit with relatively low power consumption. Power consumption can be reduced.

The charge conversion unit includes a detection diode unit for detecting the charge transferred from the charge transfer element and converting the charge into a signal voltage, and the clamp circuit includes the source follower of the previous stage in the multi-stage source follower circuit. A clamp capacitor disposed between a signal voltage output unit of the circuit and a gate of the subsequent source follower circuit, and the clamp capacitor is preferably 100 times or more larger than the capacitance of the detection diode unit; . Thereby, the voltage drop by the kTC noise contained in the signal voltage from the said latter source follower circuit or a field through can be suppressed. For this reason, it is not necessary to provide a separate clamp circuit further downstream of the latter source follower circuit, and the circuit configuration can be simplified.

The clamp circuit has a gate connected to the first clamp transistor whose transfer pulse is input, a drain connected to the source of the first clamp transistor, and a source connected to the gate of the subsequent source follower circuit. And a second clamp transistor having a gate that receives a pulse having a phase opposite to that of the transfer pulse, the gate of the second clamp transistor being half the size of the gate of the first clamp transistor. It is preferable that

  According to the above configuration, the field through due to the transfer pulse seen in the output signal of the source follower circuit at the subsequent stage can be greatly reduced. As a result, the dynamic range of the output signal of the source follower circuit can be expanded, so that the power consumption of the multi-stage source follower circuit can be reduced.

The clamp circuit includes a first clamp transistor having a drain connected to the second power supply voltage and a source connected to a gate of the source follower circuit in the subsequent stage;
The transfer pulse is input, and a pulse signal having the same cycle as that of the transfer pulse but having a different voltage is generated by superimposing a voltage from the second power supply voltage or another power supply voltage on the input transfer pulse. It is preferable to provide a bias circuit that inputs the generated pulse signal to the gate of the first clamp transistor.

  With the above configuration, even if the high voltage level of the transfer pulse and the second power supply voltage are the same voltage level, the first clamp transistor can be driven reliably.

A solid-state imaging device according to the present invention includes a charge transfer element that transfers charges from a plurality of arranged photoelectric conversion elements by inputting a transfer pulse, and a charge conversion unit that converts the charges transferred from the charge transfer elements into a signal voltage And a multi-stage source follower circuit that amplifies the signal voltage converted by the charge converter, and a clamp circuit for clamping the output of the previous source follower circuit is disposed between the multi-stage source follower circuits. The clamp circuit drives the transfer pulse as a clamp pulse, and the charge conversion unit includes a detection diode unit for detecting the charge transferred from the charge transfer element and converting it into a signal voltage, The clamp circuit includes a signal voltage output unit of the preceding source follower circuit and the subsequent source follower of the multistage source follower circuits. Includes a clamp capacitor arranged between the gate of the follower circuit, the clamp capacitor is larger 100 or more times the capacity of the detector diode unit.

  Thereby, there is an effect that the clamping operation can be performed accurately without variation.

It is a circuit diagram showing the structure of the solid-state imaging device which concerns on 1st Embodiment. It is a figure showing the timing of the signal of the circuit of the solid-state imaging device concerning a 1st embodiment. It is the figure which expanded the output signal of the solid-state imaging device shown in FIG. It is a circuit diagram showing the structure of the solid-state imaging device which concerns on 2nd Embodiment. It is a top view showing schematic structure of the clamp transistor of the solid-state imaging device concerning a 2nd embodiment, and a cancellation transistor. It is a figure showing the timing of the signal of the circuit of the solid-state imaging device concerning a 2nd embodiment. It is a circuit diagram showing the structure of the solid-state imaging device which concerns on 3rd Embodiment. It is a figure showing the circuit structure of the automatic bias generation circuit shown in FIG. It is a figure showing the timing of the signal of the automatic bias generation circuit of FIG. It is the circuit diagram which showed the electric charge detection part vicinity of the conventional CCD type image sensor. It is a figure showing the timing of the signal of the charge detection part of the conventional CCD type image sensor. FIG. 12 is an enlarged view of an output VOUT100 that is an output waveform shown in FIG.

  Hereinafter, embodiments of the present invention will be described in detail.

[Embodiment 1]
(Circuit configuration of the solid-state imaging device 10)
FIG. 1 is a circuit diagram illustrating a configuration of a solid-state imaging device 10 according to the first embodiment.

  As an example, the solid-state imaging device 10 is a CCD image sensor.

  FIG. 1 shows the vicinity of the charge detection portion of the CCD image sensor.

The solid-state imaging device 10 includes a horizontal CCD (charge transfer device) 11 for transferring the photoelectrically converted charge, the detector diode (detector diode unit) FD to voltage conversion by the transferred charge detection capacitance C _FD, detector diode Multi-stage source follower circuits 12, 13, 14 having FD as input, a reset transistor Tr 18, and a clamp circuit CL are provided.

  The source follower circuit 12 includes an amplification transistor Tr12 and a constant current load transistor Tr15. The source follower circuit 13 includes an amplification transistor Tr13 and a constant current load transistor Tr16. The source follower circuit 14 includes an amplification transistor Tr14 and a constant current load transistor Tr17.

Clamping circuit CL comprises a clamping transistor (first clamp transistor) Tr19 and the clamp capacitor _{C CP.}

  In the solid-state imaging device 10, although not shown, a plurality of vertical CCDs arranged in the vertical direction (row direction) are connected to the horizontal CCD 11 arranged in the horizontal direction (column direction). Light receiving sensors (photoelectric conversion elements) as a plurality of pixels are arranged along the extending direction of each vertical CCD.

  This light receiving sensor accumulates signal charges corresponding to the intensity of incident light, and outputs the accumulated signal charges to the vertical CCD to which it is connected. The horizontal CCD 11 outputs the signal charge output from the light receiving sensor for each line of the vertical CCD.

  The horizontal CCD 11 sequentially applies signal charges for one line, which are line-shifted from a plurality of vertical CCDs, which are signal charges from the light receiving sensor, in response to the input of two layers of horizontal transfer clock pulses (transfer pulses) φH1 and φH2. Forward to.

  The horizontal CCD 11 is connected to gates H1 and H2 and an output gate OG. A horizontal transfer clock pulse φH1 is input to the gate H1, and a horizontal transfer clock pulse φH2 is input to the gate H2. The horizontal transfer clock pulse φH2 is an inversion pulse of the horizontal transfer clock pulse φH1.

  The output of the horizontal CCD 11 is connected to the cathode of the detection diode FD, the source of the reset transistor Tr18, and the gate of the amplification transistor Tr12.

  The detection diode FD, the detection capacitor CFD, and the reset transistor Tr18 constitute a charge detection unit (charge conversion unit). The charge detection unit sequentially converts the signal charge output from the horizontal CCD 11 into a signal voltage and outputs the signal voltage to a subsequent circuit.

The detection diode FD has a cathode connected to the output side which is the front end side of the horizontal CCD 11, and an anode is grounded. The detection diode FD is a floating diffusion part. The detection diode FD obtains a signal voltage by converting the voltage of the signal charge transferred from the horizontal CCD 11 by the detection capacitor C _FD .

  The reset transistor Tr18 discharges the signal charge from the horizontal CCD 11 to the reset drain RD. The reset drain RD, which is the drain of the reset transistor Tr18, is connected to the power supply voltage VRD, and the source is connected to the output of the horizontal CCD 11, the detection diode FD, and the gate of the amplification transistor Tr12.

  A reset pulse φR is input to the gate of the reset transistor Tr18. The reset transistor Tr18 performs a reset operation of discharging the signal charge from the horizontal CCD 11 to the reset drain RD when the reset pulse φR is applied.

  Three stages of source follower circuits 12, 13, and 14 are arranged after the charge detection section, and the charge detection section is connected to the first stage source follower circuit 12.

  The source follower circuits 12, 13, and 14 are multi-stage source followers that amplify the signal voltage converted by the charge detection unit.

  The source follower circuit 12 is a first stage source follower, the source follower circuit 13 is a second stage source follower, and the source follower circuit 14 is a third stage source follower.

  Then, an output of the source follower circuit 13 is clamped between a second-stage source follower circuit (front-stage source follower circuit) 13 and a third-stage source follower circuit (second-stage source follower circuit) 14. A clamp circuit CL is provided.

  The source follower circuit 12 includes an amplification transistor Tr12 and a constant current load transistor Tr15.

  The gate of the amplification transistor Tr12 is connected to the source of the detection diode FD and the reset transistor Tr18, the drain is connected to the power supply voltage (first power supply voltage) VOD, and the source is connected to the drain of the constant current load transistor Tr15. Has been. The source of the amplification transistor Tr12 is connected to the gate of the next-stage amplification transistor Tr13.

  The gate of the constant current load transistor Tr15 is connected to the bias terminal Bs, the drain is connected to the source of the amplification transistor Tr12 and the gate of the amplification transistor Tr13, and the source is grounded.

  The source follower circuit 13 includes an amplification transistor Tr13 and a constant current load transistor Tr16.

The gate of the amplification transistor Tr13 is connected to the source of the amplification transistor Tr12 and the drain of the constant current load transistor Tr15, the drain is connected to the power supply voltage VOD, and the source is connected to the drain of the constant current load transistor Tr16 and the clamp circuit CL. It is connected to the clamp capacitor C _CP to be configured. The source of the amplifying transistor Tr13 via the clamp capacitor _{C CP,} which is connected to the gate of the amplifying transistor Tr14 is the next stage of the source follower circuit 14.

The gate of the constant current load transistor Tr16 is connected to the bias terminal Bs, the drain source is connected to the source and the clamp capacitor C _CP of the amplification transistor Tr13 is grounded.

An output portion of the signal voltage of the second stage of the source follower circuit 13, referred to the source of the amplifying transistor Tr 13, and the output OUT1 of the connection between the clamp capacitor C _CP. The output at the output section OUT1 is referred to as output VOUT1. That is, the output VOUT1 is an output from the second-stage source follower circuit 13 and is a signal input to the clamp circuit CL.

Clamping circuit CL comprises a clamp transistor Tr19, and a clamp capacitor _{C CP.}

The clamp capacitor C _CP is disposed between the source (output unit OUT1) of the amplification transistor Tr13 and the drain of the constant current load transistor Tr16, the gate of the amplification transistor Tr14, and the source of the clamp transistor Tr19.

The clamp capacitor C _CP is considerably larger than the detection capacitor C _FD . As an example, the capacitance of the clamp capacitor C _CP is about 100 to 1000 times larger than the detection capacitor C _FD .

The drain of the clamp transistor Tr19 is connected to the drain and source voltage (second power supply voltage) VOD2 of the amplifying transistor Tr14, the source is connected to the gate and the clamp capacitance _{C CP} of the amplification transistor Tr14. A horizontal transfer clock pulse φH1 for driving the horizontal CCD 11 is input as a clamp pulse to the gate of the clamp transistor Tr19.

  The source follower circuit 14 includes an amplification transistor Tr14 and a constant current load transistor Tr17.

The gate of the amplifying transistor Tr14 is connected to the source and drain of the constant current load transistor Tr16 of the amplifying transistor Tr13 via the clamp capacitor _{C CP,} the drain is connected to the drain of the power supply voltage VOD2 and clamp transistor Tr19, The source is connected to the drain of the constant current load transistor Tr17 and the output part OUT2.

  The constant current load transistor Tr16 has a gate connected to the bias terminal Bs, a drain connected to the source of the amplification transistor Tr14, and a source grounded.

  An output VOUT2 that is an output signal of the solid-state imaging device 10 is output from the output unit OUT2.

  Thus, the source follower circuits 12 and 13 that are the previous stage of the clamp circuit CL are connected to the power supply voltage VOD as the power supply voltages of the source follower circuits 12, 13, and 14, and the source that is the subsequent stage of the clamp circuit CL The follower circuit 14 is connected to the power supply voltage VOD2.

  The power supply voltage VOD2 is a power supply voltage that is lower than the power supply voltage VOD.

  A bias voltage Vbias is applied from the bias terminal Bs to the gates of the constant current load transistors Tr15, 16, and 17. As an example of the bias voltage Vbias, a DC voltage of about 0.8 V is applied.

(Operation of the circuit of the solid-state imaging device 10)
Next, the operation of the circuit of the solid-state imaging device 10 shown in FIG. 1 will be described with reference to FIGS.

  FIG. 2 is a diagram illustrating signal timing of the circuit of the solid-state imaging device 10 according to the present embodiment.

  As shown in FIG. 2, 1CLK (one cycle) of the signal of the reset pulse φR is the reference cycle. The reset pulse φR and the horizontal transfer clock pulses φH1 and φH2 are synchronized.

  The period in which the reset pulse φR is high is time T1, the period in which the reset pulse φR is falling low and the horizontal transfer clock pulse φH1 is high is time T2, and the horizontal transfer clock pulse φH1 is at the falling level. A period in which the signal is low is defined as time T3.

  During the period when the reset pulse φR is high at time T1, the horizontal transfer clock pulse φH1 is also high. During the period when the horizontal transfer clock pulse φH1 is high, no signal charge is output from the horizontal CCD 11 to the detection diode FD, and the signal charge is accumulated under the gate H1. During the period when the reset pulse φR is high at time T1, the potential of the detection diode FD is fixed to the same power supply voltage VRD as that of the reset drain RD.

  At time T1, the voltage level of the output VOUT1 is high (the voltage level at this time is V1H), and the level of the output VOUT2 is also high (the voltage level at this time is V2H).

  Next, at time T2, the level of the reset pulse φR becomes low, and the potential of the detection diode FD decreases by the feedthrough amount. At this time, the detection diode FD is in a floating state. At this time, kTC noise is superimposed on the signal component (signal voltage) from the detection diode FD. For this reason, kTC noise is superimposed on the output VOUT1. On the other hand, the output VOUT2 does not change.

  At time T2, the level of the output VOUT1 drops from high (V1H) to the negative voltage level by the feedthrough. The voltage level at this time is V1M. The voltage level of the output VOUT2 is high (V2H).

Next, at time T3, the horizontal transfer clock pulse φH1 becomes low, the horizontal transfer clock pulse φH2 becomes high, and the signal charge stored under the gate H1 is transferred to the detection diode FD through the output gate OG. The The detection diode FD converts the signal charge transferred from the horizontal CCD 11 into a signal voltage by the detection capacitor C _FD .

  Due to the converted signal voltage, the output VOUT1 is lowered from the voltage level V1M by the amount indicated by the arrow A1 in FIG. The voltage level of the output VOUT1 at this time is set to V1L1.

  Further, at time T3, the voltage level of the output VOUT2 drops from high (V2H) to low as much as indicated by the arrow B1 in FIG. The voltage level of the output VOUT1 at this time is set to V2L1.

  A range indicated by arrows A1 and B1 in FIG. 2 is a signal level. That is, it is a signal component. In this way, the signal component is superimposed on the output VOUT2, and is output from the output unit OUT2.

  Note that when the output VOUT2 falls from high to low at time T3, the voltage level slightly decreases from high (V2H) to the negative side due to kTC noise superimposed on the output VOUT2, and then low (at this time). The voltage level of the signal falls to V2L1.

  That is, although not shown in FIG. 2, the arrow B1 indicates a range from the voltage level at which the voltage level slightly decreases from high (V2H) to the voltage level at low (V2L1).

  However, in the solid-state imaging device 10, since the clamp circuit CL is arranged between the second-stage source follower circuit 13 and the third-stage source follower circuit 14, kCT generated when the output VOUT2 is switched between high and low. The effect of noise is small. A detailed description thereof will be described later.

  Then, at time T3 of the next cycle, the output VOUT1 is reduced from the voltage level V1M by the amount indicated by the arrow A2 in FIG. 2 so that the signal component is superimposed (the voltage level at this time is set to the voltage level V1L2), and the output VOUT2 Is superimposed from the voltage level (not shown in FIG. 2) slightly lowered to the negative side due to the kTC noise from the high level by the amount indicated by the arrow B2 in FIG. 2 (the output VOUT2 at this time The voltage level is V2L2.)

  Here, assuming that the signal charge Qsig transferred from the horizontal CCD 11 to the detection diode FD during the period of time T3, the output voltage (signal voltage) from the detection diode FD at this time is expressed by the following equation. .

Vsig = G · Qsig / C _FD (Formula 1)
C _FD is the capacitance of the detection capacitor C _FD . G is the total gain of the three stages of the source follower circuits 12, 13 and 14, and shows a value of about 0.8 to 0.9. For example, when C _FD = 2 (fF), the charge to voltage conversion rate is about 64 uV / el.

  The voltage of the output gate OG is about 1V, and the power supply voltage VRD of the reset drain RD and the power supply voltage VOD connected to the output drains of the amplification transistors Tr12 and Tr13 are both about 12V.

  Here, in the solid-state imaging device 10, a clamp circuit CL is arranged between the second-stage source follower circuit 13 and the third-stage source follower circuit 14, and the gate of the clamp transistor Tr19 constituting the clamp circuit CL. Is supplied with a horizontal transfer clock pulse φH1, and its drain is connected to the power supply voltage VOD2.

  Thereby, the clamp circuit CL uses the horizontal transfer clock pulse φH1 as a clamp pulse and is driven in synchronization with the horizontal transfer clock pulse φH1. Therefore, the output VOUT2 of the third-stage source follower circuit 14 is clamped at the period of the horizontal transfer clock pulse φH1.

That is, when the horizontal transfer clock pulse φH1 is high, the voltage of the power supply voltage VOD2 is input to the third-stage source follower circuit 14, and when the horizontal transfer clock pulse φH1 is low, the voltage level of the output VOUT1 remains as it is as the clamp capacitance. is AC coupled by C _CP, a source follower circuit 14 of the voltage level third stage output VOUT1 is input. And it is output as output VOUT2.

  Thus, since the clamp circuit CL is driven by using the horizontal transfer clock pulse φH1 as a clamp pulse, the output VOUT2 obtained by the amplification of the third-stage source follower circuit 14 and the drive of the clamp circuit CL are synchronized. And an accurate clamping operation can be performed.

  FIG. 3 is an enlarged view of the output signal of the solid-state imaging device 10 shown in FIG. In FIG. 3, the outputs VOUT1 and VOUT2 and the horizontal transfer clock pulse φH1 in FIG. 2 are shown enlarged.

  During a period when the horizontal transfer clock pulse φH1 is high at time T1 and T2, the horizontal transfer clock pulse φH1 high is input to the gate of the clamp transistor Tr19, and is applied to the drain of the third-stage amplification transistor Tr14. The power supply voltage VOD2 is output from the source of the amplification transistor Tr14. As a result, during the period when the horizontal transfer clock pulse φH1 is high, the output VOUT2 is clamped to the output of the third-stage source follower circuit 14.

  At time T3, the horizontal transfer clock pulse φH1 changes from high to low, and accordingly, the output VOUT2 also changes in voltage level from high (V2H) to low (V2L1). When the output VOUT2 transitions from high (V2H) to low (V2L1), the output VOUT2 once decreases in voltage level in the negative direction due to the feedthrough and kTC noise remaining (at this time) The voltage level decreases to V2M from there.

  However, as shown by the broken line N1 in FIG. 3, the output VOUT2 is (V2H) after entering the time T3 as shown by the broken line N2 in FIG. 3, as compared with the influence of the kTC noise remaining in the output VOUT1 at the time T2. The effect of kTC noise when switching from low to low (V2L1) is much less.

This is because the capacitance of the clamp capacitor C _CP of the clamp circuit CL: C _CP and the capacitance of the detection capacitor C _FD : C _FD are set to satisfy C _CP >> C _FD . As an example, C _CP is about 100 to 1000 times C _FD .

  Thus, since the output VOUT2 is already less affected by the kTC noise, it is no longer necessary to clamp the output VOUT2 in the subsequent IC chip of the output unit OUT2.

  Further, since the clamping operation in the clamping circuit CL is performed by the horizontal transfer clock pulse φH1, it is synchronized with the signal phase of the output VOUT1, the output VOUT2, etc., and it is not necessary to finely adjust the individual timing for clamping.

  Further, when the output VOUT2 according to the present embodiment is compared with the output VOUT100 described as the conventional example, the output VOUT2 has a narrow bandwidth necessary for signal level transmission, and the output of the source follower circuits 12, 13, and 14 is reduced. Impedance can be maintained higher than the conventional example. This contributes to a reduction in current of the third-stage source follower circuit 14. As a result, the power consumption of the solid-state imaging device 10 can be reduced.

  Further, since the output VOUT2 is output to the outside of the solid-state imaging device 10, the current consumption of the third-stage source follower circuit 14 is normally the largest when the impedance of the source follower circuits 12, 13, and 14 is reduced.

  Therefore, a power supply voltage VOD2 which is a power supply different from the power supply voltage VOD applied to the first and second stage source follower circuits 12 and 13 is applied to the source follower circuit 14 so that the power supply voltage VOD2 is lower than the power supply voltage VOD. .

  As a result, the power supply voltage VOD2 applied to the source follower circuit 14 with high power consumption is lower than the power supply voltage VOD applied to the source follower circuits 12 and 13 with relatively low power consumption. Can do.

  For example, if the power supply voltage VOD = 12V and the power supply voltage VOD2 = 3V, and 5 mA is passed through the third-stage source follower circuit 14, the power-supply voltage VOD is supplied to the third-stage source follower circuit 14. Compared with the case where it is applied, the power consumption can be reduced by 45 mW.

[Embodiment 2]
Next, a second embodiment of the present invention will be described with reference to FIGS. For convenience of explanation, members having the same functions as those in the drawings described in the first embodiment are given the same reference numerals, and descriptions thereof are omitted.

  FIG. 4 is a circuit diagram illustrating a configuration of the solid-state imaging device 20 according to the second embodiment.

  The solid-state imaging device 20 is different from the solid-state imaging device 10 in that a clamp circuit CL2 is provided instead of the clamp circuit CL. Other configurations of the solid-state imaging device 20 are the same as those of the solid-state imaging device 10.

  The clamp circuit CL2 has a configuration in which a cancel transistor (second clamp transistor) Tr20 is added to the clamp circuit CL.

  The cancel transistor Tr20 is arranged between the clamp transistor Tr19 and the input side of the third stage amplification transistor Tr14.

The drain of the cancel transistor Tr20 is connected to the source of the clamp transistor Tr19, the source of the cancel transistor Tr20 is connected to the gate and the clamp capacitance _{C CP} of the amplification transistor Tr14. The source of the clamp transistor Tr19 is also connected to the source of the cancel transistor Tr20.

  A horizontal transfer clock pulse φH2, which is an inverted pulse of the horizontal transfer clock pulse φH1, is input to the gate of the cancel transistor Tr20.

  The gate size of the cancel transistor Tr20 is smaller than that of the clamp transistor Tr19.

  FIG. 5 is a plan view illustrating a schematic configuration of the clamp transistor Tr19 and the cancel transistor Tr20.

  As shown in FIG. 5, an active region Tr20Ac of the cancel transistor Tr20 is arranged below the gate Tr20G of the cancel transistor Tr20. An active region Tr19Ac of the clamp transistor Tr19 is disposed below the gate Tr20G of the clamp transistor Tr19.

  One end of the active region Tr19Ac of the clamp transistor Tr19 is connected to the power supply voltage VOD2 by the metal wiring ML19. As a result, one end of the active region Tr19Ac of the clamp transistor Tr19 serves as the drain Tr19D.

  The other end of the active region Tr19Ac is connected to one end and the other end of the active region Tr20Ac of the clamp transistor Tr20 by a metal wiring ML20. Thereby, the other end of the active region Tr19Ac serves as the source Tr19S. Further, one end of the active region Tr20Ac of the clamp transistor Tr20 is a drain Tr20D, and the other end is a source Tr20S.

  When the gate width of the cancel transistor Tr20 is W20, the gate length is L20, the gate width of the clamp transistor Tr19 is W19, and the gate length is L19, the gate lengths L20 and L19 are the same. It is smaller than the width W19. As an example, the gate width W20 is half of the gate width W10.

  Thus, the gate size of the cancel transistor Tr20 is smaller than the gate size of the clamp transistor Tr19. As an example, the gate size of the cancel transistor Tr20 is half of the gate size of the clamp transistor Tr19.

  Here, when the horizontal transfer clock pulse φH1 changes from low to high, field through appears in the output from the source Tr19S of the clamp transistor Tr19. This field through is proportional to the amplitude of the horizontal transfer clock pulse φH1 and half of the gate size of the clamp transistor Tr19 (LW / 2 if L19 = L, W19 = W). This is because the field through usually appears on both sides of the drain and source of the transistor.

  Therefore, the cancel transistor Tr20 having a smaller gate size than the clamp transistor Tr19 is connected to the source Tr19S of the clamp transistor Tr19. Then, by inputting the horizontal transfer clock pulse φH2 which is the reverse phase of the horizontal transfer clock pulse φH1 to the cancel transistor Tr20, the same amount of field through which is opposite in phase to the field through appearing at the output of the source Tr19S is supplied to the source Tr19S. Can be added to the output.

  As a result, the field through by the clamp transistor Tr19 can be canceled by the cancel transistor Tr20.

  Thereby, as shown in FIG. 6, the feedthrough of the horizontal transfer clock pulse φH1 seen in the waveform of the output VOUT2 can be greatly reduced.

  FIG. 6 is a diagram illustrating signal timing of a circuit of the solid-state imaging device 20 according to the second embodiment.

  That is, as shown in FIG. 6, when the horizontal transfer clock pulse ΦH1 becomes low at time T3, the voltage level of the output VOUT2 is once lowered from the high (V2H) level due to kTC noise (the voltage level at this time is reduced). V2M1), and then falls to Row (V2L1).

  At this time, the voltage level V2M1 once lowered is higher than V2M, and the difference between the voltage levels V2M1 and V2L1 (arrow B3 in FIG. 6) is larger than the difference between the voltage levels V2M and V2L1 (arrow B1 in FIG. 3). Similarly, the difference between the voltage levels V2M1 and V2L2 (arrow B4 in FIG. 6) is larger than the difference between the voltage levels V2M and V2L2 (arrow B2 in FIG. 3).

  For this reason, according to the solid-state imaging device 20, the signal operation range (dynamic range) can be expanded, and the power supply voltage VOD2 can be further lowered. As a result, the source follower circuits 12, 13, and 14 can be reduced. Power consumption can be reduced.

[Embodiment 3]
Next, a third embodiment of the present invention will be described with reference to FIGS. For convenience of explanation, members having the same functions as those in the drawings described in the first and second embodiments are denoted by the same reference numerals and description thereof is omitted.

  FIG. 7 is a circuit diagram illustrating a configuration of a solid-state imaging device 30 according to the third embodiment.

  The solid-state imaging device 30 is different from the solid-state imaging device 10 in that it includes a clamp circuit CL3 instead of the clamp circuit CL. Other configurations of the solid-state imaging device 30 are the same as those of the solid-state imaging device 10.

  The clamp circuit CL3 has a configuration in which an automatic bias generation circuit 31 is added to the clamp circuit CL.

That is, the clamp circuit CL3 includes an automatic bias generating circuit 31, the clamp transistor Tr19, and a clamp capacitor _{C CP.}

  In the solid-state imaging device 10 described above, for example, when the high level of the clamp pulse and the voltage VOD2 are both 3V, for example, there is a problem that the clamp transistor Tr19 is not turned ON at the high level of the clamp pulse. In order to solve the problem, the solid-state imaging device 30 is configured to superimpose a DC bias voltage on the horizontal transfer clock pulse φH1, generate a pulse signal φH1B, and use the pulse signal φH1B as a clamp pulse.

  The automatic bias generation circuit (bias circuit) 31 is connected to the gate of the clamp transistor Tr19. The automatic bias generation circuit 31 receives the horizontal transfer clock pulse φH1, superimposes a DC bias voltage on the horizontal transfer clock pulse φH1, generates a pulse signal φH1B, and inputs it to the gate of the clamp transistor Tr19. Accordingly, the clamp transistor Tr19 drives the pulse signal φH1B input from the automatic bias generation circuit 31 as a clamp pulse.

  The automatic bias generation circuit 31 can be configured by a circuit as shown in FIG.

  FIG. 8 is a diagram showing a circuit configuration of the automatic bias generation circuit 31 shown in FIG. The circuit configuration shown in FIG. 8 is an example of the automatic bias generation circuit 31.

  The automatic bias generation circuit 31 includes a power supply voltage VOD2, a transistor Tr31 whose drain is connected to the power supply voltage VOD2 and whose gate and source are short-circuited, a resistor R31 whose drain and source are connected to both ends, and a transistor The gate and source of Tr31 and one end of resistor R31 and the output side are connected, and a capacitor C31 to which horizontal transfer clock pulse φH1 is input is provided.

  The end of the metal wiring connecting the source and gate of the transistor Tr31 (the end opposite to the side where the resistor R31 and the capacitor C31 are connected) is connected to the gate of the clamp transistor Tr19. Then, the pulse signal φH1B is input to the gate of the clamp transistor Tr19 from the end of the metal wiring connected to the gate of the Tr19 and connecting the source and gate of the transistor Tr31.

  The transistor Tr31 is a transistor having the same design as the clamp transistor Tr19. The transistor Tr31 is manufactured on the same semiconductor substrate as the clamp transistor Tr19. Therefore, fluctuations in the characteristics of the power supply voltage VOD2 and the clamp transistor Tr19 due to temperature and manufacturing variations can be offset, and various adjustments such as the operation timing and voltage level of the automatic bias generation circuit 31 are unnecessary.

  FIG. 9 is a diagram showing signal timings of the automatic bias generation circuit 31 of FIG.

  When the horizontal transfer clock pulse φH1 is input to the automatic bias generation circuit 31, the automatic bias generation circuit 31 superimposes the power supply voltage VOD2 on the input horizontal transfer clock pulse φH1, thereby generating the horizontal transfer clock pulse φH1. A pulse signal φH1B having the same cycle and different voltage is generated. Then, the automatic bias generation circuit 31 inputs the generated pulse signal φH1B to the gate of the clamp transistor Tr19.

  In FIG. 9, the high voltage level of the horizontal transfer clock pulse φH1 is represented as 3V.

  Thereby, even if the high voltage level of the horizontal transfer clock pulse φH1 and the power supply voltage VOD2 are the same voltage level (for example, 3 V), the clamp transistor Tr19 can be driven reliably.

  The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention.

  The present invention can be used for a solid-state imaging device such as a CCD.

10.20.30 Solid-state imaging device 11 Horizontal CCD (Charge Transfer Element)
12.13.14 Source follower circuit 31 Automatic bias generation circuit (bias circuit)
C _CP clamp capacitor C _FD detection capacitor (capacitance of charge conversion unit, detection diode unit)
CL / CL2 Clamp circuit FD Detection diode (charge converter, detection diode)
H1, H2 Gate OG Output gate RD Reset drain Tr12 / Tr13 / Tr14 Amplifying transistor Tr15 / 16/17 Constant current load transistor Tr18 Reset transistor (charge converter)
Tr19 Clamp transistor (first clamp transistor)
Tr20 cancel transistor (second clamp transistor)
Tr31 Transistor VOD / VOD2 Power supply voltage OUT1 / OUT2 Output unit VOUT1 / VOUT2 Output φH1 Horizontal transfer clock pulse (transfer pulse)
φH2 Horizontal transfer clock pulse (pulse)
φH1B pulse signal

Claims (4)

A charge transfer element that transfers charges from a plurality of arranged photoelectric conversion elements by inputting a transfer pulse; and
A charge converter that converts the charge transferred from the charge transfer element into a signal voltage;
A multi-stage source follower circuit that amplifies the signal voltage converted by the charge converter,
Between the multi-stage source follower circuit, a clamp circuit for clamping the output of the previous source follower circuit is arranged,
The clamp circuit drives the transfer pulse as a clamp pulse ,
The charge conversion unit includes a detection diode unit for detecting the charge transferred from the charge transfer element and converting it into a signal voltage,
The clamp circuit includes, among the multi-stage source follower circuits, a signal voltage output unit of the source follower circuit in the preceding stage arranged in the preceding stage of the clamp circuit and a latter stage arranged in the subsequent stage of the clamp circuit. It has a clamp capacitor arranged between the gate of the source follower circuit,
The solid-state imaging device , wherein the clamp capacitance is 100 times or more larger than the capacitance of the detection diode section . Of the multi- stage source follower circuits, a first power supply voltage is applied to the preceding source follower circuit, and a second power supply voltage lower than the first power supply voltage is applied to the subsequent source follower circuit. And
The solid-state imaging device according to claim 1, wherein the second power supply voltage is applied to the clamp circuit. The clamp circuit includes a first clamp transistor in which the transfer pulse is input to a gate;
A drain connected to a source of the first clamp transistor, a source connected to a gate of the source follower circuit in the subsequent stage, and a second clamp transistor to which a pulse having an opposite phase to the transfer pulse is input to the gate. ,
The magnitude of the gate of the second clamp transistor, a solid-state imaging device according to claim 1 or 2, characterized in that is half the size of the gate of the first clamp transistor. The clamp circuit includes a first clamp transistor having a drain connected to the second power supply voltage and a source connected to a gate of the source follower circuit in the subsequent stage;
The transfer pulse is input, and a pulse signal having the same cycle as that of the transfer pulse but having a different voltage is generated by superimposing a voltage from the second power supply voltage or another power supply voltage on the input transfer pulse. The solid-state imaging device according to claim 2, further comprising: a bias circuit that inputs the generated pulse signal to the gate of the first clamp transistor.

Images