JP6060719B2 - PLL circuit - Google Patents

Description

  The present invention relates to a low voltage PLL circuit.

  Conventionally, PLL circuits have been widely used, and their basic circuit configuration is shown in FIG. The PLL circuit 100 generally includes a phase frequency comparison circuit (PFD) 20, a charge pump (CP) 200, a low-pass filter (LF) 30, and a voltage controlled oscillation circuit (VCO) 40. A reference signal REF from the outside and a feedback signal FB from the voltage controlled oscillation circuit (VCO) 40 are input to the phase frequency comparison circuit 20, and the phase difference signal is passed through the charge pump 200 by the phase frequency comparison circuit 20. And connected to the low-pass filter 30. The low-pass filter 30 removes unnecessary components of the phase difference signal, converts it to a DC voltage according to its output, and drives and inputs it to the voltage controlled oscillation circuit 40. In the oscillation circuit 40, a signal whose frequency is changed by a DC voltage is output, which becomes an output of the PLL circuit 100. This output is input to the phase frequency comparison circuit 20 as a feedback signal FB. After inputting the reference signal REF, the signal repeats a loop in the PLL circuit 100, and finally becomes a stable output of the PLL circuit 100. The period until the output is stabilized is called a lockup time. This PLL circuit is applied in various ways such as a synthesizer, a demodulator circuit for data transmission, an FM demodulator circuit, or a motor rotation speed control. A method of using feedback between the output of the PLL circuit 100 and the feedback signal FB via a frequency divider circuit and inputting it to the phase frequency comparison circuit 20 is common.

  Known documents are shown below.

JP-A-10-004350 JP-A-2005-073124

  In the semiconductor integrated circuit, development of high integration is constantly advanced. However, in the deep submicron process, it is necessary to configure the circuit only with a low-voltage power supply and a low-breakdown voltage MOS device as compared with the conventional one. When a PLL circuit is configured with only a low-voltage power supply and a low-breakdown-voltage MOS device, the maximum performance is derived by optimizing the circuit constants under the limitation of the power supply voltage range and device characteristics, and the performance limit is set.

But,
Problem 1
When designed with only a low-breakdown-voltage MOS device, the power supply voltage is lowered, which has the effect of reducing power consumption. On the other hand, the voltage dynamic range is narrowed, resulting in deterioration in signal-to-noise ratio (SN ratio) characteristics and increased characteristic variations. It was a problem. Therefore, when the required characteristics are essential, the problem has been avoided by increasing the number of power supplies (partially increasing the voltage).

Problem 2
For the element circuits VCO and CP circuit constituting the PLL circuit, when the voltage dynamic range is narrowed, the effective control voltage range is similarly narrowed. In order to compensate the VCO frequency variable range required at this time including environmental conditions and manufacturing variations, it is necessary to widen the frequency variable range of the voltage range per unit by increasing the VCO control sensitivity. This has been the main cause of increasing the phase noise and the required characteristic of the maximum frequency operation margin of the feedback frequency dividing circuit which is an element circuit of the PLL circuit, which has also caused an increase in power consumption.

  The present invention solves such problems, and an object thereof is to provide a PLL circuit that can suppress an increase in phase noise and power consumption by adding a relatively simple compensation circuit.

  In the PLL circuit of the present invention, after the PLL lockup, the compensation circuit determines at high speed whether the VCO control voltage is near the center voltage (50% of the power supply voltage) of the CP output voltage. If it is not near the center voltage, the problem is solved by changing the VCO oscillation frequency range characteristics step by step so that the PLL is locked near the center of the CP output voltage.

That is, the invention of claim 1 of the present invention is
At least in a PLL circuit in which a phase frequency comparison circuit, a charge pump, a low pass filter, and a voltage controlled oscillation circuit are connected in this order,
Having a compensation circuit for compensating the control voltage of the voltage controlled oscillation circuit after lock-up,
The compensation circuit divides the power supply voltage of the charge pump step by step, and outputs a divided voltage;
A comparison circuit that compares the control voltage of the voltage controlled oscillation circuit after the lock-up and the divided voltage step by step, and detects a voltage difference;
In response to the detected voltage difference, a frequency variable circuit that changes the oscillation frequency range characteristics of the voltage controlled oscillation circuit,
And a PLL circuit that repeats compensation until the control voltage of the voltage controlled oscillator circuit locks up near the center of the power supply voltage of the charge pump after changing the oscillation frequency range characteristic and locking up again. It is a thing.

The invention of claim 2 of the present invention
In the voltage divider circuit, a switch is connected to each node between the divided voltages,
In the comparison circuit, the divided voltage is connected to the inverting input of the voltage comparison circuit via a switch, the control voltage of the voltage controlled oscillation circuit is connected to the non-inverting input, and the latch signal is obtained by inverting the voltage difference of the input. Output
The frequency variable circuit is a frequency dividing circuit that converts the output signal of the voltage controlled oscillation circuit into a signal having a frequency that operates in the compensation circuit;
A pulse circulation circuit for outputting a switch selection pulse for turning on the switch in order of the divided voltage from the signal output from the frequency dividing circuit;
A register A for storing a switch selection pulse when a latch signal is input;
An addition / subtraction circuit for adding / subtracting a numerical value corresponding to the stored switch selection pulse to / from the oscillation frequency range characteristic selection code of the frequency adjustment unit of the voltage controlled oscillation circuit and outputting an improved oscillation frequency range characteristic selection code;
A register B for storing an improved oscillation frequency range characteristic selection code at the time of inputting a latch signal, and inputting the stored selection code to a frequency adjustment unit of the voltage controlled oscillation circuit;
A frequency lock detection circuit that outputs an initialization signal to the pulse circulation circuit from the lockup signal input from the phase frequency comparison circuit;
The PLL circuit according to claim 1, comprising:

  Since the present invention is configured as described above, the VCO control sensitivity can be lowered compared to the normal operation by compensating the operation so that the PLL is locked near the center of the CP output voltage without depending on environmental conditions and manufacturing variations. In addition, it is possible to design a PLL circuit that contributes to improving PLL characteristics by reducing VCO phase noise. In addition, it can be expected that the required characteristics of the maximum frequency operation margin of the feedback frequency divider circuit will be lowered and contribute to the reduction of PLL power consumption.

1 is a circuit diagram showing a first embodiment of a PLL circuit of the present invention. FIG. 3 is a circuit diagram showing a second embodiment of a PLL circuit of the present invention. It is a circuit diagram of the basic structural example of the conventional PLL circuit. It is explanatory drawing which showed an example of the oscillation frequency range characteristic which concerns on the example of embodiment of the PLL circuit of this invention.

  Hereinafter, modes for carrying out the present invention will be described.

FIG. 1 is a circuit diagram showing a first embodiment of a PLL circuit of the present invention. The PLL circuit according to this embodiment includes at least a phase frequency comparison circuit 2, a charge pump 20, a low-pass filter 3, and a voltage controlled oscillation circuit 4 connected in this order. And it has the compensation circuit 5 which compensates the control voltage of the voltage controlled oscillation circuit 4 after lockup,
The compensation circuit 5 divides the power supply voltage of the charge pump 20 step by step, and outputs a divided voltage.
A comparison circuit 7 for comparing the control voltage of the voltage-controlled oscillation circuit 4 after the lock-up and the divided voltage stepwise to detect a voltage difference;
A frequency variable circuit 8 that changes the oscillation frequency range characteristic of the voltage controlled oscillation circuit 4 in response to the detected voltage difference;
After the oscillation frequency is changed and locked up again, compensation is repeated until the control voltage of the voltage controlled oscillation circuit 4 is locked up near the center of the power supply voltage of the charge pump 20.

With such a configuration, the PLL of the present embodiment performs the following operation.
First, the initial lockup state is stabilized by the phase frequency comparison circuit 2, the charge pump 20, the low pass filter 3, and the voltage controlled oscillation circuit 4. The control voltage of the voltage controlled oscillation circuit 4 in this lockup state is applied to the comparison circuit 7. The comparison circuit 7 is applied with the divided voltage of the power supply voltage of the charge pump 20 generated in the voltage dividing circuit 6 to the other input terminal after the lockup state is stabilized. The divided voltage is changed stepwise, for example, from a low voltage, and a divided voltage that matches the control voltage is selected. Corresponding to the voltage difference between the divided voltage and the voltage at the center of the power supply voltage of the charge pump 20, the frequency variable circuit 8 changes the oscillation frequency range characteristic of the voltage controlled oscillation circuit 4 so that the voltage difference is reduced. change. After changing the oscillation frequency range characteristics and locking up again, compensation is repeated until the control voltage of the voltage controlled oscillation circuit 4 is locked up near the center of the power supply voltage of the charge pump 20.

The oscillation frequency range characteristic of the voltage-controlled oscillation circuit 4 can be exemplified by a circuit using a normally used LC resonance circuit.
The LC resonance type oscillation frequency Fo = 1 / SQRT (2π * L * C). In order to construct a VCO (voltage controlled oscillation circuit), in general, the capacitance C is C ± ΔC, and for each capacitance, a varactor element whose capacitance varies with the voltage is adopted. Is realized. However, due to variations in manufacturing of L and C, in actuality, Fo is finished to deviate from the target value. Therefore, even if there is variation, ± ΔC is designed to be large so as to include the target value.

  Although the configuration of the varactor element has been described above, it is possible to shift the frequency uniformly by turning ON / OFF a simple C that does not change its capacity with respect to the voltage using an electrical switch.

  In this way, in this embodiment, the PLL can be locked up near the center of the power supply voltage of the charge pump 20.

  The control voltage of the voltage controlled oscillation circuit 4 can be the output voltage of the low pass filter 3 or the output voltage of the charge pump 20. In the figure, the output voltage of the charge pump 20 is used. In general, the CP power supply voltage is equal to the power supply voltage of the circuit.

  FIG. 2 is a circuit diagram showing a second embodiment of the PLL circuit of the present invention. This is a more specific example with respect to the first embodiment. However, in FIG. 2, the phase frequency comparison circuit 2, the charge pump 20, and the low-pass filter 3 are not shown, and the voltage-controlled oscillation circuit 14 shows a part of the frequency control unit. Further, as the frequency control unit, an LCR circuit connected in parallel to a circuit having a negative resistance function is exemplified, and the frequency adjustment unit 144 is formed of a CR circuit. As the frequency adjustment unit 144, FIG. 2 illustrates a configuration in which three different CR circuits each having a switch are connected in parallel. This 3CR circuit is selected by switching the switches SC0, SC1, and SC2 according to the DC input voltage value that is the control voltage of the voltage controlled oscillation circuit 4, and the oscillation frequency range characteristics are changed and locked up. Go. This selection is coded SC [2: 0].

  In FIG. 2, the compensation circuit 15 in the present embodiment has the following configuration. In the voltage dividing circuit 16, the charge pump power supply is divided into eight, and switches S0, S1, S2,..., S7 are connected to nodes between the divided voltages in order of increasing voltage.

  In the comparison circuit 17, the divided voltage is connected to the inverting input via the switches S0, S1, S2,..., S7, and the control voltage of the voltage controlled oscillation circuit 14 is connected to the non-inverting input. . Then, the latch signal Latch is output by inversion of the input voltage difference.

The frequency variable circuit 18
A frequency dividing circuit 19 for converting an output signal of the voltage controlled oscillation circuit 14 into a signal having a frequency operated by the compensation circuit 15;
A pulse circulation circuit 21 that outputs a switch selection pulse S [7: 0] for turning on the switch in order of increasing divided voltage from the signal output from the frequency divider circuit 19;
A register A12 for storing a switch selection pulse S [7: 0] when the latch signal Latch is input;
Numerical values -4, -3, -2, -1, 0, +1, +2, and +3 corresponding to the stored switch selection pulse S [7: 0] are used as the oscillation frequency of the frequency adjusting unit 144 of the voltage controlled oscillation circuit 14. An addition / subtraction circuit 11 for adding / subtracting to / from the range characteristic selection code SC [2: 0] and outputting an improved oscillation frequency range characteristic selection code;
A register B13 for storing an improved oscillation frequency range characteristic selection code upon input of the latch signal Latch, and inputting the stored selection code to the frequency adjustment unit 144 of the voltage controlled oscillation circuit 14;
A frequency lock detection circuit 22 that outputs an initialization signal to the pulse circulation circuit 21 from the lockup signal input from the phase frequency comparison circuit 2;
Consists of.

With such a configuration, the PLL of the present embodiment performs the following operation.
First, the initial lock-up state is stabilized by the phase frequency comparison circuit 2, the charge pump 20, the low-pass filter 3, and the voltage-controlled oscillation circuit 14. The control voltage of the voltage controlled oscillation circuit 14 in the lockup state is applied to the non-inverting input of the comparison circuit 17. Further, the output signal of the voltage controlled oscillation circuit 14 is applied to the frequency dividing circuit 19, and the frequency dividing circuit 19 outputs a signal having a frequency for operating the compensation circuit 15 to the pulse circulation circuit 21.

  The pulse circulation circuit 21 outputs a switch selection pulse S [7: 0] for turning on the switch in order from the lowest divided voltage. When the lockup state is stabilized, the lockup state is detected by the frequency lock detection circuit 22 and the pulse circulation circuit 21 is initialized. From the initialized pulse circulation circuit 21, switch selection pulses S [7: 0] for turning on the switches S 0, S 1, S 2,..., S 7 are output in the descending order of the divided voltage of the voltage dividing circuit 16. Then, the switch is sequentially turned on and off, and the divided voltage is input to the inverting input of the comparison circuit 17 via the switch.

  The comparison circuit 17 outputs a latch signal Latch when the voltage difference between the control voltage of the voltage controlled oscillation circuit 14 and the divided voltage is inverted.

  The latch signal Latch is input to the register A12 and latched. As an input signal of the register A12, the output of the pulse circulation circuit 21 is connected. Therefore, the register A12 latches the switch selection pulse S [7: 0] corresponding to the divided voltage when inverted. The register A12 outputs to the addition / subtraction circuit 11.

  In the addition / subtraction circuit 11, numerical values −4, −3, −2, −1, 0, +1, +2, and +3 corresponding to the switch selection pulse S [7: 0] input from the register A 12 are input to the frequency adjustment unit 144. The oscillation frequency range characteristic selection code SC [2: 0] is added to or subtracted from, and the improved oscillation frequency range characteristic selection code is output. This corresponds to the voltage difference between the latched divided voltage and the center voltage of the power supply voltage of the charge pump 20, and the voltage control oscillation circuit 4 so that the voltage difference is reduced by the frequency variable circuit 8. This is to change the oscillation frequency range characteristic of the. In this example, the voltage corresponding to the switch S4 is illustrated as the voltage near the center of the power supply voltage of the charge pump 20. Therefore, the numerical values +3, +2, +1, 0, −1, −2, −3, and −4 correspond to the switches S0, S1, S2, S3, S4, S5, S6, and S7. From this, the control voltage of the voltage controlled oscillation circuit 14 approaches the voltage near the center of the power supply voltage of the charge pump 20 with the oscillation frequency range characteristic selected by the improved oscillation frequency range characteristic selection code.

  The improved oscillation frequency range characteristic selection code is input to the register B13 and latched by the latch signal Latch. The oscillation frequency range characteristic selection code SC is input as an improved oscillation frequency range characteristic selection code SC from the register B13 to change the oscillation frequency range characteristic.

  FIG. 4 illustrates the oscillation frequency range characteristic using the oscillation frequency range characteristic selection code SC as a parameter. The horizontal axis represents the control voltage of the voltage controlled oscillation circuit, and the vertical axis represents the oscillation frequency. The selection code SC is selected so that the control voltage has a value half V / 2 of the charge pump voltage V.

  After changing the oscillation frequency range characteristic and locking up again, compensation is repeated until the output voltage of the charge pump 20 locks up near the center of the power supply voltage of the charge pump 20. In this example, when the switch S4 is ON, the operation is repeated several times until the comparison circuit determines, and the compensation ends.

  In this way, even in this embodiment, the PLL can be locked up near the center of the power supply voltage of the charge pump 20.

  In this embodiment, the oscillation frequency range characteristic selection code SC [2: 0] of the frequency adjustment unit 144 is 3 bits (3CR circuit), but the accuracy of frequency adjustment can be increased by increasing the number of bits. High accuracy can be achieved.

  After the switch selection pulse to be corrected in the register A12 is selected and latched, it is preferable to suspend unnecessary circuit operations. For this reason, as illustrated in the figure, it is preferable to provide a reset circuit 23 that is connected to the output of the register A12 and outputs the reset signal RESET in a selected state, and is input to the frequency dividing circuit 19 to be in the reset state. In this example, the condition for generating the reset signal is such that the switch S4 is H and the other switches are L.

  However, when the lock state is not realized or when the lock state is removed in the middle, the frequency lock detection circuit 22 performs control to release the reset state.

  Also, the initial value described at the input of the adder / subtractor circuit and the initial value of the output of the register B are set as design representative values.

  An example of the frequency lock detection circuit 22 is a circuit that uses the output of the phase frequency comparison circuit 2. In other words, since the PLL lockup state is in an equilibrium state, the output pulse width on the high voltage output side and the low voltage output side of the phase frequency comparison circuit 2 is the same, and the frequency lock state is detected by detecting this. It can be assumed that

  As the pulse circulation circuit, a commonly used shift register can be exemplified.

  As described above, as shown in the embodiment of the present invention, the PLL of the present invention can compensate the operation so that the PLL is locked near the center of the CP output voltage without being affected by environmental conditions and manufacturing variations. As a result, the VCO control sensitivity can be designed to be lower and the variation can be designed smaller than usual, and a PLL circuit that contributes to improving the PLL characteristics by reducing the VCO phase noise can be obtained.

  The lower the power supply voltage, the smaller the voltage range that can be handled as signal information for a circuit that handles analog quantities, and the proportion of steady noise increases, but the PLL of the present invention always operates at the optimum position. Therefore, even if there is a manufacturing variation at a low voltage as in the deep submicron process, it can be eliminated.

  In addition, it can be expected that the required characteristics of the maximum frequency operation margin of the feedback frequency divider circuit will be lowered and contribute to the reduction of PLL power consumption.

DESCRIPTION OF SYMBOLS 1 ... PLL circuit 2 ... Phase frequency comparison circuit 20 ... Charge pump 3 ... Low pass filter 4 ... Voltage controlled oscillation circuit 5 ... Compensation circuit 6 ... Voltage divider circuit 7 ... Comparator circuit 8 ... Variable frequency circuit 11 ... Addition / subtraction circuit 12 ... Register A
13... Register B
14. Voltage controlled oscillation circuit 15 ... Compensation circuit 16 ... Voltage divider circuit 17 ... Comparison circuit 18 ... Frequency variable circuit 19 ... Frequency divider circuit 21 ... .... Pulse circulation circuit 22 ... Frequency lock detection circuit 23 ... Reset circuit 30 ... Low pass filter 40 ... Voltage controlled oscillation circuit 100 ... PLL circuit 200 ... Charge pump

Claims (2)

At least in a PLL circuit in which a phase frequency comparison circuit, a charge pump, a low pass filter, and a voltage controlled oscillation circuit are connected in this order,
Having a compensation circuit for compensating the control voltage of the voltage controlled oscillation circuit after lock-up,
The compensation circuit divides the power supply voltage of the charge pump step by step, and outputs a divided voltage;
A comparison circuit that compares the control voltage of the voltage controlled oscillation circuit after the lock-up and the divided voltage step by step, and detects a voltage difference;
In response to the detected voltage difference, a frequency variable circuit that changes the oscillation frequency range characteristics of the voltage controlled oscillation circuit,
A PLL circuit characterized by repeating the compensation until the control voltage of the voltage controlled oscillator circuit locks up near the center of the power supply voltage of the charge pump after changing the oscillation frequency range characteristic and locking up again. In the voltage divider circuit, a switch is connected to each node between the divided voltages,
In the comparison circuit, the divided voltage is connected to the inverting input of the voltage comparison circuit via a switch, the control voltage of the voltage controlled oscillation circuit is connected to the non-inverting input, and the latch signal is obtained by inverting the voltage difference of the input. Output
The frequency variable circuit is a frequency dividing circuit that converts the output signal of the voltage controlled oscillation circuit into a signal having a frequency that operates in the compensation circuit;
A pulse circulation circuit for outputting a switch selection pulse for turning on the switch in order of the divided voltage from the signal output from the frequency dividing circuit;
A register A for storing a switch selection pulse when a latch signal is input;
An addition / subtraction circuit for adding / subtracting a numerical value corresponding to the stored switch selection pulse to / from the oscillation frequency range characteristic selection code of the frequency adjustment unit of the voltage controlled oscillation circuit and outputting an improved oscillation frequency range characteristic selection code;
A register B for storing an improved oscillation frequency range characteristic selection code at the time of inputting a latch signal, and inputting the stored selection code to a frequency adjustment unit of the voltage controlled oscillation circuit;
A frequency lock detection circuit that outputs an initialization signal to the pulse circulation circuit from the lockup signal input from the phase frequency comparison circuit;
The PLL circuit according to claim 1, comprising:

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