JP6060527B2 - Semiconductor package - Google Patents

Semiconductor package Download PDF

Info

Publication number
JP6060527B2
JP6060527B2 JP2012125429A JP2012125429A JP6060527B2 JP 6060527 B2 JP6060527 B2 JP 6060527B2 JP 2012125429 A JP2012125429 A JP 2012125429A JP 2012125429 A JP2012125429 A JP 2012125429A JP 6060527 B2 JP6060527 B2 JP 6060527B2
Authority
JP
Japan
Prior art keywords
semiconductor package
substrate
lid
components
heat
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2012125429A
Other languages
Japanese (ja)
Other versions
JP2013251412A (en
Inventor
鈴木 卓也
卓也 鈴木
康則 藤本
康則 藤本
朝之 福田
朝之 福田
剛 一丸
剛 一丸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Socionext Inc
Original Assignee
Socionext Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Socionext Inc filed Critical Socionext Inc
Priority to JP2012125429A priority Critical patent/JP6060527B2/en
Publication of JP2013251412A publication Critical patent/JP2013251412A/en
Application granted granted Critical
Publication of JP6060527B2 publication Critical patent/JP6060527B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

本願は、半導体パッケージ用の蓋、及び半導体パッケージに関する。   The present application relates to a lid for a semiconductor package and a semiconductor package.

近年、半導体パッケージに搭載する部品点数が増加する傾向にある(例えば、特許文献1を参照)。例えば、CPU(Central Processing Unit)やメモリといった各部品を半
導体パッケージに搭載すれば、電子機器の小型化やパフォーマンスの向上を実現できる。
In recent years, the number of components mounted on a semiconductor package tends to increase (see, for example, Patent Document 1). For example, if each component such as a CPU (Central Processing Unit) and a memory is mounted on a semiconductor package, the electronic device can be reduced in size and performance can be improved.

特開2007−95860号公報Japanese Patent Laid-Open No. 2007-95860

多数の部品を搭載した半導体パッケージが故障した場合、故障原因となっている部品を交換することが望まれる。しかし、部品が半導体パッケージに封入されている場合、部品の交換作業を行うことは難しい。   When a semiconductor package on which a large number of components are mounted fails, it is desirable to replace the component causing the failure. However, when the component is enclosed in the semiconductor package, it is difficult to replace the component.

また、半導体パッケージに搭載する部品点数の増大により、基板の面積が広がると、次のような問題が生じ得る。半導体パッケージは、例えば、下面に形成された多数の半田ボールを介して、半導体パッケージ以外の電子部品を搭載した電子基板と電気的に接続される。この場合、半導体パッケージの下面に形成された半田ボールに接触不良が発生すると、電子機器の動作に不具合が生じる虞がある。半田ボールの接触不良の発生原因の一つに、例えば、各半田ボールの先端の高さの不均一が挙げられる。半田ボールの先端の高さが不均一となる原因には、例えば、半田ボールを形成する際の加工精度の他、半導体パッケージの基板の反りが挙げられる。半導体パッケージの基板の反りに起因する半田ボールの先端の高さのばらつきは、半導体パッケージの基板の面積が大きくなるに従い、顕著になる。   Further, when the area of the substrate increases due to an increase in the number of components mounted on the semiconductor package, the following problems may occur. For example, the semiconductor package is electrically connected to an electronic substrate on which electronic components other than the semiconductor package are mounted via a large number of solder balls formed on the lower surface. In this case, if a contact failure occurs in the solder ball formed on the lower surface of the semiconductor package, there is a risk that a malfunction may occur in the operation of the electronic device. One of the causes of poor contact of solder balls is, for example, nonuniformity in the height of the tips of the solder balls. The cause of the uneven height of the tip of the solder ball includes, for example, the warpage of the substrate of the semiconductor package in addition to the processing accuracy when forming the solder ball. The variation in the height of the solder ball tip due to the warpage of the substrate of the semiconductor package becomes more significant as the area of the substrate of the semiconductor package increases.

そこで、本願は、フリップチップ実装タイプ半導体パッケージに於ける搭載部品への物理的なアクセスを可能にしつつ、基板の反りを矯正可能な半導体パッケージ用の蓋、及び半導体パッケージを提供することを課題とする。   Therefore, the present application has an object to provide a lid for a semiconductor package and a semiconductor package capable of correcting the warp of the substrate while allowing physical access to the mounted components in the flip chip mounting type semiconductor package. To do.

本願は、次のような半導体パッケージ用の蓋を開示する。
半導体チップ及び他の部品が搭載された基板を覆う半導体パッケージ用の蓋であって、
前記基板に接着される板材と、
前記板材の前記基板が接着される面に形成され、前記半導体チップを収容する凹部と、
前記板材の両面に開口させて前記凹部と異なる位置に形成され、前記他の部品を収容する貫通孔部と、を備える、
半導体パッケージ用の蓋。
The present application discloses the following lid for a semiconductor package.
A lid for a semiconductor package covering a substrate on which a semiconductor chip and other components are mounted,
A plate material bonded to the substrate;
A recess formed on the surface of the plate to which the substrate is bonded, and housing the semiconductor chip;
A through-hole portion that is formed in a position different from the concave portion and is opened on both surfaces of the plate material, and accommodates the other components.
A lid for semiconductor packages.

また、本願は、次のような半導体パッケージを開示する。
半導体チップ及び他の部品が搭載される基板と、
前記基板に接着される板材と、
前記板材の前記基板が接着される面に形成され、前記半導体チップを収容する凹部と、
前記板材の両面に開口させて前記凹部と異なる位置に形成され、前記他の部品を収容す
る貫通孔部と、を備える、
半導体パッケージ。
The present application also discloses the following semiconductor package.
A substrate on which a semiconductor chip and other components are mounted;
A plate material bonded to the substrate;
A recess formed on the surface of the plate to which the substrate is bonded, and housing the semiconductor chip;
A through-hole portion that is formed in a position different from the concave portion and is opened on both surfaces of the plate material, and accommodates the other components.
Semiconductor package.

上記半導体パッケージ用の蓋、及び半導体パッケージであれば、搭載部品への物理的なアクセスを可能にしつつ、基板の反りを矯正可能となる。   The lid for the semiconductor package and the semiconductor package can correct the warpage of the substrate while allowing physical access to the mounted components.

実施形態に係る半導体パッケージ用の蓋を示した図の一例である。It is an example of the figure which showed the lid | cover for semiconductor packages which concerns on embodiment. 図1において符号B−Bで示す線で板材を切断した場合の断面図の一例である。It is an example of sectional drawing at the time of cut | disconnecting a board | plate material with the line | wire shown by code | symbol BB in FIG. 図1において符号A−Aで示す線で板材を切断した場合の断面図の一例である。It is an example of sectional drawing at the time of cut | disconnecting a board | plate material with the line | wire shown by code | symbol AA in FIG. 蓋に備わっている凹部や貫通孔部と、蓋に覆われる基板に搭載されている半導体チップ及び他の部品との位置関係の一例を示した図である。It is the figure which showed an example of the positional relationship with the recessed part and through-hole part with which a cover was equipped, and the semiconductor chip and other components mounted in the board | substrate covered with a cover. 蓋を基板に接着した半導体パッケージの上面図の一例である。It is an example of the top view of the semiconductor package which adhere | attached the lid | cover on the board | substrate. 図5において符号C−Cで示す線で半導体パッケージを切断した場合の断面図の一例である。FIG. 6 is an example of a cross-sectional view when the semiconductor package is cut along a line indicated by a symbol CC in FIG. 5. 図5において符号D−Dで示す線で半導体パッケージを切断した場合の断面図の一例である。FIG. 6 is an example of a cross-sectional view when the semiconductor package is cut along a line indicated by reference sign DD in FIG. 5. 連通部の変形例を示した図の一例である。It is an example of the figure which showed the modification of the communication part. 従来技術に係る半導体パッケージ用の蓋を斜め下側から見た斜視図の一例である。It is an example of the perspective view which looked at the lid | cover for semiconductor packages which concerns on a prior art from diagonally lower side. 従来技術に係る半導体パッケージ用の蓋を基板に接着した半導体パッケージの内部構造図の一例である。It is an example of the internal structure figure of the semiconductor package which adhered the lid | cover for semiconductor packages based on a prior art to the board | substrate. 従来技術に係る半導体パッケージ用の蓋を基板から取り外した状態を示した図の一例である。It is an example of the figure which showed the state which removed the lid | cover for semiconductor packages which concerns on a prior art from the board | substrate. 基板に搭載されている他の部品を取り外した状態を示した図の一例である。It is an example of the figure which showed the state which removed the other components mounted in the board | substrate. 蓋と熱伝導材料とを取り除いた従来技術に係る半導体パッケージを示した図の一例である。It is an example of the figure which showed the semiconductor package which concerns on the prior art which remove | eliminated the lid | cover and the heat conductive material. 実施形態に係る半導体パッケージを上側から見た場合の、蓋と基板との接着部分を示した図の一例である。It is an example of the figure which showed the adhesion part of a lid | cover and a board | substrate when the semiconductor package which concerns on embodiment is seen from the upper side. 従来技術に係る半導体パッケージを上側から見た場合の、蓋と基板との接着部分を示した図の一例である。It is an example of the figure which showed the adhesion part of a lid | cover and a board | substrate at the time of seeing the semiconductor package which concerns on a prior art from the upper side. 放熱フィンを取り付けた半導体パッケージの内部構造の一例を示した図の一例である。It is an example of the figure which showed an example of the internal structure of the semiconductor package which attached the radiation fin. 変形例に係る放熱フィンを取り付けた半導体パッケージの内部構造図の一例である。It is an example of the internal structure figure of the semiconductor package which attached the radiation fin which concerns on a modification. 放熱フィンを取り付けた従来技術に係る半導体パッケージの内部構造図の一例である。It is an example of the internal structure figure of the semiconductor package which concerns on the prior art which attached the radiation fin. 変形例に係る放熱フィンを取り付けた半導体パッケージの一例を示した上面図の一例である。It is an example of the top view which showed an example of the semiconductor package which attached the radiation fin which concerns on a modification. 図18において符号E−Eで示す線で本変形例に係る半導体パッケージを切断した場合の断面図の一例である。It is an example of sectional drawing at the time of cut | disconnecting the semiconductor package which concerns on this modification with the line shown with the code | symbol EE in FIG. 放熱フィンを取り付けた従来技術に係る半導体パッケージの内部構造を示した図の一例である。It is an example of the figure which showed the internal structure of the semiconductor package based on the prior art which attached the radiation fin. 第一変形例に係る半導体パッケージの上面図の一例である。It is an example of the top view of the semiconductor package which concerns on a 1st modification. 図21において符号F−Fで示す線で半導体パッケージを切断した場合の断面図の一例である。FIG. 22 is an example of a cross-sectional view in the case where the semiconductor package is cut along a line indicated by a symbol FF in FIG. 21. 図21において符号G−Gで示す線で半導体パッケージを切断した場合の断面図の一例である。FIG. 22 is an example of a cross-sectional view in the case where the semiconductor package is cut along a line indicated by reference sign GG in FIG. 21. 第二変形例に係る半導体パッケージの上面図の一例である。It is an example of the top view of the semiconductor package which concerns on a 2nd modification. 図24において符号H−Hで示す線で本変形例に係る半導体パッケージを切断した場合の断面図の一例である。FIG. 25 is an example of a cross-sectional view of the semiconductor package according to the present modification taken along the line HH in FIG. 24. 図24において符号I−Iで示す線で本変形例に係る半導体パッケージを切断した場合の断面図の一例である。FIG. 25 is an example of a cross-sectional view when the semiconductor package according to the present modification is cut along a line indicated by reference numeral II in FIG. 24.

以下、本願発明の実施形態について説明する。以下に示す実施形態は、本願発明の一態様を例示したものであり、本願発明の技術的範囲を以下の態様に限定するものではない。   Hereinafter, embodiments of the present invention will be described. The embodiment described below exemplifies one aspect of the present invention, and does not limit the technical scope of the present invention to the following aspect.

<実施形態>
図1は、本実施形態に係る半導体パッケージ用の蓋を示した図の一例である。本実施形態に係る半導体パッケージ用の蓋1は、半導体チップ及び他の部品が搭載された基板を覆う半導体パッケージ用の蓋であり、板材2を備える。板材2は、半導体チップ及び他の部品が搭載された基板を覆うように、基板に接着される部材である。よって、板材2は、半導体チップや他の部品の放熱を妨げない材質で形成されていることが好ましい。また、後述するように、半導体パッケージ用の蓋1は、基板の反りを矯正する機能を担うため、温度上昇により容易に軟化しない材質で形成されていることが好ましい。さらに、放熱体としての機能を有し、熱伝達性に優れ、且つ、温度上昇により容易に軟化しない材質としては、例えば、熱伝導率の高い銅やその他の各種金属類を挙げることができる。
<Embodiment>
FIG. 1 is an example of a diagram illustrating a lid for a semiconductor package according to the present embodiment. A lid 1 for a semiconductor package according to the present embodiment is a lid for a semiconductor package that covers a substrate on which a semiconductor chip and other components are mounted, and includes a plate 2. The plate member 2 is a member bonded to the substrate so as to cover the substrate on which the semiconductor chip and other components are mounted. Therefore, it is preferable that the board | plate material 2 is formed with the material which does not prevent the heat dissipation of a semiconductor chip or another component. Further, as will be described later, since the lid 1 for a semiconductor package has a function of correcting the warp of the substrate, it is preferably formed of a material that does not easily soften due to a temperature rise. Furthermore, examples of the material that has a function as a heat radiator, has excellent heat transfer properties, and does not easily soften due to a temperature rise include copper and other various metals having high thermal conductivity.

図2は、図1において符号A−Aで示す線で板材2を切断した場合の断面図の一例である。また、図3は、図1において符号B−Bで示す線で板材2を切断した場合の断面図の一例である。図1〜図3に示すように、板材2には、基板が接着される面(以下、接着面という)3に形成される凹部4、板材2の接着面3とその裏側の面との間を貫通する貫通孔部5、及び、凹部4と貫通孔部5とを連通する連通部6が形成されている。   FIG. 2 is an example of a cross-sectional view when the plate member 2 is cut along a line indicated by AA in FIG. Moreover, FIG. 3 is an example of a cross-sectional view when the plate member 2 is cut along a line indicated by reference numeral BB in FIG. As shown in FIGS. 1 to 3, the plate member 2 has a concave portion 4 formed on a surface (hereinafter referred to as an adhesive surface) 3 to which the substrate is bonded, between the adhesive surface 3 of the plate member 2 and the surface on the back side thereof. And a communication portion 6 that communicates the recess 4 and the through-hole portion 5 with each other.

図4は、蓋1に備わっている凹部4や貫通孔部5と、蓋1に覆われる基板11に搭載されている半導体チップ12及び他の部品13との位置関係の一例を示した図である。図4に示すように、凹部4は、基板11に搭載されている半導体チップ12に対応する部位に形成されている。また、貫通孔部5は、基板11に搭載されている他の部品13に対応する部位に形成されている。   FIG. 4 is a diagram showing an example of the positional relationship between the recess 4 and the through-hole portion 5 provided in the lid 1 and the semiconductor chip 12 and other components 13 mounted on the substrate 11 covered by the lid 1. is there. As shown in FIG. 4, the recess 4 is formed in a portion corresponding to the semiconductor chip 12 mounted on the substrate 11. In addition, the through-hole portion 5 is formed in a portion corresponding to another component 13 mounted on the substrate 11.

図5は、蓋1を基板11に接着した半導体パッケージ10の上面図の一例である。蓋1には貫通孔部5が備わっているため、図5に示すように、基板11が蓋1の板材2に覆われた状態であっても、貫通孔部5を通じて蓋1の上側から他の部品13へ物理的にアクセス可能である。よって、例えば、貫通孔部5に収容されている他の部品13のうち何れかの部品が故障もしくは部品と基板間の接合に接触不良が発生した場合、蓋1を外すことなく当該部品を交換可能である。   FIG. 5 is an example of a top view of the semiconductor package 10 in which the lid 1 is bonded to the substrate 11. Since the lid 1 is provided with the through-hole portion 5, as shown in FIG. 5, even when the substrate 11 is covered with the plate material 2 of the lid 1, the other side is provided through the through-hole portion 5 from the upper side of the lid 1 Can be physically accessed. Therefore, for example, when any one of the other components 13 accommodated in the through-hole portion 5 fails or a contact failure occurs in the bonding between the component and the board, the component is replaced without removing the lid 1. Is possible.

なお、図2から図4では、貫通孔部5の内壁が基板11から垂直に立ち上がるように図示されている。しかし、貫通孔部5は、このような形状に限定されるものではない。貫通孔部5は、例えば、接着面3側の開口部の大きさが、接着面3と反対側の開口部の大きさより狭くなっていてもよい。貫通孔部5の接着面3側の開口部の大きさが、接着面3と反対側の開口部の大きさよりも狭ければ、基板11に接触する接着面3の面積が大きくなるので、接着力を高めることが可能である。   2 to 4, the inner wall of the through-hole portion 5 is illustrated so as to rise vertically from the substrate 11. However, the through-hole part 5 is not limited to such a shape. In the through-hole portion 5, for example, the size of the opening on the bonding surface 3 side may be narrower than the size of the opening on the opposite side to the bonding surface 3. If the size of the opening on the bonding surface 3 side of the through-hole portion 5 is narrower than the size of the opening on the side opposite to the bonding surface 3, the area of the bonding surface 3 in contact with the substrate 11 is increased. It is possible to increase power.

図6は、図5において符号C−Cで示す線で半導体パッケージ10を切断した場合の断
面図の一例である。蓋1を基板11に接着した状態において、半導体チップ12は、図6に示すように、熱伝導材料(TIM:Thermal Interface Material)14を介して蓋1に接着されている。よって、半導体チップ12で発生した熱は、熱伝導材料14を経由して蓋1へ伝達される。
FIG. 6 is an example of a cross-sectional view of the semiconductor package 10 taken along the line CC in FIG. In a state where the lid 1 is bonded to the substrate 11, the semiconductor chip 12 is bonded to the lid 1 via a thermally conductive material (TIM: Thermal Interface Material) 14 as shown in FIG. 6. Therefore, the heat generated in the semiconductor chip 12 is transmitted to the lid 1 via the heat conductive material 14.

図7Aは、図5において符号D−Dで示す線で半導体パッケージ10を切断した場合の断面図の一例である。熱を伝達する材料には、様々なものが考案されているが、例えば、揮発性の溶剤に熱伝導率の高い粉末材料等を配合したものを熱伝導材料14として用いる場合、熱伝導材料14が硬化する過程で蒸発する成分が凹部4内で閉じ込められる虞がある。密閉された空間で溶剤成分等が蒸発すると、空間内の圧力が上がる。仮に、凹部4内の圧力が外部より高い場合、残圧が半導体パッケージ10の信頼性に悪影響を及ぼす虞がある。しかし、本実施形態に係る半導体パッケージ用の蓋1には、連通部6が設けられているため、凹部4内で揮発した成分は、連通部6および貫通孔部5を介して外部へ放出される。よって、凹部4内の圧力が外部より高い状態で保たれることが無い。   FIG. 7A is an example of a cross-sectional view when the semiconductor package 10 is cut along a line indicated by reference sign DD in FIG. Various materials have been devised for transferring heat. For example, when a material obtained by blending a volatile solvent with a powder material having high thermal conductivity or the like is used as the heat conducting material 14, the heat conducting material 14 is used. There is a possibility that a component that evaporates in the process of hardening is confined in the recess 4. When the solvent component or the like evaporates in the sealed space, the pressure in the space increases. If the pressure in the recess 4 is higher than the outside, the residual pressure may adversely affect the reliability of the semiconductor package 10. However, since the communication package 6 is provided in the lid 1 for a semiconductor package according to this embodiment, the components volatilized in the recess 4 are released to the outside through the communication 6 and the through hole 5. The Therefore, the pressure in the recess 4 is not kept higher than the outside.

なお、連通部6は、板材2の接着面3に形成した凹状の溝に限定されるものではない。すなわち、連通部6は、板材2が基板11に接着された状態において、凹部4と貫通孔部5とを連通可能なものであれば如何なるものであってもよい。   The communication portion 6 is not limited to the concave groove formed on the bonding surface 3 of the plate member 2. That is, the communication part 6 may be any one as long as it can communicate the recess 4 and the through-hole part 5 with the plate member 2 bonded to the substrate 11.

また、連通部6は、蓋1から省略することも可能である。例えば、熱伝導材料14が各種の成分を蒸発させないものである場合、凹部4が密閉された空間となっていても残圧の問題が生じないため、連通部6を省略可能である。   Further, the communication part 6 can be omitted from the lid 1. For example, when the heat conductive material 14 does not evaporate various components, the communication section 6 can be omitted because the problem of residual pressure does not occur even if the recess 4 is a sealed space.

図7Bは、連通部6の変形例を示した図の一例である。凹部4に残留する残圧の防止という目的に鑑みれば、連通部6は、例えば、図7Bに示すように、凹部4内の圧力を外部と同じにするために必要な大きさに制限してもよい。連通部6の大きさが、凹部4内の圧力を外部と同じにするために必要な大きさに制限されていれば、凹部4内に異物等が侵入する可能性を低下させることが可能である。   FIG. 7B is an example of a diagram illustrating a modified example of the communication unit 6. In view of the purpose of preventing the residual pressure remaining in the recess 4, the communicating portion 6 is limited to a size required to make the pressure in the recess 4 the same as the outside, as shown in FIG. 7B, for example. Also good. If the size of the communication portion 6 is limited to a size necessary for making the pressure in the concave portion 4 the same as that of the outside, it is possible to reduce the possibility that foreign matter or the like enters the concave portion 4. is there.

図8は、従来技術に係る半導体パッケージ用の蓋101を斜め下側から見た斜視図の一例である。従来技術に係る半導体パッケージ用の蓋101は、図8に示すように、基板を覆うように基板に接着される板状の板材102を備える。板材102には、接着面103に凹部104が形成されている。従来技術に係る半導体パッケージ用の蓋101に備わっている凹部104は、本実施形態に係る凹部4と異なり、基板に搭載されている全ての部品を包括的に収容する。このような蓋101を用いると、例えば、次のような問題がある。   FIG. 8 is an example of a perspective view of a lid 101 for a semiconductor package according to the prior art as viewed obliquely from below. As shown in FIG. 8, a lid 101 for a semiconductor package according to the prior art includes a plate-like plate material 102 bonded to a substrate so as to cover the substrate. A recess 104 is formed in the bonding surface 103 of the plate material 102. Unlike the recess 4 according to the present embodiment, the recess 104 provided in the lid 101 for a semiconductor package according to the prior art comprehensively accommodates all components mounted on the substrate. When such a lid 101 is used, for example, there are the following problems.

図9は、従来技術に係る半導体パッケージ用の蓋101を基板111に接着した半導体パッケージ110の内部構造図の一例である。蓋101に備わっている凹部104は、基板111に搭載されている半導体チップ112や他の部品113を包括的に収容する。また、蓋101には、蓋1に備わっていた貫通孔部5に相当する開口部類が存在しない。よって、基板111が蓋101に覆われた状態においては、蓋101の上側から他の部品113への物理的なアクセスが不可能である。従って、例えば、凹部104に収容されている何れかの部品が故障もしくは部品と基板間の接合に接触不良が発生した場合、当該部品を交換するには、蓋101を取り外す必要がある。   FIG. 9 is an example of an internal structure diagram of a semiconductor package 110 in which a semiconductor package lid 101 according to the prior art is bonded to a substrate 111. The recess 104 provided in the lid 101 comprehensively accommodates the semiconductor chip 112 and other components 113 mounted on the substrate 111. Further, the lid 101 does not have openings corresponding to the through hole 5 provided in the lid 1. Therefore, in a state where the substrate 111 is covered with the lid 101, physical access to the other components 113 from the upper side of the lid 101 is impossible. Therefore, for example, when any component housed in the recess 104 fails or a contact failure occurs in the bonding between the component and the substrate, the lid 101 needs to be removed to replace the component.

図10は、従来技術に係る半導体パッケージ用の蓋101を基板111から取り外した状態を示した図の一例である。また、図11は、基板111に搭載されている他の部品113を取り外した状態を示した図の一例である。蓋101を、例えば、図10に示すように、基板111から取り外すことにより、蓋101に覆われていた半導体チップ112や
他の部品113が外部に露出し、物理的なアクセスが可能な状態となる。これにより、例えば、図11に示すように、基板111に搭載されていた他の部品113を取り外し、正常な部品への交換等を行うことが可能となる。
FIG. 10 is an example of a diagram showing a state in which the lid 101 for a semiconductor package according to the prior art is removed from the substrate 111. FIG. 11 is an example of a diagram illustrating a state in which another component 113 mounted on the substrate 111 is removed. For example, as shown in FIG. 10, by removing the lid 101 from the substrate 111, the semiconductor chip 112 and other components 113 covered by the lid 101 are exposed to the outside and are physically accessible. Become. As a result, for example, as shown in FIG. 11, it is possible to remove another component 113 mounted on the substrate 111 and replace it with a normal component.

図12は、蓋101と熱伝導材料114とを取り除いた従来技術に係る半導体パッケージ110を示した図の一例である。例えば、基板111に搭載されている部品の交換を行った後、蓋101を再び基板111に取り付ける場合、半導体チップ112を熱伝導性材料で蓋101に接着する必要がある。よって、半導体チップ112上に残っていた熱伝導材料114の除去作業が必要となる。   FIG. 12 is an example of a diagram illustrating a semiconductor package 110 according to the prior art from which the lid 101 and the heat conductive material 114 are removed. For example, when the lid 101 is attached again to the substrate 111 after replacement of components mounted on the substrate 111, it is necessary to bond the semiconductor chip 112 to the lid 101 with a thermally conductive material. Therefore, it is necessary to remove the heat conductive material 114 remaining on the semiconductor chip 112.

このように、従来技術に係る半導体パッケージ用の蓋101を用いると、例えば、基板111に搭載されている部品の交換を行う場合に、蓋101の取り外しや熱伝導材料114の除去等を行う必要がある。すなわち、従来技術に係る蓋101を用いた半導体パッケージ110については、部品交換に多大な手間を要するため、基板111に搭載されている部品が故障もしくは部品と基板間の接合に接触不良が発生した場合、当該半導体パッケージ110については廃棄せざるを得ないのが実情である。一方、本実施形態に係る半導体パッケージ10であれば、基板11に搭載されている部品のうちの他の部品13については外部から物理的にアクセス可能な貫通孔部5に配置されているため、蓋1を取り外すことなく部品交換を行うことが可能である。   As described above, when the lid 101 for a semiconductor package according to the prior art is used, for example, when replacing a component mounted on the substrate 111, it is necessary to remove the lid 101 or remove the heat conductive material 114. There is. That is, the semiconductor package 110 using the lid 101 according to the prior art requires a great deal of time to replace the components, so that a component mounted on the substrate 111 has failed or a contact failure has occurred in the bonding between the component and the substrate. In such a case, the semiconductor package 110 must be discarded. On the other hand, in the case of the semiconductor package 10 according to the present embodiment, the other components 13 among the components mounted on the substrate 11 are arranged in the through-hole portion 5 that is physically accessible from the outside. It is possible to replace parts without removing the lid 1.

また、本実施形態に係る半導体パッケージ10であれば、他の部品13については蓋1と基板11とを接着した後に基板11に取り付けることも可能である。よって、半導体パッケージ10の製造工程の終盤で他の部品13を基板11に取り付けることにより、他の部品13に加わる熱的な影響を低減することも可能である。   Further, in the case of the semiconductor package 10 according to the present embodiment, the other components 13 can be attached to the substrate 11 after the lid 1 and the substrate 11 are bonded. Therefore, by attaching the other component 13 to the substrate 11 at the final stage of the manufacturing process of the semiconductor package 10, it is possible to reduce the thermal influence applied to the other component 13.

図13は、本実施形態に係る半導体パッケージ10を上側から見た場合の、蓋1と基板11との接着部分を示した図の一例である。本実施形態に係る半導体パッケージ用の蓋1は、板状の板材2の接着面3の中央部に凹部4を形成し、凹部4の周囲に貫通孔部5を形成したものである。よって、板材2の接着面3のうち、凹部4や貫通孔部5、連通部6が形成されていない部分は、基板11に当接し、接着されることになる。例えば、本実施形態に係る半導体パッケージ用の蓋1の場合、接着部分15は、図13に示すように、格子状に形成される。   FIG. 13 is an example of a diagram illustrating a bonding portion between the lid 1 and the substrate 11 when the semiconductor package 10 according to the present embodiment is viewed from the upper side. The lid 1 for a semiconductor package according to the present embodiment is formed by forming a recess 4 in the center of the bonding surface 3 of a plate-like plate material 2 and forming a through hole 5 around the recess 4. Therefore, a portion of the bonding surface 3 of the plate member 2 where the concave portion 4, the through-hole portion 5, and the communication portion 6 are not formed comes into contact with and adheres to the substrate 11. For example, in the case of the lid 1 for a semiconductor package according to the present embodiment, the bonding portions 15 are formed in a lattice shape as shown in FIG.

図14は、従来技術に係る半導体パッケージ110を上側から見た場合の、蓋101と基板111との接着部分を示した図の一例である。従来技術に係る半導体パッケージ用の蓋101は、板状の板材102の接着面103に、基板111に搭載されている全ての部品を収容する凹部104を形成したものである。よって、板材102の接着面103のうち、凹部104が形成されない領域は、蓋1の縁の部分となる。このため、接着部分115は、図14に示すように、蓋101の縁の部分に形成されることになる。   FIG. 14 is an example of a diagram illustrating a bonding portion between the lid 101 and the substrate 111 when the semiconductor package 110 according to the related art is viewed from the upper side. A lid 101 for a semiconductor package according to the prior art is formed by forming a recess 104 in the adhesive surface 103 of a plate-like plate material 102 to accommodate all components mounted on a substrate 111. Therefore, a region of the bonding surface 103 of the plate member 102 where the concave portion 104 is not formed is an edge portion of the lid 1. For this reason, the adhesion part 115 is formed in the edge part of the lid | cover 101, as shown in FIG.

図13及び図14を見比べると明らかなように、本実施形態に係る半導体パッケージ10は、従来技術に係る半導体パッケージ110に比べると、基板11と蓋1との接着部分が多い。特に、本実施形態に係る半導体パッケージ10は、従来技術に係る半導体パッケージ110においては接着されていない基板11の中央付近、換言すると、半導体チップ12の周辺が蓋1に接着される。よって、本実施形態に係る半導体パッケージ10は、従来技術に係る半導体パッケージ110に比べると、基板11の反りを矯正する効果が高い。   As is apparent from a comparison of FIGS. 13 and 14, the semiconductor package 10 according to the present embodiment has more bonding portions between the substrate 11 and the lid 1 than the semiconductor package 110 according to the related art. In particular, in the semiconductor package 10 according to the present embodiment, the vicinity of the center of the substrate 11 that is not bonded in the semiconductor package 110 according to the related art, in other words, the periphery of the semiconductor chip 12 is bonded to the lid 1. Therefore, the semiconductor package 10 according to the present embodiment has a higher effect of correcting the warpage of the substrate 11 than the semiconductor package 110 according to the related art.

すなわち、本実施形態に係る半導体パッケージ10は、基板11の反りが矯正されているため、基板の中央部分が蓋に接着されていない従来技術に係る半導体パッケージ110
に比べて、基板の反りに起因する半田ボールの先端の高さのばらつきが小さい。よって、各半田ボールの先端の高さの誤差が、製品としての半導体パッケージに許容されている誤差の範囲を逸脱する可能性が低くなり、不良品の発生を減らすことが可能である。
That is, in the semiconductor package 10 according to this embodiment, since the warpage of the substrate 11 is corrected, the semiconductor package 110 according to the related art in which the central portion of the substrate is not bonded to the lid.
Compared to the above, the variation in the height of the solder ball tip due to the warpage of the substrate is small. Therefore, the possibility that the error in the height of the tip of each solder ball deviates from the range of errors allowed for the semiconductor package as a product is reduced, and the occurrence of defective products can be reduced.

図15は、放熱フィン20を取り付けた半導体パッケージ10の内部構造の一例を示した図の一例である。半導体パッケージ10には、例えば、図15に示すように、蓋1及び他の部品13に熱伝導材料14で接着される放熱フィン20を取り付けることも可能である。半導体パッケージ10に放熱フィン20を取り付けた場合、半導体チップ12及び他の部品13で発生する熱は、放熱フィン20によって効果的に放熱される。   FIG. 15 is an example of a diagram illustrating an example of the internal structure of the semiconductor package 10 to which the radiation fins 20 are attached. For example, as shown in FIG. 15, the semiconductor package 10 may be provided with heat radiating fins 20 that are bonded to the lid 1 and other components 13 with a heat conductive material 14. When the radiation fins 20 are attached to the semiconductor package 10, the heat generated in the semiconductor chip 12 and other components 13 is effectively radiated by the radiation fins 20.

半導体パッケージ10に放熱フィン20を取り付ける場合、多数のフィンが設けられた基材21の下面のうち他の部品13と対応する位置に、例えば、他の部品13の熱を基材21に伝熱する凸部22を設けることが望ましい。凸部22を設けることにより、他の部品13で発生する熱についても、放熱フィン20から放熱させることが可能となる。なお、半導体パッケージ10には、放熱フィン20に代わり、例えば、水冷式の放熱部材やその他各種の放熱部材を取り付けることも可能である。   When attaching the heat radiation fin 20 to the semiconductor package 10, for example, heat of the other component 13 is transferred to the base material 21 at a position corresponding to the other component 13 on the lower surface of the base material 21 provided with a large number of fins. It is desirable to provide the convex part 22 which does. By providing the convex portions 22, it is possible to dissipate heat generated in the other components 13 from the heat radiation fins 20. For example, a water-cooled heat radiating member or other various heat radiating members can be attached to the semiconductor package 10 instead of the heat radiating fins 20.

図16は、変形例に係る放熱フィン20Aを取り付けた半導体パッケージ10の内部構造図の一例である。例えば、他の部品13が放熱フィン20による放熱を必要としない部品である場合、上記放熱フィン20に取り付けられていた凸部22は、省略することも可能である。   FIG. 16 is an example of an internal structure diagram of the semiconductor package 10 to which the radiation fins 20A according to the modification are attached. For example, when the other component 13 is a component that does not require heat radiation by the heat radiation fin 20, the convex portion 22 attached to the heat radiation fin 20 can be omitted.

図17は、放熱フィン120を取り付けた従来技術に係る半導体パッケージ110の内部構造図の一例である。半導体パッケージ110には、例えば、図17に示すように、蓋101に熱伝導材料114で接着される放熱フィン120を取り付けることも可能である。半導体パッケージ110に放熱フィン120を取り付けた場合、半導体チップ112で発生する熱は、放熱フィン120によって効果的に放熱される。しかし、他の部品113については、熱伝導材料で蓋101に接着されていないため、他の部品113で発生する熱については、放熱フィン120に放熱されない。   FIG. 17 is an example of an internal structure diagram of the semiconductor package 110 according to the prior art to which the heat radiation fin 120 is attached. For example, as shown in FIG. 17, the semiconductor package 110 may be provided with heat radiating fins 120 that are bonded to the lid 101 with a heat conductive material 114. When the radiation fins 120 are attached to the semiconductor package 110, the heat generated in the semiconductor chip 112 is effectively radiated by the radiation fins 120. However, since the other components 113 are not bonded to the lid 101 with a heat conductive material, the heat generated in the other components 113 is not radiated to the radiating fins 120.

また、仮に、他の部品113を、熱伝導材料で蓋101に接着した場合、次のような問題が生じ得る。例えば、半導体チップ112よりも発熱量の少ない他の部品113を、熱伝導材料で蓋101に接着した場合、蓋101が熱伝導材料の役割を果たし、半導体チップ112の熱が他の部品113へ伝達される可能性がある。このため、他の部品113を熱伝導材料で蓋101に接着すると、他の部品113を更に高温にする虞がある。   Also, if another component 113 is bonded to the lid 101 with a heat conductive material, the following problem may occur. For example, when another component 113 that generates less heat than the semiconductor chip 112 is bonded to the lid 101 with a heat conductive material, the lid 101 serves as a heat conductive material, and the heat of the semiconductor chip 112 is transferred to the other component 113. May be transmitted. For this reason, if the other component 113 is bonded to the lid 101 with a heat conductive material, the other component 113 may be further heated.

一方、本実施形態に係る半導体パッケージ10であれば、他の部品13の熱を放熱フィン20へ直接伝達させることが可能である。よって、従来技術に係る半導体パッケージ110に比べて、半導体チップ12から他の部品13へ熱が伝達される可能性を抑制することが可能である。なお、図15で示したように、蓋1及び他の部品13を熱伝導材料14で放熱フィン20に接着した場合、半導体チップ12の熱が他の部品13へ放熱フィン20を介して伝達され得る。しかし、放熱フィン20は、空気で冷却されている。よって、半導体チップ12から放熱フィン20を介して他の部品13へ伝達される熱の量は、半導体チップ112から蓋101を介して他の部品113へ伝達される熱の量に比べて少ないと考えられる。従って、熱に対する耐性が異なる部品同士を半導体パッケージ10に搭載した場合であっても、耐熱性の低い部品に与える熱的な影響を緩和することが可能である。   On the other hand, with the semiconductor package 10 according to the present embodiment, the heat of the other components 13 can be directly transmitted to the radiation fins 20. Therefore, it is possible to suppress the possibility that heat is transferred from the semiconductor chip 12 to the other component 13 as compared to the semiconductor package 110 according to the related art. As shown in FIG. 15, when the lid 1 and the other component 13 are bonded to the heat radiation fin 20 with the heat conductive material 14, the heat of the semiconductor chip 12 is transmitted to the other component 13 through the heat radiation fin 20. obtain. However, the radiation fin 20 is cooled with air. Therefore, the amount of heat transferred from the semiconductor chip 12 to the other component 13 via the heat radiation fin 20 is less than the amount of heat transferred from the semiconductor chip 112 to the other component 113 via the lid 101. Conceivable. Therefore, even when components having different heat resistance are mounted on the semiconductor package 10, it is possible to mitigate the thermal influence on the components having low heat resistance.

図18は、変形例に係る放熱フィン20A1,20A2を取り付けた半導体パッケージ10の一例を示した上面図の一例である。半導体チップ12から放熱フィンを介して他の
部品13へ伝達される半導体チップ12の熱量を抑制したい場合、放熱フィンを、例えば、以下のようにすることも可能である。すなわち、例えば、図18に示すように、他の部品13を冷却する放熱フィン20A1を、半導体チップ12の熱を除去する放熱フィン20A2と別体にしてもよい。
FIG. 18 is an example of a top view illustrating an example of the semiconductor package 10 to which the radiation fins 20A1 and 20A2 according to the modification are attached. When it is desired to suppress the amount of heat of the semiconductor chip 12 transmitted from the semiconductor chip 12 to the other components 13 via the radiation fins, the radiation fins can be configured as follows, for example. That is, for example, as shown in FIG. 18, the radiating fin 20 </ b> A <b> 1 that cools the other components 13 may be separated from the radiating fin 20 </ b> A <b> 2 that removes the heat of the semiconductor chip 12.

図19は、図18において符号E−Eで示す線で本変形例に係る半導体パッケージ10を切断した場合の断面図の一例である。他の部品13を冷却する放熱フィン20A1を、半導体チップ12の熱を除去する放熱フィン20A1と別体とする場合、放熱フィン20A1と放熱フィン20A1との間には、放熱フィン20A1を形成する部材よりも熱伝導率の低い空隙が介在することになる。よって、半導体チップ12から放熱フィン20A1,20A2を介して他の部品13へ伝達される熱の量は、半導体パッケージ10に放熱フィン20を取り付けた場合よりも減少させることが可能である。   FIG. 19 is an example of a cross-sectional view of the semiconductor package 10 according to the present modification taken along the line EE in FIG. When the radiating fin 20A1 that cools the other components 13 is separated from the radiating fin 20A1 that removes the heat of the semiconductor chip 12, a member that forms the radiating fin 20A1 between the radiating fin 20A1 and the radiating fin 20A1. In other words, a void having a lower thermal conductivity is interposed. Therefore, the amount of heat transferred from the semiconductor chip 12 to the other components 13 via the heat radiation fins 20A1 and 20A2 can be reduced as compared with the case where the heat radiation fins 20 are attached to the semiconductor package 10.

図20は、放熱フィンを取り付けた従来技術に係る半導体パッケージの内部構造を示した図の一例である。例えば、半導体チップ112Aを覆い、他の部品113Aについては覆わない蓋101Aを取り付けた半導体パッケージ110Aの場合、図20に示すように、蓋101Aと他の部品113Aを熱伝導材料114で蓋101Aに接着することも可能である。この場合、半導体パッケージ110に存在する放熱の問題は解消可能である。しかし、半導体パッケージ110Aの蓋101Aは、基板111Aの中央部分に接着されているため、基板111Aの反りを矯正することは構造的に不可能となる。   FIG. 20 is an example of a diagram illustrating an internal structure of a semiconductor package according to the related art to which a radiation fin is attached. For example, in the case of the semiconductor package 110A in which the lid 101A that covers the semiconductor chip 112A and does not cover the other components 113A is attached, the lid 101A and the other components 113A are attached to the lid 101A with a heat conductive material 114 as shown in FIG. It is also possible to bond. In this case, the problem of heat dissipation existing in the semiconductor package 110 can be solved. However, since the lid 101A of the semiconductor package 110A is bonded to the central portion of the substrate 111A, it is structurally impossible to correct the warp of the substrate 111A.

図21は、第一変形例に係る半導体パッケージ10Aの上面図の一例である。上記実施形態に係る半導体パッケージ10は、例えば、基板に2つの半導体チップ12A1,12A2を搭載可能なように変形してもよい。例えば、図21に示す半導体パッケージ10Aの蓋1Aには、他の部品13Aを収容する貫通孔部5Aが設けられている。よって、半導体パッケージ10Aは、蓋1Aを外すことなく、他の部品13Aへ物理的にアクセス可能である。   FIG. 21 is an example of a top view of the semiconductor package 10A according to the first modification. For example, the semiconductor package 10 according to the embodiment may be modified so that two semiconductor chips 12A1 and 12A2 can be mounted on a substrate. For example, the lid 1A of the semiconductor package 10A shown in FIG. 21 is provided with a through-hole portion 5A that accommodates another component 13A. Therefore, the semiconductor package 10A can physically access the other components 13A without removing the lid 1A.

図22は、図21において符号F−Fで示す線で半導体パッケージ10Aを切断した場合の断面図の一例である。基板11Aに2つの半導体チップ12A1,12A2を搭載する場合、半導体パッケージ10Aに用いる蓋1Aには、例えば、半導体チップ12A1,12A2をそれぞれ収容可能な大きさを有する2つの凹部4A1,4A2を形成するようにしてもよい。   FIG. 22 is an example of a cross-sectional view of the semiconductor package 10A taken along the line indicated by the reference sign FF in FIG. When two semiconductor chips 12A1 and 12A2 are mounted on the substrate 11A, the lid 1A used for the semiconductor package 10A is formed with, for example, two recesses 4A1 and 4A2 each having a size capable of accommodating the semiconductor chips 12A1 and 12A2. You may do it.

図23は、図21において符号G−Gで示す線で半導体パッケージ10Aを切断した場合の断面図の一例である。凹部4A1と凹部4A2との間には、凹部4A1と凹部4A2とを仕切るように、基板11Aに当接する部材が残されており、基板11Aに接着されている。よって、本変形例に係る半導体パッケージ10Aは、従来技術に係る半導体パッケージ110に比べると、基板11の反りを矯正する効果が高い。   FIG. 23 is an example of a cross-sectional view of the semiconductor package 10A taken along the line GG in FIG. A member that contacts the substrate 11A is left between the recess 4A1 and the recess 4A2 so as to partition the recess 4A1 and the recess 4A2, and is bonded to the substrate 11A. Therefore, the semiconductor package 10A according to the present modification has a higher effect of correcting the warp of the substrate 11 than the semiconductor package 110 according to the related art.

図24は、第二変形例に係る半導体パッケージ10Bの上面図の一例である。例えば、図24に示すように、半導体チップ12Bの周囲に配置される他の部品13Bの数が比較的少ない場合、貫通孔部5Bは、他の部品13Bの収容に必要な大きさに制限してもよい。貫通孔部5Bを他の部品13Bの収容に必要な大きさに制限すると、蓋1Bと基板との接着部分の面積が増加し、また、蓋1Bの剛性も向上するため、基板の反りを矯正する効果を高めることが可能である。   FIG. 24 is an example of a top view of a semiconductor package 10B according to the second modification. For example, as shown in FIG. 24, when the number of other components 13B arranged around the semiconductor chip 12B is relatively small, the through-hole portion 5B is limited to a size necessary for accommodating the other components 13B. May be. If the through-hole portion 5B is limited to a size necessary for accommodating another component 13B, the area of the bonding portion between the lid 1B and the substrate increases, and the rigidity of the lid 1B is improved, so that the warpage of the substrate is corrected. It is possible to enhance the effect.

図25は、図24において符号H−Hで示す線で本変形例に係る半導体パッケージ10Bを切断した場合の断面図の一例である。蓋1Bには、凹部4Bと貫通孔部5Bとを連通する連通部6Bが形成されている。よって、例えば、揮発性の溶剤に熱伝導性の粉末材料
等を配合したものを熱伝導材料14Bとして用いた場合であっても、凹部4B内で揮発した成分は、連通部6Bおよび貫通孔部5Bを介して外部へ放出される。よって、凹部4B内の圧力が外部より高い状態で保たれることが無い。
FIG. 25 is an example of a cross-sectional view of the semiconductor package 10B according to the present modification taken along the line HH in FIG. The lid 1B is formed with a communication portion 6B that allows the recess 4B and the through hole portion 5B to communicate with each other. Therefore, for example, even when a material obtained by blending a volatile solvent with a heat conductive powder material or the like is used as the heat conductive material 14B, the components volatilized in the recesses 4B are separated from the communicating portion 6B and the through hole portion. It is discharged to the outside through 5B. Therefore, the pressure in the recess 4B is not kept higher than the outside.

図26は、図24において符号I−Iで示す線で本変形例に係る半導体パッケージ10Bを切断した場合の断面図の一例である。凹部4Bと連通部6Bとの間には、凹部4Bと連通部6Bとを仕切るように、基板11Bに当接する部材が残されており、基板11Bに接着されている。よって、本変形例に係る半導体パッケージ10Bは、従来技術に係る半導体パッケージ110に比べると、基板11Bの反りを矯正する効果が高い。   FIG. 26 is an example of a cross-sectional view of the semiconductor package 10B according to the present modification taken along the line II in FIG. A member that contacts the substrate 11B is left between the recess 4B and the communication portion 6B so as to partition the recess 4B and the communication portion 6B, and is bonded to the substrate 11B. Therefore, the semiconductor package 10B according to this modification has a higher effect of correcting the warp of the substrate 11B than the semiconductor package 110 according to the related art.

1,1A,1B,101,101A・・蓋:2,102・・板材:3,103・・接着面:4,4A1,4A2,4B,104・・凹部:5,5A,5B・・貫通孔部:6,6B・・連通部:10,10A,10B,110,110A・・半導体パッケージ:11,11A,11B,111,111A・・基板:12,12A1,12A2,12B,112,112A・・半導体チップ:13,13A,13B,113,113A・・他の部品:14,14B,114・・熱伝導材料:15,115・・接着部分:20,20A,20A1,20A2,120,120A・・放熱フィン:21・・基材:22・・凸部: 1, 1A, 1B, 101, 101A ... Lid: 2, 102 ... Plate material: 3, 103 ... Adhesive surface: 4, 4A1, 4A2, 4B, 104 ... Recess: 5, 5A, 5B ... Through-hole Part: 6, 6B Communication unit: 10, 10A, 10B, 110, 110A Semiconductor package: 11, 11A, 11B, 111, 111A Substrate: 12, 12A1, 12A2, 12B, 112, 112A Semiconductor chip: 13, 13A, 13B, 113, 113A .. Other parts: 14, 14B, 114 .. Thermal conductive material: 15, 115 .. Adhesive parts: 20, 20A, 20A1, 20A2, 120, 120A .. Radiating fins: 21 .. Base material: 22 .. Projection:

Claims (2)

基板と、
前記基板上に搭載された半導体チップ及び他の部品と
前記基板に接着され板材と、を有し、
前記板材の前記基板が接着される面に形成され、前記半導体チップを収容する凹部と、
前記板材の両面に開口させて前記凹部と異なる位置に形成され、前記他の部品を収容し、全体が前記他の部品よりも平面視で大きい貫通孔部と、を備える、
半導体パッケージ。
A substrate,
The semiconductor chip and other parts products mounted on the substrate,
A plate material bonded to the substrate ,
A recess formed on the surface of the plate to which the substrate is bonded, and housing the semiconductor chip;
Is formed at a position different from the concave portion is opened on both sides of the plate, to accommodate the other components, and a large through hole in a plan view than entirely the other part,
Semiconductor package.
前記板材に接着され第一の放熱部材と、
前記貫通孔部に収容された前記他の部品に接着され第二の放熱部材と、を更に備える、
請求項に記載の半導体パッケージ。
A first heat radiating member adhered to the plate,
Further comprising a second heat radiating member adhered to the other parts housed in the through hole,
The semiconductor package according to claim 1 .
JP2012125429A 2012-05-31 2012-05-31 Semiconductor package Expired - Fee Related JP6060527B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2012125429A JP6060527B2 (en) 2012-05-31 2012-05-31 Semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2012125429A JP6060527B2 (en) 2012-05-31 2012-05-31 Semiconductor package

Publications (2)

Publication Number Publication Date
JP2013251412A JP2013251412A (en) 2013-12-12
JP6060527B2 true JP6060527B2 (en) 2017-01-18

Family

ID=49849812

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2012125429A Expired - Fee Related JP6060527B2 (en) 2012-05-31 2012-05-31 Semiconductor package

Country Status (1)

Country Link
JP (1) JP6060527B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6351371B2 (en) * 2014-05-19 2018-07-04 太陽誘電株式会社 Elastic wave device

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57124456A (en) * 1981-01-26 1982-08-03 Mitsubishi Electric Corp Semiconductor device
JPS6020538A (en) * 1983-07-15 1985-02-01 Hitachi Ltd Semiconductor device
JP3676091B2 (en) * 1998-08-10 2005-07-27 富士通株式会社 Semiconductor device
JP2005136272A (en) * 2003-10-31 2005-05-26 Hitachi Cable Ltd Semiconductor device for mounting high frequency component
JP4691455B2 (en) * 2006-02-28 2011-06-01 富士通株式会社 Semiconductor device

Also Published As

Publication number Publication date
JP2013251412A (en) 2013-12-12

Similar Documents

Publication Publication Date Title
CN106057747B (en) Semiconductor package including heat spreader and method of manufacturing the same
US10453802B2 (en) Semiconductor package structure, semiconductor device and method for manufacturing the same
TWI464850B (en) Semiconductor package module
JP5898919B2 (en) Semiconductor device
JP5899768B2 (en) Semiconductor package, wiring board unit, and electronic device
JP2008091714A (en) Semiconductor device
US8779603B2 (en) Stacked semiconductor device with heat dissipation
CN111446217A (en) Semiconductor device with a plurality of semiconductor chips
JP2006073651A (en) Semiconductor device
US7786571B2 (en) Heat-conductive package structure
US9653373B2 (en) Semiconductor package including heat spreader and method for manufacturing the same
JP4593616B2 (en) Semiconductor device
CN111627871A (en) Semiconductor package
JP2007305761A (en) Semiconductor device
KR102228461B1 (en) Semiconductor Package Device
US20080036077A1 (en) Package structure and heat sink module thereof
KR101069288B1 (en) Semiconductor package
JP6060527B2 (en) Semiconductor package
JP2017126668A (en) Semiconductor package
US7310224B2 (en) Electronic apparatus with thermal module
JP2007281201A (en) Semiconductor device
US11177189B2 (en) Module including heat dissipation structure
KR20180023488A (en) Semiconductor Package and Manufacturing Method for Semiconductor Package
JP6323672B2 (en) Semiconductor device and manufacturing method thereof
TWI619411B (en) Interconnect structure

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20150128

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20150619

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20151113

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20151117

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20160114

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20160607

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20160901

A911 Transfer to examiner for re-examination before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20160909

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20161115

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20161128

R150 Certificate of patent or registration of utility model

Ref document number: 6060527

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

LAPS Cancellation because of no payment of annual fees