JP6030033B2 - Memory device - Google Patents

Description

  The present invention relates to a memory device in which reading and writing are performed in synchronization with different clock signals, for example, an asynchronous FIFO memory device.

  A FIFO memory device is generally used as a buffer for temporarily storing data. In particular, when data is exchanged between circuit blocks synchronized with different clock signals, an asynchronous FIFO memory device that can operate even when reading and writing are asynchronous is used.

FIG. 16 is a diagram showing a configuration of a conventional asynchronous FIFO memory device described in Patent Document 1. In FIG.
In general, a FIFO memory device includes a counter that generates a write destination address (write pointer), a counter that generates a read destination address (read pointer), and a comparison circuit for the write pointer and the read pointer. This comparison circuit generates a signal indicating the current storage state (full state / empty state) and the number of data stored.
The conventional asynchronous FIFO memory device 3 shown in FIG. 16 has a circuit area (WCLK domain) that operates based on a write clock signal WCLK and a circuit area (RCLK domain) that operates based on a read clock signal RCLK. Have. A counter 32_1 that generates a write pointer is provided in the WCLK domain, and a counter 33_1 that generates a read pointer is provided in the RCLK domain. Since the write pointer and the read pointer are generated in different clock domains, the comparison circuit is also provided independently in each clock domain (32_5, 33_5).

  Further, in the asynchronous FIFO memory device 3 shown in FIG. 16, since the write pointer and the read pointer need to be compared in the comparison circuit (32_5, 33_5) provided in each of the two clock domains, it is generated in another clock domain. A synchronization circuit for synchronizing the pointers provided is provided in each clock domain (32_2, 33_2).

  Further, in the counters 32_1 and 33_1 of the asynchronous FIFO memory device 3 shown in FIG. 16, the write pointer and the read pointer are generated as gray codes. In the case of a code in which a plurality of bits can be changed at the same time (binary code, etc.), there is a possibility that the code is erroneously converted into a completely different code at the time of synchronization. Johnson counter codes, etc.) have the advantage that no such erroneous conversion occurs. However, the gray code has a bit length longer than that of the binary code, and if the comparison process is performed as it is, the circuit scale becomes large. Therefore, in the asynchronous FIFO memory device 3 shown in FIG. A circuit for converting each pointer from gray code to binary code is provided (32_3, 32_4, 33_3, 33_4).

JP 2010-268302 A

  In the asynchronous FIFO memory device 3 shown in FIG. 16, the pointer generation counter (32_1, 33_1) and the comparison circuit (32_5, 33_5) are provided in two clock domains (WCLK domain, RCLK domain), respectively. A synchronization circuit (32_2, 33_2) is required to refer to pointers generated in the other clock domain. Also, a gray code to binary code conversion circuit (32_3, 32_4, 33_3, 33_4) is required to prevent erroneous conversion due to synchronization of multi-bit pointers. Therefore, there is a problem that the circuit scale becomes large and the design becomes complicated.

  The present invention has been made in view of such circumstances, and an object thereof is to provide a memory device that can reduce the circuit scale while being able to read and write in synchronization with different clock signals. There is.

  A memory device according to the present invention is a memory device that writes data in synchronization with a first clock signal and reads data in synchronization with a second clock signal, wherein the writing is synchronized with the first clock signal. When a request signal is input, a read wait signal is output in which the write request signal is synchronized with the second clock signal, and when a read request signal is input in synchronization with the second clock signal, the read request signal is output A request arbitration unit that outputs a write wait signal synchronized with the first clock signal, and a write enable signal generated on condition that the write wait signal is not output in synchronization with the first clock signal. When input, the first clock signal is selected and output, and is generated on condition that the read wait signal is not output. When a read enable signal is input in synchronization with the second clock signal, the clock selection unit selects and outputs the second clock signal; and when the write enable signal is input, the clock selection unit selects When data is written to the address corresponding to the write pointer in synchronization with the clock signal and the read enable signal is input, the data corresponding to the read pointer is synchronized with the clock signal selected by the clock selection unit. When a memory unit that reads data from an address, the write enable signal is input, a write pointer update unit that updates the write pointer in synchronization with the clock signal selected by the clock selection unit, and the read enable signal When input, the clock selection unit A read pointer update unit that updates the read pointer in synchronization with the selected clock signal, and a status signal related to the number of data stored in the memory unit based on the write pointer and the read pointer. And a state signal generation unit.

In the memory device, when a write request signal synchronized with the first clock signal is input, a read wait signal in which the write request signal is synchronized with the second clock signal is output from the request arbitration unit, and the read While the wait signal is output, generation of the read enable signal is awaited. When a read request signal synchronized with the second clock signal is input, a write wait signal in which the read request signal is synchronized with the first clock signal is output from the request arbitration unit, and the write wait signal is output. During this time, the generation of the write enable signal is awaited. When the write enable signal is input, the write clock signal is selected by the clock selection unit, and data is written to the memory unit in synchronization with the selected write clock signal. When the read enable signal is input, the read clock signal is selected by the clock selection unit, and data is read from the memory unit in synchronization with the selected read clock signal.
As described above, in the memory device, the input timings of both are adjusted so that the write enable signal for enabling the write operation and the read enable signal for enabling the read operation do not compete with each other.
In the memory device, the memory unit, the write pointer update unit, the read pointer update unit, and the status signal generation unit operate in synchronization with a single clock signal selected by the clock selection unit.
Therefore, the memory device does not require a circuit for synchronizing pointers (write pointer, read pointer) and a circuit for converting the code of the pointer. Further, it is not necessary to provide a circuit for generating a status signal on each of the writing side and the reading side.

  Preferably, the request arbitration unit includes a first synchronization unit that synchronizes the read request signal with the first clock signal, and a second synchronization unit that synchronizes the write request signal with the second clock signal. And an arbitration control unit. The arbitration control unit, when a signal obtained by synchronizing the read request signal with the first clock signal (hereinafter referred to as “first synchronization signal”) is output in the first synchronization unit, The input of the write request signal to the second synchronization unit may be suppressed, or a signal obtained by synchronizing the write request signal with the second clock signal (hereinafter referred to as “second synchronization signal”). .) May be output from the second synchronization unit, the input of the read request signal to the first synchronization unit may be suppressed.

  According to the above configuration, the first synchronization signal can be output as the write wait signal, the second synchronization signal can be output as the read wait signal, and the write wait signal and the read wait signal can be output. It is possible to prevent both the write operation and the read operation from entering a standby state due to a conflict with the wait signal.

  Preferably, the arbitration control unit receives the write request signal when the write request signal is input, on the condition that the first synchronization signal is not output in the first synchronization unit. While holding in synchronization with the clock signal and inputting the held write request signal to the second synchronization unit, when holding the write request signal, the output of the write wait signal is suppressed, When the input of the write request signal is completed, the holding of the write request signal is released, and when the write request signal is not held, the write waiting according to the first synchronization signal of the first synchronization unit is released. A signal may be output.

  According to the above configuration, when the write request signal is input when the first synchronization signal is not output in the first synchronization unit, the write request signal is synchronized with the first clock signal. Are held in the arbitration control unit, and the held write request signal is input to the second synchronization unit. While the write request signal is held in the arbitration control unit, the output of the write wait signal is suppressed. When the input of the write request signal ends, the arbitration control unit releases the holding of the write request signal. When the write request signal is not held in the arbitration control unit, the write wait signal corresponding to the first synchronization signal of the first synchronization unit is output from the arbitration control unit. When the first synchronization signal is output from the first synchronization unit when the write request signal is not held in the arbitration control unit, the arbitration is performed while the output of the first synchronization signal continues. Since the write request signal is not held in the control unit, the input of the write request signal to the second synchronization unit is suppressed.

  Preferably, when the read request signal is input, the arbitration control unit outputs the read request signal to the second on condition that the second synchronization signal is not output in the second synchronization unit. While holding in synchronization with the clock signal, the held read request signal is input to the first synchronization unit, and when holding the read request signal, the output of the read waiting signal is suppressed, When the input of the read request signal is finished, the holding of the read request signal is canceled, and when the read request signal is not held, the read waiting according to the second synchronization signal of the second synchronization unit is released. A signal may be output.

  According to the above configuration, when the read request signal is input when the second synchronization signal is not output in the second synchronization unit, the read request signal is synchronized with the second clock signal. Are held in the arbitration control unit, and the held read request signal is input to the first synchronization unit. While the read request signal is held in the arbitration control unit, the output of the read wait signal is suppressed. When the input of the read request signal ends, the arbitration control unit releases the holding of the read request signal. When the read request signal is not held in the arbitration control unit, the read wait signal corresponding to the second synchronization signal of the second synchronization unit is output from the arbitration control unit. When the second synchronization signal is output from the second synchronization unit when the read request signal is not held in the arbitration control unit, the arbitration is performed while the output of the second synchronization signal continues. Since the read request signal is not held in the control unit, the input of the read request signal to the first synchronization unit is suppressed.

  Preferably, the arbitration control unit outputs the second synchronization signal when the second synchronization signal is output from the second synchronization unit on the condition that the read request signal is not input. The second synchronization signal is held in synchronization with the second clock signal, the held second synchronization signal is output as the read waiting signal, and when the second synchronization signal is held, the first synchronization unit When the output of the second synchronization signal from the second synchronization unit is terminated, the holding of the second synchronization signal is canceled and the read waiting signal is output. When the processing is terminated and the second synchronization signal is not held, a signal corresponding to the input read request signal may be input to the first synchronization unit.

  According to the above configuration, when the second synchronization signal is output from the second synchronization unit when the read request signal is not input, the second synchronization signal is output from the arbitration control unit. While being held in synchronization with the second clock signal, the held second synchronization signal is output as the read waiting signal. While the second synchronization signal is held in the arbitration control unit, input of the read request signal to the first synchronization unit is suppressed. When the output of the second synchronization signal from the second synchronization unit ends, the arbitration control unit releases the holding of the second synchronization signal and the output of the read waiting signal ends. When the second synchronization signal is not held in the arbitration control unit, a signal corresponding to the input read request signal is input to the first synchronization unit. When the read request signal is input when the second synchronization signal is not held in the arbitration control unit, the second synchronization signal is input in the arbitration control unit while the input of the read request signal continues. Is not held, so that the output of the read waiting signal is suppressed.

  Preferably, the arbitration control unit outputs the first synchronization signal when the first synchronization signal is output from the first synchronization unit on the condition that the write request signal is not input. The first synchronization signal is held in synchronization with the first clock signal, and the held first synchronization signal is output as the write wait signal. When the first synchronization signal is held, the second synchronization unit When the output of the first synchronization signal from the first synchronization unit is terminated, the holding of the first synchronization signal is released and the write wait signal is output. When the processing is terminated and the first synchronization signal is not held, a signal corresponding to the input write request signal may be input to the second synchronization unit.

  According to the above configuration, when the first synchronization signal is output from the first synchronization unit when the write request signal is not input, the first synchronization signal is While being held in synchronization with the first clock signal, the held first synchronization signal is output as the write wait signal. While the first synchronization signal is held in the arbitration control unit, the input of the write request signal to the second synchronization unit is suppressed. When the output of the first synchronization signal from the first synchronization unit ends, the arbitration control unit releases the holding of the first synchronization signal and ends the output of the write wait signal. When the first synchronization signal is not held in the arbitration control unit, a signal corresponding to the input write request signal is input to the second synchronization unit. When the write request signal is input when the first synchronization signal is not held in the arbitration control unit, the first synchronization signal is input in the arbitration control unit while the input of the write request signal continues. Is not held, so that the output of the write wait signal is suppressed.

  Preferably, the memory devices operate in synchronization with a clock signal selected by the clock selection unit, and are connected in cascade so as to constitute a shift register for transferring serial data when performing a scan test. Flip-flops. In this case, the clock selection unit selects and outputs either the first clock signal or the second clock signal in the first operation mode in which the plurality of flip-flops constitute the shift register. It's okay. The clock selection unit selects and outputs the first clock signal when the write enable signal is input in the second operation mode in which data is held in the plurality of flip-flops. When the read enable signal is input, the second clock signal may be selected and output.

  According to the present invention, the memory unit, the write pointer update unit, the read pointer update unit, and the status signal generation unit operate in synchronization with a single clock signal selected by the clock selection unit. No pointer synchronization or code conversion as in the apparatus is required, and it is not necessary to provide a state signal generation unit in each of the writing system and the reading system, so that the circuit scale can be reduced.

It is a figure which shows an example of the input-output signal of the asynchronous FIFO memory device based on embodiment of this invention. It is a figure which shows an example of a structure of the asynchronous FIFO memory device based on embodiment of this invention. It is a figure which shows an example of a structure of the request arbitration part in the asynchronous FIFO memory device which concerns on the 1st Embodiment of this invention. FIG. 6 is a timing diagram for explaining an example of the operation of the asynchronous FIFO memory device according to the first embodiment, and shows a case where a write process and a read process are executed without waiting. FIG. 6 is a timing diagram for explaining an example of the operation of the asynchronous FIFO memory device according to the first embodiment, showing a case where a write process is awaited for a preceding read process. FIG. 6 is a timing chart for explaining an example of the operation of the asynchronous FIFO memory device according to the first embodiment, showing a case where a read process is waited for a preceding write process. It is a figure which shows an example of a structure of the request | requirement arbitration part in the asynchronous FIFO memory device based on the 2nd Embodiment of this invention. FIG. 10 is a timing chart for explaining an example of the operation of the asynchronous FIFO memory device according to the second embodiment, and shows a case where a read process is waited for a preceding write process. FIG. 10 is a timing diagram for explaining an example of the operation of the asynchronous FIFO memory device according to the second embodiment, and shows a case where a write process is waited for a preceding read process. It is a figure which shows an example of a structure of the request arbitration part in the asynchronous FIFO memory device which concerns on the 3rd Embodiment of this invention. FIG. 10 is a timing chart for explaining an example of the operation of the asynchronous FIFO memory device according to the third embodiment, and shows a case where a read process is waited for a preceding write process. FIG. 10 is a timing chart for explaining an example of the operation of the asynchronous FIFO memory device according to the third embodiment, and shows a case where a write process is waited for a preceding read process. It is a figure which shows an example of a structure of the asynchronous FIFO memory device based on the 4th Embodiment of this invention. It is a figure which shows an example of a structure of the clock selection part in the asynchronous FIFO memory device based on 4th Embodiment. It is a figure which shows an example of a clock gating circuit. It is a figure which shows the structure of the conventional asynchronous FIFO memory device.

<First Embodiment>
As a first embodiment of the present invention, an asynchronous FIFO memory device to which the present invention is applied will be described.

FIG. 1 is a diagram illustrating an example of input / output signals of the asynchronous FIFO memory device 1 according to the first embodiment.
Signals input / output in the asynchronous FIFO memory device 1 are divided into signals synchronized with the write clock signal WCLK and signals synchronized with the read clock signal RCLK. The write request signal WREQ, the write enable signal WEN, the write data WD, and the write wait function enable signal W_WAIT_EN are input signals synchronized with the write clock signal WCLK, and the write wait signal W_WAIT and the write status signal W_NUM / FULL are write clock signals. This is an output signal synchronized with WCLK. On the other hand, the read request signal RREQ, the read enable signal REN, and the read wait function enable signal R_WAIT_EN are input signals synchronized with the read clock signal RCLK, and the read data RD, the read wait signal R_WAIT, and the read status signal R_NUM / FULL are read. The output signal is synchronized with the clock signal RCLK.

  When writing the data WD to the asynchronous FIFO memory device 1, the writing side device inputs the write request signal WREQ to the asynchronous FIFO memory device 1 in advance. The asynchronous FIFO memory device 1 synchronizes the write request signal WREQ with the read clock signal RCLK and outputs it to the read side device as a read wait signal R_WAIT described later.

  The device on the writing side checks whether or not a write wait signal W_WAIT is output from the asynchronous FIFO memory device 1 after a predetermined time has elapsed since the write request signal WREQ was input to the asynchronous FIFO memory device 1. When the write wait signal W_WAIT is not output, the writing side device inputs the write enable signal WEN to the asynchronous FIFO memory device 1. When the write enable signal WEN is input, the asynchronous FIFO memory device 1 takes in the data WD in synchronization with the write clock signal WCLK and stores it in the storage area. When the write wait signal W_WAIT is output from the asynchronous FIFO memory device 1, the write side device inputs the write enable signal WEN to the asynchronous FIFO memory device 1 until the output of the write wait signal W_WAIT is completed (negotiated). To wait.

  On the other hand, when reading data RD from the asynchronous FIFO memory device 1, the reading side device inputs a read request signal RREQ to the asynchronous FIFO memory device 1 in advance. The asynchronous FIFO memory device 1 synchronizes the read request signal RREQ with the write clock signal WCLK, and outputs it to the write side device as the write wait signal W_WAIT described above.

  The device on the reading side checks whether or not a read wait signal R_WAIT is output from the asynchronous FIFO memory device 1 after a predetermined time has elapsed since the read request signal RREQ was input to the asynchronous FIFO memory device 1. When the read wait signal R_WAIT is not output, the read side device inputs the read enable signal REN to the asynchronous FIFO memory device 1. When the read enable signal REN is input, the asynchronous FIFO memory device 1 reads the data RD from the storage area in synchronization with the read clock signal RCLK. When the read wait signal R_WAIT is output from the asynchronous FIFO memory device 1, the read side device inputs the read enable signal REN to the asynchronous FIFO memory device 1 until the output of the read wait signal R_WAIT ends (negates). To wait.

As described above, the write wait signal W_WAIT for waiting for the write operation is a signal obtained by synchronizing the read request signal RREQ with the write clock signal WCLK. The read-side device asynchronously reads the read request signal RREQ sufficiently before the read enable signal REN so that the asynchronous FIFO memory device 1 has sufficient time to synchronize the read request signal RREQ with the write wait signal W_WAIT. Input to the FIFO memory device 1. Further, the reading side device holds the input of the read request signal RREQ until the input of the enable signal REN is completed. As a result, since the write wait signal W_WAIT is output to the writing side device when the read enable signal REN is input, it is possible to prevent writing during the read.
The write wait function valid signal W_WAIT_EN is a signal for setting the output of the write wait signal W_WAIT valid or invalid. When the write wait function enable signal W_WAIT_EN is in an invalid state, the asynchronous FIFO memory device 1 stops outputting the write wait signal W_WAIT.

The read wait signal R_WAIT for waiting for the read operation is a signal obtained by synchronizing the write request signal WREQ with the read clock signal RCLK as described above. The device on the writing side sets the write request signal WREQ sufficiently before the write enable signal WEN so that the time for synchronizing the write request signal WREQ with the read wait signal R_WAIT is sufficiently secured in the asynchronous FIFO memory device 1. Input to the asynchronous FIFO memory device 1. The writing side device holds the input of the write request signal WREQ until the input of the write enable signal WEN is completed. As a result, since the read wait signal R_WAIT is output to the read side device when the write enable signal WEN is input, it is possible to prevent the read from being performed at the time of writing.
The read wait function valid signal R_WAIT_EN is a signal for setting the output of the read wait signal R_WAIT valid or invalid. When the read wait function valid signal R_WAIT_EN is in an invalid state, the asynchronous FIFO memory device 1 stops outputting the read wait signal R_WAIT.

  The write state signal W_NUM / FULL and the read state signal R_NUM / FULL are signals indicating states related to the number of data stored in the asynchronous FIFO memory device 1. The write state signal W_NUM / FULL indicates the number of data accumulated (or writable) in the memory unit 30 and whether or not the upper limit (full state) of the number of data writable in the memory unit 30 has been reached. . The read state signal R_NUM / FULL indicates the number of data accumulated (or readable) in the memory unit 30 and whether or not the lower limit (empty state) of the number of data readable from the memory unit 30 has been reached. . The writing side device and the reading side device control writing and reading of data in the asynchronous FIFO memory device 1 based on these signals.

FIG. 2 is a diagram illustrating an example of the configuration of the asynchronous FIFO memory device 1 according to the first embodiment.
As shown in FIG. 2, for example, the asynchronous FIFO memory device 1 includes a request arbitration unit 10, a clock selection unit 20, a memory unit 30, a write pointer update unit 40, a read pointer update unit 50, and a status signal generation unit. 60.

  The request arbitration unit 10 is a circuit that performs arbitration so as to prevent competition between a write operation and a read operation, and a write request signal WREQ input from a write side device and a read request signal input from a read side device. In response to RREQ, a write request signal WREQ for waiting the read process is output at the time of writing, and a write wait signal W_WAIT for waiting the write process is output at the time of reading.

  That is, when the write request signal WREQ synchronized with the write clock signal WCLK is input by the writing side device, the request arbitration unit 10 synchronizes the write request signal WREQ with the read clock signal RCLK, and reads it as a read wait signal R_WAIT. Output to the device. When the read request signal RREQ synchronized with the read clock signal RCLK is input by the read side device, the request arbitration unit 10 synchronizes the read request signal RREQ with the write clock signal WCLK, and writes it as a write wait signal W_WAIT. Output to the device.

  The request arbitration unit 10 prevents the read wait signal R_WAIT or the write wait signal W_WAIT from being in a standby state by preventing both the read and write from being in a standby state due to the simultaneous output of both the read wait signal R_WAIT and the write wait signal W_WAIT. Either one is output with priority over the other. For example, the request arbitration unit 10 suppresses the output of the other signal when outputting one signal.

  FIG. 3 is a diagram illustrating an example of the configuration of the request arbitration unit 10 in the asynchronous FIFO memory device 1 according to the first embodiment. The request arbitration unit 10 illustrated in FIG. 3 includes a first synchronization unit 11, a second synchronization unit 12, and an arbitration control unit 15.

The first synchronization unit 11 synchronizes the read request signal RREQ input from the device on the read side with the write clock signal WCLK, and outputs it as a write wait signal W_WAIT.
The second synchronization unit 12 synchronizes the write request signal WREQ input from the writing side device via the arbitration control unit 15 with the read clock signal RCLK and outputs it as a read wait signal R_WAIT.

  The arbitration control unit 15 suppresses input of the write request signal WREQ to the second synchronization unit 12 when a signal obtained by synchronizing the read request signal RREQ with the write clock signal WCLK is output from the first synchronization unit 11. To do. In the example of FIG. 3, the arbitration control unit 15 is a gate circuit that performs a logical product operation. Input to section 12. When the output value of the first synchronization unit 11 is “0”, the write request signal WREQ is input to the second synchronization unit 12 as it is, but when the output value of the first synchronization unit 11 becomes “1” ( When the write wait signal W_WAIT is output), the input signal of the second synchronization unit 12 is “0” regardless of whether the write request signal WREQ is input. As a result, when both the read request signal RREQ and the write request signal WREQ are input, the output of the write wait signal W_WAIT is prioritized and the write processing enters a standby state.

In the request arbitration unit 10 shown in FIG. 3, the arbitration control unit 15 is provided so that the read request signal RREQ has priority over the write request signal WREQ. However, in another example of this embodiment, the write request signal WREQ is provided. May be provided to give priority to the read request signal RREQ. For example, when a gate circuit similar to that shown in FIG. 3 is provided on the input side of the first synchronization unit 11 and a read waiting signal R_WAIT is output from the second synchronization unit 12, reading to the first synchronization unit 11 is performed. The input of the request signal RREQ may be suppressed.
The above is the description of the request arbitration unit 10.

Returning to the description of FIG.
The clock selection unit 20 is a circuit that selects either the write clock signal WCLK or the read clock signal RCLK and outputs the selected clock signal MUX_CLK. That is, when the write enable signal WEN is input in synchronization with the write clock signal WCLK from the write side device, the clock selection unit 20 selects and outputs the write clock signal WCLK, and the read clock signal from the read side device. When the read enable signal REN is input in synchronization with RCLK, the read clock signal RCLK is selected and output.

  When the write enable signal WEN is input from the writing device, the memory unit 30 writes the data WD to an address corresponding to the write pointer WP in synchronization with the selected clock signal MUX_CLK. Further, when the read enable signal REN is input from the read side device, the memory unit 30 reads the data RD from the address corresponding to the read pointer RP in synchronization with the selected clock signal MUX_CLK.

  The write pointer update unit 40 is a circuit that generates a write pointer WP that designates a write destination address of the data WD in the memory unit 30, and updates the write pointer WP every time the data WD is written in the memory unit 30. . That is, when the write enable signal WEN is input from the writing side device, the write pointer update unit 40 updates the write pointer WP in synchronization with the selected clock signal MUX_CLK.

  The read pointer update unit 50 is a circuit that generates a read pointer RP that designates a read source address of the data RD in the memory unit 30, and updates the read pointer RP every time the data RD is read in the memory unit 30. . That is, when the read enable signal REN is input from the read-side device, the read pointer update unit 50 updates the read pointer RP in synchronization with the selected clock signal MUX_CLK.

  The write pointer update unit 40 and the read pointer update unit 50 are configured using, for example, a counter that generates a binary code.

  Based on the write pointer WP and the read pointer RP, the status signal generator 60 generates status signals (write status signal W_NUM / FULL, read status signal R_NUM / FULL) related to the number of data stored in the memory unit 30. .

When data is written (when the read waiting signal R_WAIT is output from the request arbitration unit 10), the status signal generation unit 60 outputs a status signal synchronized with the write clock signal WCLK, and the data is read. In the case (when the write wait signal W_WAIT is output from the request arbitration unit 10), a state signal synchronized with the read clock signal RCLK is output.
Therefore, the device on the writing side acquires the write state signal W_NUM / FULL synchronized with the write clock signal WCLK (or does not change statically) from the state signal generation unit 60 except for the period in which the write wait signal W_WAIT is output. it can.
Further, the reading-side device acquires from the state signal generation unit 60 the read state signal R_NUM / FULL that is synchronized with (or does not change statically) the read clock signal RCLK except for the period in which the read wait signal R_WAIT is output. it can.

  Here, the operation of the asynchronous FIFO memory device 1 according to the first embodiment having the above-described configuration will be described with reference to the timing diagrams of FIGS.

  First, with reference to the timing chart of FIG. 4, the operation when the writing process and the reading process are executed without waiting will be described.

  When writing, the writing side device first starts supplying the write clock signal WCLK, and then asynchronously sends the write request signal WREQ (FIG. 4B) and the write data WD (FIG. 4D). Input to the FIFO memory device 1 (t11). The request arbitration unit 10 receives the write request signal WREQ, but does not output the read wait signal R_WAIT (FIG. 4 (J)) since the read clock signal RCLK is not supplied from the read side device at this time.

  When a predetermined time has elapsed after the input of the write request signal WREQ is started (t12), the writing side apparatus determines whether or not the write wait signal W_WAIT (FIG. 4E) is output. Since the write wait signal W_WAIT is not output, the write side device inputs the write enable signal WEN (FIG. 4C) to the asynchronous FIFO memory device 1.

  The clock selection unit 20 having received the write enable signal WEN outputs the write clock signal WCLK as the selected clock signal MUX_CLK ((L) in FIG. 4) (t13). The memory unit 30 stores the write data WD supplied from the writing side device at an address corresponding to the write pointer WP in synchronization with the selected clock signal MUX_CLK. At this time, the write pointer update unit 40 updates the write pointer WP in synchronization with the selected clock signal MUX_CLK (write clock signal WCLK). When the write pointer WP is updated, the status signal generator 60 generates a status signal (FIG. 4K) corresponding to the new write pointer WP. Since data has been written, the number of data accumulations indicated by the status signal increases from “N” to “N + 1”.

  When the data writing is completed, the writing side device negates the write request signal WREQ and the write enable signal WEN and stops supplying the write clock signal WCLK to the asynchronous FIFO memory device 1.

  When performing reading, the reading-side device first starts supplying the read clock signal RCLK to the asynchronous FIFO memory device 1, and then inputs the read request signal RREQ (FIG. 4G) to the asynchronous FIFO memory device 1. (T14). The request arbitration unit 10 receives the read request signal RREQ, but does not output the write wait signal W_WAIT (FIG. 4E) because the write clock signal WCLK is not supplied from the write side device at this time.

  When a predetermined time has elapsed after the input of the read request signal RREQ is started (t15), the read side apparatus determines whether or not the read wait signal R_WAIT (FIG. 4 (J)) is output. Since the read wait signal R_WAIT is not output, the read side device inputs the read enable signal REN to the asynchronous FIFO memory device 1.

  The clock selection unit 20 that has received the read enable signal REN outputs the read clock signal RCLK as the selected clock signal MUX_CLK (FIG. 4 (L)) (t16). The memory unit 30 reads the data RD from the address corresponding to the read pointer RP in synchronization with the selected clock signal MUX_CLK, and outputs the data RD to the read-side device. At this time, the read pointer update unit 50 updates the read pointer RP in synchronization with the selected clock signal MUX_CLK (read clock signal RCLK). When the read pointer RP is updated, the status signal generator 60 generates a status signal (FIG. 4K) corresponding to the new read pointer RP. Since data has been read, the number of data stored indicated by the status signal decreases from “N + 1” to “N”.

  When the reading of the data is completed, the reading side device negates the read request signal RREQ and the read enable signal REN and stops supplying the read clock signal RCLK to the asynchronous FIFO memory device 1.

  Next, with reference to the timing chart of FIG. 5, the operation when the write process is waited for the preceding read process will be described.

  In the example of FIG. 5, the read request signal RREQ (FIG. 5G) is first generated from the reading side device (t21). After the read request signal RREQ is generated, the writing side device starts supplying the write clock signal WCLK (t22). The request arbitration unit 10 of the asynchronous FIFO memory device 1 synchronizes the read request signal RREQ with the write clock signal WCLK and outputs it to the write side device as a write wait signal W_WAIT (FIG. 5E) (t23). The request arbitration unit 10 synchronizes the read request signal RREQ with, for example, two clock cycles (t22, t23).

  The device on the writing side generates the write request signal WREQ (FIG. 5B) after starting the supply of the write clock signal WCLK (t24). However, while the write wait signal W_WAIT (FIG. 5 (E)) is output from the request arbitration unit 10, the write-side device receives the write enable signal WEN (FIG. 5 (C)) to the asynchronous FIFO memory device 1. Wait for input.

  When the write request signal WREQ is input from the writing side device, the request arbitration unit 10 has already output the write wait signal W_WAIT. Therefore, the request arbitration unit 10 does not synchronize the write request signal WREQ with the read clock signal RCLK, and does not output the read wait signal R_WAIT (FIG. 5 (J)) (t25, t26). That is, since the input of the write request signal WREQ to the second synchronization unit 12 is suppressed by the arbitration control unit 15 (FIG. 3), the second synchronization unit 12 does not output the read waiting signal R_WAIT.

  The device on the reading side inputs the read enable signal REN (FIG. 5H) to the asynchronous FIFO memory device 1 after a predetermined time has elapsed from the start of input of the read request signal RREQ (t27). The clock selection unit 20 having received the read enable signal REN outputs the read clock signal RCLK as the selected clock signal MUX_CLK (FIG. 5 (L)) (t28). The memory unit 30 reads the data RD from the address corresponding to the read pointer RP in synchronization with the selected clock signal MUX_CLK, and outputs it to the read-side device. The read pointer update unit 50 updates the read pointer RP in synchronization with the selected clock signal MUX_CLK (read clock signal RCLK). When the read pointer RP is updated, the status signal generator 60 generates a status signal (FIG. 5 (K)) corresponding to the new read pointer RP. Since data has been read, the number of data stored indicated by the status signal decreases from “N” to “N−1”. When reading of the data RD is completed, the reading side device negates the read request signal RREQ and the read enable signal REN and stops supplying the read clock signal RCLK to the asynchronous FIFO memory device 1.

  When the input of the read request signal RREQ from the read side device is completed (t28), the request arbitration unit 10 ends the output of the write wait signal W_WAIT after two clock cycles of the write clock signal WCLK (t210). When the output of the write wait signal W_WAIT is completed, the writing side device inputs the write enable signal WEN to the asynchronous FIFO memory device 1 (t211). The clock selection unit 20 to which the write enable signal WEN is input outputs the write clock signal WCLK as the selected clock signal MUX_CLK ((L) in FIG. 5) (t212). The memory unit 30 stores the write data WD supplied from the writing side device at an address corresponding to the write pointer WP in synchronization with the selected clock signal MUX_CLK. The write pointer update unit 40 updates the write pointer WP in synchronization with the selected clock signal MUX_CLK (write clock signal WCLK). When the write pointer WP is updated, the status signal generator 60 generates a status signal (FIG. 5K) corresponding to the new write pointer WP. Since data has been written, the number of data accumulations indicated by the status signal increases from “N−1” to “N”. When the data writing is completed, the writing side device negates the write request signal WREQ and the write enable signal WEN and stops supplying the write clock signal WCLK to the asynchronous FIFO memory device 1.

  Next, with reference to the timing chart of FIG. 6, the operation when the read process is waited for the preceding write process will be described.

  In the example of FIG. 6, the write request signal WREQ (FIG. 6B) is first generated from the writing side device (t31). After the write request signal WREQ is generated, the reading side device starts supplying the read clock signal RCLK (t32). The request arbitration unit 10 of the asynchronous FIFO memory device 1 synchronizes the write request signal WREQ with the read clock signal RCLK and outputs it to the read side device as a read wait signal R_WAIT (FIG. 6 (J)) (t33). Similar to the read request signal RREQ, the request arbitration unit 10 synchronizes the write request signal WREQ with, for example, two clock cycles (t32, t33).

  The device on the reading side generates the read request signal RREQ (FIG. 6G) after starting to supply the read clock signal RCLK (t36). However, since the read wait signal R_WAIT is output from the request arbitration unit 10, the read side device waits for the input of the read enable signal REN to the asynchronous FIFO memory device 1.

  The device on the writing side inputs the write enable signal WEN (FIG. 6C) to the asynchronous FIFO memory device 1 after a predetermined time has elapsed from the start of input of the write request signal WREQ (t34). The clock selection unit 20 having received the write enable signal WEN outputs the write clock signal WCLK as the selected clock signal MUX_CLK ((L) in FIG. 6) (t35). The memory unit 30 takes in the data WD from the writing side device in synchronization with the selected clock signal MUX_CLK, and stores the data WD at an address corresponding to the write pointer WP. The write pointer update unit 40 updates the write pointer WP in synchronization with the selected clock signal MUX_CLK (write clock signal WCLK). When the write pointer WP is updated, the status signal generation unit 60 generates a status signal (FIG. 6 (K)) corresponding to the new write pointer WP. Since data has been written, the number of data accumulations indicated by the status signal increases from “N” to “N + 1”. When the writing of the data WD is completed, the writing side device negates the write request signal WREQ and the write enable signal WEN and stops supplying the write clock signal WCLK to the asynchronous FIFO memory device 1.

  When the input of the write request signal WREQ from the writing side device is completed (t35), the request arbitration unit 10 ends the output of the read wait signal R_WAIT after two clock cycles of the read clock signal RCLK (t38). When the output of the read wait signal R_WAIT is completed, the read side device inputs the read enable signal REN to the asynchronous FIFO memory device 1 (t39). The clock selection unit 20 having received the read enable signal REN outputs the read clock signal RCLK as the selected clock signal MUX_CLK (FIG. 6 (L)) (t310). The memory unit 30 reads out the data RD stored at the address corresponding to the read pointer RP in synchronization with the selected clock signal MUX_CLK, and outputs the data RD to the read-side device. The read pointer update unit 50 updates the read pointer RP in synchronization with the selected clock signal MUX_CLK (read clock signal RCLK). When the read pointer RP is updated, the status signal generator 60 generates a status signal (FIG. 6 (K)) corresponding to the new read pointer RP. Since data has been read, the number of data stored indicated by the status signal decreases from “N + 1” to “N”. When the reading of the data is completed, the reading side device negates the read request signal RREQ and the read enable signal REN and stops supplying the read clock signal RCLK to the asynchronous FIFO memory device 1.

As described above, according to the asynchronous FIFO memory device 1 according to the present embodiment, when the write request signal WREQ synchronized with the write clock signal WCLK is input from the write side device, the write request signal WREQ is read as the read clock signal. A read wait signal R_WAIT synchronized with RCLK is output from the request arbitration unit 10 to the read side device, and while the read wait signal R_WAIT is output, the read side device waits for generation of the read enable signal REN. . When a read request signal RREQ synchronized with the read clock signal RCLK is input from the read side device, a write wait signal W_WAIT obtained by synchronizing the read request signal RREQ with the write clock signal WCLK is sent from the request arbitration unit 10 to the write side. While the data is output to the apparatus and the write wait signal W_WAIT is output, the write side apparatus waits for the generation of the write enable signal WEN. When the write enable signal WEN is input from the write side device, the write clock signal WCLK is selected as the selection clock signal MUX_CLK in the clock selection unit 20, and when the read enable signal REN is input from the read side device, the read clock The signal RCLK is selected as the selected clock signal MUX_CLK in the clock selection unit 20.
As described above, according to the asynchronous FIFO memory device 1 according to the present embodiment, the write enable signal WEN that enables the write operation and the read enable signal REN that enables the read operation do not conflict with each other. Since the timing is adjusted, the clock selection unit 20 generates a single selected clock signal MUX_CLK without glitches.
In the asynchronous FIFO memory device 1 according to the present embodiment, the memory unit 30, the write pointer update unit 40, the read pointer update unit 50, and the status signal generation unit 60 include a single selected clock generated by the clock selection unit 20. It operates in synchronization with the signal MUX_CLK.
Therefore, unlike the conventional asynchronous FIFO memory device (FIG. 16), a circuit for synchronizing the write pointer with the read clock signal and a circuit for synchronizing the read pointer with the write clock signal are not required. Since a gray code or the like does not have to be used as a measure for preventing erroneous conversion accompanying the conversion, a circuit for converting the gray code or the like into a binary code is unnecessary. Furthermore, it is not necessary to provide a circuit for generating a status signal (a signal indicating the number of accumulated data, a full state, an empty state, etc.) on each of the writing side and the reading side.
Therefore, the asynchronous FIFO memory device 1 according to the present embodiment can greatly reduce the circuit scale as compared with the conventional device, and the configuration is simple and the design is easy.

Further, the conventional asynchronous FIFO memory device is provided with a circuit for generating status signals (signals indicating the number of data accumulation, full status, empty status, etc.) in the clock domain on the write side and the clock domain on the read side. In order to generate the status signal in each clock domain, it is necessary to synchronize the pointers generated in the other clock domain. However, if control is performed such that the clock signal is temporarily stopped in order to suppress power consumption and noise generation, a correct status signal can be obtained because the pointer of the other clock domain cannot be synchronized and acquired in that clock domain. The problem of not being able to occur. For example, in the case of a system that notifies an occurrence or release of an event according to the FIFO accumulation state to the reading side or writing side, it is necessary to always generate a correct state signal in each clock domain. Must always be supplied.
In contrast, in the asynchronous FIFO memory device 1 according to the present embodiment, the write pointer WP generated by the write pointer update unit 40 that operates in synchronization with the write clock signal WCLK and the read that operates in synchronization with the read clock signal RCLK. The read pointer RP generated by the pointer update unit 50 is used as it is for the generation of the status signal in the status signal generation unit 60 (used without being synchronized). Therefore, a correct state signal can be generated even when one of the write clock signal WCLK and the read clock signal RCLK is temporarily stopped. Therefore, even in a system that constantly monitors the accumulation state of the FIFO, it is possible to control to temporarily stop the clock signal.

<Second Embodiment>
Next, a second embodiment of the present invention will be described.
In the asynchronous FIFO memory device 1 according to the first embodiment described above, the request arbitration unit 10 performs control so that one of the read request signal RREQ and the write request signal WREQ has priority over the other. Therefore, for example, when the read request signal RREQ has priority, even when the write request signal WREQ is generated first, the write wait signal W_WAIT is output by the read request signal RREQ generated later and the write processing is waited. There is a possibility that.
In contrast, in the asynchronous FIFO memory device 1 according to the present embodiment, only one request (read request, write request) is not always given priority, but a request that occurs earlier in time is more likely to be given priority. .

  The asynchronous FIFO memory device 1 according to the second embodiment has the same configuration as that of the asynchronous FIFO memory device 1 shown in FIG. 2, but the internal configuration of the request arbitration unit 10 is different from that shown in FIG. Yes.

  FIG. 7 is a diagram illustrating an example of the configuration of the request arbitration unit 10 in the asynchronous FIFO memory device according to the second embodiment. The request arbitration unit 10 illustrated in FIG. 7 includes first synchronization units 11 and 12 similar to the request arbitration unit 10 illustrated in FIG. 3 and an arbitration control unit 13.

  When the write request signal WREQ is input from the writing side device, the arbitration control unit 13 synchronizes the read request signal RREQ with the write clock signal WCLK (hereinafter may be referred to as a synchronization signal S11). Is held in synchronization with the write clock signal WCLK, and the held write request signal WREQ (S13) is held in the second synchronization unit on the condition that the first synchronization unit 11 does not output the write request signal WREQ. 12 is input. As a result, since the read wait signal R_WAIT in which the write request signal WREQ is synchronized is output to the read side device, the read side device is put in a standby state.

  When the arbitration control unit 13 holds the write request signal WREQ, the arbitration control unit 13 suppresses the output of the write wait signal W_WAIT to the writing side device. Even if the synchronization signal S11 of the read request signal RREQ is output from the first synchronization unit 11 after holding the write request signal WREQ, the arbitration control unit 13 suppresses the output of the write wait signal W_WAIT, so that the write process proceeds. .

  When the input of the write request signal WREQ ends, the arbitration control unit 13 cancels the holding of the write request signal WREQ. As a result, the output of the read wait signal R_WAIT from the second synchronization unit 12 is completed, so that a read process can be performed in the read side device.

  When the arbitration control unit 13 does not hold the write request signal WREQ, the arbitration control unit 13 outputs a write wait signal W_WAIT corresponding to the synchronization signal S11 of the first synchronization unit 11 to the writing side device. Since the arbitration control unit 13 does not hold the write request signal WREQ even if the write request signal WREQ is input later when the synchronization signal S11 in which the read request signal RREQ is synchronized is output, the second synchronization unit No read wait signal R_WAIT is output from 12, and the read process proceeds.

The arbitration control unit 13 includes logic gate circuits 131, 132, 133, and 135 and a flip-flop 134 as shown in FIG.
The logic gate circuit 131 outputs a logical product of a signal obtained by logically inverting the output signal of the first synchronization unit 11 and the write request signal WREQ.
The logic gate circuit 132 outputs a logical sum of the output signal of the logic gate circuit 131 and the signal held in the flip-flop 134.
The logic gate circuit 133 outputs a logical product of the output signal of the logic gate circuit 132 and the write request signal WREQ.
The flip-flop 134 holds the output signal of the logic gate circuit 133 in synchronization with the write clock signal WCLK. The signal held by the flip-flop 134 is input to the second synchronization unit 12.
The logic gate circuit 135 outputs a logical product of a signal obtained by logically inverting the signal held in the flip-flop 134 and the output signal of the first synchronization unit 11 as a write wait signal W_WAIT.

  Here, the operation of the asynchronous FIFO memory device 1 according to the second embodiment having the above-described arbitration control unit 13 will be described with reference to the timing charts of FIGS.

  First, with reference to the timing chart of FIG. 8, the operation when the read process is waited for the preceding write process will be described.

  In the example of FIG. 8, the read request signal RREQ (FIG. 8 (I)) is first generated from the read side device (t41), and then the write request signal WREQ (FIG. 8 (B)) is output from the write side device. Occurs (t42). When the write request signal WREQ is input to the arbitration control unit 13, the read request signal RREQ is not yet synchronized and is output from the first synchronization unit 11 as the synchronization signal S11 (FIG. 8F). Absent. Therefore, the arbitration control unit 13 holds the write request signal WREQ in synchronization with the next rise (t43) of the write clock signal WCLK, and inputs it to the second synchronization unit 12 as a signal S13 (FIG. 8C). .

  After the signal S13 holding the write request signal WREQ is output (t43), the first synchronization unit 11 outputs the synchronization signal S11 (FIG. 8F) of the read request signal RREQ. Since the arbitration control unit 13 already holds the write request signal WREQ at this time, the arbitration control unit 13 does not output the synchronization signal S11 as the write wait signal W_WAIT to the writing side device.

  The second synchronization unit 12 synchronizes the write request signal WREQ (FIG. 8C) held in the arbitration control unit 13 as the signal S13 with the read clock signal RCLK at two clock cycles (t44, t45), and reads The waiting signal R_WAIT (FIG. 8L) is output to the reading side device. As a result, the input of the read enable signal REN is waited in the read side apparatus.

  When a predetermined time has elapsed from the input of the write request signal WREQ (FIG. 8B) (t46), the write wait signal W_WAIT (FIG. 8G) is not output from the arbitration control unit 13, so the write side The device generates a write enable signal WEN (FIG. 8D). The clock selection unit 20 that has received the write enable signal WEN outputs the write clock signal WCLK as the selected clock signal MUX_CLK (FIG. 8N) (t47). The memory unit 30 stores the write data WD supplied from the writing side device at an address corresponding to the write pointer WP in synchronization with the selected clock signal MUX_CLK. Further, the write pointer update unit 40 updates the write pointer WP in synchronization with the selected clock signal MUX_CLK (write clock signal WCLK). When the write pointer WP is updated, the status signal generator 60 generates a status signal (FIG. 8M) corresponding to the new write pointer WP. Since data has been written, the number of data accumulations indicated by the status signal increases from “N” to “N + 1”.

  When the data writing is completed, the writing side device negates the write request signal WREQ and the write enable signal WEN (t47). When the input of the write request signal WREQ ends, the arbitration control unit 13 releases the hold of the write request signal WREQ (sets the signal S13 to “0”) at the next rising edge (t48) of the write clock signal WCLK. The device on the writing side stops supplying the write clock signal WCLK after the arbitration control unit 13 releases the holding of the write request signal WREQ. When the arbitration control unit 13 releases the holding of the write request signal WREQ, the arbitration control unit 13 uses the synchronization signal S11 (FIG. 8 (F)) output from the first synchronization unit 11 as a write wait signal W_WAIT (FIG. 8 (G)). Output to the writing device.

  When the signal S13 (FIG. 8C) holding the write request signal WREQ is negated, the second synchronization unit 12 waits for a read waiting signal R_WAIT (FIG. 8 (L) after two clock cycles (t49, t410). Negate)). When the output of the read wait signal R_WAIT is completed, the read side device inputs the read enable signal REN (FIG. 8 (J)) to the asynchronous FIFO memory device 1 (t411). The clock selection unit 20 to which the read enable signal REN is input outputs the read clock signal RCLK as the selected clock signal MUX_CLK ((N) in FIG. 8) (t412). The memory unit 30 reads out the data RD stored at the address corresponding to the read pointer RP in synchronization with the selected clock signal MUX_CLK, and outputs the data RD to the read-side device. The read pointer update unit 50 updates the read pointer RP in synchronization with the selected clock signal MUX_CLK (read clock signal RCLK). When the read pointer RP is updated, the status signal generator 60 generates a status signal (FIG. 8M) corresponding to the new read pointer RP. Since data has been read, the number of data stored indicated by the status signal decreases from “N + 1” to “N”. When the reading of the data is completed, the reading side device negates the read request signal RREQ and the read enable signal REN and stops supplying the read clock signal RCLK to the asynchronous FIFO memory device 1.

  Next, with reference to the timing chart of FIG. 9, the operation when the writing process is waited for the preceding reading process will be described.

  Also in the example of FIG. 9, the read request signal RREQ (FIG. 9 (I)) is first generated from the read side device (t51), and then the write request signal WREQ (FIG. 9 (B)) from the write side device. Occurs (t53). However, in the example of FIG. 9, at the same timing (t53) as the generation of the write request signal WREQ, the first synchronization unit 11 outputs the synchronization signal S11 of the read request signal RREQ (FIG. 9 (F)). Since the synchronization signal S11 of the read request signal RREQ is output, the arbitration control unit 13 does not hold the write request signal WREQ in the next clock cycle (t54) and keeps the signal S13 as “0”. That is, the arbitration control unit 13 does not transmit the write request signal WREQ to the second synchronization unit 12. On the other hand, since the arbitration control unit 13 does not hold the write request signal WREQ, the arbitration control unit 13 outputs the synchronization signal S11 of the read request signal RREQ as it is to the writing side device as the write wait signal W_WAIT. As a result, the input of the write enable signal WEN is waited in the writing side apparatus.

  When a predetermined time has elapsed from the input of the read request signal RREQ (FIG. 9 (I)) (t55), the read wait signal R_WAIT is not output from the arbitration control unit 13, and therefore the read side device reads the read enable signal REN ( 9J) is generated. The clock selection unit 20 that has received the read enable signal REN outputs the read clock signal RCLK as the selected clock signal MUX_CLK (FIG. 9 (N)) (t56). The memory unit 30 reads the data RD from the address corresponding to the read pointer RP in synchronization with the selected clock signal MUX_CLK, and outputs it to the read-side device. The read pointer update unit 50 updates the read pointer RP in synchronization with the selected clock signal MUX_CLK (read clock signal RCLK). When the read pointer RP is updated, the status signal generator 60 generates a status signal (FIG. 9M) corresponding to the new read pointer RP. Since data has been read, the number of data stored indicated by the status signal decreases from “N” to “N−1”. When reading of the data RD is completed, the reading side device negates the read request signal RREQ and the read enable signal REN and stops supplying the read clock signal RCLK.

  When the input of the read request signal RREQ from the reading side device is completed (t56), the first synchronization unit 11 outputs the synchronization signal S11 after two clock cycles (t57, t58) of the read clock signal RCLK. finish. At this time, since the arbitration control unit 13 does not hold the write request signal WREQ (since the signal S13 is “0”), the synchronization signal S11 is output as it is as the write wait signal W_WAIT (FIG. 9 (G)). Yes. Therefore, when the output of the synchronization signal S11 ends, the output of the write wait signal W_WAIT also ends.

  When the output of the write wait signal W_WAIT is completed, the writing side device generates the write enable signal WEN (FIG. 9C) (t59). The clock selector 20 having received the write enable signal WEN outputs the write clock signal WCLK as the selected clock signal MUX_CLK (FIG. 9 (N)) (t510). The memory unit 30 stores the write data WD supplied from the writing side device at an address corresponding to the write pointer WP in synchronization with the selected clock signal MUX_CLK. The write pointer update unit 40 updates the write pointer WP in synchronization with the selected clock signal MUX_CLK (write clock signal WCLK). When the write pointer WP is updated, the status signal generator 60 generates a status signal (FIG. 9M) corresponding to the new write pointer WP. Since data has been written, the number of data accumulations indicated by the status signal increases from “N−1” to “N”. The device on the writing side negates the write request signal WREQ and the write enable signal WEN when the data writing is completed.

  When the output of the synchronization signal S11 of the read request signal RREQ ends (t58), the arbitration control unit 13 holds the write request signal WREQ (t59). However, since the read clock signal RCLK has already stopped at this time, the second synchronization unit 12 does not perform synchronization and the read wait signal R_WAIT is not output. When the write request signal WREQ is negated (t510), the arbitration control unit 13 releases the hold of the write request signal WREQ (t511). The device on the writing side stops supplying the write clock signal WCLK after the arbitration control unit 13 releases the holding of the write request signal WREQ.

As described above, according to the asynchronous FIFO memory device 1 according to the present embodiment, when the write request signal WREQ is input from the write side device, the synchronization signal S11 of the read request signal RREQ is the first synchronization unit. 11, the write request signal WREQ is held in the arbitration control unit 13 in synchronization with the write clock signal WCLK, and the held write request signal WREQ is input to the second synchronization unit 12 on the condition that the write request signal WREQ is not output. Then, a read waiting signal R_WAIT is output from the second synchronization unit 12 to the reading side device. When the write request signal WREQ is held in the arbitration control unit 13, the output of the write wait signal W_WAIT to the writing side device is suppressed. When the input of the write request signal WREQ from the writing side device ends, the arbitration control unit 13 releases the holding of the write request signal WREQ, and the output of the read waiting signal R_WAIT from the second synchronization unit 12 to the reading side device ends. To do. When the write request signal WREQ is not held in the arbitration control unit 13, the write wait signal W_WAIT corresponding to the synchronization signal S11 of the first synchronization unit 11 is output to the writing side device.
That is, when the input of the write request signal WREQ from the writing side device is earlier than the output of the synchronization signal S11 of the read request signal RREQ in the first synchronization unit 11, the write request has priority over the read request, and the read request Waits until the writing process is finished. Conversely, when the output of the synchronization signal S11 of the read request signal RREQ in the first synchronization unit 11 is earlier than the input of the write request signal WREQ from the writing side device, the read request has priority over the write request, and the write request The request is waited until the reading process is completed.
Therefore, each of the writing process and the reading process can be executed in a balanced manner according to the frequency of occurrence, as compared with a method in which either writing or reading is always prioritized.

Although the arbitration control unit 13 illustrated in FIG. 7 holds the write request signal WREQ and inputs it to the second synchronization unit 12, the present embodiment is not limited to this example.
In another example of the present embodiment, the arbitration control unit 13 inputs a read request signal RREQ instead of the write request signal WREQ, and the second synchronization unit 12 instead of the output signal (S13) of the first synchronization unit 11. The read wait signal R_WAIT may be output instead of the write wait signal W_WAIT.
In this example, when the read request signal RREQ is input from the read side device, the arbitration control unit 13 is provided on the condition that the signal that synchronizes the write request signal WREQ is not output in the second synchronization unit 12. The read request signal RREQ is held in synchronization with the read clock signal RCLK, and the held read request signal RREQ is input to the first synchronizer 11, and the read request signal RREQ is held when the read request signal RREQ is held. When the output of the signal R_WAIT is suppressed and the input of the read request signal RREQ is terminated, the holding of the read request signal RREQ is released, and when the read request signal RREQ is not held, the output signal of the second synchronization unit 12 is A corresponding read waiting signal R_WAIT is output.
When the input of the read request signal RREQ from the reading side device is earlier than the output of the synchronization signal of the write request signal WREQ in the second synchronization unit 12, the read request has priority over the write request, and the write request is read. Wait until the processing is completed. Conversely, when the output of the synchronization signal of the write request signal WREQ in the second synchronization unit 12 is earlier than the input of the read request signal RREQ from the read side device, the write request has priority over the read request, and the read request Waits until the writing process is finished.
Therefore, also in this case, each of the writing process and the reading process can be executed in a well-balanced manner according to the frequency of occurrence, as compared with a method in which one of writing and reading is always prioritized.

<Third Embodiment>
Next, a third embodiment of the present invention will be described.
In the asynchronous FIFO memory device 1 according to the second embodiment described above, a request signal (write request signal WREQ, read request signal RREQ) is held in order to arbitrate a write request and a read request, and the held request signal is synchronized. (The first synchronization unit 11 and the second synchronization unit 12). In the asynchronous FIFO memory device 1 according to the present embodiment, the synchronization unit (the first synchronization unit 11 and the second synchronization unit 12). The synchronization signals (S11, S12) output from the unit 12) are held, and the held synchronization signals are output as wait signals (write wait signal W_WAIT, read wait signal R_WAIT).

  The asynchronous FIFO memory device 1 according to the third embodiment has the same configuration as that of the asynchronous FIFO memory device 1 shown in FIG. 2, but the internal configuration of the request arbitration unit 10 is shown in FIGS. It is different from what is shown.

  FIG. 10 is a diagram illustrating an example of the configuration of the request arbitration unit 10 in the asynchronous FIFO memory device according to the third embodiment. The request arbitration unit 10 illustrated in FIG. 10 includes first synchronization units 11 and 12 similar to the request arbitration unit 10 illustrated in FIG. 3 and an arbitration control unit 14.

  The arbitration control unit 14 reads the write request signal WREQ from the second synchronization unit 12 when a signal S12 that is synchronized with the read clock signal RCLK (hereinafter may be referred to as a synchronization signal S12) is output from the second synchronization unit 12. The synchronization signal S12 is held in synchronization with the read clock signal RCLK on the condition that the read request signal RREQ is not input from the device, and the held synchronization signal S12 is set as a read wait signal R_WAIT on the reading side. Output to the device. As a result, the reading-side apparatus is in a state of waiting for the reading process.

  The arbitration control unit 14 suppresses the input of the read request signal RREQ to the first synchronization unit 11 when holding the synchronization signal S12 of the write request signal WREQ. Even if the read request signal RREQ is input after the synchronization signal S1 is held, the arbitration control unit 14 suppresses the input of the read request signal RREQ to the first synchronization unit 11, and thus the write wait signal W_WAIT is not output. The writing process proceeds.

  When the output of the write request signal WREQ from the writing side device ends and the synchronization signal S12 from the second synchronization unit 12 ends, the arbitration control unit 14 releases the holding of the synchronization signal S12 and reads The output of the wait signal R_WAIT is terminated. As a result, reading processing can be performed in the reading-side apparatus.

  When the arbitration control unit 14 does not hold the synchronization signal S12 of the write request signal WREQ, the arbitration control unit 14 inputs a signal S14 corresponding to the read request signal RREQ input from the read side device to the first synchronization unit 11. . Even when the synchronization signal S12 of the write request signal WREQ is output from the second synchronization unit 12 later when the read request signal RREQ is input, the arbitration control unit 14 does not hold the synchronization signal S12. The read wait signal R_WAIT is not output, and the read process proceeds.

The arbitration control unit 13 includes logic gate circuits 141, 142, 143, 145 and a flip-flop 144 as shown in FIG.
The logic gate circuit 141 outputs a logical product of a signal obtained by logically inverting the read request signal RREQ and the output signal of the second synchronization unit 12.
The logic gate circuit 142 outputs a logical sum of the output signal of the logic gate circuit 141 and the signal held in the flip-flop 144.
The logic gate circuit 143 outputs a logical product of the output signal of the logic gate circuit 142 and the output signal of the second synchronization unit 12.
The flip-flop 144 holds the output signal of the logic gate circuit 143 in synchronization with the read clock signal RCLK. The signal held by the flip-flop 144 is output to the reading side device as a read wait signal R_WAIT.
The logic gate circuit 145 inputs a logical product of a signal obtained by logically inverting the signal held in the flip-flop 144 and the read request signal RREQ to the first synchronization unit 11.

  Here, the operation of the asynchronous FIFO memory device 1 according to the third embodiment having the arbitration control unit 14 described above will be described with reference to the timing charts of FIGS.

  First, with reference to the timing chart of FIG. 11, the operation when the read process is waited for the preceding write process will be described.

  When the write request signal WREQ (FIG. 11B) is input from the writing side device (t61), the second synchronization unit 12 passes the two clock cycles of the read clock signal RCLK (t62, t63), and the second synchronization unit 12 The synchronization signal S12 (FIG. 11 (K)) of the signal WREQ is output. When the synchronization signal S12 of the write request signal WREQ is output, since the read request signal RREQ (FIG. 11G) has not been input from the read side device, the arbitration control unit 14 determines the next write clock. At the rising edge (t64) of the signal WCLK, the synchronization signal S12 of the write request signal WREQ is held, and this is output as a read wait signal R_WAIT (FIG. 11 (L)) to the read side device. As a result, the input of the read enable signal REN is waited in the read side apparatus.

  When the arbitration control unit 14 outputs the read waiting signal R_WAIT (t64), the reading side device generates the read request signal RREQ (FIG. 11G). At this time, since the arbitration control unit 14 holds the synchronization signal S12 of the write request signal WREQ, the arbitration control unit 14 does not input the read request signal RREQ to the first synchronization unit 11. As a result, since the write wait signal W_WAIT is not output, the write process proceeds in the writing side device.

  When a fixed time has elapsed from the input of the write request signal WREQ (FIG. 11B) (t65), the write wait signal W_WAIT (FIG. 11E) is not output from the arbitration control unit 14, so the write side The device generates a write enable signal WEN (FIG. 11C). The clock selector 20 that has received the write enable signal WEN outputs the write clock signal WCLK as the selected clock signal MUX_CLK (FIG. 11 (N)) (t66). The memory unit 30 stores the write data WD supplied from the writing side device at an address corresponding to the write pointer WP in synchronization with the selected clock signal MUX_CLK. Further, the write pointer update unit 40 updates the write pointer WP in synchronization with the selected clock signal MUX_CLK (write clock signal WCLK). When the write pointer WP is updated, the status signal generator 60 generates a status signal (FIG. 11M) corresponding to the new write pointer WP. Since data has been written, the number of data accumulations indicated by the status signal increases from “N” to “N + 1”. When the data writing is completed, the writing side device negates the write request signal WREQ and the write enable signal WEN and stops supplying the write clock signal WCLK.

  When the input of the write request signal WREQ (FIG. 11B) from the writing side device is completed (t66), the second synchronizer 12 ends the two clock cycles (t67, t68) of the read clock signal RCLK. The output of the synchronization signal S12 (FIG. 11 (K)) of the write request signal WREQ is terminated. When the output of the synchronization signal S12 from the second synchronization unit 12 is completed, the arbitration control unit 14 releases the holding of the synchronization signal S12 in the next clock cycle (t69) of the read clock signal RCLK, and the read waiting signal The output of R_WAIT (FIG. 11 (L)) is terminated. When the output of the read wait signal R_WAIT is completed, the read side device generates the read enable signal REN (t610). The clock selector 20 that has received the read enable signal REN outputs the read clock signal RCLK as the selected clock signal MUX_CLK (FIG. 11 (N)) (t611). The memory unit 30 reads out the data RD stored at the address corresponding to the read pointer RP in synchronization with the selected clock signal MUX_CLK, and outputs the data RD to the read-side device. The read pointer update unit 50 updates the read pointer RP in synchronization with the selected clock signal MUX_CLK (read clock signal RCLK). When the read pointer RP is updated, the status signal generator 60 generates a status signal (FIG. 11M) corresponding to the new read pointer RP. Since data has been read, the number of data stored indicated by the status signal decreases from “N + 1” to “N”. When the reading of the data is completed, the reading-side device negates the read request signal RREQ and the read enable signal REN and stops supplying the read clock signal RCLK.

  Next, with reference to the timing chart of FIG. 12, the operation when the writing process is waited for the preceding reading process will be described.

  When the write request signal WREQ (FIG. 12B) is input from the writing side device (t71), the second synchronization unit 12 passes the two clock cycles of the read clock signal RCLK (t72, t73), The synchronization signal S12 (FIG. 12 (K)) of the signal WREQ is output. When the synchronization signal S12 of the write request signal WREQ is output, the arbitration control unit 14 holds the synchronization signal S12 because the read request signal RREQ (FIG. 12G) has already been input from the reading side device. And the read wait signal R_WAIT (11 (L)) is not output. As a result, the reading process proceeds in the reading-side apparatus.

  On the other hand, since the arbitration control unit 14 does not hold the synchronization signal S12 of the write request signal WREQ, the read request signal RREQ input from the read side device is used as the signal S14 (12 (H)) for the first synchronization. Input to section 11. The first synchronizer 11 receiving the signal S14 outputs the write wait signal W_WAIT after two clock cycles (t74, t75) of the write clock signal WCLK. As a result, the input of the write enable signal WEN is waited in the writing side apparatus.

  When a predetermined time has elapsed from the input of the read request signal RREQ (FIG. 12G) (t76), the read wait signal R_WAIT is not output from the arbitration control unit 14, and therefore the read side device reads the read enable signal REN ( 12 (I)) is generated. The clock selection unit 20 that has received the read enable signal REN outputs the read clock signal RCLK as the selected clock signal MUX_CLK (FIG. 12 (N)) (t77). The memory unit 30 reads the data RD from the address corresponding to the read pointer RP in synchronization with the selected clock signal MUX_CLK, and outputs it to the read-side device. The read pointer update unit 50 updates the read pointer RP in synchronization with the selected clock signal MUX_CLK (read clock signal RCLK). When the read pointer RP is updated, the status signal generator 60 generates a status signal (FIG. 12M) corresponding to the new read pointer RP. Since data has been read, the number of data stored indicated by the status signal decreases from “N” to “N−1”. When reading of the data RD is completed, the reading side device negates the read request signal RREQ and the read enable signal REN and stops supplying the read clock signal RCLK.

  When the signal S14 is negated along with the negation of the read request signal RREQ, the first synchronizer 11 generates the write wait signal W_WAIT (FIG. 12E) after two clock cycles (t78, t79) of the write clock signal WCLK. Negate. When the output of the write wait signal W_WAIT from the arbitration control unit 14 is completed, the writing side device generates the write enable signal WEN (FIG. 12C) (t710). The clock selection unit 20 having received the write enable signal WEN outputs the write clock signal WCLK as the selected clock signal MUX_CLK (FIG. 12 (N)) (t711). The memory unit 30 stores the write data WD supplied from the writing side device at an address corresponding to the write pointer WP in synchronization with the selected clock signal MUX_CLK. The write pointer update unit 40 updates the write pointer WP in synchronization with the selected clock signal MUX_CLK (write clock signal WCLK). When the write pointer WP is updated, the status signal generator 60 generates a status signal (FIG. 12M) corresponding to the new write pointer WP. Since data has been written, the number of data accumulations indicated by the status signal increases from “N−1” to “N”. When the data writing is completed, the writing side device negates the write request signal WREQ and the write enable signal WEN and stops supplying the write clock signal WCLK.

As described above, according to the asynchronous FIFO memory device 1 according to the present embodiment, when the synchronization signal S12 obtained by synchronizing the write request signal WREQ is output from the second synchronization unit 12, the device on the reading side On condition that the read request signal RREQ is not input, the synchronization signal S12 of the write request signal WREQ is held in the arbitration control unit 14 in synchronization with the read clock signal RCLK, and the held synchronization signal S12 is read. The waiting signal R_WAIT is output to the reading device. When the arbitration control unit 14 holds the synchronization signal S12 of the write request signal WREQ, the input of the read request signal RREQ to the first synchronization unit 11 is suppressed. When the input of the write request signal WREQ from the writing side device is completed and the output of the synchronization signal S12 in the second synchronization unit 12 is completed, the arbitration control unit 14 synchronizes the write request signal WREQ with the synchronization signal S12. Is released, and the output of the read wait signal R_WAIT to the read-side device ends. When the arbitration control unit 14 does not hold the synchronization signal S12 of the write request signal WREQ, the signal S14 corresponding to the read request signal RREQ input from the reading side device is input to the first synchronization unit 11, In response to this, a write wait signal W_WAIT is output to the writing side device.
That is, when the input of the read request signal RREQ from the read side device is earlier than the output of the synchronization signal S12 of the write request signal WREQ in the second synchronization unit 12, the read request has priority over the write request, The request is waited until the reading process is completed. Conversely, when the output of the synchronization signal S12 of the write request signal WREQ in the second synchronization unit 12 is earlier than the input of the read request signal RREQ from the reading side device, the write request has priority over the read request, The read request is waited until the writing process is completed.
Therefore, also in this embodiment, each of the writing process and the reading process can be executed in a balanced manner according to the frequency of occurrence, as compared with a method in which one of writing and reading is always prioritized.

Note that the arbitration control unit 14 illustrated in FIG. 10 holds the synchronization signal S12 of the second synchronization unit 12 and outputs it as the read wait signal R_WAIT, but this embodiment is not limited to this example.
In another example of the present embodiment, the arbitration control unit 14 inputs the write request signal WREQ instead of the read request signal RREQ, and the first synchronization unit 11 instead of the output signal (S12) of the second synchronization unit 12. The output wait signal W_WAIT may be output instead of the read wait signal R_WAIT.
In this example, when the synchronization signal S11 obtained by synchronizing the read request signal RREQ is output from the first synchronization unit 11, the arbitration control unit 14 does not receive the write request signal WREQ from the writing side device. As a condition, the synchronization signal S11 of the read request signal RREQ is held in synchronization with the write clock signal WCLK, and is output as a write wait signal W_WAIT to the writing side device. When the synchronization signal S11 of the read request signal RREQ is held, the arbitration control unit 14 suppresses the input of the write request signal WREQ to the second synchronization unit 12, thereby reading to the reading side device. The output of the wait signal R_WAIT is suppressed. When the output of the synchronization signal S11 of the read request signal RREQ is completed in the first synchronization unit 11, the arbitration control unit 14 releases the holding of the synchronization signal S11 of the read request signal RREQ and writes to the writing side device. The output of the wait signal W_WAIT is terminated. When the synchronization signal S11 of the read request signal RREQ is not held, the arbitration control unit 14 inputs a signal S14 corresponding to the write request signal WREQ input from the writing side device to the second synchronization unit 12.
That is, when the input of the write request signal WREQ from the writing device is earlier than the output of the synchronization signal S11 of the read request signal RREQ in the first synchronization unit 11, the write request has priority over the read request, and the read The request is waited until the writing process is completed. Conversely, when the output of the synchronization signal S11 of the read request signal RREQ in the first synchronization unit 11 is earlier than the input of the write request signal WREQ from the writing side device, the read request has priority over the write request, The write request is waited until the read process is completed.
Therefore, also in this case, each of the writing process and the reading process can be executed in a well-balanced manner according to the frequency of occurrence, as compared with a method in which one of writing and reading is always prioritized.

<Fourth Embodiment>
Next, a fourth embodiment of the present invention will be described.
The asynchronous FIFO memory device according to this embodiment is obtained by adding a scan test configuration to the asynchronous FIFO memory device according to each of the above-described embodiments.

  FIG. 13 is a diagram illustrating an example of the configuration of the asynchronous FIFO memory device 1 according to the fourth embodiment. The asynchronous FIFO memory device 1 according to the present embodiment has the same configuration as the asynchronous FIFO memory device 1 shown in FIG. 2, for example, and includes a plurality of combinational circuits 75 and a plurality of scan test flip-flops 80. It is comprised using. The plurality of flip-flops 80 constituting the circuit are connected in cascade so as to constitute a shift register for transferring serial data when the scan test is performed.

  In the example of FIG. 13, the asynchronous FIFO memory device 1 includes a multiplexer circuit 90 for switching a clock signal input to the clock selection unit 20 during a scan test. When performing a normal operation, the multiplexer circuit 90 inputs predetermined clock signals (CK1, CK2) to the clock selection unit 20 as a write clock signal WCLK and a read clock signal RCLK, respectively. When the input signal of the terminal SCAN_MODE is asserted), the clock signals SCAN_CLK1 and SCAN_CLK2 supplied from a predetermined test device are input to the clock selection unit 20 as the write clock signal WCLK and the read clock signal RCLK. Thereby, in the scan test, the inspection is performed based on the clock signals SCAN_CLK1 and SCAN_CLK2 generated by the test apparatus.

FIG. 14 is a diagram illustrating an example of the configuration of the clock selection unit 20 in the present embodiment. FIG. 15 is a diagram illustrating an example of the configuration of the clock gating circuits 21-1 and 21-2 included in the clock selection unit 20 illustrated in FIG.
The clock selection unit 20 illustrated in FIG. 14 includes clock gating circuits 21-1 and 21-2, a multiplexer circuit 22, a flip-flop 23, and an OR circuit 24. The clock gating circuits 21-1 and 21-2 include an OR circuit 25, a latch circuit 26, and an AND circuit 27, respectively.

  In the clock gating circuits 21-1 and 21-2, the OR circuit 25 outputs the logical sum of the input signal (signal SCAN_EN) from the terminal SCAN_EN and the enable signal (write enable signal WEN, read enable signal REN). To do. The latch circuit 26 holds the output signal of the OR circuit 25 and outputs it to the AND circuit 27 when the input clock signals (write clock signal WCLK, read clock signal RCLK) rise from “0” to “1”. . The AND circuit 27 outputs a logical product of the output signal of the latch circuit 26 and the input clock signal.

  When the signal SCAN_EN or the write enable signal WEN is “1”, the clock gating circuit 21-1 outputs the input write clock signal WCLK. When the signal SCAN_EN and the write enable signal WEN are both “0”, Fix the output to “0”.

  When the signal SCAN_EN or the read enable signal REN is “1”, the clock gating circuit 21-2 outputs the input read clock signal RCLK, and when both the signal SCAN_EN and the read enable signal REN are “0”, Fix the output to “0”.

The flip-flop 23 holds the read enable signal REN in synchronization with the fall of the read clock signal RCLK.
The OR circuit 24 outputs a logical sum of the signal SCAN_EN and the signal held in the flip-flop 23.
The multiplexer circuit 22 selects the output of the clock gating circuit 21-1 when the output signal of the OR circuit 24 is “0”, and the clock gating circuit when the output signal of the OR circuit 24 is “1”. Select the output of 21-2. The signal selected in the multiplexer circuit 22 is output as the selected clock signal MUX_CLK.

  Here, an operation when the scan test is performed in the asynchronous FIFO memory device 1 having the above-described configuration will be described.

  When the scan test is performed, the signal of the terminal SCAN_MODE input to the multiplexer circuit 90 is asserted. As a result, the clock signals SCAN_CLK1 and SCAN_CLK2 supplied from the predetermined test apparatus are input to the clock selection unit 20 as the write clock signal WCLK and the read clock signal RCLK, respectively.

When the signal SCAN_EN is set to “1”, the serial data supplied from the test apparatus is sequentially shifted (shifted) in a plurality of flip-flops 80 (scan chains) connected in cascade to form a shift register. mode).
When the signal SCAN_EN is set to “1”, the multiplexer circuit 22 selects the output of the clock gating circuit 21-2, and the clock gating circuit 21-2 outputs the read clock signal RCLK as it is. In the clock selector 20, the read clock signal RCLK is output as the selected clock signal MUX_CLK. This selected clock signal MUX_CLK is supplied to some flip-flop groups 95.
Therefore, in the shift mode in which data is shifted in the scan chain, the serial data of the flip-flop group 95 is shifted based on the read clock signal RCLK.

When the data shift is completed, the signal SCAN_EN is set to “0”. As a result, the input and output of each flip-flop 80 are connected to the same data path as in the normal operation. Each flip-flop 80 holds an input signal from the combinational circuit 75 (capture mode).
When the read enable signal REN is “1” when the signal SCAN_EN is “0”, the signal is output from the clock gating circuit 21-2 during the period in which the read enable signal REN delayed by the flip-flop 23 is “1”. The read clock signal RCLK is selected by the multiplexer circuit 22 and input to each flip-flop 80 of the flip-flop group 95.
When the signal SCAN_EN is “0” and the read enable signal REN is “0” and the write enable signal WEN is “1”, the write clock signal WCLK output from the clock gating circuit 21-1 is transmitted by the multiplexer circuit 22. Is selected and input to each flip-flop 80 of the flip-flop group 95.
When the read enable signal REN is “0” and the write enable signal WEN is “0” when the signal SCAN_EN is “0”, the output of the clock gating circuit 21-1 selected by the multiplexer circuit 22 is “0”. Therefore, the selected clock signal MUX_CLK is fixed to “0”.
As described above, in the capture mode in which the signal from the combinational circuit 75 is held in each flip-flop 80, the clock signal (write clock signal WCLK, read clock) corresponding to the enable signal (write enable signal WEN, read enable signal REN). Signal RCLK) is selected by the clock selector 20 and input to each flip-flop 80 of the flip-flop group 95.

  As described above, according to the asynchronous FIFO memory device 1 according to the present embodiment, in the scan test shift mode, the read clock signal RCLK is supplied to each flip-flop 80 constituting the scan chain, and the scan test capture is performed. In the mode, clock signals (write clock signal WCLK and read clock signal RCLK) corresponding to the enable signals (write enable signal WEN, read enable signal REN) are supplied to each flip-flop 80. Thereby, the write operation and the read operation of the asynchronous FIFO memory device 1 can be correctly inspected in the scan test.

  In the above-described embodiment, the read clock signal RCLK is selected in the shift mode. However, in another example of the present embodiment, the write clock signal WCLK may be selected.

  As mentioned above, although some embodiment of this invention was described, this invention is not limited only to said form, The other various variation is included.

  For example, the circuit configuration in the above-described embodiment is an example, and may be changed to another circuit configuration having an equivalent function.

  In the above-described embodiments, the FIFO memory device is taken as an example. However, the present invention is not limited to this, and the present invention can also be applied to a memory device such as a LIFO or a ring buffer.

DESCRIPTION OF SYMBOLS 1 ... Asynchronous FIFO memory device, 10 ... Request arbitration part, 11, 12 ... 1st synchronization part, 13, 14, 15 ... Arbitration control part 20 ... Clock selection part, 30 ... Memory part, 40 ... Write pointer update part, DESCRIPTION OF SYMBOLS 50 ... Read pointer update part, 60 ... State signal generation part, 100, 100A, 100B ... Power storage apparatus state estimation system, 101 ... Power storage apparatus, 102 ... AC signal source part, 103 ... Current detection part, 104 ... Voltage detection part, 105: internal impedance calculation unit, 106: state estimation unit, RL: load, C1: capacitor.

Claims (7)

A memory device that writes data in synchronization with a first clock signal and reads data in synchronization with a second clock signal,
When a write request signal synchronized with the first clock signal is input, a read wait signal is generated by synchronizing the write request signal with the second clock signal, and a read request signal synchronized with the second clock signal is output. A request arbitration unit that outputs a write wait signal obtained by synchronizing the read request signal with the first clock signal;
When a write enable signal generated on condition that the write wait signal is not output is input in synchronization with the first clock signal, the first clock signal is selected and output, and the read wait signal is output. A clock selection unit that selects and outputs the second clock signal when a read enable signal generated on the condition that the signal is not output is input in synchronization with the second clock signal;
When the write enable signal is input, data is written to an address corresponding to a write pointer in synchronization with the clock signal selected by the clock selection unit, and when the read enable signal is input, the clock selection unit A memory unit that reads data from an address corresponding to a read pointer in synchronization with the clock signal selected in
When the write enable signal is input, a write pointer update unit that updates the write pointer in synchronization with the clock signal selected by the clock selection unit;
When the read enable signal is input, a read pointer update unit that updates the read pointer in synchronization with the clock signal selected by the clock selection unit;
A memory device comprising: a status signal generating unit that generates a status signal related to the number of data stored in the memory unit based on the write pointer and the read pointer. The request arbitration unit
A first synchronization unit that synchronizes the read request signal with the first clock signal;
A second synchronization unit for synchronizing the write request signal with the second clock signal;
When a signal obtained by synchronizing the read request signal with the first clock signal (hereinafter referred to as a “first synchronization signal”) is output from the first synchronization unit, to the second synchronization unit. In the second synchronization section, a signal (hereinafter referred to as a “second synchronization signal”) in which the input of the write request signal is suppressed or the write request signal is synchronized with the second clock signal is transmitted to the second synchronization unit. The memory device according to claim 1, further comprising: an arbitration control unit that suppresses input of the read request signal to the first synchronization unit when output. The arbitration control unit, when the write request signal is input, sets the write request signal as the first clock signal on condition that the first synchronization signal is not output in the first synchronization unit. The write request signal is held in synchronization, and the held write request signal is input to the second synchronization unit. When the write request signal is held, the output of the write wait signal is suppressed, and the write request signal When the input is completed, the holding of the write request signal is released, and when the write request signal is not held, the write wait signal corresponding to the first synchronization signal of the first synchronization unit is output. The memory device according to claim 2, wherein: When the read request signal is input, the arbitration control unit converts the read request signal into the second clock signal on condition that the second synchronization signal is not output from the second synchronization unit. Holding the read request signal to the first synchronization unit, and holding the read request signal, the output of the read wait signal is suppressed and the read request signal is suppressed. When the input is completed, the holding of the read request signal is released, and when the read request signal is not held, the read waiting signal corresponding to the second synchronization signal of the second synchronization unit is output. The memory device according to claim 2, wherein: When the second synchronization signal is output from the second synchronization unit, the arbitration control unit outputs the second synchronization signal to the second clock on condition that the read request signal is not input. Holding the second synchronization signal in synchronization with a signal and outputting the held second synchronization signal as the read waiting signal, and holding the second synchronization signal, the reading to the first synchronization unit When the input of the request signal is suppressed and the output of the second synchronization signal from the second synchronization unit ends, the holding of the second synchronization signal is canceled and the output of the read waiting signal is ended. 3. The memory device according to claim 2, wherein when the second synchronization signal is not held, a signal corresponding to the input read request signal is input to the first synchronization unit. 4. When the first synchronization signal is output from the first synchronization unit, the arbitration control unit outputs the first synchronization signal to the first clock on condition that the write request signal is not input. Holds the first synchronization signal as the write wait signal, and holds the first synchronization signal when the first synchronization signal is held. When the input of the request signal is suppressed and the output of the first synchronization signal from the first synchronization unit is terminated, the holding of the first synchronization signal is canceled and the output of the write wait signal is terminated, 3. The memory device according to claim 2, wherein when the first synchronization signal is not held, a signal corresponding to the input write request signal is input to the second synchronization unit. 4. Each of which operates in synchronization with the clock signal selected by the clock selection unit, and includes a plurality of flip-flops cascaded to form a shift register that transfers serial data when performing a scan test;
The clock selector is
In the first operation mode in which the plurality of flip-flops constitute the shift register, either the first clock signal or the second clock signal is selected and output,
In the second operation mode in which each of the plurality of flip-flops holds data, when the write enable signal is input, the first clock signal is selected and output, and the read enable signal is input The memory device according to claim 1, wherein the second clock signal is selected and output.