JP2001285346A - Fifo type memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a calculation capable of correct number of stored data constantly for FIFO type memory. SOLUTION: In the FIFO type memory comprising a dual type memory 31 for data storing, a writing counter 32 creating a writing address WA of the memory according to a writing pulse signal WP to the memory 31, a reading counter 33 creating a reading address RA of the memory according to a reading pulse signal RE to the memory 31, and a capacity monitoring counter 37 calculating the number of stored data by the up and down according to the pulse signal WP and the pulse signal RE, the pulse signal WP or the pulse signal RE are synchronized to a clock signal CKB/CKA of the reading side or the writing side.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a FIFO type memory, and more particularly, to a dual port type memory for storing data, a write counter for generating a write address of the memory in accordance with a write pulse signal to the memory, FIFO type memory including a read counter for generating a read address of a memory in accordance with a read pulse signal to the memory, and a capacity monitoring counter for counting the number of data stored by up / down in accordance with the write pulse signal and the read pulse signal About. This type of memory is widely used in clock transfer circuits (elastic buffers) of transmission devices.

[0002]

2. Description of the Related Art FIG. 7 is a block diagram of a conventional FIFO type memory, showing an example of application to a clock transfer circuit. In the figure, reference numeral 11 denotes a dual port RAM (DPRAM) having two access ports for data writing and reading,
12 is a write counter (WCTR) for generating a write address of the DPRAM 11, 13 is a read counter (RCTR) for generating a read address of the DPRAM 11, and 14 is a serial / parallel which converts serial data SI of a transmission line input into parallel data. Conversion unit (S / P), 15 is DPR
A parallel / serial converter (P / S) for converting parallel data output from AM11 into serial data SO, where A is A
An ND gate circuit, 16 is a capacity monitoring unit for monitoring the number of data stored in the DPRAM 11, and 17 is a capacity monitoring counter (MCTR) composed of an up / down counter that counts up with a write pulse signal WP of the DPRAM 11 and counts down with a read enable signal RE. ), 18 are decoders (DEC) for outputting the buffer full signal BF = 1 when the count output of the capacity monitoring counter 17 is N (maximum), and 19 are for outputting the buffer empty signal BE = 1 when the count output of the capacity monitoring counter 17 is 0. Output decoder (DEC)
It is.

The S / P 14 converts the serial data SI input to the transmission line into parallel data of a predetermined number of bits by the clock signal CKA on the writing (transmission line) side, and in synchronization with the completion of the conversion, the write clock signal WCK. Is output. This write clock signal WCK is input to an AND gate circuit A1, and the AND gate circuit A1 outputs a buffer full signal BF = 1.
If not, a write pulse signal WP is output. The parallel data is transferred to the DPRAM by this write pulse signal WP.
11 is written. The WCTR 12 and the MCTR 17 are each incremented by +1 when the write pulse signal WP falls.

On the other hand, the P / S 15 converts read data from the DPRAM 11 into serial data by a clock signal CKB on the read (device) side, and outputs a read clock signal RCK in synchronization with the completion of the conversion. This read clock signal RCK is input to the AND gate circuit A2, and
Gate circuit A2 outputs read enable signal RE when buffer empty signal BE is not 1. The next data is read from the DPRAM 11 by the read enable signal RE. Also, the read enable signal RE
RCTR13 is incremented by 1 when MCTR falls and MCTR13
17 is decremented by one.

When the write pulse signal WP and the read enable signal RE are generated simultaneously, the DPRAM 11
Inside, data writing and reading are automatically performed by the internal arbitration. On the other hand, the write pulse signal W
If the falling edges of P and the read enable signal RE occur exactly at the same time, the current count output is maintained without being counted up or down. In this way, normally, the MCTR 17 accurately monitors the number of data stored in the DPRAM 11, so that the write data from the transmission line is read out to the device side without excess or deficiency.

[0006]

According to the conventional method, since the clock signals CKA and CKB are asynchronous with each other, the write pulse signal WP and the read enable signal R
Frequently, E may approach or overlap with each other. If the falling edges of both signals overlap exactly, MC
Since the YR 17 maintains the current count output without being counted up or down, no error occurs with the number of data stored in the DPRAM 11. If the falling of both signals is slightly shifted, the counting operation of the MCTR 17 becomes unstable. That is, for example, +1 is given by the immediately preceding write pulse signal WP.
The read enable signal RE immediately after is not decremented by −1, or −1 by the immediately preceding read enable signal RE.
However, it may happen that the write pulse signal WP is not incremented by +1. As a result, an erroneous capacity monitoring signal (BF, BE) is generated, and writing of data larger than the storage capacity and reading of empty data are performed.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and an object of the present invention is to provide a FIFO memory capable of always counting the number of stored data.

[0008]

The above-mentioned problem is solved, for example, by referring to FIG.
Is solved. That is, the FIF of the present invention (1)
The O-type memory includes a dual-port type memory 31 for storing data, and a write counter 3 for generating a write address WA of the memory according to a write pulse signal WP to the memory 31.
2, a read counter 33 for generating a read address RA of the memory according to a read pulse signal RE to the memory 31,
In a FIFO type memory having a capacity monitoring counter 37 for counting the number of stored data by going up / down according to the write pulse signal WP and the read pulse signal RE, a write pulse signal W to the capacity monitor counter 37 is provided.
P or the read pulse signal RE is synchronized with the clock signal CKB / CKA on the read side or the write side.

FIG. 1 shows a case where the read pulse signal RE to the capacity monitoring counter 37 is synchronized with the clock signal CKA on the writing side, and the write pulse signal WP to the capacity monitoring counter 37 is synchronized with the reading side. May be synchronized with the clock signal CKB.

According to the present invention (1), the read pulse signal RE to the capacity monitoring counter 37 is transmitted to the write side clock signal C.
Due to the configuration synchronized with KA, the count-down (read-out pulse) signal RP of the output is exactly the same in phase as the count-up (write-in pulse) signal WP to the capacity monitoring counter 37, or is separated by at least one clock or more. Therefore, the count-up and count-down signals are not input to the capacity monitoring counter 37 at a critical timing, so that the correct data storage number can always be counted.

Preferably, in the present invention (2), in the above-mentioned present invention (1), the count output of the capacity monitoring counter is decoded in units of the number of bytes of the ATM cell.
The configuration is such that the number of stored TM cells can be monitored. Therefore, it is possible to monitor the capacity in units of the number of ATM cells, and it is easy to use especially when applied to a clock transfer circuit of an ATM (asynchronous transfer mode) system.

Preferably, in the present invention (3),
In the present invention (2), a cell empty alarm signal is output when the number of stored ATM cells is less than the first predetermined number, and a cell full alarm signal is output when the number exceeds the second predetermined number. . Accordingly, capacity alarm monitoring can be easily performed in units of the number of ATM cells.

Preferably, in the present invention (4),
In the present invention (1), the alarm detection unit which compares the write address of the write counter with the count output of the capacity monitoring counter at a timing when the read address of the read counter is 0, and generates an alarm signal when the addresses do not match is provided. Prepare.

According to the present invention (1), the counting operation of the capacity monitoring counter 37 can be stabilized.
2. There may be a case where the read counter 33 or the capacity monitoring counter 37 malfunctions. If left unchecked, proper data transfer cannot be expected. Therefore, in the present invention (4), it is noted that at the timing of the read address RA = 0 of the read counter 33, the write address WA of the write counter 32 and the count output MC of the capacity monitoring counter 37 should match. If not, an alarm signal is generated. Therefore, the continuation of the malfunction of the FIFO memory can be effectively prevented.

Preferably, in the present invention (5),
In the above present invention (1), the previous write address is latched, the output is compared with the output of the write counter after the count is updated, and if the difference between them is equal to or greater than a predetermined value, an alarm signal for generating an alarm signal is generated. It has a unit.

Normally, the count output (write address) WA of the write counter 32 is incremented by one at the time of data writing, so that the count (address) difference from the previous time is one. However, this is not always the case if the write counter 32 malfunctions due to the influence of noise or the like. Therefore, in the present invention (5), when these differences are equal to or more than a predetermined value, an alarm signal is generated.
Therefore, the continuation of the malfunction of the FIFO memory can be effectively prevented.

Preferably, in the present invention (6),
In the above present invention (1), the alarm detection unit that latches the previous read address, compares the output with the output of the read counter after updating the count, and generates an alarm signal when the difference between them is equal to or more than a predetermined value. Prepare. The read counter 33 can be similarly configured.

Preferably, in the present invention (7),
In the present invention (1), the count output of the previous capacity monitoring counter is latched and the output is compared with the output of the capacity monitoring counter after the count is updated. If the difference between them is greater than a predetermined value, an alarm signal is generated. An alarm detection unit that performs the operation.

Normally, the count output MC of the capacity monitoring counter 37 is incremented by one at the time of data writing and decremented by one at the time of data reading. Therefore, the count difference from the previous time is ± 1. However, due to the influence of noise or the like, the capacity monitoring counter 3
This is not the case if 7 malfunctions. Therefore, in the present invention (7), when these differences are equal to or larger than a predetermined value, an alarm signal is generated. Therefore, the continuation of the malfunction of the FIFO memory can be effectively prevented.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings. Note that the same reference numerals indicate the same or corresponding parts throughout the drawings.

FIG. 2 is a block diagram of a FIFO type memory according to the embodiment, showing an example of application to a clock transfer circuit. In the figure, reference numeral 31 denotes a dual port RAM (DPR) having two access ports for data writing and reading.
AM), 32 is a write counter (WCTR) for generating a write address of the DPRAM 31; 33 is a read counter (RCTR) for generating a read address of the DPRAM 31;
Reference numeral 4 denotes a serial / parallel converter (S / P) for converting serial data SI input from the transmission path into parallel data;
Is a parallel-to-serial converter (P / P) that converts parallel data output from the DPRAM 31 into serial data SO.
S), A is an AND gate circuit, O is an OR gate circuit, 3
6 is a capacity monitoring unit for monitoring the abnormal operation of the FIFO type memory and the number of data stored in the DPRAM 31, and 37 is a DPRAM
A capacity monitoring counter (MCTR) composed of an up / down counter that counts up by 31 write pulse signals WP and counts down by read pulse signals RP, and 38 is a count output MC = N (maximum) of the capacity monitoring counter 37
And the buffer output signal BF = 1 and the count output MC =
A decoder (DEC) that outputs a buffer full warning signal FLW = 1 at N−1, 39 is a count output MC = 0 of the capacity monitoring counter 37 and a buffer empty signal BE =
1, a decoder (DEC) that outputs a buffer empty alarm signal EPW = 1 when the count output MC = 1, 4
0 is a read enable signal RE to the capacity monitoring counter 37
Circuit (DIF) 41 for synchronizing the clock signal CKA with the write-side clock signal CKA, decodes the count output MC of the capacity monitoring counter 37 in units of bytes of ATM cells, and monitors the number of stored ATM cells. The configured cell number converter (CCT) 42 outputs a cell empty warning signal CEW = 1 when the number of stored ATM cells falls below a first predetermined number (eg, 1), and outputs a second predetermined number. A decoder (DEC) 43 that outputs a cell-full warning signal CFW = 1 by exceeding (for example, M-1), 43
Is an alarm detection unit that detects various abnormal operations regarding the data transfer operation of the FIFO type memory and outputs an alarm signal ALM = 1.

The operations of S / P 34 and P / S 35 may be the same as those described with reference to FIG. Here, the parallel data output from S / P 34 is changed to D by write pulse signal WP.
The data is written to the PRAM 31. The WCTR 32 and the MCTR 37 are each incremented by 1 by the fall of the write pulse signal WP. RCTR13 is incremented by 1 when the read enable signal RE falls, and the MCTR 37 is decremented by 1 when the read pulse signal RP obtained by differentiating the fall of the read enable signal RE with the clock signal CKA.

When the write pulse signal WP and the read pulse signal RP are generated substantially simultaneously, data writing and data reading are automatically performed in the DPRAM 31 by its internal arbitration function. On the other hand, if the falling of the write pulse signal WP and the falling of the read pulse signal RP occur simultaneously in the MCTR 37, the current count output MC is maintained without being counted up or down. Therefore, M
The count-up and count-down signals are not input to the CTR 37 at critical (slightly shifted) timings, so that the correct data storage number can always be counted. Hereinafter, the capacity monitoring unit 36 will be described in detail.

3 to 5 are detailed explanatory diagrams (1) to (3) of the capacity monitoring unit according to the embodiment. FIG. 3 (A) shows the configuration of the differentiating circuit 40, and FIG. 3 (B) shows its operation timing. Each chart is shown. Here, FF1 and FF2 are D-type flip-flops. Read enable signal RE =
During 0, the inverted output Q / = 1 of FF1 and the output Q of FF2
Since = 0, the read pulse signal RP of the output of the AND gate circuit A3 = 0. Even if the read enable signal RE changes from 0 to 1, the read pulse signal RP = 0 due to the inverted output Q / = 0 of the FF1 and the output Q = 1 of the FF2. When the read enable signal RE changes from 1 to 0, FF1
, The read pulse signal RP becomes 1 only for one clock period. Therefore, a read pulse signal RP synchronized with the clock signal CKA is generated in synchronization with the fall of the read enable signal RE.

FIG. 3C shows a cell number conversion unit (CCT) 41.
Is shown. Here, CMP is a comparator,
ENC is an encoder. CMP1 compares the count output MC of the capacity monitoring counter (MCTR) 37 with a predetermined number M1, and if MC ≧ M1, the comparison result signal m1 = 1
Is output. Here, the predetermined number M1 is, for example, the number of bytes of one ATM cell = 53 or the number of bytes of the payload portion thereof =
48 or n times these (n is a natural number). CM
P2 compares the count output MC of the capacity monitoring counter 37 with a predetermined number M2, and outputs a comparison result signal m2 = 1 when MC ≧ M2. Here, the predetermined number M2 is, for example, 2 ×
M1 (at least M2> M1). The CMP3 compares the count output MC of the capacity monitoring counter 37 with a predetermined number M3, and outputs a comparison result signal m3 = 1 when MC ≧ M3. Here, the predetermined number M3 is 3 × M1.

The encoder ENC receives input signals m1 to m3.
, And outputs a signal CELC of the number of storage cells based on. Specifically, an example of the encoding method is “m3, m2, m
When “1” = “0,0,0”, the number of cells CELC = 0 (binary notation), and when “m3, m2, m1” = “0,0,1”, the number of cells CELC = 1, “m3, m2, m1 "=
When “0,1, ×”, the number of cells CELC = 2, “m3, m
When “2, m1” = “1, ×, ×”, the number of cells CELC = 3
Is output. Here, the symbol x represents the logic “1 /” of the bit signal.
"0" indicates no sensing. Although not shown, four or more cells can be counted in the same manner.

FIG. 4A is a diagram showing an example of the configuration of the alarm detection unit 43. Read address RA of read counter 33
= 0, the write address W of the write counter 32
A and the count output MC of the capacity monitoring counter 37 are compared, and when they do not match, an alarm signal is generated.

It should be noted that some alarm detection units 4 will be described below.
Although the third configuration is shown, these may be provided individually in the capacity monitoring unit 36, or one or more of them may be provided in combination. Also, as shown in FIG.
The alarm signal ALM of the output 3 is guided to the reset terminal of each counter via the OR gate circuit 01, and initializes each counter in the same manner as the reset signal SRS input from the outside.

In FIG. 4A, the comparator CMP
Reference numeral 4 compares the write address WA with the count output MC of the capacity monitoring counter 37. If WA ≠ MC when the read address RA = 0, an alarm signal ALM1 = 1 is output. When the read address RA１0, the alarm signal ALM1 = 0 is always present.

FIG. 4B is a diagram showing another example of the alarm detection section 43. The previous write address WA is latched and its output is compared with the output of the write counter 32 after the count is updated. When these differences are equal to or greater than a predetermined value, it indicates a case where an alarm signal is generated. In the figure, a latch circuit L
UT1 outputs the input write address WA to the write pulse signal WP.
Latch at the rising edge of. Thereafter, the write address WA is incremented by +1 (updated) at the fall of the write pulse signal WP.
Is done. The subtractor 51 outputs the updated write address WA
Subtracting the latched write address WAL from
The comparator CMP5 outputs the difference output (usually 1) and a predetermined number 2
Compare with If A ≧ B, the alarm signal A
LM2 = 1 is output.

As shown in FIG. 2, the write counter 32
Outputs a carry signal CAW = 1 when it counts up to its maximum value = N, and is initialized to a count output WA = 0 at the next fall of the write pulse signal WP. FIG. 4 (B)
And the AND gate circuit A4 outputs the carry signal CAW =
When the write pulse signal WP is input at 1, a reset signal is generated, and the latch circuit LUT1 is reset. Therefore, in this case, WA = WAL = 0, and no alarm is detected. Although the figure shows an example of application to the write counter 32, the present invention can be similarly applied to the read counter 33.

FIG. 5 is a diagram showing another example of the alarm detection unit 43. The count output MC of the previous capacity monitoring counter 37 is shown in FIG.
Is latched, the output is compared with the count output MC of the capacity monitoring counter 37 after the count is updated, and when the difference is equal to or greater than a predetermined value, an alarm signal is generated. In the figure, a latch circuit LUT2 latches the count output MC of the capacity monitoring counter 37 at the time of each rise of the write pulse signal WP or the read pulse signal RP. Thereafter, the capacity monitoring counter 37 is incremented by ± 1 (updated) to the count output MC at each falling of the write pulse signal WP or the read pulse signal RP.

On the other hand, the RS type FF3 is usually
Forcibly set / reset by the write pulse signal WP or the read pulse signal RP. Selectors SEL1, SEL2
Selects and outputs the updated count output MC of the capacity monitoring counter 37 or the latch output MCL of the latch circuit LUT2 according to the output Q / = "0/1" of the FF3.
When the selection signal S = 0, the input terminal a is selected, and when the selection signal S = 1, the input terminal b is selected.

Therefore, if only the write pulse signal WP is generated, SEL1 selects and outputs the updated MC.
SEL2 selects and outputs the latched MCL. Thereby, the subtractor 53 normally outputs MC-MCL = 1. The comparator CMP6 has a subtraction output A and a predetermined number B
= 2, and if A ≧ B, the alarm signal A
LM3 = 1 is output.

When only the read pulse signal RP is generated, SEL1 selects and outputs the latched MCL, and SEL2 selects and outputs the updated MC. Thus, the subtractor 53 normally outputs MCL-MC = 1.
When A ≧ B, the comparator CMP6 outputs an alarm signal ALM3 = 1.

When the write pulse signal WP and the read pulse signal RP are generated simultaneously, the outputs of the AND gate circuits A5 and A6 are deactivated by the operation of the NAND gate circuit NA1, so that the FF3 is turned off. Keep state.
On the other hand, the latch LUT2 latches the count output MC of the capacity monitoring counter 37, but this count output MC is not counted up or down. Therefore, the last alarm detection mode (up direction or down direction)
Is maintained.

FIG. 6 is a diagram showing a partial configuration of a clock transfer circuit according to another embodiment, and mainly shows the configuration of a serial / parallel conversion unit. Here, 5-bit data consisting of 4-bit parallel data ID0 to ID3 and 1-bit parity bit IDP is serially input. The odd-numbered data among them is the latch pulse signal L
P1 latches the data in the register REG1, and the even-numbered data is stored in the register R by the latch pulse signal LP2.
The data is latched by EG2 and converted into parallel data of 8-bit data + 2 parity.

The parity checker PCK1 performs a parity check on the latch data D0 to D3 and the latch parity P0, and outputs an error signal PER0 = 1 when an error is detected. The parity checker PCK2 performs a parity check on the latch data D4 to D7 and the latch parity P1, and outputs an error signal PER1 = 1 when an error is detected. These error signals are logically ORed by the OR gate circuit 03 and notified to the device side. Thereby, a data error occurring on the transmission line side can be inspected.

On the other hand, the parity generation unit PG generates a new parity bit signal P3 based on the latch data D0 to D7.
Generate Then, the latch data D0 to D7 and the generated parity P3 are written into the DPRAM 31.
Although not shown, by performing a parity check on the read data of the DPRAM 31, a FIFO type memory (DPRA
The data error generated in M31) can be checked.

Although the above embodiment has been described with specific numerical examples, the present invention is not limited to these numerical examples.

Although the preferred embodiments of the present invention have been described, it goes without saying that various changes can be made in the configuration, control, and combination of these components without departing from the spirit of the present invention.

[0042]

As described above, according to the present invention, the FIF
Since malfunctions due to the approach of the phase of the reading clock in the O-type memory can be effectively avoided, the number of stored data can be always counted, and a highly reliable FIFO type memory can be provided.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram of a FIFO memory according to the embodiment;

FIG. 3 is a detailed explanatory diagram (1) of a capacity monitoring unit according to the embodiment;

FIG. 4 is a detailed explanatory diagram (2) of the capacity monitoring unit according to the embodiment;

FIG. 5 is a detailed explanatory diagram (3) of the capacity monitoring unit according to the embodiment;

FIG. 6 is a diagram illustrating a partial configuration of a clock transfer circuit according to another embodiment.

FIG. 7 is a block diagram of a conventional FIFO memory.

[Explanation of symbols]

 31 Dual Port RAM (DPRAM) 32 Write Counter (WCTR) 33 Read Counter (RCTR) 34 Serial / Parallel Converter (S / P) 35 Parallel / Serial Converter (P / S) 36 Capacity Monitor 37 Capacity Monitor Counter (MCTR) 38, 39 Decoder (DEC) 40 Differentiating circuit (DIF) 41 Cell number conversion unit (CCT) 42 Decoder (DEC) 43 Alarm detection unit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H04L 13/08 H04L 11/20 G (72) Inventor Takanori Uegaki 2-3-3 Shin-Yokohama, Kohoku-ku, Yokohama-shi, Kanagawa No. 9 Fujitsu Digital Technology Co., Ltd. In-house (72) Susumu Suwa 2-3-9 Shin-Yokohama, Kohoku-ku, Yokohama, Kanagawa Prefecture Fujitsu Digital Technology Co., Ltd. F-term (reference) 5B060 AB18 AC07 5K030 HA10 KA03 KA21 KA21 MA13 MB15 5K034 AA06 HH48 HH64 MM08 TT01 9A001 BB02 BB03 EE02 KK56 LL06 LL09

Claims (7)

[Claims] 1. A dual-port memory for storing data, a write counter for generating a memory write address in accordance with a write pulse signal to the memory, and a memory read address in accordance with a read pulse signal for the memory And a capacity monitoring counter for counting the number of data stored by going up / down in accordance with the write pulse signal and the read pulse signal. A FIFO memory in which a pulse signal is synchronized with a clock signal on a read side or a write side. 2. The count output of the capacity monitoring counter is set to AT
2. The FIFO type memory according to claim 1, wherein the number of bytes of the M cell is decoded as a unit, and the number of stored ATM cells can be monitored. 3. A cell empty warning signal is output when the number of stored ATM cells falls below a first predetermined number, and a cell full warning signal is output when the number of ATM cells exceeds a second predetermined number. The F according to claim 2,
IFO type memory. 4. An alarm detecting section for comparing a write address of a write counter with a count output of a capacity monitoring counter at a timing when a read address of the read counter is 0, and generating an alarm signal when they do not match. The FIFO type memory according to claim 1, wherein 5. An alarm detector for latching a previous write address, comparing the output with the output of a write counter after updating the count, and generating an alarm signal if the difference is equal to or greater than a predetermined value. 2. The method according to claim 1, wherein
3. The FIFO memory according to claim 1. 6. An alarm detecting section for latching a previous read address and comparing the output with the output of a read counter after updating the count, and generating an alarm signal when the difference is equal to or more than a predetermined value. Claim 1.
3. The FIFO memory according to claim 1. 7. An alarm detection for latching a previous count output of the capacity monitoring counter, comparing the output with the output of the capacity monitoring counter after the count is updated, and generating an alarm signal when the difference between them is equal to or greater than a predetermined value. The FIFO type memory according to claim 1, further comprising a unit.