JP4825065B2 - Clock transfer circuit - Google Patents

Description

  The present invention relates to an interface circuit of a semiconductor integrated circuit (LSI or the like) having a high-speed data transfer function called a DDR (Double Data Rate) mode, and in particular, both edges of a supplied clock (clock signal; hereinafter the same). The present invention relates to a clock transfer circuit for resampling data transferred in synchronism with the clock in synchronization with one edge of an integer multiple clock generated from the clock.

  A data transfer method for transferring data transmitted in synchronization with both edges (rising and falling) of a supplied clock is called a DDR transfer method. This method is generally used for data transfer between LSIs (Large Scale Integration), DRAM read / write, etc. because the clock frequency can be reduced, or the transfer rate can be doubled as usual without changing the clock frequency. Has been. Note that a device adopting a DDR transfer system is provided with an interface called a DDR interface that performs processing such as supplying a clock for data transfer. Since this DDR interface is a well-known technique, a detailed description thereof will be omitted.

  On the other hand, especially in ASIC (Application Specific Integrated Circuit) and the like, a circuit design that operates in synchronization with one edge (rising or falling) of a supplied clock without adopting the DDR transfer method. Is generally done.

  For this reason, for example, when data transfer is attempted between an ASIC and an LSI adopting the DDR transfer method, data output in synchronization with both edges from the LSI side is doubled in frequency on the LSI side. It is necessary to prepare an interface circuit for resampling in synchronization with one edge of the clock, that is, for changing the frequency for sampling data.

  In general, in this type of interface circuit (clock transfer circuit), a first storage element that stores data supplied from an LSI via a DDR interface in synchronization with a rising edge of a clock supplied from the DDR interface, and a supply A second storage element for storing data in synchronization with the falling edge of the clock, for example, multiplication using a PLL (Phase Locked Loop) from a clock supplied from the LSI side (DDR interface) The circuit generates a clock having a double frequency, and stores the first storage element and the second storage element using an edge (rising or falling) on one side of the generated double clock. By alternately reading data, the clock is switched.

  However, when clocks are switched in this way, if the reading order of data stored in the first storage element and the data stored in the second storage element is shifted from the writing order, There arises a problem that the transfer order is reversed and the data is resampled as a different data group.

  On the other hand, this problem has never been pointed out and no solution has been proposed.

  Therefore, an object of the present invention is to prevent the data stored in the first memory element and the data stored in the second memory element from being read out of the write order and being resampled (data missing or The object is to provide a clock transfer circuit that does not fail.

To achieve the above-described object, according to the clock transfer circuit of the first aspect of the present invention, in the clock transfer circuit applied to the interface adopting the DDR transfer method,
A first synchronized reset circuit for releasing the reset signal in synchronization with the rising edge of the first DDR clock signal supplied from the DDR interface; and a rising edge of the second DDR clock signal obtained by inverting the first DDR clock signal. Output from the first and second synchronization reset circuits from the second synchronization reset circuit that releases the reset signal in synchronization, the output of the first synchronization reset circuit, and the output of the second synchronization reset circuit A phase determination circuit for determining which of the reset signals is reset first.

  In addition, based on the first memory write enable signal generated due to the determination result of the phase determination circuit, the input data supplied from the DDR interface is stored in synchronization with the rising edge of the first DDR clock signal. Based on the first memory element to be started and the second memory write enable signal generated based on the determination result of the phase determination circuit, the input data is stored in synchronization with the rising edge of the second DDR clock signal. A second memory element that starts the first address generation circuit, a first address generation circuit that generates a write address signal to the first memory element in synchronization with the first DDR clock signal, and a second DDR clock signal. And a second address generation circuit for generating a write address signal for the second memory element.

  Further, based on the first memory read enable signal generated due to the determination result of the phase determination circuit, it synchronizes with the transfer clock signal having a frequency twice the frequency of the first or second DDR clock signal. A third address generation circuit for generating a read address signal for reading input data stored in the first storage element, and a second memory read enable generated based on a determination result of the phase determination circuit A fourth address generation circuit is provided that generates a read address signal for reading input data stored in the second storage element in synchronization with the change clock signal based on the signal.

  According to the clock transfer circuit of the second aspect of the present invention, in the clock transfer circuit applied to the interface adopting the DDR transfer method, it is synchronized with the rising edge of the first DDR clock signal supplied from the DDR interface. A first synchronized reset circuit that releases the reset signal and a second synchronized reset circuit that releases the reset signal in synchronization with the rising edge of the second DDR clock signal obtained by inverting the first DDR clock signal; , Based on the output of the first synchronization reset circuit and the output of the second synchronization reset circuit, which one of the reset signals output from the first and second synchronization reset circuits is determined to be reset first A phase determination circuit is provided.

  In addition, based on the first memory write enable signal generated due to the determination result of the phase determination circuit, the input data supplied from the DDR interface is stored in synchronization with the rising edge of the first DDR clock signal. Based on the first memory element to be started and the second memory write enable signal generated based on the determination result of the phase determination circuit, the input data is stored in synchronization with the rising edge of the second DDR clock signal. A second storage element for starting the process.

  A first address generation circuit that generates a write address signal to the first storage element in synchronization with the first DDR clock signal, and a second address to the second storage element in synchronization with the second DDR clock signal. A second address generation circuit for generating a write address signal is provided.

  Further, a transfer clock signal having a frequency twice as high as that of the first or second DDR clock signal based on the first and second memory read enable signals generated due to the determination result of the phase determination circuit. A fifth address generation circuit is provided that generates an address signal for reading input data stored in the first and second storage elements based on the count enable in synchronization with the first and second storage elements.

  In the present invention, the phase determination circuit operates in synchronization with the rising edge of the first DDR clock signal, and the reset is released by the first synchronous reset signal synchronized with the rising edge of the first DDR clock signal. A second flip-flop that operates in synchronization with the rising edge of the second DDR clock signal and is released from the reset by a second synchronous reset signal that is synchronized with the rising edge of the second DDR clock signal. Each of the first and second flip-flops maintains a low level L state during the reset period, and the first flip-flop resets the first and second synchronous reset signals. Based on the shift in release timing, the second flip-flop is reset at the timing when the reset of the first flip-flop is released. When the second flip-flop is at the high level H, the first or second state is maintained by holding the low level L state when the second flip-flop is at the high level H. It is preferable to determine which of the first or second storage element has started storing the input data by determining which of the DDR clock signals is synchronized with the reset.

  According to the clock transfer circuit of the first aspect of the present invention, the phase determination circuit determines whether the data is stored first from the first storage element or the second storage element after reset release. Since the data reading order is determined, no data is lost even if the reset is released first from either the reset signal synchronized with the first DDR clock or the reset signal synchronized with the second DDR clock. Data can be transferred without fail without fail.

  According to the clock transfer circuit of the second aspect of the present invention, since only one address generation circuit is used when reading data from the first and second storage elements, the circuit scale is reduced. Can be planned.

  According to a preferred embodiment of the present invention, since the phase determination circuit has only two flip-flops, data can be transferred reliably without data loss / failure with a simpler circuit configuration. Can be made possible.

  Embodiments of the present invention will be described below with reference to the drawings. In the drawing, each component is merely schematically shown to the extent that the present invention can be understood. The conditions described below are merely preferred examples within the scope of the present invention.

(First embodiment)
1 to 4 are diagrams for explaining a first embodiment of the present invention. First, the configuration will be described, and then the operation will be described. In this embodiment, as shown in FIG. 1, an LSI that adopts the DDR method is used to transfer a clock from an LSI that adopts the DDR method to an ASIC that does not employ the DDR method. The case where the performed data is transferred will be described. The same applies to the following embodiments.

  FIG. 1 is a block diagram schematically showing an example of a usage application of the present invention. As shown in FIG. 1, it is assumed that a reset signal a, a DDR clock d, and a DDR clock e are input to the clock transfer circuit 100 from the DDR interface 4 included in the LSI 2. Further, it is assumed that DDR data f is input from the LSI 2 through the DDR interface 4. Further, it is assumed that a high-level signal “1” and a low-level signal “0” for controlling switching of a circuit, which will be described later, constituting the clock transfer circuit 100 are input from a signal generation circuit (not shown). The signal generation circuit may be provided in the clock transfer circuit 100. Further, the high level signal “1” and the low level signal “0” correspond to the high level “H” and the low level “L”, which are the logical levels of the logical operation, respectively.

  Further, it is assumed that the clock transfer circuit 100 outputs the transfer clock g and the data h after clock transfer to the ASIC 6.

[Configuration of First Embodiment]
FIG. 2 is a block diagram showing an example of the configuration of the clock transfer circuit according to the present invention. 3 and 4 are timing charts (write (write) system and read (read) system) for explaining the operation of the clock transfer circuit of the present invention. Hereinafter, description will be made with reference mainly to FIG. 2 and with reference to FIGS. 3 and 4 as appropriate.

  The clock transfer circuit 100 in FIG. 2 includes a first synchronization reset circuit 10 (synchronization registers 10_1 and 10_2), a second synchronization reset circuit 12 (synchronization registers 12_1 and 12_2), and a phase determination circuit 18 (phases). Determination registers 18_1 and 18_2), a first address generation circuit, that is, a memory write address generation circuit 24_1, a second address generation circuit, that is, a memory write address generation circuit 24_2, a third address generation circuit, that is, a memory read address generation circuit 38_1, 4 address generation circuit, that is, memory read address generation circuit 38_2, a first storage element, that is, memory 26_1, and a second storage element, that is, memory 26_2.

  Further, the clock transfer circuit 100 includes, as peripheral circuits, memory write data capture circuits 14_1 and 14_2, memory write enable generation circuits 22_1 and 22_2, memory write enable delay circuits 32_1 to 32_n (n is a natural number), phase determination acquisition. Insertion circuit 28_1, 28_2, 30_1, 30_2, memory read-on generation circuit 34_1, 34_2, binary counter 36_1, 36_2, memory read data capture circuit 42_1, 42_2, integrated timing generation circuit 40_1, 40_2, memory read data integration circuit 44. OR circuits 48 and 50 and a multiplier circuit 52 are provided.

  The clock transfer circuit 100 also receives a reset signal (hereinafter also simply referred to as reset) a, DDR clock (hereinafter also referred to as first DDR clock) d and DDR clock (hereinafter referred to as “reset”) from the DDR interface 4. Also referred to as a second DDR clock.) E is input, and DDR data f is input from the LSI 2 via the DDR interface 4. The DDR clock “d” and the DDR clock “e” have a phase inversion relationship. Further, for example, in the clock transfer circuit 100, a transfer clock g multiplied by a double frequency is generated from the DDR clock d or e supplied from the DDR interface 4 by the multiplier circuit 52 using a PLL or the like. Is done. Further, the DDR data f input to the clock transfer circuit 100 is output as the clock-changed data h that is transferred to the transfer clock g having a frequency twice the frequency of the DDR clock. That is, the generation cycle of the DDR data f and the generation cycle of the data h are the same cycle, but the cycle of the clock for generating the DDR data f is 2T, and the cycle of the clock for generating the data h is T. , Data f and data h are generated at the rising edge of each clock.

  Hereinafter, processing generated as the data h after clock change from the DDR data f described above will be described.

  In the synchronization registers 10_1 and 10_2 (first synchronization reset circuit), the reset signal a is input to the reset terminal, and the DDR clock d is input to the clock input terminal. The high level signal “1” is input to the synchronization register 10_1, and the output of the synchronization register 10_1 is input to the synchronization register 10_2. The first synchronization reset circuit is asynchronously reset by the reset signal a, and when the reset is released, the high level signal “1” is shifted by two cycles with the DDR clock d and outputs the DDR clock synchronous reset signal b (see FIG. 3). ).

  The synchronization registers 12_1 and 12_2 (second synchronization reset circuit) each receive a reset signal a at its reset terminal and a DDR clock e at its clock input terminal. The high level signal “1” is input to the synchronization register 12_1, and the output of the synchronization register 12_1 is input to the synchronization register 12_2. The second synchronization reset circuit is asynchronously reset by the reset signal a, and shifts the high level signal “1” by two cycles with the DDR clock e when the reset is released, and outputs a DDR clock synchronization reset signal c. In the present invention, description will be made assuming that the synchronization reset is performed first after the first synchronization reset circuit.

  The DDR clock synchronization reset signal b is input to the reset terminal of the memory write data fetch circuit 14_1, and the DDR clock d is input to the clock input terminal. The memory write data fetch circuit 14_1 fetches the DDR data f at the rising edge of the DDR clock d and inputs it to the memory 26_1. In this case, the DDR data f is write data of the memory 26_1 (hereinafter also referred to as a first storage element).

  The DDR clock synchronization reset signal c is input to the reset terminal of the memory write data fetch circuit 14_2, and the DDR clock e is input to the clock input terminal. The memory write data fetch circuit 14_2 fetches the DDR data f at the rising edge of the DDR clock e and inputs it to the memory 26_2. In this case, the DDR data f is write data of the memory 26_2 (hereinafter also referred to as a second storage element).

  The DDR clock synchronization reset signal b is input to the reset terminal of the phase determination register 18_1, and the DDR clock d is input to the clock input terminal. The output signal of the phase determination register 18_1 is input to the phase determination register 18_2 and also input to the phase determination fetch circuit 28_1. The phase determination register 18_1 is also referred to as a first flip-flop.

  The DDR clock synchronization reset signal c is input to the reset terminal of the phase determination register 18_2, and the DDR clock e is input to the clock input terminal. The output signal of the phase determination register 18_2 is input to the phase determination register 18_1 and also input to the phase determination fetch circuit 30_1. The phase determination register 18_2 is also referred to as a second flip-flop.

  The phase determination register 18_1 captures “1” if the output signal of the phase determination register 18_2 is “0” at the rising edge of the DDR clock d, and captures “0” if it is “1”. The phase determination register 18_2 captures “1” when the output signal of the phase determination register 18_1 is “0” at the rising edge of the DDR clock e, and captures “0” when the output signal is “1”. The phase determination register 18_1 and the phase determination register 18_2 are collectively referred to as a phase determination circuit 18.

  The DDR clock synchronization reset signal b is input to the reset terminal of the memory write enable generation circuit 22_1 (negative logic), and the DDR clock d is input to the clock input terminal. Further, the low level signal “0” is input to the memory write enable generation circuit 22_1, and the output signal is input to the memory write address generation circuit 24_1 and the memory 26_1. The memory write enable generation circuit 22_1 takes a fixed value, that is, a low level signal “0” at the rising edge of the DDR clock d, and generates a write enable signal (hereinafter also referred to as a first memory write enable signal) of the memory 26_1. To do.

  The DDR clock synchronization reset signal c is input to the reset terminal of the memory write enable generation circuit 22_2 (negative logic), and the DDR clock e is input to the clock input terminal. Further, the low level signal “0” is input to the memory write enable generation circuit 22_2, and the output signal is input to the memory write address generation circuit 24_2 and the memory 26_2. The memory write enable generation circuit 22_2 takes a fixed value, that is, a low level signal “0” at the rising edge of the DDR clock d, and generates a write enable signal (hereinafter also referred to as a second memory write enable signal) of the memory 26_2. To do. In the above description and the following description, the write enable signal and the memory write enable signal are also simply referred to as a write enable and a memory write enable.

  The DDR clock synchronization reset signal b is input to the reset terminal of the memory write address generation circuit 24_1 (first address generation circuit), and the DDR clock d is input to the clock input terminal. The memory write address generation circuit 24_1 counts up at the rising edge of the DDR clock d when the output signal of the memory write enable generation circuit 22_1 is “0”, and generates the write address of the memory 26_1.

  The DDR clock synchronization reset signal c is input to the reset terminal of the memory write address generation circuit 24_2 (second address generation circuit), and the DDR clock e is input to the clock input terminal. The memory write address generation circuit 24_2 counts up at the rising edge of the DDR clock e when the output signal of the memory write enable generation circuit 22_2 is “0”, and generates the write address of the memory 26_2.

  The memory 26_1 receives the outputs from the DDR clock d and the memory write data fetch circuit 14_1 synchronized with the DDR clock d, the memory write enable generation circuit 22_1, and the memory write address generation circuit 24_1 on the write side. The DDR data f is written to the memory 26_1. That is, when the output of the memory write enable generation circuit 22_1 is “0”, the output of the memory write data capture circuit 14_1 is set to the write address (address) which is the output of the memory write address generation circuit 24_1 at the rising edge of the DDR clock d. Write data (DDR data f) is written.

  In addition, the memory 26_1 receives the output from the transfer clock g, the OR circuit 48 synchronized with the transfer clock g, and the output of the memory read address generation circuit 38_1 on the read side, and is written from the memory 26_1. Reading (reading) of the DDR data f is performed. That is, when the memory read enable signal i (first memory read enable signal), which is the output of the OR circuit 48, is “0”, the output of the memory read address generation circuit 38_1 is synchronized with the rising edge of the transfer clock g. Data at a certain read address (address) is output as memory read data k to the memory read data fetch circuit 42_1. Hereinafter, the memory read enable signal is simply referred to as memory read enable. The output when the memory read enable i is “1” holds the previous value, that is, the data stored in the memory 26_1 in the past. It is also possible to configure the memory to output indeterminate data without holding the previous value. The timing charts of FIG. 3 and FIG. 4 are for holding the previous value.

  The memory 26_2 receives the output signals from the DDR clock e and the memory write data capture circuit 14_2, the memory write enable generation circuit 22_2, and the memory write address generation circuit 24_2 that are synchronized with the DDR clock e on the write side, The DDR data f is written from the memory 26_2. That is, when the output signal of the memory write enable generation circuit 22_2 is “0”, a write address (address) signal (also simply referred to as a write address) that is an output signal of the memory write address generation circuit 24_2 at the rising edge of the DDR clock e. ), Write data (DDR data f) that is an output signal of the memory write data fetch circuit 14_2 is written to the memory 26_2.

  Further, the memory 26_2 receives, on the read side, output signals from the OR clock 50 and the memory read address generation circuit 38_2 in synchronization with the transfer clock and the transfer clock, and the DDR written from the memory 26_2. Data is read. That is, when the memory read enable j (second memory read enable) that is the output signal of the OR circuit 50 is “0”, the output signal of the memory read address generation circuit 38_2 is synchronized with the rising edge of the transfer clock g. The read address (address) signal (also simply referred to as a read address) is output as memory read data 1 to the memory read data fetch circuit 42_2. The output signal when the memory read enable j is “1” holds the previous value, that is, the data previously stored in the memory 26_2. Note that, similarly to the memory 26_1, it may be configured by a memory that outputs indeterminate data without holding the previous value. The timing charts of FIG. 3 and FIG. 4 are for holding the previous value.

  In the memory write enable delay circuits 32_1 to 32_n, the reset signal a is input to each reset terminal, and the transfer clock g is input to the clock input terminal. The output signal of the memory write enable delay circuit 32_n is input to the memory read-on generation circuits 34_1 and 34_2. The memory write enable delay circuits 32_1 to 32_n capture the output signal of the memory write enable generation circuit 22_1 synchronized with the DDR clock d at the rising edge of the transfer clock g and shift n stages. This is to provide a distance between the memory write address and the read address, that is, to delay the signal. The output signal of the memory write enable delay circuit 32_n generates the memory read enable i and the memory read enable j. It becomes the original signal to do.

  Note that this delay may be performed on the output of the memory write enable generation circuit 22_2. That is, as already described, since this delay circuit is for providing a distance between the write address and the read address, the output signal of the memory write enable generation circuit 22_1 that is shifted by a half phase by the DDR clock and This is because it is not necessary to shift the output signals of the memory write enable generation circuit 22_2 separately (an approximate distance may be maintained). Note that it is not preferable to shift these separately because the first stage capture may cause a shift of one cycle of the DDR clock due to clock jitter or the like. Therefore, only one of the output signal of the memory write enable generation circuit 22_1 and the output signal of the memory write enable generation circuit 22_2 is shifted. In this embodiment, the output signal of the memory write enable generation circuit 22_1 is delayed.

  A reset signal a is input to each reset terminal of the phase determination fetch circuits 28_1 and 28_2, and a transfer clock g is input to the clock input terminal. The output signal of the phase determination acquisition circuit 28_1 is input to the phase determination acquisition circuit 28_2, and the output of the phase determination acquisition circuit 28_2 is input to the memory read-on generation circuit 34_1. The phase determination capture circuits 28_1 and 28_2 capture the output signal of the phase determination register 18_1 synchronized with the DDR clock d at the rising edge of the transfer clock g, and shift the output signal of the phase determination register 18_1.

  The reset signal a is input to each reset terminal of the phase determination fetch circuits 30_1 and 30_2, and the transfer clock g is input to the clock input terminal. The output signal of the phase determination acquisition circuit 30_1 is input to the phase determination acquisition circuit 30_2, and the output signal of the phase determination acquisition circuit 30_2 is input to the memory read-on generation circuit 34_2. The phase determination capture circuits 30_1 and 30_2 capture the output signal of the phase determination register 18_2 synchronized with the DDR clock e at the rising edge of the transfer clock, and shift the output signal of the phase determination register 18_2.

  In the memory read-on generation circuit 34_1, the reset signal a is input to the reset terminal, and the transfer clock g is input to the clock input terminal. The output signal of the memory read-on generation circuit 34_1 is input to the OR circuit 48, the binary counter 36_1, and the memory read-on generation circuit 34_2. The memory read-on generation circuit 34_1 performs the following operation in synchronization with the transfer clock g when the output signal of the memory write enable delay circuit 32_n is “0”. That is, if the output signal of the phase determination capture circuit 28_2 is “1”, “0” is held, and if the output signal of the phase determination capture circuit 28_2 is “0”, the memory read-on generation circuit 34_2 Capture the output signal. The output signal of the memory read-on generation circuit 34_1 is an original signal for generating the memory read enable i.

  In the memory read-on generation circuit 34_2, the reset signal a is input to the reset terminal, and the transfer clock g is input to the clock input terminal. The output signal of the memory read-on generation circuit 34_2 is input to the OR circuit 50, the binary counter 36_2, and the memory read-on generation circuit 34_1. The memory read-on generation circuit 34_2 performs the following operation in synchronization with the transfer clock g when the output signal of the memory write enable delay circuit 32_n is “0”. That is, the memory read-on generation circuit 34_2 holds “0” if the output of the phase determination capture circuit 30_2 is “1”, and if the output signal of the phase determination capture circuit 30_2 is “0”, The output signal of the memory read-on generation circuit 34_1 is captured. The output signal of the memory read-on generation circuit 34_2 is an original signal for generating the memory read enable j.

  In the binary counter 36_1, a reset signal a is input to a reset terminal, and a transfer clock g is input to a clock input terminal. The output signal of the binary counter 36_1 is input to the OR circuit 48, the integrated timing generation circuit 40_1, and the memory read address generation circuit 38_1. The binary counter 36_1 toggles (repeats H "1" and L "0" in synchronization with the transfer clock when the output signal of the memory read-on generation circuit 34_1 is "0". A memory read enable i is obtained by ORing the output signal of the memory read-on generation circuit 34_1 and the output signal of the binary counter 36_1.

  In the binary counter 36_2, a reset signal a is input to a reset terminal, and a transfer clock g is input to a clock input terminal. The output signal of the binary counter 36_2 is input to the OR circuit 50, the integrated timing generation circuit 40_2, and the memory read address generation circuit 38_2. The binary counter 36_2 toggles in synchronization with the transfer clock when the output of the memory read-on generation circuit 34_2 is “0”. The memory read enable j is obtained by ORing the output signal of the memory read-on generation circuit 34_2 and the output signal of the binary counter 36_2.

  In the memory read address generation circuit 38_1 (third address generation circuit), the reset signal a is input to the reset terminal, and the transfer clock g is input to the clock input terminal. The memory read address generation circuit 38_1 counts up at the rising edge of the transfer clock when the output signal of the binary counter 36_1 is “1”, and generates the read address of the memory 26_1.

  In the memory read address generation circuit 38_2 (fourth address generation circuit), the reset signal a is input to the reset terminal, and the transfer clock g is input to the clock input terminal. The memory read address generation circuit 38_2 generates a read address of the memory 26_2 by counting up at the rising edge of the transfer clock when the output signal of the binary counter 36_2 is “1”.

  In the memory read data fetch circuit 42_1, the reset signal a is input to the reset terminal, and the transfer clock g is input to the clock input terminal. The memory read data fetch circuit 42_1 fetches the memory read data k at the rising edge of the transfer clock g.

  In the memory read data fetch circuit 42_2, the reset signal a is input to the reset terminal, and the transfer clock g is input to the clock input terminal. The memory read data capturing circuit 42_2 captures the memory read data 1 at the rising edge of the transfer clock g.

  In the integrated timing generation circuit 40_1, the reset signal a is input to the reset terminal, and the transfer clock g is input to the clock input terminal. The output signal of the integration timing generation circuit 40_1 is input to the memory read data integration circuit 44. The integrated timing generation circuit 40_1 is a register that delays the binary counter 36_1 by one cycle.

  In the integrated timing generation circuit 40_2, the reset signal a is input to the reset terminal, and the transfer clock g is input to the clock input terminal. The output signal of the integration timing generation circuit 40_2 is input to the memory read data integration circuit 44. The integrated timing generation circuit 40_2 is a register that delays the binary counter 36_2 by one cycle.

  In the memory read data integration circuit 44, the reset signal a is input to the reset terminal, and the transfer clock g is input to the clock input terminal. The memory read data integration circuit 44 receives the output signal of the memory read data acquisition circuit 42_1 when the output signal of the integration timing generation circuit 40_1 is “1” at the rising edge of the transfer clock g, and the integration timing generation circuit 40_2. When the output signal is “1”, the output signal of the memory read data fetch circuit 42_2 is fetched, and the DDR data f is outputted as the data h after the clock change.

[Operation of First Embodiment]
<Writing data to memory>
First, the writing of DDR data f to the first and second memory elements 26_1 and 26_2 will be described with reference to the timing chart of FIG.

  The DDR data f transferred to the clock transfer circuit 100 via the DDR interface 4 is stored in the memory 26_1 via the memory write data fetch circuit 14_1 in synchronization with the rising edge of the DDR clock d, and DDR. In synchronization with the rising edge of the clock e, the data is stored in the memory 26_2 via the memory write data fetch circuit 14_2. As already described, the phases of the DDR clock d and the DDR clock e are inverted. Therefore, the DDR data f transferred to the clock transfer circuit via the DDR interface is alternately written in the memory 26_1 and the memory 26_2 in terms of time.

  Addresses for storing the DDR data f in the memory 26_1 and the memory 26_2 are generated by the memory write address generation circuit 24_1 and the memory write address generation circuit 24_2. The memory write address generation circuit 24_1 and the memory write address generation circuit 24_2 operate in synchronization with the rising edge of the DDR clock d and the rising edge of the DDR clock e, respectively. In other words, when either clock is used as a reference, the addresses for storing the DDR data f in the memory 26_1 and the memory 26_2 operate so that the addresses are updated in synchronization with the half-phase shifted clocks. (See FIG. 3).

  Further, the memory write address generation circuit 24_1 and the memory write address generation circuit 24_2 start to operate in response to output signals of the corresponding memory write enable generation circuit 22_1 (negative logic) and the memory write enable generation circuit 22_2 (negative logic), respectively. In this embodiment, the memory write address generation circuit 24_1 starts its operation earlier than the memory write address generation circuit 24_2.

  The memory write enable generation circuit 22_1 operates to capture a fixed value, that is, a low level signal “0” in synchronization with the DDR clock d, and a DDR clock synchronization reset signal b synchronized with the DDR clock d from the synchronization register 10_2. Is entered. Similarly, the memory write enable generation circuit 22_2 operates to capture a fixed value, that is, a low level signal “0” in synchronization with the DDR clock e, and synchronizes with the DDR clock e from the synchronization register 12_2. A reset signal c is input.

  In the present invention, in the memory write enable generation circuit 22_1 and the memory write enable generation circuit 22_2 and the phase determination circuit 18 described later, the output signal of the synchronization register 10_2 in the memory write enable generation circuit 22_1 and the phase determination register 18_1. The release timing of the DDR clock synchronization reset signal (first synchronization reset signal) b is the same (the delay of the DDR clock synchronization reset signal b is within one cycle). Similarly, in the memory write enable generation circuit 22_2 and the phase determination register 18_2, the release timing of the DDR clock synchronization reset signal (second synchronization reset signal) c that is the output signal of the synchronization register 12_2 is the same (DDR clock synchronization reset). The delay of the signal c is within 1 cycle). As a result, the phase determination result, that is, the determination result of the phase determination circuit 18 indicating whether the writing of the DDR data f is first started from the memory 26_1 or the memory 26_2, and the writing of the DDR data f is actually started. Will always match the side.

<Reading data from memory>
Next, with reference to the timing chart of FIG. 4, an operation for reading the DDR data f stored in the first and second storage elements 26_1 and 26_2 will be described.

  The phase determination capture circuits 28_2 and 30_2 that have captured the output signals of the phase determination circuit 18 (phase determination registers 18_1 and 18_2) in synchronization with the transfer clock g are the sources of memory read enable of the memory 26_1 and the memory 26_2, respectively. Signals are output to the memory read-on generation circuit 34_1 and the memory read-on generation circuit 34_2 which are signal generation means. The memory read-on generation circuit 34_1 and the memory read-on generation circuit 34_2 can write DDR data from either the memory 26_1 or the memory 26_2 based on the signals input from the phase determination acquisition circuit 28_2 and the phase determination acquisition circuit 30_2. It is determined whether it has been started (described later), and a memory read enable original signal is generated for the memory on which writing has been started first.

  Output signals of the memory read-on generation circuit 34_1 and the memory read-on generation circuit 34_2, which are original signal generation means for memory read enable, are input to the binary counters 36_1 and 36_2, and the binary counter 36_1 is input to the memory read-on generation circuit 34_1. The binary counter 36_2 toggles in synchronization with the transfer clock when the output of the memory read-on generation circuit 34_2 is "0". The OR logic output of the binary counter 36_1 and the memory read-on generation circuit 34_1 becomes the memory read enable i, and the OR logic output of the binary counter 36_2 and the memory read-on generation circuit 34_2 becomes the memory read enable j.

  Output signals of the binary counters 36_1 and 36_2 are input to the third and fourth address generation circuits, and the memory read address generation circuit 38_1 and the memory read address generation circuit 38_2, which are the third and fourth address generation circuits, When the binary counter 36_1 and the binary counter 36_2 are "1", the counter is counted up in synchronization with the transfer clock.

  Based on the read addresses generated by the memory read address generation circuits 38_1 and 38_2, the memory read enable i, and the memory read enable j, the DDR data read from the memory 26_1 and the memory 26_2 is temporarily read from the memory read data. After being read out by the memory circuit 42_1 and the memory read data capturing circuit 42_2, it is input to the memory read data integration circuit 44, and the clock is changed from the DDR clock d and the DDR clock e to the transfer clock g. The post data h is output from the clock transfer circuit 100 of the present invention to the ASIC 6.

  Next, the aforementioned phase determination circuit that is a feature of the present invention will be described in detail.

  The phase determination circuit operates in synchronization with the DDR clock d, and receives the DDR clock synchronization reset signal b, which is the output signal of the synchronization register 10_2, synchronized with the DDR clock d, the phase determination register 18_1 (first And a phase determination register 18_2 that operates in synchronization with the DDR clock e and receives the DDR clock synchronization reset signal c that is synchronized with the DDR clock e and that is an output signal of the synchronization register 12_2. 2 flip-flops). The output signal from the phase determination register 18_1 is input to the phase determination register 18_2, and the output signal from the phase determination register 18_2 is input to the phase determination register 18_1.

  The states of the first flip-flop and the second flip-flop constituting the phase determination register 18_1 and the phase determination register 18_2 are (L, L) while both the DDR clock synchronization reset signal b and the DDR clock synchronization reset signal c are reset. ). Here, the parentheses indicate (the state of the first flip-flop, the state of the second flip-flop).

  When the reset of the DDR clock synchronization reset signal b is released, the first flip-flop holds the high level H when the state of the second flip-flop is the low level L, and the state of the second flip-flop When is at the high level H, the low level L is held. When the reset of the DDR clock synchronization reset signal c is released, the second flip-flop holds H when the state of the first flip-flop is L, and the state of the first flip-flop is H In the case, L is held.

  Here, each reset signal input to the first flip-flop and the second flip-flop is input in a form synchronized with a half-phase shifted clock. As a result, the resetting of these flip-flops is always canceled at a timing shifted by a half phase of the clock. Therefore, at the time of reset release, one of the flip-flops always changes state from L to H, and the state continues to be held. That is, the state is maintained until the state transits to either (H, L) or (L, H) and the reset becomes valid again. In this embodiment (timing chart), the case of (H, L) and the case where DDR data is written first from the memory 26_1 is described as an example.

  With these operations, even when each reset is released in a phase-free manner with respect to DDR clock d and DDR clock e, in this phase determination circuit, which clock was released before the reset was released first. The memory read-on generation circuit 34_1 and the memory read-on generation, which are the original signals of the memory read enable i and the memory read enable j of the memory 26_1 and the memory 26_2, are output using the output signal of the phase determination circuit. By controlling the generation of the output signal of the circuit 34_2, it is possible to realize the clock change while avoiding the failure (error) of the output order with respect to the input order of the DDR data.

[Effects of First Embodiment]
Therefore, according to this embodiment, in the phase determination register 18_1 and the phase determination register 18_2, after the reset is released, it is determined which of the memory 26_1 and the memory 26_2 has been stored first, and the data reading order is determined. Therefore, even if the reset is released first from either the DDR clock synchronization reset b synchronized with the DDR clock d or the DDR clock synchronization reset c synchronized with the DDR clock e, that is, supplied from the DDR interface. It is possible to provide an interface circuit (clock transfer circuit) that can reliably transfer data without losing or failing data without depending on the release timing of the DDR clock and the reset signal.

  In addition, according to this embodiment, the buffer amounts of the memory 26_1 and the memory 26_2, and the address value generated by the memory write address generation circuit 24_1 and the address value generated by the memory read address generation circuit 38_1 are provided with a distance. By optimally setting the number of stages of the delay circuits (memory write enable delay circuits 32_1 to 32_n), it is caused by jitter generated in a circuit such as a PLL that generates a switching clock having a double frequency from the supplied DDR clock. It is possible to avoid data loss / destruction.

(Second Embodiment)
5 and 6 are diagrams for explaining a second embodiment of the present invention. First, the configuration will be described, and then the operation will be described. FIG. 5 is a block diagram showing an example of the configuration of the clock transfer circuit 200 according to the second embodiment of the present invention. FIG. 6 shows the operation of the clock transfer circuit according to the second embodiment of the present invention ( It is a timing chart for explaining a lead system.

  5, components having the same configuration and the same function as those in FIG. 2 are denoted by the same reference numerals, and description thereof is omitted or simplified. Hereinafter, description will be made with reference to FIG. 5 and with reference to FIG. 6 as appropriate.

[Configuration of Second Embodiment]
In the first embodiment, the case where two counter circuits used for address generation, such as the third and fourth address generation circuits, have been described, but the outputs of the memory read address generation circuit 38_1 and the memory read address generation circuit 38_2. The change point of the read address is the two-cycle width of the transfer clock g, and access to the memory 26_1 and the memory 26_2 is performed once every two cycles of the transfer clock g and is alternately performed every time. Therefore, in this embodiment, the memory read address generation circuit 38_1 and the memory read address generation circuit 38_2, which are two address generation counters, can be configured by one address generation counter (memory read address generation circuit 46). I can do it.

  The memory read address generation circuit 46, which is the fifth address generation circuit, receives a reset signal a at its reset terminal and a transfer clock g at its clock input terminal. Further, the output signal of the binary counter 36_1 is input to the memory read address generation circuit 46. The output signal (address) of the memory read address generation circuit 46 is input to the memory 26_1 and the memory 26_2.

[Operation of Second Embodiment]
In the memory read address generation circuit 46 as the fifth address generation circuit, an output signal of the following logical expression is generated as a count enable signal (also simply referred to as count enable) of the memory read address generation circuit 46 (FIG. 6). reference). The count enable is a timing signal used when counting memory read addresses. When the count enable is 1, the address counter is increased in synchronization with the rising edge of the transfer clock g.
Count enable = {(binary counter 36_1) AND (phase determination capture circuit 28_2)} OR
{(Binary counter 36_2) AND (phase determination capture circuit 30_2)} (1)
In Expression (1), only the output signal of the binary counter that started writing first is output. When this count enable is 1, it counts up at the rising edge of the transfer clock g and becomes the read address of the memory 26_1 and the memory 26_2.

[Effects of Second Embodiment]
Therefore, according to this embodiment, the same operational effects as the first embodiment can be obtained, and in the first embodiment, the second and third address generation circuits are used in comparison with the first and second address generation circuits. In the second embodiment, only one fifth address generation circuit needs to be used, and the effect of reducing the circuit scale can be obtained.

(Modification of embodiment)
As described above, the clock transfer circuit is used as an interface between an LSI and an ASIC, for example, but is also applicable to an interface with a general-purpose PHY (physical layer) chip of a high-speed interface such as G-bit Ethernet. Is possible.

  Further, the present invention is not limited to the above-described embodiments, and modifications, improvements and the like within the scope that can achieve the object of the present invention are also included in the present invention.

  For example, the best configuration for carrying out the present invention has been disclosed in the above description, but the present invention is not limited to this. That is, the present invention has been illustrated and described with particular reference to particular embodiments, but may be configured with respect to the above-described embodiments without departing from the scope of the technical idea and objects of the invention. Various modifications can be made by those skilled in the art in operation, quantity, and other detailed configurations.

  Therefore, the description limited to the configuration, operation, etc. disclosed above is exemplary for easy understanding of the present invention, and does not limit the present invention. The description of the name of the configuration excluding a part or all of the limitation is included in the present invention.

It is the block diagram which showed roughly an example of the use application of this invention. It is the block diagram which showed one structural example of the clock transfer circuit concerning 1st Embodiment of this invention. It is a timing chart for demonstrating the operation | movement (write system) of the clock transfer circuit concerning 1st Embodiment of this invention. It is a timing chart for demonstrating the operation | movement (read system) of the clock transfer circuit concerning 1st Embodiment of this invention. It is the block diagram which showed the example of 1 structure of the clock transfer circuit concerning 2nd Embodiment of this invention. It is a timing chart for demonstrating operation | movement (read type | system | group) of the clock transfer circuit concerning 2nd Embodiment of this invention.

Explanation of symbols

2 ... LSI
4 ... DDR interface 6 ... ASIC
100, 200: Clock transfer circuit 10_1, 10_2: Synchronization register (10: first synchronization reset circuit)
12_1, 12_2 ... synchronization register (12: second synchronization reset circuit)
14_1, 14_2 ... Memory write data fetch circuit 18 ... Phase determination circuit 18_1 ... Phase determination register (first flip-flop)
18_2 ... Phase determination register (second flip-flop)
22_1, 22_2 ... Memory write enable generation circuit 24_1 ... Memory write address generation circuit (first address generation circuit)
24_2 ... Memory write address generation circuit (second address generation circuit)
26_1 ... Memory (first storage element)
26_2 ... Memory (second storage element)
28_1, 28_2, 30_1, 30_2 ... Phase determination fetch circuit 32_1-32_n ... Memory write enable delay circuit 34_1, 34_2 ... Memory read-on generator circuit 36_1, 36_2 ... Binary counter 38_1 ... Memory read address generator circuit (third address) Generation circuit)
38_2 ... Memory read address generation circuit (fourth address generation circuit)
40_1, 40_2 ... Integrated timing generation circuit 42_1, 42_2 ... Memory read data fetch circuit 44 ... Memory read data integration circuit 46 ... Memory read address generation circuit (fifth address generation circuit)
48, 50 ... OR circuit 52 ... Multiplication circuit

Claims (3)

In the clock transfer circuit applied to the interface adopting the DDR transfer method,
A first synchronized reset circuit for releasing the reset signal in synchronization with the rising edge of the first DDR clock signal supplied from the DDR interface;
A second synchronized reset circuit for releasing a reset signal in synchronization with a rising edge of a second DDR clock signal obtained by inverting the first DDR clock signal;
Which of the reset signals output from the first and second synchronization reset circuits was previously reset based on the output of the first synchronization reset circuit and the output of the second synchronization reset circuit A phase determination circuit for determining
Storage of input data supplied from the DDR interface in synchronization with the rising edge of the first DDR clock signal based on the first memory write enable signal generated based on the determination result of the phase determination circuit. A first storage element that starts
Based on the second memory write enable signal generated due to the determination result of the phase determination circuit, the storage of the input data is started in synchronization with the rise of the second DDR clock signal. A storage element;
A first address generation circuit that generates a write address signal to the first storage element in synchronization with the first DDR clock signal;
A second address generation circuit that generates a write address signal to the second storage element in synchronization with the second DDR clock signal;
Based on the first memory read enable signal generated due to the determination result of the phase determination circuit, it synchronizes with the transfer clock signal having a frequency twice the frequency of the first or second DDR clock signal. A third address generation circuit for generating a read address signal for reading the input data stored in the first storage element;
Based on the second memory read enable signal generated due to the determination result of the phase determination circuit, the input data stored in the second storage element is read in synchronization with the change clock signal. And a fourth address generation circuit for generating a read address signal for the clock transfer circuit. In the clock transfer circuit applied to the interface adopting the DDR transfer method,
A first synchronized reset circuit for releasing the reset signal in synchronization with the rising edge of the first DDR clock signal supplied from the DDR interface;
A second synchronized reset circuit for releasing a reset signal in synchronization with a rising edge of a second DDR clock signal obtained by inverting the first DDR clock signal;
Which of the reset signals output from the first and second synchronization reset circuits was previously reset based on the output of the first synchronization reset circuit and the output of the second synchronization reset circuit A phase determination circuit for determining
Storage of input data supplied from the DDR interface in synchronization with the rising edge of the first DDR clock signal based on the first memory write enable signal generated based on the determination result of the phase determination circuit. A first storage element that starts
Based on the second memory write enable signal generated due to the determination result of the phase determination circuit, the storage of the input data is started in synchronization with the rise of the second DDR clock signal. A storage element;
A first address generation circuit that generates a write address signal to the first storage element in synchronization with the first DDR clock signal;
A second address generation circuit that generates a write address signal to the second storage element in synchronization with the second DDR clock signal;
Based on the first and second memory read enable signals generated due to the determination result of the phase determination circuit, the transfer clock signal having a frequency twice the frequency of the first or second DDR clock signal And a fifth address generation circuit for generating an address signal for reading the input data stored in the first and second storage elements based on a count enable. Clock transfer circuit. The phase determination circuit includes:
A first flip-flop that operates in synchronization with a rising edge of the first DDR clock signal and is released from a reset by a first synchronous reset signal that is synchronized with the rising edge of the first DDR clock signal;
A second flip-flop that operates in synchronization with the rising edge of the second DDR clock signal and is released from reset by a second synchronous reset signal that is synchronized with the rising edge of the second DDR clock signal;
The first and second flip-flops both maintain a low level L state during the reset period, and the first flip-flop shifts the reset release timing of the first and second synchronous reset signals. When the second flip-flop is at the low level L at the timing when the reset of the first flip-flop is released, the state transits to the high level H, and the second flip-flop In the case of the level H, by holding the low level L state, it is determined in synchronization with the first or second DDR clock signal that the reset is released, so that the first or second 3. The clock change according to claim 1, wherein the storage device determines whether the storage of the input data is started from any one of the two storage elements. Road.

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