JP6028704B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device.

  2. Description of the Related Art Conventionally, semiconductor devices are configured by bonding wires or the like to electrode pads provided on the surface. At the time of bonding, stress may act on the interlayer insulating film below the electrode pad through the electrode pad, and there is a problem that a crack or the like is generated in the interlayer insulating film depending on the stress. As a technique for dealing with this problem, a semiconductor device shown in Patent Document 1 below is known.

  In the semiconductor device disclosed in Patent Document 1, an electrode pad is disposed via an organic SOG layer and a reinforcing insulating layer stacked on an internal wiring layer, and via a via provided below the electrode pad covered with a passivation layer. The electrode pad and the internal wiring layer are configured to be electrically connected. For this reason, even when stress is applied through the electrode pad during bonding, the organic SOG layer is protected by the high-strength reinforcing insulating layer, so that the occurrence of cracks in the organic SOG layer is prevented.

JP 2000-340569 A

  By the way, due to limitations due to the downsizing of the substrate, an internal wiring layer may have to be disposed below the portion of the electrode pad where a pressing force acts during bonding or inspection using a probe. In this case, the configuration disclosed in Patent Document 1 cannot be adopted, and the internal wiring layer may be plastically deformed due to the pressing force, and other insulation is caused by the elastically deformed internal wiring layer. The layer can crack.

  The present invention has been made to solve the above-described problems, and the object of the present invention is to be laminated on the internal wiring layer even when the internal wiring layer located below the electrode pad is plastically deformed. An object of the present invention is to provide a semiconductor device capable of suppressing the occurrence of cracks in an insulating layer.

In order to achieve the above object, a semiconductor device according to claim 1 is an internal wiring layer (23) and a plurality of insulating layers (33, 34) stacked on the internal wiring layer, An electrode pad (25) disposed above the plurality of insulating layers, at least a portion thereof facing at least a portion of the internal wiring layer via the plurality of insulating layers, and the plurality of insulating layers The layer is such that the Young's modulus of the adjacent insulating layer (34) laminated on the internal wiring layer is smaller than the Young's modulus of the other insulating layer (33), and the breaking strength of the adjacent insulating layer is that of the other insulating layer. The other insulating layer is composed mainly of one of silicon nitride and tetraethoxysilane, and the Young's modulus of the adjacent insulating layer is 80 GPa or less. .
In addition, the code | symbol in the parenthesis of a claim and the said means shows a corresponding relationship with the specific means as described in embodiment mentioned later.

In the first aspect of the invention, a plurality of insulating layers are laminated on the internal wiring layer, and at least a part of the electrode pad faces at least a part of the internal wiring layer through the plurality of insulating layers. The plurality of insulating layers are such that the Young's modulus of the adjacent insulating layer in contact with the internal wiring layer is smaller than the Young's modulus of the other insulating layer, and the breaking strength of the adjacent insulating layer is larger than the breaking strength of the other insulating layer. Configured. The other insulating layer is mainly composed of either silicon nitride or tetraethoxysilane, and the Young's modulus of the adjacent insulating layer is 80 GPa or less.

  As a result, even when the internal wiring layer located below the acting portion is plastically deformed by the pressing force acting on the electrode pad, the Young's modulus of the adjacent insulating layer in contact with the internal wiring layer is relatively small. Therefore, the stress generated in the adjacent insulating layer due to the strain due to plastic deformation of the internal wiring layer is reduced. For this reason, the stress transmitted to another insulating layer via this adjacent insulating layer can be reduced. In particular, since the adjacent insulating layer is configured such that the breaking strength of the adjacent insulating layer is higher than that of the other insulating layers, the occurrence of cracks in the adjacent insulating layer itself due to plastic deformation of the internal wiring layer can also be suppressed. Therefore, even when the internal wiring layer located below the electrode pad is plastically deformed, the occurrence of cracks in the insulating layer laminated on the internal wiring layer can be suitably suppressed.

1 is a cross-sectional view showing a semiconductor device according to a first embodiment. It is a graph which shows the stress-strain characteristic of an elastic material and an elastic-plastic material. FIG. 3A is a cross-sectional view illustrating a state in which the relaxation layer is formed on the third wiring layer, and FIG. 3B is a simulation result of stress distribution in the configuration of FIG. FIG. 4A is a cross-sectional view showing a state in which the relaxation layer is formed between the first TEOS layer and the P-SiN layer, and FIG. 4B is a simulation result of stress distribution in the configuration of FIG. It is. FIG. 5A is a cross-sectional view showing a state in which the relaxation layer is formed between the P-SiN layer and the second TEOS layer, and FIG. 5B is a simulation result of stress distribution in the configuration of FIG. It is. 6A is a cross-sectional view showing a state in which the relaxation layer is formed between the second TEOS layer and the electrode pad, and FIG. 6B is a simulation result of stress distribution in the configuration of FIG. is there. FIG. 7A is a cross-sectional view showing a state in which a relaxation layer is not formed, and FIG. 7B is a simulation result of stress distribution in the configuration of FIG. It is the graph which put together the stress simulation result of FIGS. It is a simulation result of the stress distribution when the Young's modulus of the relaxation layer shown in FIG. 3 (A) is set to 40 GPa. It is a simulation result of stress distribution when the Young's modulus of the relaxation layer shown in FIG. 3 (A) is set to 70 GPa. It is a simulation result of stress distribution when the Young's modulus of the relaxation layer shown in FIG. 3 (A) is set to 100 GPa. It is a graph which shows the relationship between the Young's modulus of a relaxation layer, and the largest principal stress in a 1st TEOS layer, a P-SiN layer, and a relaxation layer. FIG. 13A is a cross-sectional view showing a state in which the first TEOS layer is formed on the third wiring layer, and FIG. 13B shows the relaxation layer and the first TEOS layer in this order on the third wiring layer. It is sectional drawing which shows the formed state. FIG. 14A is a cross-sectional view showing a state in which the first TEOS layer, the relaxation layer, and the second TEOS layer are formed in this order on the third wiring layer, and FIG. 14B shows the state on the third wiring layer. FIG. 6 is a cross-sectional view showing a state in which a first TEOS layer and a relaxation layer are formed in this order. It is sectional drawing which shows the state formed in order of the relaxation layer and the 1st TEOS layer on the 3rd wiring layer. FIG. 16A is a cross-sectional view showing a state in which a relaxation layer and a P-SiN layer are formed in this order on the third wiring layer, and FIG. 16B shows a state in which P-SiN is formed on the third wiring layer. It is sectional drawing which shows the state formed in order of the layer, the relaxation layer, and the P-SiN layer. FIG. 17A is a cross-sectional view showing a state in which the relaxation layer, the first TEOS layer, and the P-SiN layer are formed in this order on the third wiring layer, and FIG. 17B shows the state on the third wiring layer. 2 is a cross-sectional view showing a state in which a first TEOS layer, a relaxation layer, and a P-SiN layer are formed in this order. It is a graph which shows the result of having simulated the maximum principal stress which acts on each layer when the distance between a 3rd wiring layer and a relaxation layer is changed. FIG. 4 is a graph showing a result of simulating the maximum principal stress acting on the relaxation layer, the first TEOS layer, and the P-SiN layer when the thickness of the first TEOS layer is changed in the configuration shown in FIG. It is sectional drawing which shows the principal part of the semiconductor device which concerns on the modification of this embodiment.

[First Embodiment]
Hereinafter, a first embodiment of a semiconductor device according to the present invention will be described with reference to the drawings.
The semiconductor device 10 according to the present embodiment is a device that is employed as an electronic control device for a vehicle, for example, and is configured by laminating a plurality of wiring layers and insulating layers on a semiconductor substrate 11 made of silicon. .

  In the present embodiment, as shown in FIG. 1, the semiconductor device 10 includes three wiring layers (a first wiring layer 21, a second wiring layer 22, and a third wiring layer 23) as a plurality of wiring layers arranged on the inner layer side. These wiring layers 21 to 23 are mainly composed of aluminum, copper, or the like. Each of the wiring layers 21 to 23 constitutes a predetermined wiring pattern by being electrically connected to the electrode pad 25 or the like disposed on the surface via the via 24 or the like. The electrode pad 25 is mainly composed of aluminum or copper. The third wiring layer 23, which is the uppermost layer of each wiring layer, corresponds to an example of an “internal wiring layer”, and a part of the third wiring layer 23 extends in the vertical direction via a part of the electrode pad 25 and a plurality of insulating layers. It arrange | positions so that it may oppose.

  In addition, the semiconductor device 10 has three insulating layers (a first insulating layer 31, a second insulating layer 32, and a third insulating layer 33) as a plurality of insulating layers, and a Young's modulus lower than these insulating layers 31 to 33. A relaxation layer 34 is provided as an insulating layer. In particular, the relaxation layer 34 is configured such that its breaking strength is greater than the breaking strength of the third insulating layer 33.

  The first insulating layer 31 is disposed so as to be interposed between the first wiring layer 21 and the second wiring layer 22, and the second insulating layer 32 is disposed between the second wiring layer 22 and the third wiring layer 23. It arrange | positions so that it may interpose. The third insulating layer 33 and the relaxing layer 34 are interposed between the third wiring layer 23 and the electrode pad 25, and are disposed on the third wiring layer 23 by laminating the relaxing layer 34 and the third insulating layer 33 in this order. ing. The constituent materials and thicknesses of the insulating layers 31 to 33 and the relaxing layer 34 will be described later. Further, the relaxing layer 34 may correspond to an example of “adjacent insulating layer”.

Next, a characteristic configuration of the present invention will be described with reference to the drawings.
FIG. 2 shows the relationship (stress-strain diagram) between externally applied stress and strain for elastic materials such as silicon and silicon oxide and elastoplastic materials such as aluminum and copper. In FIG. 2, the slope of the graph corresponds to the Young's modulus. As shown in FIG. 2, in the elastic material, the strain increases in proportion to the stress acting from the outside. On the other hand, in the elastic-plastic material, the strain increases in proportion to the externally acting stress in the elastic property region, but the Young's modulus (slope) decreases in the plastic property region that has undergone plastic deformation. The strain (deformation degree) increases with respect to the stress acting from the outside.

  Since the third wiring layer 23 is made of an elastic-plastic material mainly composed of aluminum or copper, when the probe is pressed against the electrode pad 25 (indicated by reference numeral N in FIG. 1 or the like) When the third wiring layer 23 positioned below is plastically deformed by the pressing force and the strain increases, the strain on the insulating layer and the like on the third wiring layer 23 also increases. When the strain becomes large in this way, a crack may occur in the insulating layer or the like on the third wiring layer 23. In particular, since the inspection using the probe is usually performed a plurality of times, if the probe is pressed many times against the same part of the electrode pad 25 and the thickness of the part of the electrode pad 25 becomes thin, the third wiring layer 23 As a result, the pressing force acting on the second wiring layer 23 increases, and the possibility of cracks occurring in the insulating layer on the third wiring layer 23 increases.

  Therefore, in the present embodiment, in order to suppress the influence of the distortion of the plastically deformed third wiring layer 23 on the insulating layer on the third wiring layer 23, among the plurality of insulating layers stacked on the third wiring layer 23 The lowermost relaxation layer 34 is configured to have a lower Young's modulus and higher fracture strength than the other insulating layers (the third insulating layer 33 in the example of FIG. 1) laminated on the relaxation layer 34. did.

  Hereinafter, the reason why the relaxation layer 34 is formed on the third wiring layer 23 will be described in detail with reference to FIGS. 3 to 6, two layers (hereinafter, referred to as a first TEOS layer 35 and a second TEOS layer 36) composed mainly of tetraethoxysilane, and silicon nitride mainly located between both TEOS layers 35 and 37. A case where a layer configured as follows (hereinafter referred to as a P-SiN layer 37) and a relaxation layer 34 are laminated with a predetermined thickness between the third wiring layer 23 and the electrode pad 25 will be described. And about the result of having simulated the stress distribution when the said pressing force acts on the electrode pad 25 using the position of the relaxation layer 34 with respect to both the TEOS layers 35 and 36 and the P-SiN layer 37 as a parameter, FIGS. It explains using.

  3A is a cross-sectional view showing a state in which the relaxation layer 34 is formed on the third wiring layer 23, and FIG. 3B is a simulation of stress distribution in the configuration of FIG. 3A. It is a result. 4A is a cross-sectional view showing a state in which the relaxation layer 34 is formed between the first TEOS layer 35 and the P-SiN layer 37, and FIG. 4B is a stress in the configuration of FIG. 4A. It is a simulation result of distribution. 5A is a cross-sectional view showing a state in which the relaxation layer 34 is formed between the P-SiN layer 37 and the second TEOS layer 36, and FIG. 5B is a stress in the configuration of FIG. 5A. It is a simulation result of distribution. FIG. 6A is a cross-sectional view showing a state in which the relaxation layer 34 is formed between the second TEOS layer 36 and the electrode pad 25, and FIG. 6B shows the stress distribution in the configuration of FIG. It is a simulation result. FIG. 7A is a cross-sectional view showing a state in which the relaxation layer 34 is not formed, and FIG. 7B is a simulation result of stress distribution in the configuration of FIG. The configuration on the lower layer side than the third wiring layer 23 is common in FIGS. 3 to 7 and the simulation described later, and the first wiring layer 21, the first insulating layer 31, and the like are formed on the semiconductor substrate 11 made of silicon. The second wiring layer 22, the second insulating layer 32, and the third wiring layer 23 are stacked in this order with a predetermined thickness.

  8 is a graph summarizing the stress simulation results of FIGS. 3 to 7. The result shown in FIG. 3 corresponds to FIG. 8 (e), and the result shown in FIG. 4 corresponds to FIG. 8 (d). 5 corresponds to FIG. 8C, the result shown in FIG. 6 corresponds to FIG. 8B, and the result shown in FIG. 7 corresponds to FIG. 8A. Further, the fracture limit stress of the TEOS layer and the P-SiN layer shown in FIG. 8 is based on the amount of warpage when the result of a known three-point bending test is modeled by simulation and fractured (cracked) with a single film. It is an estimated value. In FIG. 8, the maximum principal stress acting on the first TEOS layer 35 is shown as Sa1, the maximum principal stress acting on the P-SiN layer 37 is Sa2, and the maximum principal stress acting on the relaxation layer 34 is shown as Sa3.

  As can be seen from FIGS. 3B to 7B, a large stress is applied to the layer on the third wiring layer 23. In the configuration in which the relaxation layer 34 is provided (FIGS. 3 to 6), the maximum principal stress Sa1 acting on the first TEOS layer 35 and P-SiN are compared with the configuration in which the relaxation layer 34 is not provided (FIG. 7). The maximum principal stress Sa2 acting on the layer 37 is small. As can be seen from FIG. 8, the maximum principal stress Sa1 acting on the first TEOS layer 35 is 24% in the configuration of FIG. 3, 10% in the configuration of FIG. 4, and the configuration of FIG. 16% and 15% in the configuration of FIG. That is, the stress acting on the first TEOS layer 35, the P-SiN layer 37, and the like can be reduced by providing the relaxation layer 34.

  In particular, in the configuration in which the relaxation layer 34 is provided, the maximum principal stress of the first TEOS layer 35 is the smallest when the relaxation layer 34 is disposed on the third wiring layer 23 as shown in FIG. (See FIG. 8 (e)). In the configuration in which the relaxation layer 34 is provided, the relaxation layer 34 is disposed on the third wiring layer 23 as shown in FIG. 3A, or the first TEOS layer 35 as shown in FIG. 4A. When the relaxation layer 34 is disposed between the P-SiN layers 37, the maximum principal stress of the P-SiN layer 37 is the smallest (see FIGS. 8D and 8E).

  That is, by disposing the relaxing layer 34 on the third wiring layer 23, the stress acting on the insulating layers 35 to 37 stacked on the relaxing layer 34 is more preferably reduced. Generation of cracks can be effectively suppressed.

  In the configuration in which the relaxation layer 34 is provided, the maximum principal stress of the first TEOS layer 35 is less than the fracture limit stress of the first TEOS layer 35, and the maximum principal stress of the P-SiN layer 37 is all the P-SiN layer 37. From the fact that it is less than the fracture limit stress, it can be seen that the occurrence of cracks in each of the insulating layers 35 to 37 is effectively suppressed.

  Next, when the relaxation layer 34 is formed at the position shown in FIG. 3A, the stress distribution when the pressing force acts on the electrode pad 25 was simulated using the Young's modulus of the relaxation layer 34 as a parameter. A result is demonstrated using FIGS. 9-12. FIG. 9 is a simulation result of the stress distribution when the Young's modulus of the relaxation layer 34 shown in FIG. 3A is set to 40 GPa. FIG. 10 is a simulation result of the stress distribution when the Young's modulus of the relaxation layer 34 shown in FIG. 3A is set to 70 GPa. FIG. 11 shows a simulation result of the stress distribution when the Young's modulus of the relaxation layer 34 shown in FIG. 3A is set to 100 GPa. FIG. 12 is a graph showing the relationship between the Young's modulus of the relaxation layer 34 and the maximum principal stress in the first TEOS layer 35, the P-SiN layer 37, and the relaxation layer 34, and is obtained from the simulation results of FIGS. It summarizes the maximum principal stress. In FIG. 12, the maximum principal stress acting on the first TEOS layer 35 is illustrated as Sb1, the maximum principal stress acting on the P-SiN layer 37 is represented as Sb2, and the maximum principal stress acting on the relaxation layer 34 is illustrated as Sb3. The simulation result of the stress distribution when the Young's modulus of the relaxation layer 34 is set to 150 GPa is also included.

  As can be seen from FIG. 12, the maximum principal stress Sb1 of the first TEOS layer 35 is less than the fracture limit stress even when the Young's modulus of the relaxation layer 34 is changed, and decreases as the Young's modulus of the relaxation layer 34 increases. Further, the maximum principal stress Sb2 of the P—SiN layer 37 is less than the fracture limit stress even when the Young's modulus of the relaxation layer 34 is changed, and decreases as the Young's modulus of the relaxation layer 34 increases. In particular, in the region where the Young's modulus of the relaxation layer 34 is about 80 GPa or less, the maximum principal stress Sb3 of the relaxation layer 34 is less than the fracture limit stress of the first TEOS layer 35. Therefore, it is preferable to set the Young's modulus of the relaxing layer 34 to about 80 GPa or less.

  Next, simulation results regarding the maximum principal stress acting on each layer when the distance between the third wiring layer 23 and the relaxation layer 34 is changed will be described with reference to FIGS. In the following description, a simulation result in which the thickness of the relaxation layer 34 is set to 0.5 μm will be described. FIG. 13A is a cross-sectional view showing a state in which the first TEOS layer 35 (thickness 1 μm) is formed on the third wiring layer 23, and FIG. 13B shows the state on the third wiring layer 23. 2 is a cross-sectional view showing a state in which a relaxation layer 34 and a first TEOS layer 35 (thickness 1 μm) are formed in this order. FIG. 14A shows a state in which the first TEOS layer 35 (thickness 0.5 μm), the relaxation layer 34, and the second TEOS layer 36 (thickness 0.5 μm) are formed in this order on the third wiring layer 23. FIG. 14B is a cross-sectional view showing a state in which the first TEOS layer 35 (thickness 1 μm) and the relaxation layer 34 are formed in this order on the third wiring layer 23. FIG. 15 is a cross-sectional view showing a state in which the relaxing layer 34 and the first TEOS layer 35 (thickness 2 μm) are formed in this order on the third wiring layer 23. FIG. 16A is a cross-sectional view showing a state in which the relaxation layer 34 and the P-SiN layer 37 (thickness 1 μm) are formed in this order on the third wiring layer 23, and FIG. 3 is a cross-sectional view showing a state in which a P-SiN layer 37a (thickness 0.5 μm), a relaxation layer 34, and a P-SiN layer 37b (thickness 0.5 μm) are formed in this order on the three wiring layers 23. FIG. 17A shows a state in which the relaxing layer 34, the first TEOS layer 35 (thickness 0.5 μm), and the P-SiN layer 37 (thickness 0.5 μm) are formed on the third wiring layer 23 in this order. FIG. 17B shows a first TEOS layer 35 (thickness 0.5 μm), a relaxation layer 34, and a P-SiN layer 37 (thickness 0.5 μm) in this order on the third wiring layer 23. It is sectional drawing which shows the state formed by.

  FIG. 18 is a graph showing the result of simulating the maximum principal stress at the position where a crack occurs when the distance between the third wiring layer 23 and the relaxation layer 34 is changed, and FIG. P0, the result of FIG. 13B is P1, the result of FIG. 14A is P2, the result of FIG. 14B is P3, the result of FIG. 15 is P4, and the result of FIG. P5, the result of FIG. 16B is indicated by P6, the result of FIG. 17A is indicated by P7, and the result of FIG. 17B is indicated by P8.

  As shown in FIG. 18, the maximum principal stress at the position where the crack is generated increases as the relaxation layer 34 moves away from the third wiring layer 23, while the crack increases as the distance between the third wiring layer 23 and the relaxation layer 34 decreases. It can be seen that the maximum principal stress at the position where the occurrence occurs is small. For this reason, the distance between the third wiring layer 23 and the relaxation layer 34 is 0 (zero), that is, the configuration in which the relaxation layer 34 is formed immediately above the third wiring layer 23 (P1, P4, P5, P7 in FIG. 18). In the reference), the maximum principal stress at the position where the crack is generated becomes the smallest regardless of the type and thickness of the insulating film disposed on the relaxing layer 34.

  Next, in the configuration shown in FIG. 3A, the relationship between the thickness of the first TEOS layer 35 and the maximum principal stress acting on the relaxation layer 34, the first TEOS layer 35, and the P-SiN layer 37 will be described with reference to FIG. I will explain. FIG. 19 shows a simulation of the maximum principal stress acting on the relaxation layer 34, the first TEOS layer 35, and the P-SiN layer 37 when the thickness of the first TEOS layer 35 is changed in the configuration shown in FIG. It is a graph which shows a result. In FIG. 19, the maximum principal stress acting on the first TEOS layer 35 is illustrated as Sc1, the maximum principal stress acting on the P-SiN layer 37 is represented as Sc2, and the maximum principal stress acting on the relaxation layer 34 is illustrated as Sc3.

  As can be seen from FIG. 19, even when the thickness of the first TEOS layer 35 is changed, the maximum principal stress Sc3 acting on the relaxation layer 34 and the maximum principal stress Sc1 acting on the first TEOS layer 35 are not significantly changed. When the thickness of the first TEOS layer 35 is about 0.2 μm or more, the maximum principal stress Sc2 acting on the P-SiN layer 37 is less than the fracture limit stress of the P-SiN layer 37. That is, in the configuration in which the first TEOS layer 35 is disposed on the relaxing layer 34, even if the thickness of the first TEOS layer 35 changes in the range of about 0.2 um to 1 um, cracks are generated in each of the insulating layers 35 to 37. It can be effectively suppressed.

  Therefore, in the semiconductor device 10 according to the present embodiment, the relaxation layer 34 formed on the third wiring layer 23 is replaced with another insulation layered on the relaxation layer 34 based on the above-described simulation results and the like. A material having a lower Young's modulus (for example, 80 GPa) and higher fracture strength than the layer (the third insulating layer 33 in the example of FIG. 1), for example, a material mainly composed of spin-on-glass (SOG). In particular, as can be seen from FIG. 8, as the third insulating layer 33 composed of two or more insulating layers, the configuration shown in FIG. 3A, that is, the first TEOS layer 35, the P-SiN layer 37, the second TEOS By adopting an insulating structure in which the layers 36 are stacked in this order, the stress acting on the first TEOS layer 35, the P-SiN layer 37, and the like can be more suitably reduced.

  As described above, in the semiconductor device 10 according to the present embodiment, a plurality of insulating layers (33, 34) are stacked on the third wiring layer 23, and at least a part of the electrode pad 25 is a plurality of insulating layers. Is opposed to at least a part of the third wiring layer 23. In the plurality of insulating layers, the Young's modulus of the relaxing layer 34 (adjacent insulating layer) in contact with the third wiring layer 23 is smaller than the Young's modulus of the other insulating layer (33), and the breaking strength of the relaxing layer 34 is other than that. It is comprised so that it may become larger than the destructive strength of an insulating layer (33).

  As a result, even if the third wiring layer 23 located below the acting portion is plastically deformed by the pressing force acting on the electrode pad 25, the Young of the relaxation layer 34 in contact with the third wiring layer 23 is used. Since the rate is relatively small, the stress generated in the relaxation layer 34 due to strain due to plastic deformation of the third wiring layer 23 is reduced. For this reason, the stress transmitted to the other insulating layer through the relaxing layer 34 can be reduced. In particular, since the relaxation strength of the relaxation layer 34 is configured to be greater than the breakdown strength of the other insulating layers, it is possible to suppress the occurrence of cracks in the relaxation layer 34 due to plastic deformation of the third wiring layer 23. it can. Therefore, even when the third wiring layer 23 located below the electrode pad 25 is plastically deformed, the occurrence of cracks in the insulating layer laminated on the third wiring layer 23 can be suitably suppressed.

  In particular, a plurality of insulating layers are disposed between the relaxing layer 34 and the electrode pad 25, and the first TEOS layer 35, the P-SiN layer 37, the second TEOS layer 36, and the electrode pad 25 are stacked on the relaxing layer 34 in this order. Thereby, the stress which acts on the 1st TEOS layer 35, the P-SiN layer 37, etc. is reduced more suitably, and it can control suitably crack generation in each insulating layers 34-37.

In addition, this invention is not limited to the said embodiment, For example, you may actualize as follows.
(1) The relaxation layer 34 is not limited to a material mainly composed of spin-on-glass (SOG), and is laminated on the relaxation layer 34 such as a material mainly composed of a borazine compound or porous silica. The material may have a lower Young's modulus and higher fracture strength than other insulating layers. Further, as another insulating layer formed on the relaxing layer 34, for example, an insulating layer mainly composed of at least one of silicon nitride and tetraethoxysilane, or an insulating layer in which two or more of these layers are stacked is adopted. be able to. Even if it is such a structure, there can exist an effect similar to the said embodiment.

(2) FIG. 20 is a cross-sectional view showing the main part of the semiconductor device 10 according to a modification of the present embodiment.
The third wiring layer 23 and the electrode pad 25 are not limited to being electrically connected via the via 24, but are electrically connected via a plurality of vias 24a as illustrated in FIG. 20, for example. May be. Even if it is such a structure, there can exist an effect similar to the said embodiment.

(3) The semiconductor device according to the present invention is not limited to being employed in an electronic control device for a vehicle, and is a semiconductor device having other functions as long as it is a semiconductor device having a multilayer substrate on which electrode pads are arranged. Even an apparatus can be employed.

10: Semiconductor device 23 ... Third wiring layer (internal wiring layer)
25 ... Electrode pad 33 ... Insulating layer (other insulating layers)
34 ... Relaxation layer (adjacent insulating layer)
35 ... 1st TEOS layer (other insulating layers)
36 ... 2nd TEOS layer (other insulating layers)
37 ... P-SiN layer (other insulating layers)

Claims (4)

An internal wiring layer (23);
A plurality of insulating layers (33, 34) stacked on the internal wiring layer;
An electrode pad (25) disposed above the plurality of insulating layers, at least a portion of which is opposed to at least a portion of the internal wiring layer via the plurality of insulating layers;
With
In the plurality of insulating layers, the Young's modulus of the adjacent insulating layer (34) laminated on the internal wiring layer is smaller than the Young's modulus of the other insulating layer (33), and the breaking strength of the adjacent insulating layer is the other. It is configured to be larger than the fracture strength of the insulating layer,
The other insulating layer is mainly composed of either silicon nitride or tetraethoxysilane,
A semiconductor device, wherein the adjacent insulating layer has a Young's modulus of 80 GPa or less . It said adjacent insulating layer, a semiconductor device according to claim 1, characterized in that it is constituted spin-on glass, one of the borazine compound and porous silica mainly.   The other insulating layers (35 to 37) are composed of two or more insulating layers, and a layer mainly composed of silicon nitride is laminated on a layer mainly composed of tetraethoxysilane laminated on the adjacent insulating layer. The semiconductor device according to claim 1, wherein the semiconductor device is configured as follows.   The semiconductor device according to claim 1, wherein the internal wiring layer is mainly composed of aluminum or copper.

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