JP6022604B2 - マルチバンクキャッシュメモリ - Google Patents

マルチバンクキャッシュメモリ Download PDF

Info

Publication number
JP6022604B2
JP6022604B2 JP2014555583A JP2014555583A JP6022604B2 JP 6022604 B2 JP6022604 B2 JP 6022604B2 JP 2014555583 A JP2014555583 A JP 2014555583A JP 2014555583 A JP2014555583 A JP 2014555583A JP 6022604 B2 JP6022604 B2 JP 6022604B2
Authority
JP
Japan
Prior art keywords
cache memory
data
client
request
buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2014555583A
Other languages
English (en)
Japanese (ja)
Other versions
JP2015505631A (ja
JP2015505631A5 (OSRAM
Inventor
リアン、ジアン
ユ、チュン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of JP2015505631A publication Critical patent/JP2015505631A/ja
Publication of JP2015505631A5 publication Critical patent/JP2015505631A5/ja
Application granted granted Critical
Publication of JP6022604B2 publication Critical patent/JP6022604B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G06F12/0851—Cache with interleaved addressing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP2014555583A 2012-02-02 2013-01-23 マルチバンクキャッシュメモリ Expired - Fee Related JP6022604B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/364,901 2012-02-02
US13/364,901 US9274964B2 (en) 2012-02-02 2012-02-02 Multi-bank cache memory
PCT/US2013/022759 WO2013116060A1 (en) 2012-02-02 2013-01-23 Multi-bank cache memory

Publications (3)

Publication Number Publication Date
JP2015505631A JP2015505631A (ja) 2015-02-23
JP2015505631A5 JP2015505631A5 (OSRAM) 2016-06-16
JP6022604B2 true JP6022604B2 (ja) 2016-11-09

Family

ID=47790485

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2014555583A Expired - Fee Related JP6022604B2 (ja) 2012-02-02 2013-01-23 マルチバンクキャッシュメモリ

Country Status (6)

Country Link
US (1) US9274964B2 (OSRAM)
EP (1) EP2810172A1 (OSRAM)
JP (1) JP6022604B2 (OSRAM)
KR (1) KR101687883B1 (OSRAM)
CN (1) CN104094242B (OSRAM)
WO (1) WO2013116060A1 (OSRAM)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10394566B2 (en) * 2017-06-06 2019-08-27 International Business Machines Corporation Banked cache temporarily favoring selection of store requests from one of multiple store queues
KR20190037668A (ko) * 2017-09-29 2019-04-08 에스케이하이닉스 주식회사 메모리 시스템 및 그것의 동작 방법
US11853216B2 (en) * 2021-08-16 2023-12-26 Micron Technology, Inc. High bandwidth gather cache

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3967247A (en) 1974-11-11 1976-06-29 Sperry Rand Corporation Storage interface unit
JPH05210640A (ja) 1992-01-31 1993-08-20 Hitachi Ltd マルチプロセッサシステム
US6745293B2 (en) 2000-08-21 2004-06-01 Texas Instruments Incorporated Level 2 smartcache architecture supporting simultaneous multiprocessor accesses
US20030163643A1 (en) * 2002-02-22 2003-08-28 Riedlinger Reid James Bank conflict determination
JP2004046643A (ja) * 2002-07-12 2004-02-12 Sony Corp キャッシュ装置および記憶手段選択方法
US7203775B2 (en) * 2003-01-07 2007-04-10 Hewlett-Packard Development Company, L.P. System and method for avoiding deadlock
US7219185B2 (en) 2004-04-22 2007-05-15 International Business Machines Corporation Apparatus and method for selecting instructions for execution based on bank prediction of a multi-bank cache
US7571284B1 (en) * 2004-06-30 2009-08-04 Sun Microsystems, Inc. Out-of-order memory transactions in a fine-grain multithreaded/multi-core processor
US8560795B2 (en) * 2005-06-30 2013-10-15 Imec Memory arrangement for multi-processor systems including a memory queue
EP1896983B1 (en) * 2005-06-30 2011-08-10 Imec A memory arrangement for multi-processor systems
US20080282034A1 (en) * 2005-09-19 2008-11-13 Via Technologies, Inc. Memory Subsystem having a Multipurpose Cache for a Stream Graphics Multiprocessor
US7600080B1 (en) 2006-09-22 2009-10-06 Intel Corporation Avoiding deadlocks in a multiprocessor system
JP5376371B2 (ja) 2006-10-26 2013-12-25 リード・コーク・エス 並列コンピューティング・システムに使用されるネットワーク・インターフェース・カード
US8521982B2 (en) * 2009-04-15 2013-08-27 International Business Machines Corporation Load request scheduling in a cache hierarchy
US8661200B2 (en) * 2010-02-05 2014-02-25 Nokia Corporation Channel controller for multi-channel cache

Also Published As

Publication number Publication date
US20130205091A1 (en) 2013-08-08
EP2810172A1 (en) 2014-12-10
JP2015505631A (ja) 2015-02-23
CN104094242B (zh) 2017-03-01
US9274964B2 (en) 2016-03-01
KR101687883B1 (ko) 2016-12-28
WO2013116060A1 (en) 2013-08-08
CN104094242A (zh) 2014-10-08
KR20140116966A (ko) 2014-10-06

Similar Documents

Publication Publication Date Title
US11693791B2 (en) Victim cache that supports draining write-miss entries
US8521982B2 (en) Load request scheduling in a cache hierarchy
US7047322B1 (en) System and method for performing conflict resolution and flow control in a multiprocessor system
CN105900076B (zh) 用于处理多个交易的数据处理系统及方法
US8200939B2 (en) Memory management unit in a microprocessor system
US8352682B2 (en) Methods and apparatus for issuing memory barrier commands in a weakly ordered storage system
US20060112238A1 (en) Techniques for pushing data to a processor cache
KR20040045035A (ko) 힌트 버퍼를 이용한 메모리 액세스 대기시간 숨김
TW200915178A (en) Memory device and method having on-board address protection system for facilitating interface with multiple processors, and computer system using same
US9075726B2 (en) Conflict resolution of cache store and fetch requests
US20110246688A1 (en) Memory arbitration to ensure low latency for high priority memory requests
CN104471555A (zh) 用于高速缓存系统的多级互联系统及多级互联方法
JP2020030822A (ja) インメモリコンピューティングのための大容量メモリシステム
US7644221B1 (en) System interface unit
JP6022604B2 (ja) マルチバンクキャッシュメモリ
US20080307169A1 (en) Method, Apparatus, System and Program Product Supporting Improved Access Latency for a Sectored Directory
US20090144500A1 (en) Store performance in strongly ordered microprocessor architecture
US20080301376A1 (en) Method, Apparatus, and System Supporting Improved DMA Writes
US7529876B2 (en) Tag allocation method
US8205064B2 (en) Latency hiding for a memory management unit page table lookup
US12066940B2 (en) Data reuse cache
US20070180157A1 (en) Method for cache hit under miss collision handling
US20120054439A1 (en) Method and apparatus for allocating cache bandwidth to multiple processors
CN107408059B (zh) 共享多级库的跨级预取
CN118159952A (zh) 将引退页历史用于基于处理器的设备中的指令转换后备缓存器（tlb）预取

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20141016

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20151225

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20151225

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20160420

A871 Explanation of circumstances concerning accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A871

Effective date: 20160420

A975 Report on accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A971005

Effective date: 20160509

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20160517

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20160816

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20160906

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20161005

R150 Certificate of patent or registration of utility model

Ref document number: 6022604

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

LAPS Cancellation because of no payment of annual fees