JP6020931B2 - Power converter - Google Patents

Description

  The present invention relates to a power conversion device including a reactor, a main switch, and a synchronous rectification switch.

  Conventionally, as a power converter provided with a reactor and a switch, for example, there is a boost converter control system disclosed in Patent Document 1 shown below.

  This boost converter control system includes a reactor, a switch, a diode, and a control circuit. The control circuit controls the switch based on the servo command. At that time, the switch is turned off based on the change in the voltage gradient of the voltage between the terminals of the switch. When controlling the boost converter control system in the current critical mode, it is necessary to turn off the switch when the release of the energy stored in the reactor is completed. For this reason, conventionally, the reactor current is detected, and the completion of the release of the energy accumulated in the reactor is determined. However, it is possible to detect the completion of the release of the energy stored in the reactor by the change in the voltage gradient of the voltage between the terminals of the switch. Therefore, the boost converter control system can be controlled in the current critical mode without detecting the reactor current.

JP 2013-070586 A

  In the boost converter control system described above, the diode may be replaced with a synchronous rectifier switch in order to reduce the loss in the diode. When the diode is replaced with a synchronous rectification switch, even if the release of the energy stored in the reactor is completed, the voltage between the terminals of the switch does not change because the synchronous rectification switch is on. Therefore, it is not possible to detect the completion of the release of energy accumulated in the reactor. Therefore, the boost converter control system cannot be controlled in the current critical mode without detecting the reactor current.

  The present invention has been made in view of such circumstances, and in a power conversion device including a reactor, a main switch, and a synchronous rectification switch, control is performed in a current critical mode without detecting a reactor current. An object of the present invention is to provide a power conversion device capable of performing the above.

In order to solve the above-described problems, the present invention provides a reactor, a main switch that connects the power source to the reactor when turned on, supplies current to the reactor from the power source, and stores energy in the reactor, and the main switch is off The reactor is connected to the load by turning it on during the period, the energy stored in the reactor is released, the current is supplied from the reactor to the load, and connected to the main switch and the synchronous rectification switch. In a power converter comprising a control circuit that controls a main switch and a synchronous rectification switch, the control circuit detects a switching transition time indicating a transition state of a voltage between terminals of the main switch, and the detected switching transition time is React when the release of energy stored in the reactor is complete And controlling the main switch and the synchronous rectification switch to become the switching transition time target value is a switching transition time corresponding to the current.

  There is a predetermined relationship between the switching transition time and the reactor current, and the reactor current can be grasped by the switching transition time. According to this configuration, the main switch and the synchronous rectification switch are controlled based on the switching transition time. Therefore, it is possible to appropriately control the reactor current without detecting the reactor current. Therefore, the power converter can be controlled in the current critical mode without detecting the reactor current.

It is a circuit diagram of the power converter in a 1st embodiment. It is a circuit diagram of the switching transition time detection circuit shown in FIG. It is a block diagram of the controller shown in FIG. It is a wave form diagram of each part for demonstrating operation | movement of the power converter device shown in FIG. It is another waveform diagram of each part for demonstrating operation | movement of the power converter device shown in FIG. It is a graph which shows the relationship between a reactor current and switching transition time. It is a wave form diagram of each part for demonstrating operation | movement of a switching transition time detection circuit. It is a circuit diagram of the power converter device in 2nd Embodiment. FIG. 9 is a circuit diagram of the switching transition time detection circuit shown in FIG. 8. It is a block diagram of the controller shown in FIG. It is a circuit diagram of the power converter device in 3rd Embodiment. FIG. 12 is a circuit diagram of the switching transition time detection circuit shown in FIG. 11. It is a circuit diagram of the power converter device in 4th Embodiment. It is a block diagram of the controller shown in FIG. It is a circuit diagram of the power converter device in 5th Embodiment. It is a circuit diagram of the power converter device in 6th Embodiment. It is a block diagram of the controller shown in FIG. It is a circuit diagram of the power converter device in 7th Embodiment. It is a block diagram of the controller shown in FIG.

  Next, the present invention will be described in more detail with reference to embodiments.

(First embodiment)
First, the configuration of the power conversion device according to the first embodiment will be described with reference to FIGS.

  A power conversion device 1 shown in FIG. 1 converts a direct current supplied from a high voltage battery B10 (power supply) mounted on a vehicle into a low voltage direct current, and converts it into a low voltage battery B11 (load) mounted on the vehicle. It is a device that supplies and charges the low-voltage battery B11. This is a so-called step-down buck-boost converter. Here, the high voltage battery B10 is, for example, a battery having a rated voltage of 48V. The low voltage battery B11 is, for example, a battery having a rated voltage of 12V. The power converter 1 includes a smoothing capacitor 10, an FET 11 (main switch), an FET 12 (synchronous rectification switch), snubber circuits 13 and 14, a reactor 15, a smoothing capacitor 16, and a control circuit 17. ing.

  The smoothing capacitor 10 is an element that smoothes the input voltage Vin of the power conversion device 1. Smoothing capacitor 10 smoothes the voltage of high-voltage battery B10. One end of the smoothing capacitor 10 is connected to the positive terminal of the high voltage battery B10, and the other end is connected to the negative terminal of the high voltage battery B10.

  The FET 11 is an element that, when turned on, connects the high voltage battery B 10 to the reactor 15, supplies current from the high voltage battery B 10 to the reactor 15, and accumulates energy in the reactor 15. The FET 11 has a diode connected in parallel between the source and the drain.

  The FET 12 is turned on while the FET 11 is turned off to connect the reactor 15 to the low voltage battery B11, release the energy accumulated in the reactor 15, and supply current from the reactor 15 to the low voltage battery B11. It is an element to do. The FET 12 has a diode connected in parallel between the source and the drain.

  The FETs 11 and 12 are connected in series. Specifically, the source of the FET 11 is connected to the drain of the FET 12. The drain of the FET 11 is connected to one end of the smoothing capacitor 10, and the source of the FET 12 is connected to the other end of the smoothing capacitor 10 and the negative end of the low voltage battery B11. A series connection point of the FETs 11 and 12 is connected to the reactor 15. The gates of the FETs 11 and 12 are connected to the control circuit 17, respectively.

  The snubber circuits 13 and 14 are circuits that suppress the surge voltage applied to the FETs 11 and 12. The snubber circuits 13 and 14 have snubber capacitors 130 and 140, respectively. One end of the snubber capacitors 130 and 140 is connected to the drains of the FETs 11 and 12, and the other end is connected to the sources of the FETs 11 and 12.

  The reactor 15 is an element that stores or releases energy. One end of the reactor 15 is connected to the series connection point of the FETs 11 and 12, and the other end is connected to the positive terminal of the low voltage battery B11.

  The smoothing capacitor 16 is an element that smoothes the output voltage Vout of the power conversion device 1. One end of the smoothing capacitor 16 is connected to the other end of the reactor 15, and the other end is connected to the source of the FET 12.

  The control circuit 17 is a circuit that controls the FETs 11 and 12. The control circuit 17 controls the FETs 11 and 12 based on the output voltage target value Vout * of the power converter 1 input from the outside, the detected input / output voltages Vin and Vout of the power converter 1 and the switching transition time. Here, the switching transition time indicates a transition state of the source-drain voltage (terminal voltage) of the FET 11. Specifically, this is the time from when the FET 12 is instructed to turn off until the source-drain voltage of the FET 11 reaches the threshold voltage Vth. The threshold voltage Vth is set to, for example, a voltage that is 10% of the input voltage Vin of the power conversion device 1. The control circuit 17 includes a switching transition time detection circuit 170, a controller 171, and drive circuits 172 and 173.

  The switching transition time detection circuit 170 is set to a high level until the source-drain voltage of the FET 11 reaches the threshold voltage Vth after a drive signal output from the controller 171 instructs the FET 12 to be described later to turn off the FET 12. Is a circuit that outputs a pulse signal. As shown in FIG. 2, the switching transition time detection circuit 170 includes resistors 170a to 170d, a comparator 170e, and an XOR circuit 170f.

  The resistors 170a and 170b are connected in series. One end of the resistor 170a is connected to the drain of the FET 11, and one end of the resistor 170b is connected to the source of the FET 12.

  The resistors 170c and 170d are connected in series. One end of the resistor 170c is connected to the series connection point of the FETs 11 and 12, and one end of the resistor 170d is connected to the source of the FET 12.

  The non-inverting input terminal of the comparator 170e is connected to the series connection point of the resistors 170a and 170b, and the inverting input terminal is connected to the series connection point of the resistors 170c and 170d.

  Here, the resistance values of the resistors 170a to 170d are set such that the output of the comparator 170e is at a high level until the source-drain voltage of the FET 11 reaches the threshold voltage Vth.

  One input terminal of the XOR circuit 170f is connected to the output terminal of the comparator 170e, and the other input terminal is connected to the controller 171. The output end is connected to the controller 171.

  The controller 171 is a circuit that generates and outputs drive signals for the FETs 11 and 12 based on the output voltage target value Vout *, the input / output voltages Vin and Vout, and the switching transition time. The controller 171 includes a microcomputer and a program. As shown in FIG. 3, the controller 171 includes an on-time ratio calculation unit 171a, a switching transition time measurement unit 171b, a deviation calculation unit 171c, a switching transition time control unit 171d, correction calculation units 171e and 171f, A deviation calculator 171g, a voltage controller 171h, on-time calculators 171i and 171j, and a drive signal generator 171k are provided.

  The on-time ratio calculation unit 171a is a block that calculates and outputs an on-time ratio for the FETs 11 and 12 based on the input voltage Vin, the output voltage target value Vout *, and the output voltage Vout of the power converter 1. Here, the on-time ratio is a ratio of on-time when the FET is turned on / off. This is a so-called on-duty ratio.

  The switching transition time measurement unit 171b is a block that measures the pulse width of the pulse signal output from the switching transition time detection circuit 170 to determine and output the switching transition time.

  The deviation calculation unit 171c is a block that calculates and outputs a deviation between a preset switching transition time target value and the switching transition time output from the switching transition time measurement unit 171b. Here, the switching transition time target value is set based on the resonance period of the resonance circuit constituted by the inductance of the reactor 15, the capacitances of the snubber capacitors 130 and 140, and the parasitic capacitance of the circuit. For example, in consideration of the variation of 1/4 of the resonance period or the delay time of the switching transition time detection circuit 170 and the delay time of the drive circuits 172 and 173, it is set to about 80% of 1/4 of the resonance period. Yes.

  The switching transition time control unit 171d performs a proportional and integral calculation on the deviation between the switching transition time target value output from the deviation calculating unit 171c and the switching transition time, and outputs it as an on-time ratio correction value for correcting the on-time ratio. It is.

  The correction calculation unit 171e adds the on-time ratio correction value output from the switching transition time control unit 171d to the on-time ratio output from the on-time ratio calculation unit 171a to the FET 11, and outputs the corrected on-time ratio for the FET 11. It is.

  The correction calculation unit 171f subtracts the on-time ratio correction value output from the switching transition time control unit 171d from the on-time ratio output from the on-time ratio calculation unit 171a to the FET 12, and outputs it as a corrected on-time ratio for the FET 12. It is a block.

  The deviation calculating unit 171g is a block that calculates and outputs a deviation between the output voltage target value Vout * of the power conversion device 1 input from the outside and the output voltage Vout.

  The voltage control unit 171h is a block that proportionally integrates the deviation between the output voltage target value Vout * output from the deviation calculating unit 171g and the output voltage Vout, and outputs the result as a conversion coefficient.

  The on-time calculating unit 171i is a block that multiplies the corrected on-time ratio for the FET 11 output from the correction calculating unit 171e by the conversion coefficient output from the voltage control unit 171h, and outputs the result as the on-time for the FET 11.

  The on-time calculation unit 171j is a block that multiplies the corrected on-time ratio for the FET 12 output from the correction calculation unit 171f by the conversion coefficient output from the voltage control unit 171h, and outputs the result as the on-time for the FET 12.

  The drive signal generation unit 171k is a block that generates and outputs a drive signal for driving the FETs 11 and 12 based on the ON times for the FETs 11 and 12 output from the ON time calculation units 171i and 171j.

  The drive circuits 172 and 173 shown in FIG. 1 are circuits that turn on and off the FETs 11 and 12 based on the drive signal output from the drive signal generation unit 171k of the controller 171, respectively. The input terminals of the drive circuits 172 and 173 are connected to the drive signal generator 171k as shown in FIG. 3, and the output terminals are connected to the gates of the FETs 11 and 12 as shown in FIG.

  Next, the operation of the power conversion device according to the first embodiment will be described with reference to FIGS.

  First, with reference to FIG. 1 and FIGS. 4-6, the outline | summary of operation | movement of a power converter device and the relationship between a reactor current and switching transition time are demonstrated.

  In FIG. 1, when the FET 11 is turned on with the FET 12 turned off, the high voltage battery B <b> 10 is connected to the reactor 15 via the FET 11. As a result, a current is supplied from the high voltage battery B <b> 10 to the reactor 15, and energy is accumulated in the reactor 15. At this time, the reactor current IL flowing in the reactor 15 and having a positive direction from the input side to the output side increases as shown in FIG.

  Thereafter, when the FET 11 is turned off and the FET 12 is turned on during that period, the reactor 15 shown in FIG. 1 is connected to the low voltage battery B11 via the FET 12. As a result, the energy accumulated in the reactor 15 is released, and current is supplied from the reactor 15 to the low voltage battery B11. At this time, the reactor current IL decreases as shown in FIG.

  Thereafter, the same operation is repeated, power is supplied from the high voltage battery B10 to the low voltage battery B11, and the low voltage battery B11 is charged.

  When the power converter 1 shown in FIG. 1 is controlled in the current critical mode, it is necessary to turn off the FET 12 when the release of the energy stored in the reactor 15 is completed. At this time, the FET 11 is switched to zero voltage to reduce the turn-on loss of the FET 11, so that the FET 12 is turned off after the reactor current IL becomes slightly negative from 0 as shown in FIG.

  When the FET 12 is turned off, the capacitance of the snubber capacitors 130 and 140 and the parasitic capacitance of the circuit are charged by the slightly negative reactor current IL, and as shown in FIG. 5, the FETs 11 and 12 to which the reactor 15 is connected are connected. The voltage Vp at the series connection point rises and eventually becomes the input voltage Vin. When the reactor current IL in the negative direction is larger than the optimum value, the speed at which the capacitance of the snubber capacitors 130 and 140 and the parasitic capacitance of the circuit are charged by the reactor current IL is increased, and the rise of the voltage Vp is increased. On the other hand, when the reactor current IL in the negative direction is smaller than the optimum value, the rise of the voltage Vp is delayed.

  As shown in FIG. 1, the source-drain voltage of the FET 11 is obtained by subtracting the voltage Vp from the input voltage Vin. Therefore, as shown in FIG. 5, when the reactor current IL in the negative direction is larger than the optimum value, the fall of the source-drain voltage of the FET 11 becomes faster. As a result, the time until the source-drain voltage of the FET 11 becomes the threshold voltage Vth after the FET 12 is turned off, that is, the switching transition time is shortened. On the other hand, when the reactor current IL in the negative direction is smaller than the optimum value, the fall of the source-drain voltage of the FET 11 is delayed. As a result, the switching transition time becomes long.

  That is, as shown in FIG. 6, there is a relationship between the reactor current IL and the switching transition time that the switching transition time becomes shorter as the negative reactor current IL becomes larger. Therefore, the reactor current IL can be grasped from the switching transition time.

  Next, the operation of the switching transition time detection circuit will be described with reference to FIGS.

  The resistance values of the resistors 170a to 170d shown in FIG. 2 are set so that the output of the comparator 170e becomes high level until the source-drain voltage of the FET 11 reaches the threshold voltage Vth. Therefore, the comparator 170e outputs a high-level signal until the source-drain voltage of the FET 11 reaches the threshold voltage Vth, as shown in FIG. The XOR circuit 170f outputs a high level signal when the drive signal for the FET 12 is at a low level instructing the FET 12 to turn off and the output of the comparator 170e is at a high level. As a result, the switching transition time detection circuit 170 outputs a pulse signal that goes high until the source-drain voltage of the FET 11 reaches the threshold voltage Vth after the drive signal for the FET 12 instructs the FET 12 to turn off. be able to.

  Next, operations of the controller and the drive circuit will be described with reference to FIGS.

  The on-time ratio calculator 171a shown in FIG. 3 calculates and outputs an on-time ratio for the FETs 11 and 12 based on the input voltage Vin, the output voltage target value Vout *, and the output voltage Vout.

  The switching transition time measurement unit 171b measures the pulse width of the pulse signal output from the switching transition time detection circuit 170 to obtain the switching transition time. The deviation calculation unit 171c calculates a deviation between the preset switching transition time target value and the switching transition time. The switching transition time control unit 171d performs a proportional and integral calculation on the deviation between the switching transition time target value and the switching transition time, and outputs it as an on-time ratio correction value.

  The correction calculation unit 171e adds the on-time ratio correction value to the on-time ratio with respect to the FET 11, and outputs the corrected on-time ratio with respect to the FET 11. The correction calculation unit 171f subtracts the on-time ratio correction value from the on-time ratio for the FET 12, and outputs the subtracted on-time ratio for the FET 12. Thereby, the on-time ratio is corrected so that the on-time transition time becomes the on-time transition time target value.

  The deviation calculation unit 171g calculates a deviation between the output voltage target value Vout * and the output voltage Vout. The voltage control unit 171h performs a proportional and integral operation on the deviation between the output voltage target value Vout * and the output voltage Vout, and outputs the result as a conversion coefficient.

  The on-time calculator 171 i multiplies the corrected on-time ratio for the FET 11 by the conversion coefficient and outputs the result as the on-time for the FET 11. The on-time calculator 171j multiplies the corrected on-time ratio for the FET 12 by the conversion coefficient and outputs the result as the on-time for the FET 12.

  The drive signal generation unit 171k generates and outputs a drive signal for driving the FETs 11 and 12 based on the ON time for the FETs 11 and 12.

  The drive circuits 172 and 173 shown in FIG. 1 turn the FETs 11 and 12 on and off, respectively, based on the drive signal.

  As a result, the switching transition time is controlled to become the switching transition time target value. That is, the reactor current IL is controlled so as to be an optimum value. Therefore, the power conversion device 1 that supplies power from the high voltage battery B10 to the low voltage battery B11 can be controlled in the current critical mode without detecting the reactor current.

  Next, the effect of the power converter of the first embodiment will be described.

  As shown in FIG. 6, there is a predetermined relationship between the switching transition time and the reactor current IL, and the reactor current IL can be grasped by the switching transition time.

  According to the first embodiment, the control circuit 17 detects the switching transition time and controls the FETs 11 and 12 based on the switching transition time. Therefore, reactor current IL can be appropriately controlled without detecting the reactor current. Therefore, the power converter device 1 that is a buck-boost converter can be controlled in the current critical mode without detecting the reactor current. Conventionally, since there is variation in the characteristics of each element constituting the power conversion device, the reactor current in the negative direction has been purposely controlled in consideration of this. However, since variations in the characteristics of each element are reflected in the switching transition time, it is not necessary to control the reactor current IL in the minus direction to be large in the first place. Therefore, switching loss and conduction loss can be suppressed.

  According to the first embodiment, the control circuit 17 controls the FETs 11 and 12 based on the input voltage Vin, the output voltage Vout, and the deviation between the switching transition time target value and the switching transition time. Therefore, the switching transition time can be controlled to the switching transition time target value. That is, the reactor current IL can be controlled to an optimum value. Therefore, the power converter 1 can be reliably controlled in the current critical mode.

  According to the first embodiment, the control circuit 17 corrects the on-time ratio obtained by calculating the on-time ratio obtained based on the input voltage Vin and the output voltage Vout based on the deviation between the switching transition time target value and the switching transition time. The FETs 11 and 12 are controlled based on the corrected on-time ratio. Therefore, the switching transition time can be reliably controlled to the switching transition time target value.

  According to the first embodiment, the control circuit 17 controls the FETs 11 and 12 based on the deviation between the output voltage target value Vout * and the output voltage Vout. Therefore, the output voltage Vout can be controlled to the output voltage target value Vout *.

  According to the first embodiment, the control circuit 17 converts the on-time ratio corrected based on the deviation between the output voltage target value Vout * and the output voltage Vout into the on-time, and controls the FETs 11 and 12 based on the on-time. To do. Therefore, the output voltage Vout can be reliably controlled to the output voltage target value Vout *.

(Second Embodiment)
Next, the power converter device of 2nd Embodiment is demonstrated. The power conversion device of the second embodiment supplies power from the low voltage battery to the high voltage battery while the power conversion device of the first embodiment supplies power from the high voltage battery to the low voltage battery. It is a thing.

  First, the structure of the power converter device of 2nd Embodiment is demonstrated with reference to FIGS. 8-10.

  The power conversion device 2 shown in FIG. 8 converts a direct current supplied from a low-voltage battery B21 (power supply) mounted on the vehicle into a high-voltage direct current, and converts it into a high-voltage battery B20 (load) mounted on the vehicle. It is a device that supplies and charges the high-voltage battery B20. This is a so-called boost type buck-boost converter. Here, the high voltage battery B20 and the low voltage battery B21 are the same as the high voltage battery B10 and the low voltage battery B11 of the first embodiment. The power conversion device 2 includes a smoothing capacitor 26, a reactor 25, an FET 22 (main switch), an FET 21 (synchronous rectification switch), snubber circuits 24 and 23, a smoothing capacitor 20, and a control circuit 27. ing. Although there are differences in the function of each component, the configurations of the smoothing capacitor 26, the reactor 25, the FETs 22 and 21, the snubber circuits 24 and 23, and the smoothing capacitor 20 are the same as those of the smoothing capacitor 16, the reactor 15, and the first embodiment. The configuration is the same as that of the FETs 12 and 11, the snubber circuits 14 and 13, and the smoothing capacitor 10.

  The smoothing capacitor 26 is an element that smoothes the input voltage Vin of the power conversion device 2. The smoothing capacitor 26 smoothes the voltage of the low voltage battery B21. One end of the smoothing capacitor 26 is connected to the positive terminal of the low voltage battery B21, and the other end is connected to the negative terminal of the low voltage battery B21.

  The reactor 25 is an element that stores or releases energy. One end of the reactor 25 is connected to one end of the smoothing capacitor 26, and the other end is connected to the FETs 22 and 21.

  The FET 22 is an element that, when turned on, connects the low voltage battery B21 to the reactor 25, supplies current from the low voltage battery B21 to the reactor 25, and accumulates energy in the reactor 25. The FET 22 has a diode connected in parallel between the source and the drain.

  The FET 21 is turned on while the FET 22 is turned off to connect the reactor 25 to the high voltage battery B20, release the energy accumulated in the reactor 25, and supply current from the reactor 25 to the high voltage battery B20. It is an element to do. The FET 21 has a diode connected in parallel between the source and the drain.

  The FETs 22 and 21 are connected in series. Specifically, the drain of the FET 22 is connected to the source of the FET 21. A series connection point of the FETs 22 and 21 is connected to the other end of the reactor 25. The source of the FET 22 is connected to the other end of the smoothing capacitor 26 and the negative end of the high voltage battery B20, and the drain of the FET 21 is connected to the positive end of the high voltage battery B20. The gates of the FETs 22 and 21 are connected to the control circuit 27, respectively.

  The snubber circuits 24 and 23 are circuits that suppress the surge voltage applied to the FETs 22 and 21. The snubber circuits 24 and 23 have snubber capacitors 240 and 230, respectively. One end of the snubber capacitors 240 and 230 is connected to the drains of the FETs 22 and 21, and the other end is connected to the sources of the FETs 22 and 21.

  The smoothing capacitor 20 is an element that smoothes the output voltage Vout of the power conversion device 2. One end of the smoothing capacitor 20 is connected to the drain of the FET 21 and the other end is connected to the source of the FET 22.

  The control circuit 27 is a circuit that controls the FETs 22 and 21. The control circuit 27 controls the FETs 22 and 21 based on the output voltage target value Vout * of the power converter 2 input from the outside, the detected input / output voltages Vin and Vout of the power converter 2 and the switching transition time. Here, the switching transition time is the time from when the FET 21 is instructed to be turned off until the source-drain voltage (terminal voltage) of the FET 22 reaches the threshold voltage Vth. The threshold voltage Vth is set similarly to the first embodiment. The control circuit 27 includes a switching transition time detection circuit 270, a controller 271, and drive circuits 272 and 273.

  The switching transition time detection circuit 270 is set to the high level until the voltage between the source and drain of the FET 22 reaches the threshold voltage after a drive signal output from the controller 271 instructs the FET 21 to be described later to turn off the FET 21. Is a circuit that outputs a pulse signal. As shown in FIG. 9, the switching transition time detection circuit 270 includes a reference power supply 270g, resistors 270c and 270d, a comparator 270e, and an XOR circuit 270f.

  The reference power source 270g is a power source that outputs a voltage corresponding to the threshold voltage Vth. The positive end of the reference power supply 270g is connected to the comparator 270e, and the negative end is connected to the source of the FET 22.

  The resistors 270c and 270d are connected in series. One end of the resistor 270c is connected to the series connection point of the FETs 21 and 22, and one end of the resistor 270d is connected to the source of the FET 22.

  The non-inverting input terminal of the comparator 270e is connected to the positive terminal of the reference power supply 270g, and the inverting input terminal is connected to the series connection point of the resistors 270c and 270d.

  Here, the resistance values of the resistors 270c and 270d are set so that the output of the comparator 270e is at a high level until the source-drain voltage of the FET 22 reaches the threshold voltage Vth in consideration of the voltage of the reference power source 270g. Has been.

  One input terminal of the XOR circuit 270f is connected to the output terminal of the comparator 270e, and the other input terminal is connected to the controller 271. The output end is connected to the controller 271.

  The controller 271 shown in FIG. 8 is a circuit that generates and outputs drive signals for the FETs 22 and 21 based on the output voltage target value Vout *, the input / output voltages Vin and Vout, and the switching transition time. The controller 271 includes a microcomputer and a program. As shown in FIG. 10, the controller 271 includes an on-time ratio calculation unit 271a, a switching transition time measurement unit 271b, a deviation calculation unit 271c, a switching transition time control unit 271d, correction calculation units 271e and 271f, A deviation calculator 271g, a voltage controller 271h, on-time calculators 271i and 271j, and a drive signal generator 271k are provided.

  Unlike the correction calculation unit 171e of the first embodiment, the correction calculation unit 271e is a block that subtracts the on-time ratio correction value from the on-time ratio for the FET 21 and outputs it as a corrected on-time ratio for the FET 21.

  Unlike the correction calculation unit 171 f of the first embodiment, the correction calculation unit 271 f is a block that adds an ON time ratio correction value to the ON time ratio for the FET 22 and outputs the corrected ON time ratio for the FET 22.

  The controller 271 has the same configuration as the controller 171 of the first embodiment except for the correction calculation units 271e and 271f.

  Next, the operation of the power conversion device according to the second embodiment will be described with reference to FIGS.

  First, the operation of the switching transition time detection circuit will be described with reference to FIG.

  The reference power supply 270g shown in FIG. 9 outputs a voltage corresponding to the threshold voltage. The resistance values of the resistors 270c and 270d are set such that the output of the comparator 270e is at a high level until the source-drain voltage of the FET 22 reaches the threshold voltage Vth in consideration of the voltage of the reference power supply 270g. . Therefore, the comparator 270e outputs a high level signal until the source-drain voltage of the FET 22 reaches the threshold voltage Vth. The XOR circuit 270f outputs a high level signal when the drive signal for the FET 21 is at a low level instructing the FET 21 to turn off and the output of the comparator 270e is at a high level. As a result, the switching transition time detection circuit 270 outputs a pulse signal that remains high until the source-drain voltage of the FET 22 reaches the threshold voltage Vth after the drive signal for the FET 21 instructs the FET 21 to turn off. be able to.

  Next, operations of the controller and the drive circuit will be described with reference to FIGS.

  Unlike the correction calculation unit 171e of the first embodiment, the correction calculation unit 271e illustrated in FIG. 10 subtracts the on-time ratio correction value from the on-time ratio for the FET 21, and outputs the subtracted on-time ratio for the FET 21. Unlike the correction calculation unit 171f of the first embodiment, the correction calculation unit 271f adds the on-time ratio correction value to the on-time ratio for the FET 22, and outputs the corrected on-time ratio for the FET 22.

  The controller 271 performs the same operation as the controller 171 of the first embodiment except for the operations of the correction calculation units 271e and 271f.

  The drive circuits 272 and 272 shown in FIG. 8 turn the FETs 21 and 22 on and off, respectively, based on the drive signal.

  As a result, the switching transition time is controlled to become the switching transition time target value. That is, control is performed so that the reactor current IL having a positive direction from the input side to the output side becomes an optimum value. Therefore, the power conversion device 2 that supplies power from the low voltage battery B21 to the high voltage battery B20 can be controlled in the current critical mode without detecting the reactor current.

  Next, the effect of the power converter of 2nd Embodiment is demonstrated. According to the second embodiment, the same effect as that of the first embodiment can be obtained.

  In the second embodiment, an example in which the switching transition time detection circuit 270 is configured using the reference power supply 270g is described, but the present invention is not limited to this. The same configuration as that of the switching transition time detection circuit 170 of the first embodiment may be used by adjusting the resistance value of the resistor.

(Third embodiment)
Next, the power converter device of 3rd Embodiment is demonstrated. The power conversion device of the third embodiment is a combination of the power conversion device of the first embodiment and the power conversion device of the second embodiment so that power can be supplied bidirectionally between the high voltage battery and the low voltage battery. It is a thing.

  First, the configuration of the power conversion device according to the third embodiment will be described with reference to FIGS. 11 and 12.

  The power conversion device 3 shown in FIG. 11 converts a direct current supplied from a high-voltage battery B30 (power source) mounted on the vehicle into a low-voltage direct current, and converts it into a low-voltage battery B31 (load) mounted on the vehicle. It is a device that supplies and charges the low-voltage battery B31. Conversely, it is also a device for charging the high voltage battery B30 by converting the direct current supplied from the low voltage battery B31 (power supply) into a high voltage direct current and supplying it to the high voltage battery B30 (load). That is, it is a device that can supply power bidirectionally between the high-voltage battery B30 and the low-voltage battery B31. This is a so-called buck-boost buck-boost converter. The power converter 3 includes a smoothing capacitor 30, an FET 31 (main switch), an FET 32 (synchronous rectification switch), snubber circuits 33 and 34, a reactor 35, a smoothing capacitor 36, and a control circuit 37. ing. The configurations of the smoothing capacitor 30, the FETs 31, 32, the snubber circuits 33, 34, the reactor 35, and the smoothing capacitor 36 are the same as the smoothing capacitor 10, the FETs 11, 12, the snubber circuits 13, 14, the reactor 15 and the smoothing of the first embodiment. The configuration of the capacitor 16 for smoothing, the configuration of the smoothing capacitor 20, the FETs 21 and 22, the snubber circuits 23 and 24, the reactor 25, and the smoothing capacitor 26 of the second embodiment are the same.

  The control circuit 37 is a circuit that controls the FETs 31 and 32. When supplying power from the high voltage battery B30 to the low voltage battery B31, the control circuit 37 operates in the same manner as the control circuit 17 of the first embodiment, and supplies power from the low voltage battery B31 to the high voltage battery B30. In this case, the operation is the same as that of the control circuit 27 of the second embodiment. The control circuit 37 includes a switching transition time detection circuit 370, a controller 371, and drive circuits 372 and 373.

  The switching transition time detection circuit 370 is a circuit provided with the function of the switching transition time detection circuit 170 of the first embodiment and the function of the switching transition time detection circuit 270 of the second embodiment. As shown in FIG. 12, the switching transition time detection circuit 370 includes resistors 370h to 370l, comparators 370m and 370n, and XOR circuits 370o and 370p.

  The resistors 370h to 370j are connected in series. One end of the resistor 370h is connected to the drain of the FET 31, and one end of the resistor 370j is connected to the source of the FET 32.

  The resistors 370k and 370l are connected in series. One end of the resistor 370k is connected to the series connection point of the FETs 31 and 32, and one end of the resistor 370l is connected to the source of the FET 32.

  The non-inverting input terminal of the comparator 370m is connected to the series connection point of the resistors 370h and 370i, and the inverting input terminal is connected to the series connection point of the resistors 370k and 370l.

  The non-inverting input terminal of the comparator 370n is connected to the series connection point of the resistors 370k and 370l, and the inverting input terminal is connected to the series connection point of the resistors 370i and 370j.

  Here, the resistance values of the resistors 370h to 370l are determined until the output of the comparator 370m is at a high level until the source-drain voltage of the FET 31 reaches the threshold voltage Vth, and until the source-drain voltage of the FET 32 reaches the threshold voltage Vth. The output of the comparator 370n is set to a high level.

  One input terminal of the XOR circuit 370 o is connected to the output terminal of the comparator 370 m, and the other input terminal is connected to a drive signal generator (not shown) of the controller 371 that outputs a drive signal for the FET 32. The output terminal is connected to a switching transition time measuring unit (not shown) of the controller 371 that measures the switching transition time for the FET 31.

  One input terminal of the XOR circuit 370p is connected to the output terminal of the comparator 370n, and the other input terminal is connected to a drive signal generator (not shown) of the controller 371 that outputs a drive signal for the FET 31. The output terminal is connected to a switching transition time measuring unit (not shown) of the controller 371 that measures the switching transition time for the FET 32.

  A controller 371 shown in FIG. 11 is a circuit having the function of the controller 171 of the first embodiment and the function of the controller 271 of the second embodiment. The controller 371 includes the components of the controller 171 of the first embodiment and the components of the controller 271 of the second embodiment.

  The drive circuits 372 and 373 have the same functions and configurations as the drive circuits 172 and 173 of the first embodiment and the drive circuits 272 and 273 of the second embodiment.

  Next, the operation of the power conversion device according to the third embodiment will be described with reference to FIGS. 11 and 12.

  First, the operation of the switching transition time detection circuit will be described with reference to FIG.

  The resistance values of the resistors 370h to 370l shown in FIG. 12 are such that the output of the comparator 370m is at a high level and the source-drain voltage of the FET 32 is the threshold voltage Vth until the source-drain voltage of the FET 31 reaches the threshold voltage Vth. Until this time, the output of the comparator 370n is set to a high level.

  Therefore, the comparator 370m outputs a high level signal until the source-drain voltage of the FET 31 reaches the threshold voltage Vth. The XOR circuit 370o outputs a high level signal when the drive signal for the FET 32 is at a low level instructing the FET 32 to be turned off and the output of the comparator 370m is at a high level. As a result, the switching transition time detection circuit 370 outputs a pulse signal that remains high until the source-drain voltage of the FET 31 reaches the threshold voltage Vth after the drive signal for the FET 32 instructs the FET 32 to turn off. be able to.

  On the other hand, the comparator 370n outputs a high level signal until the source-drain voltage of the FET 32 reaches the threshold voltage Vth. The XOR circuit 370p outputs a high level signal when the drive signal for the FET 31 is at a low level instructing the FET 31 to be turned off and the output of the comparator 370n is at a high level. As a result, the switching transition time detection circuit 370 outputs a pulse signal that goes high until the voltage between the source and drain of the FET 32 reaches the threshold voltage Vth after the drive signal for the FET 31 instructs the FET 31 to turn off. be able to.

  Next, operations of the controller and the drive circuit will be described with reference to FIG.

  The controller 371 shown in FIG. 11 performs the same operation as the controller 171 of the first embodiment when supplying power from the high voltage battery B30 to the low voltage battery B31. On the other hand, when power is supplied from the low voltage battery B31 to the high voltage battery B30, the same operation as the controller 271 of the second embodiment is performed. The drive circuits 372 and 373 turn the FETs 31 and 32 on and off, respectively, based on the drive signal.

  As a result, the switching transition time is controlled to become the switching transition time target value. That is, the reactor current IL is controlled so as to be an optimum value. Therefore, it is possible to control the power conversion device 3 that supplies power bidirectionally between the high voltage battery B30 and the low voltage battery B31 without detecting the reactor current in the current critical mode.

  Next, the effect of the power converter of 3rd Embodiment is demonstrated. According to the third embodiment, the same effect as that of the first embodiment can be obtained.

  In the third embodiment, an example is given in which the switching transition time detection circuit 370 is configured without using a reference power supply, but the present invention is not limited to this. The switching transition time detection circuit 170 according to the first embodiment may be combined with the switching transition time detection circuit 270 according to the second embodiment.

(Fourth embodiment)
Next, the power converter device of 4th Embodiment is demonstrated. The power conversion device of the fourth embodiment detects an output current with respect to the power conversion device of the first embodiment, and controls the FET based on the detected output current.

  First, the configuration of the power conversion device according to the fourth embodiment will be described with reference to FIGS. 13 and 14.

  The power conversion device 4 shown in FIG. 13 converts a direct current supplied from a high-voltage battery B40 (power source) mounted on a vehicle into a low-voltage direct current to a low-voltage battery B41 (load) mounted on the vehicle. It is a device that supplies and charges the low-voltage battery B41. This is a so-called step-down buck-boost converter. The power converter 4 includes a smoothing capacitor 40, an FET 41 (main switch), an FET 42 (synchronous rectification switch), snubber circuits 43 and 44, a reactor 45, a smoothing capacitor 46, and a control circuit 47. ing. Furthermore, a current sensor 48 is provided. The smoothing capacitor 40, the FETs 41 and 42, the snubber circuits 43 and 44, the reactor 45, and the smoothing capacitor 46 are the smoothing capacitor 10, the FETs 11 and 12, the snubber circuits 13 and 14, the reactor 15 and the smoothing capacitor of the first embodiment. 16 has the same function and configuration.

  The current sensor 48 is an element that detects the output current Iout of the power conversion device 4. The current sensor 48 is provided in a wiring connecting the other end of the reactor 45 and the positive end of the low voltage battery B 41, and is connected to the control circuit 47.

  The control circuit 47 is a circuit that controls the FETs 41 and 42. The control circuit 47 outputs the output voltage target value Vout *, the output current target value Iout *, the detected input / output voltages Vin and Vout, the output current Iout, and the switching transition time of the power converter 4 input from the outside. The FETs 41 and 42 are controlled based on the above. Here, the switching transition time is the time from when the FET 42 is instructed to be turned off until the source-drain voltage (terminal voltage) of the FET 41 reaches the threshold voltage, and is set in the same manner as in the first embodiment. ing. The control circuit 47 includes a switching transition time detection circuit 470, a controller 471, and drive circuits 472 and 473.

  The switching transition time detection circuit 470 has the same function and the same configuration as the switching transition time detection circuit 170 of the first embodiment.

  The controller 471 is a circuit that generates and outputs drive signals for the FETs 41 and 42 based on the output voltage target value Vout *, the output current target value Iout *, the input / output voltages Vin and Vout, the output current Iout, and the switching transition time. . The controller 471 includes a microcomputer and a program. As shown in FIG. 14, the controller 471 includes an on-time ratio calculation unit 471a, a switching transition time measurement unit 471b, a deviation calculation unit 471c, a switching transition time control unit 471d, correction calculation units 471e and 471f, A deviation calculator 471g, a voltage controller 471h, on-time calculators 471i and 471j, and a drive signal generator 471k are provided. Further, a selection unit 471l, a deviation calculation unit 471m, and a current control unit 471n are provided.

  The on-time ratio calculation unit 471a, the switching transition time measurement unit 471b, the deviation calculation unit 471c, the switching transition time control unit 471d, the correction calculation units 471e and 471f, and the deviation calculation unit 471g are the on-time ratio calculation unit 171a of the first embodiment. The switching transition time measurement unit 171b, the deviation calculation unit 171c, the switching transition time control unit 171d, the correction calculation units 171e and 171f, and the deviation calculation unit 171g have the same function and the same configuration.

  The voltage control unit 471h is a block that proportionally integrates the deviation between the output voltage target value Vout * output from the deviation calculating unit 471g and the output voltage Vout, and outputs the result as an output current target value.

  The selection unit 471l is a block that selects and outputs the smaller one of the output current target value output from the voltage control unit 471h and the output current target value Iout * input from the outside as a new output current target value.

  The deviation calculation unit 471m is a block that calculates and outputs a deviation between the new output current target value output from the selection unit 471l and the output current Iout of the power conversion device 4 detected by the current sensor 48.

  The current control unit 471n is a block that proportionally integrates the deviation between the new output current target value output from the deviation calculating unit 471m and the output current Iout, and outputs the result as a conversion coefficient.

  The on-time calculating unit 471i is a block that multiplies the corrected on-time ratio for the FET 41 output from the correction calculating unit 471e by the conversion coefficient output from the current control unit 471n, and outputs the result as the on-time for the FET 41.

  The on-time calculation unit 471j is a block that multiplies the corrected on-time ratio for the FET 42 output from the correction calculation unit 471f by the conversion coefficient output from the current control unit 471n and outputs the result as the on-time for the FET 42.

  The drive signal generation unit 471k is a block that generates and outputs a drive signal for driving the FETs 41 and 42 based on the ON times for the FETs 41 and 42 output from the ON time calculation units 471i and 471j.

  The drive circuits 472 and 473 shown in FIG. 13 have the same function and the same configuration as the drive circuits 172 and 173 of the first embodiment.

  Next, the operation of the power conversion device according to the fourth embodiment will be described with reference to FIGS. 13 and 14. Since the operation of the switching transition time detection circuit 470 shown in FIG. 13 is the same as the operation of the switching transition time detection circuit 170 of the first embodiment, description thereof is omitted. The operation of the controller and the drive circuit will be described.

  The voltage control unit 471h illustrated in FIG. 14 performs a proportional and integral calculation on the deviation between the output voltage target value Vout * and the output voltage Vout, and outputs the result as an output current target value. The selection unit 471l selects and outputs the smaller one of the output current target value output from the voltage control unit 471h and the output current target value Iout * input from the outside as a new output current target value.

  The deviation calculation unit 471m calculates and outputs a deviation between the new output current target value and the output current Iout. The current control unit 471n performs a proportional and integral operation on the deviation between the new output current target value and the output current Iout, and outputs the result as a conversion coefficient. That is, unlike the controller 171 of the first embodiment, the conversion coefficient is calculated in consideration of the output current target value and the output current.

  The on-time calculation unit 471i multiplies the corrected on-time ratio for the FET 41 by the conversion coefficient output from the current control unit 471n, and outputs the result as the on-time for the FET 41. The on-time calculator 471j multiplies the corrected on-time ratio for the FET 42 by the conversion coefficient output from the current controller 471n, and outputs the result as the on-time for the FET 42.

  The drive signal generation unit 471k generates and outputs a drive signal for driving the FETs 41 and 42 based on the ON time for the FETs 41 and 42.

  The drive circuits 472 and 473 shown in FIG. 13 turn the FETs 41 and 42 on and off, respectively, based on the drive signal.

  As a result, the switching transition time is controlled to become the switching transition time target value. That is, the reactor current IL is controlled so as to be an optimum value. Therefore, the power conversion device 4 that supplies power from the high voltage battery B40 to the low voltage battery B41 can be controlled in the current critical mode without detecting the reactor current.

  Next, the effect of the power converter of 4th Embodiment is demonstrated.

  According to the fourth embodiment, as in the first embodiment, the power conversion device 4 that is a buck-boost converter can be controlled in the current critical mode without detecting the reactor current. Moreover, switching loss can be suppressed.

  According to the fourth embodiment, the control circuit 47 controls the FETs 41 and 42 based on the deviation between the output voltage target value Vout * and the output voltage Vout, the output current target value Iout * input from the outside, and the output current Iout. . Therefore, the output voltage Vout can be controlled to the output voltage target value Vout *, and the output current Iout can be controlled to the output current Iout *.

  According to the fourth embodiment, the control circuit 47 includes the output current target value obtained based on the deviation between the output voltage target value Vout * and the output voltage Vout, and the output current target value Iout * input from the outside. The smaller one is set as a new output current target value, and the FETs 41 and 42 are controlled based on the deviation between the new output current target value and the output current Iout. Therefore, the output voltage Vout can be reliably controlled to the output voltage target value Vout *, and the output current Iout can be reliably controlled to the output current Iout *.

(Fifth embodiment)
Next, the power converter device of 5th Embodiment is demonstrated. The power converter of the fifth embodiment is a flyback converter, whereas the power converter of the first embodiment is a buck-boost converter.

  First, with reference to FIG. 15, the structure of the power converter device of 5th Embodiment is demonstrated.

  The power conversion device 5 shown in FIG. 15 converts a direct current supplied from a high voltage battery B50 (power source) mounted on a vehicle into a low voltage direct current, and converts it into a low voltage battery B51 (load) mounted on the vehicle. It is a device that supplies and charges the low-voltage battery B51. This is a so-called step-down type flyback converter. Here, the high voltage battery B50 and the low voltage battery B51 are the same as the high voltage battery B10 and the low voltage battery B11 of the first embodiment. The power converter 5 includes a smoothing capacitor 50, an FET 51 (main switch), an FET 52 (synchronous rectification switch), snubber circuits 53 and 54, a transformer 55 (reactor), a smoothing capacitor 56, and a control circuit 57. And.

  The smoothing capacitor 50 has the same function and the same configuration as the smoothing capacitor 10 of the first embodiment.

  The FET 51 is an element that, when turned on, connects the high voltage battery B50 to the transformer 55, supplies current from the high voltage battery B50 to the transformer 55, and accumulates energy in the transformer 55. The FET 51 has a diode connected in parallel between the source and the drain. The drain of the FET 51 is connected to the transformer 55, and the source is connected to the other end of the smoothing capacitor 50.

  The FET 52 is turned on while the FET 51 is turned off to connect the transformer 55 to the low voltage battery B51, release the energy accumulated in the transformer 55, and supply current from the transformer 55 to the low voltage battery B51. It is an element to do. The FET 52 has a diode connected in parallel between the source and the drain. The FET 52 has a source connected to the transformer 55 and a drain connected to the positive terminal of the low-voltage battery B51.

  The snubber circuits 53 and 54 have snubber capacitors 530 and 540, respectively, and have the same function and the same configuration as the snubber circuits 13 and 14 of the first embodiment.

  The transformer 55 is an element that accumulates or releases energy, converts the supplied alternating current into an alternating current with a predetermined voltage corresponding to the turn ratio in an insulated state, and outputs the alternating current. The transformer 55 has a primary winding 550 and a secondary winding 551. One end of the primary winding 550 is connected to one end of the smoothing capacitor 50, and the other end is connected to the drain of the FET 51. One end of the secondary winding 551 is connected to the source of the FET 52, and the other end is connected to the negative terminal of the low voltage battery B51.

  The smoothing capacitor 56 has the same function as the smoothing capacitor 16 of the first embodiment. One end of the smoothing capacitor 56 is connected to the drain of the FET 52, and the other end is connected to the other end of the secondary winding 551.

  The control circuit 57 has the same function as the control circuit 17 of the first embodiment, and is a circuit that controls the FETs 51 and 52. The control circuit 57 includes a switching transition time detection circuit 570, a controller 571, drive circuits 572 and 573, and an insulation circuit 574.

  The switching transition time detection circuit 570 outputs a pulse signal that remains at a high level until the drive signal for the FET 52 output from the controller 571 instructs the FET 52 to turn off until the source-drain voltage of the FET 51 reaches the threshold voltage. It is a circuit to output. The switching transition time detection circuit 570 is connected to the controller 571 in order to obtain a drive signal for the FET 52. The source and drain of the FET 51 are connected to the source and drain of the FET 51 in order to detect the source-drain voltage. Further, it is connected to the controller 571 in order to output the detection result pulse signal to the controller 571.

  The controller 571 and the drive circuits 572 and 573 have the same function and the same configuration as the controller 171 and the drive circuits 172 and 173 of the first embodiment.

  The insulating circuit 574 is a circuit that outputs the output voltage Vout of the power converter 5 to the controller 571 in an insulated state. The input end of the insulating circuit 574 is connected to one end of the smoothing capacitor 56, and the other end is connected to the controller 571.

  Next, the operation of the power conversion apparatus according to the fifth embodiment will be described with reference to FIG.

  The switching transition time detection circuit 570 shown in FIG. 15 outputs a pulse signal that remains at a high level until the drive signal for the FET 52 instructs the FET 52 to turn off until the source-drain voltage of the FET 51 reaches the threshold voltage Vth. . Similarly to the controller 171 of the first embodiment, the controller 571 obtains the switching transition time from the pulse signal output from the switching transition time detection circuit 570, and outputs the output voltage target value Vout *, the input / output voltages Vin and Vout, and the switching Based on the transition time, drive signals for the FETs 51 and 52 are generated and output.

  The drive circuits 572 and 573 turn the FETs 51 and 52 on and off, respectively, based on the drive signal.

  As a result, similarly to the power conversion device 1 of the first embodiment, the switching transition time is controlled to become the switching transition time target value. That is, the reactor current IL is controlled so as to be an optimum value. Therefore, it is possible to control the power conversion device 5 that supplies power from the high voltage battery B50 to the low voltage battery B51 in the current critical mode without detecting the reactor current.

  Next, the effect of the power converter of 5th Embodiment is demonstrated. According to the fifth embodiment, the same effect as that of the first embodiment can also be obtained in the power conversion device 5 that is a flyback converter.

  In the fifth embodiment, the FETs 51 and 52 are controlled based on the output voltage target value Vout *, the input / output voltages Vin and Vout, and the switching transition time. However, the present invention is not limited to this. As in the power conversion device 4 of the fourth embodiment, the FETs 51 and 52 may be controlled in consideration of the output current target value Iout * and the output current Iout. Also in the power converter device 5 which is a flyback converter, the same effect as the fourth embodiment can be obtained.

(Sixth embodiment)
Next, the power converter device of 6th Embodiment is demonstrated. The power converter of 6th Embodiment changes the structure of a controller with respect to the power converter of 1st Embodiment.

  First, the configuration of the power conversion device according to the sixth embodiment will be described with reference to FIGS. 16 and 17.

  As shown in FIG. 16, the power conversion device 6 converts the direct current supplied from the high voltage battery B60 (power source) mounted on the vehicle into a low voltage direct current, and converts the low voltage battery B61 ( Load) and charge the low voltage battery B61. This is a so-called step-down buck-boost converter. Here, the high voltage battery B60 and the low voltage battery B61 are the same as the high voltage battery B10 and the low voltage battery B11 of the first embodiment. The power conversion device 6 includes a smoothing capacitor 60, an FET 61 (main switch), an FET 62 (synchronous rectification switch), snubber circuits 63 and 64, a reactor 65, a smoothing capacitor 66, and a control circuit 67. ing.

  The smoothing capacitor 60, FETs 61 and 62, snubber circuits 63 and 64, the reactor 65 and the smoothing capacitor 66 are the smoothing capacitor 10, FETs 11 and 12, the snubber circuits 13 and 14, the reactor 15 and the smoothing capacitor of the first embodiment. 16 has the same function and configuration.

  The control circuit 67 is a circuit that controls the FETs 61 and 62. The control circuit 67 controls the FETs 61 and 62 based on the output voltage target value Vout * of the power converter 6 input from the outside, the detected output voltage Vout of the power converter 6 and the switching transition time. Unlike the control circuit 17 of the first embodiment, the input voltage of the power converter 6 is not fed back when the FETs 61 and 62 are controlled. Here, the switching transition time is the time from when the FET 62 is instructed to be turned off until the source-drain voltage (terminal voltage) of the FET 61 reaches the threshold voltage Vth, and is set in the same manner as in the first embodiment. Has been. The control circuit 67 includes a switching transition time detection circuit 670, a controller 671, and drive circuits 672 and 673.

  The switching transition time detection circuit 670 has the same function and the same configuration as the switching transition time detection circuit 170 of the first embodiment.

  The controller 671 is a circuit that generates and outputs drive signals for the FETs 61 and 62 based on the output voltage target value Vout *, the output voltage Vout, and the switching transition time. The controller 671 includes a microcomputer and a program. As shown in FIG. 17, the controller 671 includes a deviation calculator 671o, a voltage controller 671p, a switching transition time measuring unit 671q, a deviation calculator 671r, a switching transition time controller 671s, and an on-time calculator. 671t and a drive signal generation unit 671u.

  The deviation calculation unit 671o is a block that calculates and outputs a deviation between the output voltage target value Vout * of the power conversion device 6 input from the outside and the output voltage Vout.

  The voltage control unit 671p is a block that proportionally and integrates the deviation between the output voltage target value Vout * output from the deviation calculating unit 671o and the output voltage Vout and outputs it as an on-time ratio for the FETs 61 and 62.

  The switching transition time measuring unit 671q and the deviation calculating unit 671r have the same function and the same configuration as the switching transition time measuring unit 171b and the deviation calculating unit 171c of the first embodiment.

  The switching transition time control unit 671s is a block that proportionally integrates the deviation between the switching transition time target value output from the deviation calculating unit 671r and the switching transition time, and outputs it as a switching cycle. Here, the switching period is the time from when the FET 61 is instructed to be turned on until the next time that the FET 61 is instructed to be turned on. This is also the time from when the FET 62 is instructed to be turned on to when the FET 62 is next turned on.

  The on-time calculator 671t is a block that calculates and outputs an on-time for the FETs 61 and 62 based on the on-time ratio output from the voltage controller 671p and the switching period output from the switching transition time controller 671s.

  The drive signal generation unit 671u is a block that generates and outputs a drive signal for driving the FETs 61 and 62 based on the ON time for the FETs 61 and 62 output from the ON time calculation unit 671t.

  The drive circuits 672 and 673 shown in FIG. 16 have the same function and the same configuration as the drive circuits 172 and 173 of the first embodiment.

  Next, the operation of the power conversion device according to the sixth embodiment will be described with reference to FIGS. 16 and 17. Since the operation of the switching transition time detection circuit 670 shown in FIG. 16 is the same as the operation of the switching transition time detection circuit 170 of the first embodiment, the description thereof is omitted. The operation of the controller and the drive circuit will be described.

  The deviation calculator 671o shown in FIG. 17 calculates and outputs the deviation between the output voltage target value Vout * and the output voltage Vout. The voltage control unit 671p performs a proportional and integral operation on the deviation between the output voltage target value Vout * and the output voltage Vout, and outputs the result as an on-time ratio for the FETs 61 and 62.

  The switching transition time measurement unit 671q measures the pulse width of the pulse signal output from the switching transition time detection circuit 670 to obtain the switching transition time. The deviation calculator 671r calculates a deviation between a preset switching transition time target value and the switching transition time. The switching transition time control unit 671s performs a proportional and integral operation on the deviation between the switching transition time target value and the switching transition time, and outputs the result as a switching cycle. The switching transition time control unit 671s shortens the switching cycle when the negative reactor current IL is larger than the optimum value. On the other hand, when the negative reactor current IL is smaller than the optimum value, the switching cycle is lengthened.

  The on-time calculator 671t calculates and outputs the on-time for the FETs 61 and 62 based on the on-time ratio and the switching period. The drive signal generation unit 671u generates and outputs a drive signal for driving the FETs 61 and 62 based on the ON time for the FETs 61 and 62.

  The drive circuits 672 and 673 shown in FIG. 16 turn the FETs 61 and 62 on and off, respectively, based on the drive signal.

  When the switching cycle is shortened, the period during which the reactor current IL is negative is shortened, and the reactor current IL in the negative direction is decreased. On the other hand, when the switching cycle becomes longer, the period during which the reactor current IL becomes negative becomes longer, and the reactor current IL in the negative direction becomes larger.

  As a result, the switching transition time is controlled to become the switching transition time target value. That is, the reactor current IL is controlled so as to be an optimum value. Therefore, the power converter 6 that supplies power from the high voltage battery B60 to the low voltage battery B61 can be controlled in the current critical mode without detecting the reactor current.

  Next, the effect of the power converter of 6th Embodiment is demonstrated.

  According to the sixth embodiment, similarly to the first embodiment, the power conversion device 6 that is a buck-boost converter can be controlled in the current critical mode without detecting the reactor current. Moreover, switching loss can be suppressed.

  According to the sixth embodiment, the control circuit 67 obtains the on-time ratio based on the deviation between the output voltage target value Vout * and the output voltage Vout, and performs switching based on the deviation between the switching transition time target value and the switching transition time. The period is obtained, and the FETs 61 and 62 are controlled based on the obtained on-time ratio and the switching period. Therefore, the output voltage Vout can be controlled to the output voltage target value Vout *, and the switching transition time can be controlled to the switching transition time target value.

  According to the sixth embodiment, the control circuit 67 obtains the on-time based on the on-time ratio and the switching period, and controls the FETs 61 and 62 based on the obtained on-time. Therefore, the ON time can be obtained reliably, and the FETs 61 and 62 can be reliably controlled based on the ON time.

(Seventh embodiment)
Next, the power converter device of 7th Embodiment is demonstrated. The power converter of 7th Embodiment detects an output current with respect to the power converter of 6th Embodiment, and controls FET based on the detected output current.

  First, the configuration of the power conversion device according to the seventh embodiment will be described with reference to FIGS. 18 and 19.

  The power conversion device 7 shown in FIG. 18 converts a direct current supplied from a high-voltage battery B70 (power supply) mounted on the vehicle into a low-voltage direct current to a low-voltage battery B71 (load) mounted on the vehicle. It is a device that supplies and charges the low-voltage battery B71. This is a so-called step-down buck-boost converter. The power conversion device 7 includes a smoothing capacitor 70, an FET 71 (main switch), an FET 72 (synchronous rectification switch), snubber circuits 73 and 74, a reactor 75, a smoothing capacitor 76, and a control circuit 77. ing. Furthermore, a current sensor 78 is provided. The smoothing capacitor 70, FETs 71 and 72, snubber circuits 73 and 74, the reactor 75, and the smoothing capacitor 76 are the smoothing capacitor 60, FETs 61 and 62, the snubber circuits 63 and 64, the reactor 65, and the smoothing capacitor of the sixth embodiment. 66 has the same function and configuration.

  The current sensor 78 is an element that detects the output current Iout of the power conversion device 7. The current sensor 78 is provided on the wiring connecting the other end of the reactor 75 and the positive end of the low voltage battery B 71, and is connected to the control circuit 77.

  The control circuit 77 is a circuit that controls the FETs 71 and 72. The control circuit 77 outputs the output voltage target value Vout *, the output current target value Iout * of the power conversion device 7 input from the outside, the input / output voltages Vin and Vout, the output current Iout and the switching transition time of the detected power conversion device 7. The FETs 71 and 72 are controlled based on the above. Here, the switching transition time is the time from when the FET 72 is instructed to be turned off until the source-drain voltage (terminal voltage) of the FET 71 reaches the threshold voltage, and is set similarly to the sixth embodiment. ing. The control circuit 77 includes a switching transition time detection circuit 770, a controller 771, and drive circuits 772 and 773.

  The switching transition time detection circuit 770 has the same function and the same configuration as the switching transition time detection circuit 670 of the sixth embodiment.

  The controller 771 is a circuit that generates and outputs drive signals for the FETs 71 and 72 based on the output voltage target value Vout *, the output current target value Iout *, the input / output voltages Vin and Vout, the output current Iout, and the switching transition time. . The controller 771 includes a microcomputer and a program. As shown in FIG. 19, the controller 771 includes a deviation calculator 771o, a voltage controller 771p, a switching transition time measurement unit 771q, a deviation calculator 771r, a switching transition time controller 771s, and an on-time calculator. 771t and a drive signal generator 771u. Furthermore, a selection unit 771v, a deviation calculation unit 771w, and a current control unit 771x are provided.

  The deviation calculator 771o has the same function and the same configuration as the deviation calculator 671o of the sixth embodiment.

  The voltage control unit 771p is a block that proportionally integrates the deviation between the output voltage target value Vout * output from the deviation calculating unit 771o and the output voltage Vout, and outputs it as an output current target value.

  Of the output current target value output by the selection unit 771v and the voltage control unit 771p and the output current target value Iout * input from the outside, this is a block that selects and outputs the smaller one as the new output current target value.

  The deviation calculator 771w is a block that calculates and outputs a deviation between the new output current target value output from the selector 771v and the output current Iout of the power converter 7 detected by the current sensor 78.

  The current control unit 771x is a block that proportionally integrates the deviation between the new output current target value output from the deviation calculating unit 771w and the output current Iout, and outputs it as an on-time ratio for the FETs 71 and 72.

  The switching transition time measuring unit 771q, the deviation calculating unit 771r, and the switching transition time controlling unit 771s have the same function and the same configuration as the switching transition time measuring unit 671q, the deviation calculating unit 671r, and the switching transition time controlling unit 671s of the sixth embodiment. is there.

  The on-time calculator 771t is a block that calculates and outputs the on-time for the FETs 71 and 72 based on the on-time ratio output from the current controller 771x and the switching period output from the switching transition time controller 771s.

  The drive signal generation unit 771u is a block that generates and outputs a drive signal for driving the FETs 71 and 72 based on the ON time for the FETs 71 and 72 output from the ON time calculation unit 771t.

  The drive circuits 772 and 773 shown in FIG. 18 have the same function and the same configuration as the drive circuits 672 and 673 of the sixth embodiment.

  Next, the operation of the power conversion apparatus according to the seventh embodiment will be described with reference to FIGS. Since the operation of the switching transition time detection circuit 770 shown in FIG. 18 is the same as the operation of the switching transition time detection circuit 670 of the sixth embodiment, the description thereof is omitted. The operation of the controller and the drive circuit will be described.

  The voltage control unit 771p shown in FIG. 19 performs proportional and integral calculations on the deviation between the output voltage target value Vout * and the output voltage Vout, and outputs the result as an output current target value. The selection unit 771v selects and outputs the smaller one of the output current target value output from the voltage control unit 771p and the output current target value Iout * input from the outside as a new output current target value.

  The deviation calculator 771w calculates and outputs the deviation between the new output current target value and the output current Iout. The current control unit 771x performs a proportional and integral calculation on the deviation between the new output current target value and the output current Iout, and outputs the result as an on-time ratio for the FETs 71 and 72. That is, unlike the controller 671 of the sixth embodiment, the on-time ratio with respect to the FETs 71 and 72 is calculated in consideration of the output current target value and the output current.

  The on-time calculator 771t calculates and outputs the on-time for the FETs 71 and 72 based on the on-time ratio and the switching period.

  The drive signal generator 771u generates and outputs a drive signal for driving the FETs 71 and 72 based on the ON time for the FETs 71 and 72.

  The drive circuits 772 and 773 shown in FIG. 18 turn the FETs 71 and 72 on and off, respectively, based on the drive signal.

  As a result, the switching transition time is controlled to become the switching transition time target value. That is, the reactor current IL is controlled so as to be an optimum value. Therefore, it is possible to control the power conversion device 7 that supplies power from the high voltage battery B70 to the low voltage battery B71 in the current critical mode without detecting the reactor current.

  Next, the effect of the power converter of 7th Embodiment is demonstrated.

  According to the seventh embodiment, similarly to the sixth embodiment, the power conversion device 7 that is a buck-boost converter can be controlled in the current critical mode without detecting the reactor current. Moreover, switching loss can be suppressed.

  According to the seventh embodiment, the control circuit 77 controls the FETs 71 and 72 based on the deviation between the output voltage target value Vout * and the output voltage Vout, the output current target value Iout * input from the outside, and the output current Iout. . Therefore, the output voltage Vout can be controlled to the output voltage target value Vout *, and the output current Iout can be controlled to the output current Iout *.

  According to the seventh embodiment, the control circuit 77 includes the output current target value obtained based on the deviation between the output voltage target value Vout * and the output voltage Vout, and the output current target value Iout * input from the outside. The smaller one is set as a new output current target value, and the FETs 71 and 72 are controlled based on the deviation between the new output current target value and the output current Iout. Therefore, the output voltage Vout can be reliably controlled to the output voltage target value Vout *, and the output current Iout can be reliably controlled to the output current Iout *.

DESCRIPTION OF SYMBOLS 1 ... Power converter, 11 ... FET (main switch), 12 ... FET (synchronous rectification switch), 15 ... Reactor, 17 ... Control circuit, B10 ... High voltage battery ( Power supply), B11 ... Low voltage battery (load)

Claims (12)

Reactors (15, 25, 35, 45, 55, 65, 75);
A main switch (11, 22, 31, 32, 41, 51, 61, 71) for connecting a power source to the reactor by turning it on, supplying current from the power source to the reactor, and storing energy in the reactor; ,
The synchronous rectification switch (12, 12) that connects the reactor to a load by turning it on during a period in which the main switch is turned off, releases the energy accumulated in the reactor, and supplies current to the load from the reactor. 21, 32, 31, 42, 52, 62, 72),
A control circuit (17, 27, 37, 47, 57, 67, 77) connected to the main switch and the synchronous rectification switch for controlling the main switch and the synchronous rectification switch;
In a power conversion device comprising:
The control circuit detects a switching transition time indicating a transition state of the voltage between the terminals of the main switch, and the detected switching transition time corresponds to a reactor current at a time when release of energy accumulated in the reactor is completed. The main switch and the synchronous rectification switch are controlled so that the switching transition time target value that is the switching transition time is set .   2. The control circuit according to claim 1, wherein the control circuit controls the main switch and the synchronous rectification switch based on an output voltage target value, an output voltage, and a deviation between the switching transition time target value and the switching transition time. The power converter described.   The control circuit (67, 77) obtains an on-time ratio based on the deviation between the output voltage target value and the output voltage, and obtains a switching period based on the deviation between the switching transition time target value and the switching transition time. The power converter according to claim 2, wherein the main switch and the synchronous rectification switch are controlled based on the ON time ratio and the switching period.   The said control circuit (67, 77) calculates | requires ON time based on an ON time ratio and a switching period, and controls the said main switch and the said synchronous rectification switch based on the calculated | required ON time. The power converter device described in 1.   The control circuit (17, 27, 37, 47, 57) calculates the on-time ratio obtained based on the input voltage and the output voltage based on the deviation between the switching transition time target value and the switching transition time. The power conversion device according to claim 2, wherein the main switch and the synchronous rectification switch are controlled on the basis of the corrected on-time ratio by correcting with a ratio correction value.   The control circuit (17, 27, 37, 47, 57) controls the main switch and the synchronous rectification switch based on a deviation between an output voltage target value and an output voltage. The power converter described.   The control circuit (17, 27, 37, 47, 57) converts an on-time ratio corrected based on a deviation between an output voltage target value and an output voltage into an on-time, and the main switch and the The power converter according to claim 6, wherein the synchronous rectifier switch is controlled.   The control circuit (47, 77) controls the main switch and the synchronous rectification switch based on a deviation between an output voltage target value and an output voltage, an output current target value input from the outside, and an output current. The power conversion device according to any one of claims 2 to 4, wherein the power conversion device is characterized in that:   The control circuit (47, 77) calculates a smaller one of the output current target value obtained based on the deviation between the output voltage target value and the output voltage and the output current target value input from the outside as a new output current target. The power converter according to claim 8, wherein the main switch and the synchronous rectification switch are controlled based on a new output current target value and a deviation between the output currents.   The switching transition time is a time from when an instruction is given to turn off the synchronous rectification switch until a voltage between terminals of the main switch becomes a threshold voltage. The power converter according to item.   The main switch (11, 22, 31, 32, 41, 61, 71) and the synchronous rectification switch (12, 21, 32, 31, 42, 62, 72) are connected in series, and one end of the main switch is connected. 11. The power conversion device according to claim 1, wherein one end of the synchronous rectification switch is connected to the load, and a series connection point is connected to the reactor. The reactor (55) is a transformer having a primary winding and a secondary winding,
The main switch (51) has one end connected to the power source and the other end connected to the primary winding.
11. The power converter according to claim 1, wherein one end of the synchronous rectification switch (52) is connected to the secondary winding and the other end is connected to the load.

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