JP6019619B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device used in an igniter for ignition of an internal combustion engine of an automobile. Built-in dynamic clamp circuit to give the ON signal to the semiconductor switch, especially when absorbing the energy accumulated in the inductance load such as the back electromotive voltage when switching with the inductance load by turning on the semiconductor switch The present invention relates to a semiconductor device.

  In an internal combustion engine ignition igniter of an automobile, a dynamic clamp circuit that gives an ON signal to the semiconductor switch when absorbing energy stored in the inductance load by turning on the semiconductor switch when switching with the inductance load. Semiconductor devices with built-in are widely used.

FIG. 10 is a configuration diagram of a main part of an ignition system using a semiconductor device incorporating a dynamic clamp circuit.
11 and 12 are configuration diagrams of a semiconductor device 1 incorporating a conventional dynamic clamp circuit. FIG. 11 is a plan view of the main part, and FIG. 12 is a cross-sectional view of the main part taken along line XX in FIG. is there.

  10, between the collector terminal 3 of the IGBT 2 constituting the semiconductor device 1 and the gate electrode 4, a constant voltage diode group 6 composed of a plurality of constant voltage diodes 6-1, 6-2,. And a dynamic clamp diode 24 constituting a dynamic clamp circuit to which the backflow prevention diode 7 is connected. A gate resistor 9 is connected between the gate electrode 4 and the gate terminal 8.

  The gate protection diodes 10 and 11 are for protecting the gate 4 of the IGBT 2 from an external surge such as ESD (Electro-Static Discharge) and have an effect of greatly attenuating the external surge together with the gate resistor 9.

  In FIG. 10, when an ON signal (High level: normally 3 to 5 V) is applied from the drive circuit 12 to the gate terminal 8, the potential of the gate 4 (gate potential) of the IGBT 2 rises through the gate resistor 9 and the IGBT 2 is turned on. To do. When the IGBT 2 is turned on, the voltage of the battery 13 is applied from the battery 13 to the primary coil 14a of the ignition coil 14, and the voltage of the battery 13 is divided by the inductance of the primary coil 14a to the primary coil 14a. A current rising with a gradient flows.

  The current flowing through the primary coil 14a of the ignition coil 14 increases with time, and an off signal (Low level: normally 0 to 1 V) is applied from the drive circuit 12 to the gate terminal 8 at a predetermined timing, so that the IGBT 2 is turned off. When the IGBT 2 is turned off, the voltage applied to the primary coil 14a of the ignition coil 14 is increased by the energy accumulated in the primary coil 14a of the ignition coil 14, and the potential of the collector terminal 3 is increased.

  As the voltage of the primary coil 14a increases, a high voltage is generated in the secondary coil 14b of the ignition coil 14 in accordance with the turn ratio of the primary coil 14a and the secondary coil 14b. A high voltage generated in the secondary coil 14b is applied between the gaps of the spark plug 15, and a discharge is generated between the caps. This discharge ignites a mixture of gasoline and air in the engine cylinder, and the cylinder starts to operate.

  In FIG. 10, when the IGBT 2 is turned on every time, the voltage of the battery 13 is applied to the primary coil 14a of the ignition coil 14 at the moment when the IGBT 2 is turned on. At this time, a voltage corresponding to the turn ratio of the primary and secondary coils 14b is generated in the secondary coil 14b. For example, if the turn ratio is 1: 100 and the battery voltage is 13V, a voltage of 1300V is generated in the secondary coil 14b. When this secondary voltage is applied to the spark plug 15, the spark plug 15 is erroneously discharged (erroneously ignited) at the moment when the IGBT 2 is turned on (in a period not having a normal timing). During this erroneous discharge, a discharge current flows from the secondary coil 14b to the GND through the spark plug 15. In order to prevent this erroneous discharge (erroneous ignition), an erroneous ignition prevention diode 16 is provided. By providing the false ignition prevention diode 16, a part of the voltage generated in the secondary coil 14b is borne by the false ignition prevention diode 15, so that the voltage applied to the spark plug 15 is reduced and the spark plug is reduced. 15 erroneous discharges can be prevented.

  When the primary current flowing through the primary coil 14a through the IGBT 2 is interrupted, a high voltage is generated at the collector terminal 3 due to the counter electromotive force of the primary coil 14a of the ignition coil (electromotive force generated by the energy accumulated in the primary coil 14a). To do. When this high voltage exceeds the avalanche voltage of the IGBT 2, an avalanche current flows through the IGBT 2 to destroy the IGBT 2.

For this reason, the dynamic clamp diode 24 is provided so that the avalanche voltage is not applied to the IGBT 2.
The dynamic clamp diode 24 functions to give the IGBT 2 a trigger signal for absorbing the energy stored in the inductance of the primary coil 14a of the ignition coil 14 by turning on the IGBT 2.

  The operation is performed by connecting the reverse voltage of the constant voltage diode group 6 and the dynamic clamp diode 24 composed of the reverse current prevention diode 7 between the gate and the collector of the IGBT 2. When a voltage equal to or higher than a clamp voltage (usually 400 to 600 V in the case of an igniter) determined by the total forward voltage of the backflow prevention diode 7 is applied between the emitter and collector of the IGBT 2, a current flows through the dynamic clamp diode 24. This current flows from the gate resistor 9 to the GND through the drive circuit 12.

  This current causes a voltage drop in the gate resistor 9. Due to this voltage drop, the voltage of the gate 4 of the IGBT 2 rises and the IGBT 2 is turned on. When the IGBT 2 is turned on, the energy stored in the inductance of the primary coil 14a is released to the GND through the IGBT 2. In other words, this energy release is absorbed by the IGBT 2.

  Depending on the design of the ignition coil 14, the clamp voltage may not be reached due to the interruption of the IGBT 2. Even with such an ignition coil 14, silent discharge may occur due to misfire or the like of the spark plug 15. During the silent discharge, the discharge voltage increases as the clamp voltage is reached. Therefore, it is necessary to add the dynamic clamp diode 24 so that the IGBT 2 is not destroyed during the silent discharge.

  In FIG. 11, an active region 21 in which an IGBT cell constituting the IGBT 2 is buried, a gate pad 22 for performing wire bonding, and an emitter pad 23 are provided in a region surrounded by the breakdown voltage structure 20. The breakdown voltage structure 20 is not particularly necessary when the voltage is low, but is required when the breakdown voltage is about 100 V or more.

  Normally, the active region 21 does not exist immediately below the gate pad 22, but the active region 21 in which the IGBT cell is embedded exists under the emitter pad 23. However, if the emitter pad 23 has a step directly under the position where wire bonding is performed, shell cracks or the like are generated due to damage during wire bonding. Since this shell crack causes a problem such as a short circuit between the collector and the emitter (CE), the cell of the active region 21 may not be formed under the emitter pad 23 in some cases.

In part of the breakdown voltage structure 20, there is a portion between the portion that becomes the collector potential on the surface of the chip peripheral portion and the portion that becomes the gate potential around the active portion (the n ⁺ diffusion region 36 and the p ⁺ diffusion region 32 shown in FIG. The constant voltage diode group 24 (constant voltage diodes 6-1.6-2 shown in FIG. 10) constituting the dynamic clamp diode 24 on the n ⁻ drift region 27 between them via the thick field oxide film 33. And a backflow prevention diode 7) are formed.

In FIG. 12, an n ⁺ buffer layer 26 and an n ⁻ drift layer 27 are stacked on a p ⁺ substrate 25. A collector electrode 38 is formed on the surface of the p ⁺ substrate 25. On the surface of the n ⁻ drift layer 27, there is an IGBT cell comprising a p base region 28, an n ⁺ emitter region 29 formed in a part thereof, and a gate electrode 31 formed of polysilicon via a gate oxide film 30. It is formed in the active region 21.
A p ⁺ diffusion region 32 is formed on the surface of the n ⁻ drift layer 27 immediately below the gate pad 22, and a polysilicon layer 31 a is formed via a field oxide film 33. The polysilicon layer 31a is connected to the gate electrode 31, and both are formed simultaneously.

  A gate Al electrode 35 is formed on the polysilicon layer 31 a via an interlayer insulating film 34, and an opening is provided in a passivation 42 indicated by a dotted line covering the gate Al electrode 35 to serve as a gate pad 22.

An n ⁺ diffusion region 36 is formed on the surface of the outermost n ⁻ drift layer 27 of this semiconductor device. .. And p regions 41-1, 41-2,... And n regions 40-1, 40-2, 40-3,... Formed in the polysilicon layer 31a are alternately formed. As a result, a series connection of constant voltage diodes and a series connection of backflow prevention diodes are formed. The low voltage diode and the backflow prevention diode become the dynamic clamp diode 24 constituting the dynamic clamp circuit 24a.

The n region 40-1 closest to the n ⁺ diffusion region 36 in the n region 40 is connected to the n ⁺ diffusion region 36 that is substantially equal to the collector potential by the Al electrode 37. As shown in FIG. 10, the dynamic clamp diode 24 is connected between the collector 3 and the gate electrode 4.

  In the cross-sectional view shown in FIG. 12, the dynamic clamp diode 24 has a polysilicon n region 40-1 / p region 41-1 / n region 40-2 / p region 41-2. Therefore, it is different from FIG. In the cross-sectional view of FIG. 12, the reverse direction junction and the forward direction junction of the diode face each other and are repeated alternately. When the n region 40-1 / p region 41-1, n region 40-2 / p region 41-2,... are formed of polysilicon by repetition, the diffusion length is short and implantation at the junction The minority carriers that are made do not affect the adjacent junction. Therefore, for example, the sum of the forward voltages of the diodes composed of the p region 41 / n region 40 is added to the sum of the reverse voltages (reverse breakdown voltages) of the diodes composed of the p region 41 / n region 40, and the clamp voltage. Becomes higher. However, the dynamic clamping diode 24 shown in FIG. 12 and the dynamic clamping diodes 6 (6-1, 6-2, 6-3,...), 7 shown in the circuit of FIG. It is.

  In the semiconductor device incorporating the above-described conventional dynamic clamp circuit 24a, the dynamic clamp diode 24 is formed on a part of the breakdown voltage structure 20 via an oxide film (field oxide film 33). Therefore, in the portion A in FIG. 11, the depletion layer just below the dynamic clamp diode 24 spreads differently from the depletion layer in a portion where the dynamic clamp diode 24 is not present. The spread of the depletion layer immediately below the dynamic clamp diode 24 is wider than the spread of the depletion layer where there is no dynamic clamp diode 24.

Then, the depletion layer is bent near the boundary, and a portion with a high electric field strength is easily formed. As a result, the breakdown voltage may not be obtained normally.
In addition, even when the withstand voltage is normal, the operation of continuous dynamic clamping at low temperatures, etc., narrows the depletion layer, increases the electric field strength, and increases the leakage current that seems to be affected by hot carriers. May occur.

  Further, when the dynamic clamp diode 24 is provided in a part of the breakdown voltage structure 20, the breakdown voltage structure is restricted, the area occupied by the breakdown voltage structure increases, the chip area increases, and the manufacturing cost increases.

  In this structure, the location where the dynamic clamp diode circuit is formed is limited to the location where the breakdown voltage structure is formed, and it is necessary to connect the breakdown voltage structure 20 and the dynamic clamp diode circuit 24a. The degree is small.

  An object of the present invention is to solve the above-described problems and provide a semiconductor device capable of preventing electric field concentration around a dynamic clamp circuit and preventing a decrease in breakdown voltage and an increase in leakage current.

  It is another object of the present invention to provide a semiconductor device capable of reducing the area occupied by the breakdown voltage structure, increasing the degree of freedom of the location where the dynamic clamp circuit is formed, and forming the dynamic clamp circuit without increasing the cost.

To achieve the above object, according to the first aspect of the present invention, the drift layer of the first conductivity type and the second conductivity type selectively formed on the surface of the drift layer are provided. A base power region, a vertical power semiconductor element having a first conductivity type emitter region selectively formed on the surface of the base region on the first main surface, and insulation on the first main surface of the power semiconductor element A plurality of loop-shaped constant voltages that are formed between the first electrode and the gate electrode that are connected to the first main surface side of the drift layer and decrease toward the center first electrode. includes a dynamic clamping diode made of polysilicon formed by a series connection of a diode, the dynamic clamping diode is arranged on the inner region of the pressure-resistant structure that surrounds the outer periphery of the vertical power semiconductor device, the Dyna Click stopper layer penetrates the drift layer immediately below the one end suppressing extension of the depletion layer of the clamping diode is arranged, it is low clamp voltage of the dynamic clamp diode as compared to the breakdown voltage of the vertical power semiconductor device, wherein The semiconductor device has a configuration in which the drift layer directly below the one end connected to the first electrode of the dynamic clamp diode is not depleted with a clamp voltage .

According to the invention described in claim 2 of the claims, in the invention described in claim 1 , the stopper layer may have the same conductivity type as the drift layer and a high concentration.
According to the invention described in claim 3 of the claims, in the invention described in claim 1 , the stopper layer includes a trench, and a polysilicon doped with a high-concentration impurity filling the trench. The insulating layer surrounding the trench or the impurity layer having the same conductivity type as the drift layer surrounding the trench may be provided.

According to the invention described in claim 4 of the claims, in the invention described in any one of claims 1 to 3 , the planar shape of the dynamic clamp diode may be circular or rectangular.

According to the invention described in claim 5 , the gate pad of the vertical power semiconductor element or the gate pad of the vertical power semiconductor element on the dynamic clamp diode in the invention described in any one of claims 1 to 4. The emitter pad may be disposed via an insulating film.

According to the invention described in claim 6 of the claims, in the invention described in any one of claims 1 to 5 , the withstand voltage of the dynamic clamp diode is preferably 100 V or more.

According to the invention described in claim 7 , the vertical power semiconductor element is an IGBT (insulated gate bipolar transistor) in the invention described in any one of claims 1-6. Alternatively, it may be a power MOSFET (MOS type field effect transistor).

  According to the present invention, by disposing the dynamic clamp circuit in a region different from the withstand voltage structure, the dynamic clamp circuit does not exist on the withstand voltage structure. An increase in leakage current can be prevented.

  Moreover, since the dynamic clamp diode acts as a field plate having a potential gradient immediately below the dynamic clamp circuit, electric field concentration hardly occurs and a stable breakdown voltage can be obtained.

  In addition, a plurality of dynamic clamp diodes are stacked with an insulating film in between, and the dynamic clamp circuit is not formed on the breakdown voltage structure, so that the dynamic clamp circuit can be reduced and the width of the breakdown voltage structure can be further reduced. it can. As a result, the manufacturing cost can be reduced.

  In addition, the degree of freedom of the location where the dynamic clamp circuit is formed can be expanded, and the dynamic clamp circuit can be formed without increasing the cost.

1 is a plan view of an essential part of a semiconductor device 100 according to a first embodiment of the present invention; It is principal part sectional drawing cut | disconnected by the XX line of FIG. It is the figure which showed the breadth of a depletion layer when a collector voltage reaches | attains a clamp voltage. It is a principal part top view of the semiconductor device 200 concerning 2nd Example of this invention. It is a principal part top view of the semiconductor device 300 concerning 3rd Example of this invention. It is principal part sectional drawing cut | disconnected by the XX line of FIG. It is a principal part top view of the semiconductor device 400 concerning 4th Example of this invention. It is principal part sectional drawing cut | disconnected by the XX line of FIG. It is a principal part top view of the semiconductor device 500 concerning 5th Example of this invention. It is a principal part block diagram of the ignition system using the semiconductor device which incorporated the dynamic clamp circuit. It is a principal part top view of the semiconductor device incorporating the conventional dynamic clamp circuit. It is principal part sectional drawing cut | disconnected by the XX line of FIG.

Embodiments will be described in the following examples.
<Example 1>
1 and 2 are configuration diagrams of a semiconductor device 100 according to a first embodiment of the present invention, in which FIG. 1 is a plan view of the main part, and FIG. 2 is a cross-sectional view of the main part taken along line XX in FIG. It is. 1 and 2, the same parts as those in FIGS. 11 and 12 are denoted by the same reference numerals.

The semiconductor device 100 includes a p ⁺ substrate 25, an n ⁺ buffer layer 26 disposed on the p ⁺ substrate, and an n ⁻ drift layer 27 disposed on the n ⁺ buffer layer 26. A p base region 28, a p ⁺ diffusion region 32 a, and an n ⁺ diffusion region 36 are provided selectively on the n ⁻ drift layer 27. An n ⁺ emitter region 29 disposed in the surface layer of the p base region 28, and a p base region 28 sandwiched between the n ⁺ emitter region 29 and the n ⁻ drift layer 27 via the gate oxide film 30. And a gate electrode 31 formed of polysilicon.

Insulating film 33 disposed on gate electrode 31 and n ⁻ drift layer 27, polysilicon layer 31 a disposed on insulating film 33 and connected to gate electrode 31, and alternately disposed on this polysilicon layer 31 a Dynamic clamp diode constituting a dynamic clamp circuit composed of an n layer 40 (40-1, 40-2, 40-3,...) And a p layer 41 (41-1, 41-2,...) 24a. Reference numerals 40 and 41 are generic numbers, and 40-1, 40-2, 40-3,..., 41-1, 41-2,.

The breakdown voltage structure 20 disposed between the n ⁺ diffusion region 36 and the p ⁺ diffusion region 32a, the interlayer insulating film 34 disposed on the polysilicon layer 31a and the gate electrode 31, and the interlayer insulating film 34. And an emitter Al electrode 23 a electrically connected to the n ⁺ emitter region 29 and the p base region 28. An Al electrode 37a electrically connected to the n ⁺ diffusion region 36a and a gate Al electrode 35 connected to the polysilicon layer 31a are provided. Gate electrode pad 22 in which gate Al electrode 35 is exposed from the opening of passivation film 42, emitter electrode pad 23 in which emitter Al electrode 23a is exposed from passivation film 42, and collector electrode 38 disposed on the surface of p ⁺ substrate 25 With.

1 and FIG. 2 is different from FIGS. 11 and 12 in that the dynamic clamp diode 24a is not on a part of the breakdown voltage structure 20, but in a p ⁺ diffusion region 32a formed in a ring shape separately from the breakdown voltage structure 20. This is that the insulating film 33 is formed on the surrounded n ⁻ drift region 27. The active region 21 in which the IGBT cell is formed and the gate pad 22 and the emitter pad 23 for wire bonding are provided in the region surrounded by the breakdown voltage structure 20 as in FIGS. is there.

Collector voltage of the IGBT2 includes a ^{p +} substrate 25, an ^{n +} buffer layer 26, n ^- drift layer 27, is applied to the Al electrode 37a through ^{the n +} diffusion region 36a, dynamic clamping diodes connected to the ^{n +} diffusion region 36a 24a.

FIG. 3 is a diagram showing the spread of the depletion layer when the collector voltage reaches the clamp voltage. As shown in FIG. 3, even if the collector voltage reaches the clamp voltage, the depletion layer 43 does not spread to the n ⁻ drift layer 27 immediately below the n ⁺ diffusion region 36a. In this figure is depicted as a depletion layer end it does not reach the n ⁺ buffer layer 26 n ^- drift layer 27 density and thickness, in some cases reaching depending on the value of the clamp voltage.

A p ⁺ region 32a is formed on the surface of n ⁻ drift layer 27 below the outermost periphery of dynamic clamp diode 24a. In Figure 2, the ^{p +} region 32a overlaps the ^{p +} region 32a is arranged at the end of the pressure-resistant structure 20. A gate Al electrode 35 is formed on a part of the dynamic clamp diode 24 a via an interlayer insulating film 34. An opening is provided in the passivation film 42 formed on the gate Al electrode 35 as the gate pad 22. Yes.

  Thus, by forming a part of the dynamic clamp diode 24a under the gate pad 22, the area efficiency can be increased. However, in this case, when the collector potential rises, the potential in the vicinity of the center of the dynamic clamp diode 24a becomes higher than the gate potential. Therefore, it is necessary to secure a sufficient breakdown voltage in consideration of the thickness and film quality of the interlayer insulating film.

  Further, when two-layer wiring such as providing the gate pad 22 via the interlayer insulating film 34 on the electrode Al, the size of the gate pad 22 can be made sufficiently large, so that the entire dynamic clamp diode 24a is directly under the gate pad 22. Can be formed. Further, the dynamic clamp diode 24a is not necessarily formed under the gate pad 22, and may be provided at an arbitrary location in the active region 21. However, no cell is formed there.

  That is, since the location where the dynamic clamp diode 24a is formed can be selected from any location other than the withstand voltage region 20, the degree of freedom in selecting the location is improved. For example, when it is formed at the center of the chip, the gate voltage rise due to dynamic clamping is less affected by the gate wiring resistance than when it is at the end, and it has the advantage that it is given evenly to the entire chip (the gate polysilicon has Since there is a wiring resistance, the gate voltage near the connection point between the dynamic clamp diode and the gate electrode rises first, and the rise in the gate voltage at a remote location is delayed, so that the current is concentrated near the chip. By placing the dynamic clamp diode in the center, the difference in distance is reduced and it can be turned on relatively uniformly.)

  In the semiconductor device 100, the vertical power semiconductor element is described by taking the IGBT 2 as an example, but it may be a power MOSFET. In an ignition system using a semiconductor device incorporating a dynamic clamp circuit, the breakdown voltage (clamp voltage) of the dynamic clamp diode 24a is preferably 100 V or more.

Alternatively, the dynamic clamp diode 24a configured by repeating the n region 40 and the p region 41 may be short-circuited with a conductive film every other pn junction composed of the n region 40 and the p region 41. In this case, the configuration is the same as that of the dynamic clamp diodes 6 and 7 in FIG. 10 in which pn diodes are connected in series.
<Example 2>
FIG. 4 is a plan view of an essential part of a semiconductor device 200 according to the second embodiment of the present invention. The difference from FIG. 1 is that the dynamic clamp diode 24b is not concentric but rectangular, and a part of the dynamic clamp diode 24b is formed under the emitter pad 23.

  This is applicable when no active region cell is formed under the emitter pad 23. In addition, the dynamic clamp diode 24b may be oval or the like, and the distance between the emitter pad 23 and the gate pad 22 is reduced so that a part of the dynamic clamp diode 24b is below the emitter pad 23 and the remaining one is below the gate pad 22. It goes without saying that the portion can be formed.

  In the first and second embodiments, the dynamic clamping diodes 24a and 24b do not exist on the breakdown voltage structure 20, so that there is no portion where electric field concentration occurs. Therefore, there is no concern about a decrease in breakdown voltage or an increase in leakage current.

Further, immediately below the dynamic clamp diodes 24a and 24b, it acts as a field plate having a potential gradient, so that electric field concentration hardly occurs and a stable breakdown voltage can be obtained.
Furthermore, since the dynamic clamp diodes 24a and 24b are not formed in the breakdown voltage structure 20, the width of the breakdown voltage structure 20 can be designed to be narrow. As a result, the chip size can be reduced and the manufacturing cost can be reduced.
<Example 3>
5 and 6 are configuration diagrams of a semiconductor device 300 according to the third embodiment of the present invention. FIG. 5 is a plan view of the main part, and FIG. 6 is a cross-sectional view of the main part taken along line XX in FIG. It is. The difference between the semiconductor device 300 and the semiconductor device 100 of the first embodiment is that the dynamic clamp diode 24a is finely processed to be a small dynamic clamp diode 24c, and a stopper layer reaching the n ⁺ buffer layer 24 at the center. 44 is provided. The stopper layer 44 is formed of a high concentration n diffusion layer 44a. By providing this stopper layer 44,
When the collector voltage reaches the clamp voltage, the depletion layer 43 extending from the left and right is prevented from being connected and pinched off at the center. Since the depletion layer 43 is prevented from being pinched off, the collector voltage is transmitted to the dynamic clamp diode 24c without a voltage drop, and the collector voltage is effectively suppressed by the clamp voltage.
<Example 4>
7 and 8 are configuration diagrams of a semiconductor device 400 according to the fourth embodiment of the present invention. FIG. 7 is a plan view of the main part, and FIG. 8 is a cross-sectional view of the main part taken along line XX in FIG. It is. The difference between the semiconductor device 400 and the semiconductor device 100 of the first embodiment is that the dynamic clamp diode 24a is a small dynamic clamp diode 24d arranged in two layers and reaches the n ⁺ buffer layer 26 in the center. The stopper layer 44 is provided.

The first-layer dynamic clamp diode 24d-1 and the second-layer dynamic clamp diode 24d-2 are formed with the same specifications, and are connected by an Al electrode 46 with the interlayer insulating film 34 interposed therebetween. The central portion of the second-layer dynamic clamp diode 24d-2 is connected to the gate pad. In this case, the same effect as in the fourth embodiment can be obtained. However, in this case, since the potential of the polysilicon layer 31a above the p ⁺ diffusion region 32a is high and the depletion layer is difficult to extend, it is necessary to devise measures such as increasing the thickness of the field oxide film 33.
<Example 5>
FIG. 9 is a plan view of an essential part of a semiconductor device 500 according to the fifth embodiment of the present invention. The difference between the semiconductor device 500 and the semiconductor device 400 of the fourth embodiment is that the stopper layer 44 reaching the n ⁺ buffer layer 26 has a trench 47, a high-concentration n diffusion layer 48 around the trench 47, and a trench 47. The point is that it is made of polysilicon 49 to be filled. The polysilicon 49 is preferably filled simultaneously with the formation of the polysilicon layer 31a. Further, an insulating layer may be disposed in place of the high-concentration n diffusion layer 48. In the case of Example 5, the same effect as that of Example 4 can be obtained. Needless to say, the stopper layer of Example 5 can also be applied to the stopper layer 44 of Example 3 or Example 4.

It is as follows when the said Examples 1-5 are put together.
1) By disposing the dynamic clamp circuit in a region different from the breakdown voltage structure, the dynamic clamp circuit does not exist on the breakdown voltage structure, so that there is no location where electric field concentration occurs, the breakdown voltage decreases, and the leakage current increases. Etc. can be prevented.
2) Immediately below the dynamic clamp circuit, the dynamic clamp diode acts as a field plate having a potential gradient, so that electric field concentration hardly occurs and a stable breakdown voltage can be obtained.
3) By stacking a plurality of dynamic clamp diodes with an insulating film interposed therebetween and not forming a dynamic clamp circuit on the breakdown voltage structure, the dynamic clamp circuit can be reduced, and the width of the breakdown voltage structure can be further reduced. it can. As a result, the manufacturing cost can be reduced.
4) The degree of freedom of the location where the dynamic clamp circuit is formed can be expanded, and the dynamic clamp circuit can be formed without increasing the cost.

1,100,200,300,400,500 Semiconductor device 2 IGBT
DESCRIPTION OF SYMBOLS 3 Collector terminal 4 Gate electrode 5 Emitter terminal 6 Constant voltage diode 7 Backflow prevention diode 8 Gate terminal 9 Gate resistance 10, 11 Gate protection diode 12 Drive circuit 13 Battery 14 Ignition coil 15 Spark plug 16 On-time false ignition prevention diode 20 Withstand voltage Structure 21 Active region 22 Gate pad 23 Emitter pad 23a Emitter Al electrode 24, 24a Dynamic clamp diode 25 p ⁺ Substrate 26 n ⁺ Buffer layer 27 n ^- Drift layer 28 p Base region 29 n ⁺ Emitter region 30 Gate oxide film 31 Gate electrode 31a polysilicon layer 32, 32a p ⁺ diffusion region 33 field oxide film 34, 45 interlayer insulating film 35 the gate Al electrode 36, 36a n ⁺ diffusion regions 37, 37a, 46 Al electrode 0 n region (collectively)
40-1, 40-2.40-3, ... n region (individual)
41 p region (generic name)
41-1, 41-2, ... p region (individual)
42 Passivation film 43 Depletion layer 44 Stopper layer 47 Trench 48 High-concentration n diffusion layer 49 Polysilicon

Claims (7)

A first conductivity type drift layer; a second conductivity type base region selectively formed on a surface of the drift layer; and a first conductivity type emitter region selectively formed on a surface of the base region. A vertical power semiconductor element having a first main surface, a first electrode formed on the first main surface of the power semiconductor element via an insulating layer and connected to the first main surface side of the drift layer, and a gate A dynamic clamp diode made of polysilicon composed of a series connection of a plurality of loop-shaped constant voltage diodes connected between the electrodes and becoming smaller toward the first electrode at the center. disposed on the inner region of the pressure-resistant structure that surrounds the outer peripheral portion of the mold power semiconductor element, and through said drift layer directly below an end of the dynamic clamping diodes suppressing extension of the depletion layer The stopper layer is arranged, the vertical power semiconductor device lower in the clamp voltage of the dynamic clamp diode as compared to the breakdown voltage of, said clamp voltage just below the one end connected to said first electrode of said dynamic clamping diode The semiconductor device, wherein the drift layer is not depleted . The semiconductor device according to claim 1 , wherein the stopper layer has the same conductivity type as the drift layer and a high concentration. The stopper layer includes a trench, polysilicon doped with a high-concentration impurity filling the trench, and an insulating layer surrounding the trench or a high-concentration impurity layer surrounding the trench and having the same conductivity type as the drift layer. The semiconductor device according to claim 1 . The semiconductor device according to any one of claims 1 to 3, the planar shape of the dynamic clamping diode characterized in that it is a round or rectangular. The semiconductor device according to any one of claims 1 to 4, a gate pad or emitter pad is characterized in that it is arranged through the insulating layer of the vertical power semiconductor element to the dynamic clamping diodes on. The semiconductor device according to any one of claims 1 to 5, the breakdown voltage of the dynamic clamp diode is characterized in that more than 100 V. The vertical power semiconductor element, IGBT semiconductor device according to any one of claims 1 to 6, characterized in that a (insulated gate bipolar transistor) or a power MOSFET (MOS field effect transistor).