JP6012743B2 - Silicon carbide semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a silicon carbide semiconductor device and a method for manufacturing the same, and more particularly to a power semiconductor device using silicon carbide and a method for manufacturing the device.

  In a conventional semiconductor device, particularly a Schottky barrier diode, a high-concentration n-type impurity layer is formed on the surface of an n-type (first conductivity type) semiconductor substrate by ion implantation into a semiconductor layer below the Schottky electrode. As a result, the forward voltage of the device was reduced (for example, Patent Document 1).

  In addition, a proposal has been made to control the forward voltage of a device by forming a high-concentration impurity layer on the surface of a semiconductor substrate by performing the above-described ion implantation through a Schottky electrode (for example, Patent Document 2).

JP 58-12372 (1st page, 4th paragraph, FIG. 4) JP-A-60-192363 (2 pages: Overview, FIG. 2)

  In the semiconductor device as described above, in order to form an n-type impurity layer localized only under the Schottky electrode by ion implantation, a dielectric substrate is previously formed on the semiconductor substrate other than the region where the Schottky electrode is formed. It was necessary to form a body membrane or the like.

  This is because if an impurity layer is formed in an unnecessary part, the substrate damage due to ion implantation cannot be recovered due to the rearrangement of impurities generated when the silicon device is heat-treated, and good characteristics cannot be obtained. is there.

  Since a process for forming and removing such a dielectric film or the like is necessary, there is a problem in that the manufacturing cost is increased.

  Further, as in Patent Document 2, in order to form an n-type impurity layer localized only under the Schottky electrode, when ion implantation is performed through the Schottky electrode, a metal layer for forming the Schottky electrode The film thickness and film quality of the film need to be strictly determined, and there is a problem that the manufacturing cost is further increased.

The present invention has been made to solve the above-described problems, and an impurity layer is formed under the Schottky electrode by a simple method to improve the forward characteristics while suppressing a decrease in breakdown voltage characteristics. An object of the present invention is to provide a silicon carbide semiconductor device and a method for manufacturing the same.

A silicon carbide semiconductor device according to one embodiment of the present invention includes a first conductivity type silicon carbide formed on a first conductivity type silicon carbide semiconductor substrate and having an impurity concentration of 3 × 10 ^{15 to} 3 × 10 ¹⁶ cm ⁻³ . A drift layer, a first conductivity type impurity layer as a first semiconductor layer formed over the entire silicon carbide drift layer, and a shot partially formed on the first conductivity type impurity layer A key electrode; and a second conductivity type termination structure that surrounds the Schottky electrode in plan view and is formed in the upper layer portion of the silicon carbide drift layer, and the impurity concentration of the first conductivity type impurity layer is: the higher than the impurity concentration of the silicon carbide drift layer, the thickness of the first conductive type impurity layer is thinner than the termination structure at 30nm or less, impure amount of the first conductivity type impurity layer, 5 × 10 ¹² this is cm ^-2 or more The features.

A method for manufacturing a silicon carbide semiconductor device according to one embodiment of the present invention includes: (a) a first conductivity type having an impurity concentration of 3 × 10 ^{15 to} 3 × 10 ¹⁶ cm ^{−3 on} a first conductivity type silicon carbide semiconductor substrate; forming a silicon carbide drift layer, (b) throughout the silicon carbide drift layer, the impurity concentration than the silicon carbide drift layer is rather high, as the first semiconductor layer thickness is below 30nm or less A step of forming a first conductivity type impurity layer, and (e) a step of etching a surface layer of the silicon carbide drift layer after the step (b) to form a recess, and (c) the first conductivity type. A step of partially forming a Schottky electrode on the impurity layer; and (d) after the step (e) and before the Schottky electrode formation, around a region where the Schottky electrode is formed , From the silicon carbide drift layer Pure object density is high, the impurity concentration than the first conductivity type impurity layer and forming a termination structure of a second conductivity type have a low, (f) the termination structure, the concave portion in the step (e) characterized Rukoto provided in contact of the bottom surface.

According to this aspect of the present invention can be formed of the first conductivity type impurity layer Schottky electrode lower portion by a simple method without using a mask. Therefore, the forward characteristics can be improved easily while suppressing a decrease in the breakdown voltage characteristics of the silicon carbide semiconductor device.

In particular, according to the method for manufacturing the silicon carbide semiconductor apparatus according to an aspect of the present invention can be formed of the first conductivity type impurity layer Schottky electrode lower portion by a simple method without using a mask. Therefore, the forward characteristics can be improved easily while suppressing a decrease in the breakdown voltage characteristics of the silicon carbide semiconductor device.

  The objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description and the accompanying drawings.

It is sectional drawing which shows the structure of SiC-SBD regarding embodiment of this invention. It is sectional drawing which shows the manufacturing process of SiC-SBD regarding embodiment of this invention. It is sectional drawing which shows the manufacturing process of SiC-SBD regarding embodiment of this invention. It is sectional drawing which shows the manufacturing process of SiC-SBD regarding embodiment of this invention. It is a figure which shows the density | concentration profile of an n + type impurity layer. It is a figure which shows the example of calculation of the implantation profile of an n + type impurity layer. It is the figure which showed the characteristic change by the formation conditions of an n + type impurity layer. It is sectional drawing which shows the structure of SiC-SBD regarding embodiment of this invention. It is a figure which shows the change of the barrier height of an n + type impurity layer. It is sectional drawing which shows the structure of the JBS diode regarding embodiment of this invention. It is sectional drawing which shows the structure of the JBS diode regarding embodiment of this invention. It is sectional drawing which shows the structure of SiC-SBD regarding embodiment of this invention. It is a figure which shows the implantation profile of an n + type impurity layer. It is a top view which shows the structure of the JBS diode regarding embodiment of this invention. It is a top view which shows the structure of the JBS diode regarding embodiment of this invention. It is a top view which shows the structure of the JBS diode regarding embodiment of this invention. It is sectional drawing which shows the structure of the JBS diode regarding embodiment of this invention. It is sectional drawing which shows the structure of the JBS diode regarding embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

<First Embodiment>
<Configuration>
FIG. 1 is a cross-sectional view showing a configuration of a silicon carbide semiconductor device according to the first embodiment of the present invention. However, in this embodiment, SiC-SBD (Shotkey Barrier Diode) is used as the silicon carbide semiconductor device.

  As shown in FIG. 1, the SiC-SBD has a polytype of 4H, for example, a silicon carbide substrate 3 containing n-type impurities at a relatively high concentration (n +), and formed on the silicon carbide substrate 3, for example, An n-type semiconductor layer 2 which is a drift layer containing an n-type impurity having a thickness of 4 to 30 μm at a relatively low concentration (n−), and an n-type impurity formed over the entire surface of the n-type semiconductor layer 2 An extremely thin n + type impurity layer 4 (first semiconductor layer) contained in a relatively high concentration (n +), and a termination structure 5 containing p type impurities partially formed in the upper layer part of the n type semiconductor layer 2 An anode electrode 1 (Schottky electrode) formed on the n + -type impurity layer 4 so that the end is located in a region corresponding to the termination structure 5, that is, surrounded by the termination structure 5 in a plan view. Is provided. The termination structure 5 is formed so as to be covered with the n + type impurity layer 4. Although a thin n layer is present immediately above the termination structure 5, it functions as a termination structure by sufficiently overlapping the termination structure 5 with the anode electrode 1.

  Further, an ohmic electrode (not shown) covered with a metal silicide film such as nickel silicide is formed on the back surface of the silicon carbide substrate 3 opposite to the side where the anode electrode 1 is disposed. The metal silicide film is covered with a metallized film suitable for solder bonding, and the metal silicide film and the metallized film constitute a cathode electrode.

<Manufacturing method>
Next, the manufacturing method of SiC-SBD is demonstrated, referring FIGS. 2-4 is a figure which shows the manufacturing process of SiC-SBD of this embodiment.

A silicon carbide substrate 3 having a specific resistance of 15 to 25 mΩcm is prepared, and an n-type semiconductor layer 2 is formed on the main surface of the silicon carbide substrate 3 by, for example, epitaxial crystal growth using a CVD method. Here, it is desirable to introduce phosphorus (P) or nitrogen (N) as an n-type impurity at a concentration of 3 × 10 ^{15 to} 3 × 10 ¹⁶ cm ^{−3 into} the n-type semiconductor layer 2 (FIG. 2). reference).

  Next, the n + type impurity layer 4 is formed over the entire surface of the n type semiconductor layer 2 by nitrogen ion implantation. For example, nitrogen ions are obliquely implanted with an acceleration energy of 10 keV and a tilt angle of 60 °, at least 30 ° or more from the <11-20> direction (see FIG. 3). In this way, an extremely thin n + type impurity layer 4 can be formed.

  In order to form the annular termination structure 5 disposed so as to surround the anode electrode 1 in a later step in the upper layer portion of the n-type semiconductor layer 2, an implantation mask (not shown) corresponding to the formation region becomes an opening. ) Is formed on the n + -type impurity layer 4.

Thereafter, ion implantation of a p-type impurity such as aluminum (Al) is performed from above the formed implantation mask to form a termination structure 5 over the n + -type impurity layer 4 (see FIG. 4). The termination structure 5 is formed in a ring shape in the upper layer portion of the n-type semiconductor layer 2. The termination structure 5 may use a floating guard ring or the like in addition to a single layer. For example, the termination structure 5 is a non-uniformly spaced floating guard ring having a minimum interval of 1 μm and an ion implantation condition such that the concentration is 2 × 10 ¹³ cm ^−2. Can be set.

  Next, after removing the implantation mask (not shown), prior to the activation annealing of the implanted impurities, a graphite film having a thickness of less than 1 μm is formed on the entire silicon carbide substrate 3 on which the n-type semiconductor layer 2 is formed. It is formed on the surface by a low pressure CVD (Chemical Vapor Deposition) method (not shown).

  After the formation of the graphite film, activation annealing at about 1700 ° C. is performed on the silicon carbide substrate 3 in an argon atmosphere, thereby completing the n + -type impurity layer 4 and the termination structure 5 made of a p-type semiconductor. Here, the surface protection by the graphite film was carried out, but other means can be used as long as the technology prevents the surface roughness.

  Next, after removing the graphite film, the entire surface of the silicon carbide substrate 3 on which the n-type semiconductor layer 2 is formed is thermally oxidized in an oxygen atmosphere to form a sacrificial oxide film (not shown). This sacrificial oxide film is a film for modifying the surface altered layer of the silicon carbide layer generated by activation annealing or the like into an oxide film and finally removing it. By removing the sacrificial oxide film, a silicon carbide layer surface that becomes a stable Schottky interface can be obtained. Here, a 17 nm dry oxide film is formed.

  Next, in order to form an ohmic electrode, after removing the surface of the back surface of the silicon carbide substrate 3 by machining, a Ni film having a thickness of 50 to 200 nm is formed. Thereafter, annealing is performed, and the Ni film in contact with the silicon carbide layer is silicided to form a Ni silicide film.

  Next, after the sacrificial oxide film remaining on the main surface of the silicon carbide substrate 3 is removed with a hydrofluoric acid solution, a Schottky such as titanium, nickel, platinum, or molybdenum having a thickness of 100 to 500 nm is formed on the entire main surface by sputtering. The anode electrode 1 is formed by forming a metal and performing etching so that the film remains on the region inside the termination structure 5.

  Although illustration is omitted, after the anode electrode 1 and the cathode electrode are formed, a wiring layer made of Al, Cu or the like is formed to protect the wiring layer and the surface of the p-type termination structure 5. For example, a polyimide resin layer is formed.

  Further, by forming a metallized film composed of a Ti / Ni / Au laminated film on the Ni silicide film on the back surface of the silicon carbide substrate 3, a cathode electrode can be formed of the metal silicide film and the metallized film. .

Here, the concentration profile of the manufactured n + -type impurity layer 4 is shown in FIG. In FIG. 5, the vertical axis represents n concentration (cm ⁻³ ) and the horizontal axis represents depth (nm).

As shown in FIG. 5, it is known that the outermost surface concentration cannot be directly read due to the overlap of impurities, but is about 5 × ¹⁸ cm ^{−3 when} interpolated from data before sacrificial oxidation. In order to obtain such a concentration profile, when the n + -type impurity layer 4 is formed (at the time of ion implantation), the implantation depth is determined in consideration of the thickness removed as a sacrificial oxide film in a later step. There is a need. In other words, it is necessary to perform ion implantation in a region deeper than the depth that is removed by removing the sacrificial oxide film.

  FIG. 6 shows a calculation example of the implantation profile of the n + -type impurity layer 4. In FIG. 6, the vertical axis represents the injection amount (au), and the horizontal axis represents the depth (μm). Note that the depth (μm) in FIG. 6 indicates the depth of the n + -type impurity layer 4 after etching by sacrificial oxidation.

For example, in order to form an ultrathin n + type impurity layer 4 of 30 nm or less in the upper layer part of the n-type semiconductor layer 2, it is desirable to perform ion implantation with an acceleration energy of 20 keV or less. That is, in consideration of the sacrificial oxidation component, for example, ions of 1 × 10 ¹⁸ cm ⁻³ or more are implanted at a depth of, for example, 15 to 25 nm, and the sacrificial oxide film is removed to etch the outermost surface by about 10 nm. It is desirable. Note that although a monovalent example of N + is shown here, a thinner layer can be formed with N2 +.

  The SiC-SBD fabricated in this way has a barrier height (ΦB) that is reduced by 0.1 eV or more compared to a device that does not form the n + -type impurity layer 4, and the forward voltage is reduced accordingly. confirmed. The reverse current was also confirmed to increase by almost two orders of magnitude at the rated voltage as the barrier height was reduced.

FIG. 7 is a diagram showing a change in characteristics depending on the formation conditions of the n + -type impurity layer 4. In FIG. 7, the vertical axis represents the change in barrier height (eV), and the horizontal axis represents the remaining dose amount (cm ⁻² ). Note that the remaining dose amount (cm ⁻² ) in FIG. 7 is an implantation amount of ions remaining as the n + -type impurity layer 4 after etching by sacrificial oxidation.

As shown in FIG. 7, the barrier height monotonously decreases as the ion implantation amount is increased and the residual dose amount is increased. Therefore, it can be seen that the controllability of the barrier height by ion implantation is good. In general, significant characteristics can be obtained by forming an n + type semiconductor of 5 × 10 ¹² cm ⁻² or more.

FIG. 13 shows an example of a depth profile when the manufacturing conditions of the n + -type impurity layer 4 are changed. The vertical axis represents the concentration (unit: cm ⁻³ ), and the horizontal axis represents the depth (nm).

  The barrier height can be reduced under each condition. Under conditions 1 and 2, the ideality coefficient (a value that becomes 1 when matched with the theoretical model and increases with a deteriorated diode, preferably less than 1.1) is approximately 1.0, and does not present a problem in the diode characteristics. It was. On the other hand, under the conditions of the comparative example, the ideal coefficients were as large as 1.1 and 1.2, and good diode characteristics could not be obtained.

  From the above, it can be seen that the n + type impurity layer 4 having a thickness of 30 nm or more cannot be applied. In general, it is expected that the breakdown voltage characteristic cannot be obtained when n + is formed on the outermost surface. However, there is no significant difference in the reverse direction characteristics of these elements, and in the sufficiently thin n + type impurity layer 4, the reverse direction characteristics are not observed. It seems that the film thickness is controlled by the forward characteristics.

  According to the SiC-SBD type diode described above, the forward characteristics can be improved by adding only the ion implantation step.

<Effect>
According to the embodiment of the present invention, a silicon carbide semiconductor device is formed on a silicon carbide substrate 3 as a first conductivity type (n-type) silicon carbide semiconductor substrate, and the first conductivity type (n-type) carbonization. An n-type semiconductor layer 2 as a silicon drift layer, an n + -type impurity layer 4 as a first conductivity type impurity layer formed over the entire n-type semiconductor layer 2, and partially on the n + -type impurity layer 4 And an anode electrode 1 as a Schottky electrode. Here, the impurity concentration of the n + -type impurity layer 4 is higher than the impurity concentration of the n-type semiconductor layer 2.

According to such a configuration, the n + -type impurity layer 4 can be formed below the anode electrode 1 by a simple method without using a mask. Therefore, the forward characteristics can be improved easily while suppressing a decrease in the breakdown voltage characteristics of the silicon carbide semiconductor device.

  According to the embodiment of the present invention, a method for manufacturing a silicon carbide semiconductor device includes: (a) a first conductivity type (n-type) n-type on a first conductivity type (n-type) silicon carbide substrate 3; A step of epitaxially growing the semiconductor layer 2, (b) a step of forming an n + type impurity layer 4 having an impurity concentration higher than that of the n type semiconductor layer 2 over the entire n type semiconductor layer 2, and (c) an n + type impurity. A step of partially forming the anode electrode 1 on the layer 4.

According to such a configuration, in the step of forming the n + -type impurity layer 4, it is not necessary to perform ion implantation using a mask, and it is possible to proceed while suppressing a decrease in breakdown voltage characteristics of the silicon carbide semiconductor device by a simpler method. Directional characteristics can be improved. In addition, since it is not necessary to add a process using a mask, manufacturing at a lower cost is possible. Here, molybdenum is used for the Schottky metal to be the anode electrode 1, but it has been confirmed that other materials such as titanium and nickel have the same effect.

Second Embodiment
<Configuration>
In the first embodiment, the n + -type impurity layer is formed by an ion implantation method, but it can also be formed by an epitaxial crystal growth method.

  FIG. 8 is a cross-sectional view showing a configuration of a silicon carbide semiconductor device (SiC-SBD) according to this embodiment of the present invention. The n + type impurity layer 4A in FIG. 8 is formed by an epitaxial crystal growth method. In addition, about the structure similar to FIG. 1, the same code | symbol is attached | subjected and detailed description is abbreviate | omitted. The configuration different from that in FIG. 1 will be described below.

  As shown in FIG. 8, SiC-SBD includes silicon carbide substrate 3, n-type semiconductor layer 2 formed on silicon carbide substrate 3, and n + -type impurities partially formed on the surface of n-type semiconductor layer 2. The layer 4A, the termination structure 5 partially formed in the upper layer portion of the n-type semiconductor layer 2, and the n + -type impurity layer 4A so that the end portion is located in a region corresponding to the termination structure 5, that is, the plane The anode electrode 1 is formed so as to be surrounded by the visual termination structure 5.

  When the n + concentration for forming the n + type impurity layer 4A is high and the film thickness of the n + type impurity layer 4A is large, the region where the termination structure 5 is formed is etched to suppress the leakage current in the in-plane direction. It is desirable to do. In this case, after forming the n + -type impurity layer 4A, a resist pattern having an opening corresponding to the termination structure 5 is formed on the n + -type impurity layer 4A (not shown). After etching the portion, p-type impurity implantation for forming the termination structure 5 is performed on the groove formed by the etching.

  In this etching process, it is not necessary to completely etch the n + -type impurity layer 4A, and conversely, the n + -type impurity layer 4A may be etched sufficiently deep as long as the characteristics of the termination structure 5 are not affected. Thereafter, after activation annealing and sacrificial oxidation, metal wiring is formed.

The change in barrier height at a film thickness of 20 nm of the n + -type impurity layer 4A when the flow rate of nitrogen is changed and the n + concentration is changed while the flow rates of silane (silicon hydride) and propane are fixed. 9 shows. In FIG. 9, the vertical axis represents the change in barrier height (eV), and the horizontal axis represents the concentration (cm ⁻³ ). FIG. 9 shows the state of the n + type impurity layer 4A after the sacrificial oxide film is removed.

Although it is considered that the characteristics vary due to short-time CVD growth on a thin film, it was confirmed that the barrier height was reduced at high concentration (high nitrogen flow rate). In general, it can be seen that significant characteristics can be obtained by forming an n + type semiconductor of 5 × 10 ¹⁸ cm ⁻³ .

  According to this configuration, the device can be easily manufactured by forming the n + -type impurity layer 4A on the silicon carbide substrate 3 by the epitaxial crystal growth method followed by the formation of the n + -type impurity layer 4A.

<Effect>
According to the embodiment of the present invention, the method includes the step of forming the n + -type impurity layer 4A as the first conductivity type impurity layer by epitaxial growth.

  According to such a configuration, an ultrathin n + type impurity layer 4A can be formed.

<Third Embodiment>
<Configuration>
In the first embodiment, the configuration of the SiC-SBD has been described, but the present invention may be applied to a JBS diode (Junction Barrier Controlled. Schottky Diode) as shown in FIG. 10 in order to reduce the reverse current. . FIG. 10 is a cross-sectional view showing a configuration of a silicon carbide semiconductor device (JBS diode) according to this embodiment of the present invention.

  As shown in FIG. 10, the JBS diode includes a silicon carbide substrate 3, an n-type semiconductor layer 2 formed on silicon carbide substrate 3, and an n + -type impurity layer 4 formed on the entire surface of n-type semiconductor layer 2. A termination structure 5 partially formed in the upper layer part of the n-type semiconductor layer 2 and an anode electrode 1 formed so that the end part is located in a region corresponding to the termination structure 5 via the n + -type impurity layer 4 And a plurality of p-type impurity layers 6 as second conductivity type impurity layers formed in a region corresponding to the region where the anode electrode 1 is located in the upper layer portion of the n-type semiconductor layer 2 below the n + -type impurity layer 4. Prepare. Even when the n + -type impurity layer 4 is left on the entire surface of the n-type semiconductor layer 2, a normal value of the reverse current of the JBS diode can be obtained.

  FIGS. 14 and 15 are plan views of the diode in which the n + type impurity layer 4 is further removed from the upper structure.

  The p-type impurity layer 6 is formed in a stripe shape or a dot shape. The maximum spacing of the p-type impurity layer 6 is not locally increased so that the electric field in the vicinity of the n + -type impurity layer 4 can be reduced by a depletion layer extending from the p-type impurity layer 6 when a reverse voltage is applied. Is desirable.

  Since the depletion layer from the p-type impurity layer 6 extends and is connected to the n layer, it is necessary that the n layer that is not depleted does not exist in plan view. Also, as shown in FIG. 16, the p-type impurity layer 6 and the termination structure 5 that also becomes the p-type impurity layer do not need to be in particular contact with each other, and it is possible to open a gap with a stripe interval or less.

In the configuration, in addition to the configuration of the first embodiment, the interval is set to 2 μm, for example, except that the p-type impurity layer 6 having a total dose amount of 4 × 10 ¹³ cm ⁻² is formed with an implantation energy of a maximum of 700 keV, for example. The configuration is the same as that of the first embodiment. The p-type impurity layer 6 is formed in the upper layer portion of the n-type semiconductor layer 2 by ion implantation through the n + -type impurity layer 4 after forming the n + -type impurity layer 4 and before forming the anode electrode 1. The

  In the JBS diode manufactured in this way, a low leakage characteristic of about 4 digits was obtained with respect to a normal SBD.

Even if the distance between the p-type impurity layers 6 is as narrow as about 1 to 1.5 μm when the concentration of the n-type semiconductor layer 2 is as high as 2 to 3 × 10 ¹⁶ cm ⁻³ , Narrowing of the current path can be avoided in the depletion layer. However, if the interval between the p-type impurity layers 6 is increased to 7 to 10 μm, the maximum electric field on the surface of the n + -type impurity layer 4 when the reverse voltage is applied exceeds 2 MVcm ^−1, and the reverse current is not sufficiently suppressed. The distance between the impurity layers 6 is preferably 5 μm or less, and more preferably 3 μm or less.

  By forming the p-type impurity layer 6 at a high concentration at a deep position, it is possible to suppress a reverse current due to a decrease in the maximum electric field on the surface of the n + -type impurity layer 4.

  In a diode having a JBS structure, when an inrush current is applied in the forward direction, a PN diode composed of a p-type impurity layer 6 and an n-type semiconductor 2 existing in the diode is used as a current path, thereby increasing an inrush current withstand capability. There is also a case to let you.

FIG. 17 shows a cross-sectional structure related to such a structure. The outermost surface concentration of the p-type impurity layer 6Y is, for example, 1 × 10 ²⁰ cm ⁻³ or more.

  At this time, the n + -type impurity layer 4Y formed on the outermost surface is effectively divided by the p-type impurity layer 6Y, or a surface oxide film due to a decrease in crystallinity of the high-concentration p-type impurity layer 6Y. Therefore, the n + type impurity layer 4Y disappears and is effectively divided. However, since current does not flow from the anode electrode 1 through the p-type impurity layer 6Y in the operation of the normal Schottky diode, this is not inconsistent with the purpose of the present application, and a low-loss and high-resistance diode can be formed. It is.

  Even in a state where the n + -type impurity layer 4 is formed on the entire surface of the n-type semiconductor layer 2, a JBS diode can be easily produced by a method similar to a normal SiC-JBS production method.

  Further, as shown in FIG. 11, by etching a predetermined portion (region where the p-type impurity layer 6B is formed) of the n + -type impurity layer 4B before forming the p-type impurity layer 6B, a p-type impurity is formed. The layer 6B can be formed in a shape as shown in FIG. 11, and the reverse leakage characteristics can be further improved. FIG. 11 is a cross-sectional view showing a configuration of a silicon carbide semiconductor device (JBS diode) according to this embodiment of the present invention. The etching depth is preferably about 0.1 to 2 μm, for example, and is deep enough to prevent the drift layer from having a sufficient breakdown voltage. The etched shape may have a sub-micron undulation and a sub-trench structure having a “W” cross section. For example, an etching shape having a taper of about 80 ° may be used.

  This structure is the same as that in the MeV implantation described above in that the p-type impurity layer 6B is mainly formed at a deep position from the surface.

  As shown in FIG. 11, the JBS diode includes a silicon carbide substrate 3, an n-type semiconductor layer 2 formed on the silicon carbide substrate 3, and an n + -type impurity layer partially formed on the surface of the n-type semiconductor layer 2. 4B, a termination structure 5B (second semiconductor layer) covered with the n + -type impurity layer 4B and partially formed in the upper layer portion of the n-type semiconductor layer 2, and a termination structure via the n + -type impurity layer 4B In the anode electrode 1 formed so that the end is located in the region corresponding to 5B and the upper layer portion of the n-type semiconductor layer 2 where the n + -type impurity layer 4B is not formed, the region corresponding to the region where the anode electrode 1 is located A plurality of p-type impurity layers 6B (third semiconductor layers).

  For example, a groove (see FIG. 11) having a depth of 0.5 μm is formed in the n + -type impurity layer 4B in the region where the p-type impurity layer 6B is to be formed, also serving as an alignment mark. Then, ions are implanted into the formed groove to form the p-type impurity layer 6B, thereby making it possible to sufficiently reduce leakage with respect to SBD.

  The p-type impurity layer 6B can be formed by implanting p-type ions with the same mask as that used for the etching process after the etching process of the n + -type impurity layer 4B. For example, the n-type impurity layer 6B It may be formed by preparing a new mask having openings each having a width 0.2 μm wider than the hole shape formed in 4B and implanting p-type ions. When a new mask is prepared, a p-type impurity layer 6B having a shape covering the side surface of the n-type semiconductor layer 2 formed by etching as shown in FIG. 11 is obtained. If such a p-type impurity layer 6B is formed, local electric field concentration can be suppressed.

  FIG. 18 shows a structure in which the p-type impurity layer 6X is formed with a mask having the same opening as the hole shape formed in the n + -type impurity layer 4B, and the p-type impurity layer is not substantially formed on the side surface of the groove. It is. Although the electric field value increases at the lower part of the side surface of the groove and in contact with the anode electrode 1, the leakage current is dominated by a region having a sufficiently low barrier height above the n-type semiconductor layer 2. Even if the structure does not form, the same effect is exhibited.

<Effect>
According to the embodiment of the present invention, ions are implanted into a groove formed by etching the n + -type impurity layer 4B as the first conductivity type impurity layer, thereby forming the p-type impurity layer 6B as the second conductivity type impurity layer. Forming a step.

  According to such a configuration, an element having excellent reverse characteristics can be obtained.

<Fourth embodiment>
<Configuration>
In the configuration shown in FIG. 8, the effective ion implantation depth can be increased to optimize the termination structure. FIG. 12 is a cross-sectional view showing a configuration of a silicon carbide semiconductor device (SiC-SBD) according to this embodiment of the present invention.

  As shown in FIG. 12, SiC-SBD includes silicon carbide substrate 3, n-type semiconductor layer 2 formed on silicon carbide substrate 3, and n + -type impurity layer 4C formed on the entire surface of n-type semiconductor layer 2. And a termination structure 5C partially formed in the upper layer portion of the n-type semiconductor layer 2 and an end portion of the termination structure 5C on the n + -type impurity layer 4C corresponding to the termination structure 5C, that is, in plan view And an anode electrode 1 surrounded by the termination structure 5C.

  The n + -type impurity layer 4C is recessed to cover the termination structure 5C at the position where the termination structure 5C is formed.

  The termination structure 5C is a groove structure, and can also serve as an alignment mark in lithography. By having such a termination structure 5C, an element having excellent reverse characteristics can be obtained. In addition, as shown in FIG. 12, it is possible to form the n + -type impurity layer 4C after the termination structure 5C is formed.

  In the above embodiment, the substrate is not rotated when forming the n + type semiconductor by the ion implantation method. However, even if the substrate is rotated, the characteristics are not deteriorated due to channeling and can be manufactured.

<Effect>
According to the embodiment of the present invention, the termination structure 5C is a groove structure.

  According to such a configuration, an element having excellent reverse characteristics can be obtained.

  In the embodiment of the present invention, the material of each component, material, conditions for implementation, and the like are also described, but these are examples and are not limited to those described.

  In addition, within the scope of the present invention, the present invention can be freely combined with each embodiment, modified with any component in each embodiment, or omitted with any component in each embodiment.

  Although the present invention has been described in detail, the above description is illustrative in all aspects, and the present invention is not limited thereto. It is understood that countless variations that are not illustrated can be envisaged without departing from the scope of the present invention.

  1 anode electrode, 2 n-type semiconductor layer, 3 silicon carbide substrate, 4,4A, 4B, 4C, 4Y n + type impurity layer, 5,5B, 5C termination structure, 6,6B, 6X, 6Y p-type impurity layer.

Claims (12)

Formed in the first conductivity type silicon carbide semiconductor base plate, and a silicon carbide drift layer of the first conductivity type impurity concentration of ^{3 × 10 15 ~3 × 10 16} cm -3,
A first conductivity type impurity layer as a first semiconductor layer formed over the entire silicon carbide drift layer;
The partially formed on the first conductive type impurity layer, and the Schottky electrodes,
Enclosing a plan view of the Schottky electrodes, it said formed upper layer portion silicon carbide drift layer, and a termination structure of a second conductivity type,
The impurity concentration of the first conductivity type impurity layer is higher than the impurity concentration of the silicon carbide drift layer ,
The thickness of the first conductivity type impurity layer is thin the termination structure by Ri thickness at 30nm or less,
Impure amount of the first conductivity type impurity layer, characterized in that it is 5 × ¹⁰ 12 ^{cm -2} or more,
Silicon carbide semiconductor device.   Impurity concentration formed on the silicon carbide semiconductor substrate of the first conductivity type is 3 × 10 ¹⁵ ~ 3x10 ¹⁶ cm ^-3 A silicon carbide drift layer of the first conductivity type,
  A first conductivity type impurity layer as a first semiconductor layer provided on the silicon carbide drift layer;
  A Schottky electrode partially formed on the first conductivity type impurity layer;
  A second conductivity type termination structure formed on the silicon carbide drift layer upper layer portion surrounding the Schottky electrode in plan view;
  A recess formed on the surface of the silicon carbide drift layer,
  The impurity concentration of the first conductivity type impurity layer is higher than the impurity concentration of the silicon carbide drift layer,
  The termination structure is provided in contact with the bottom surface of the recess,
  The first conductivity type impurity layer is provided over the entire region of the first conductivity type of the silicon carbide drift layer,
  Silicon carbide semiconductor device.   The first conductivity type impurity layer has a thickness of 30 nm or less,
  The silicon carbide semiconductor device according to claim 2.   The first conductivity type impurity layer is 5 × 10 5. ¹² cm ^-2 It has the above impurities,
  The silicon carbide semiconductor device according to claim 2. And further comprising the formed in stripes or dots on the upper layer portion silicon carbide drift layer, a third semiconductor layer of a second conductivity type of the Schottky collector Gokushita,
The silicon carbide semiconductor device according to claim 2 . The third semiconductor layer has a groove structure,
The silicon carbide semiconductor device according to claim 5 . The outermost surface impurity concentration of the third semiconductor layer is 1 × 10 ²⁰ cm ⁻³ or more,
The silicon carbide semiconductor device according to claim 5 or 6 .   The Schottky electrode is any one of titanium, nickel, platinum, and molybdenum,
  The silicon carbide semiconductor device according to claim 1. (A) a step of impurity concentration in the silicon carbide semiconductor base board of the first conductivity type to form a first conductivity type silicon carbide drift layer of ^{3 × 10 15 ~3 × 10 16} cm -3,
(B) throughout the silicon carbide drift layer, wherein the silicon carbide drift layer by Ri impurity concentration is high, thickness to form a first conductive type impurity layer as a first semiconductor layer which is under 30nm or less Process,
(E) after the step (b), etching the surface layer of the silicon carbide drift layer to form a recess;
(C) on the first conductive type impurity layer, a step of partially forming the Schottky electrodes,
After; (d) step (e), and before the Schottky collector-pole formation, the shot around the region where the key electrode is formed, a high impurity concentration Ri by said silicon carbide drift layer, the first conductivity type impurity layer by Ri impurity concentration and forming a termination structure of a second conductivity type have a low,
(F) the termination structure is characterized Rukoto provided in contact with the bottom surface of the recess in said step (e),
A method for manufacturing a silicon carbide semiconductor device. The step (b) is a step of forming the first conductivity type impurity layer by oblique implantation of ions,
A method for manufacturing a silicon carbide semiconductor device according to claim 9 . The oblique implantation of the ions in the step (b) has a tilt angle of 30 ° or more and an acceleration energy of 20 KeV or less,
A method for manufacturing a silicon carbide semiconductor device according to claim 10 . A step of forming a third semiconductor layer of a second conductivity type in stripes or dots on the silicon carbide drift layer on layer of the Schottky collector Gokushita, by etching the first conductive type impurity layer A third semiconductor layer is formed by ion implantation into the formed groove.
A method for manufacturing a silicon carbide semiconductor device according to claim 9 .

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