JP6009719B2 - Signal transmission circuit and power conversion device including the same - Google Patents

Description

  The present invention relates to a signal transmission circuit that transmits a signal via a transformer, and a power conversion device including the signal transmission circuit.

For example, in an inverter that drives a three-phase AC motor or the like, a conventional signal transmission circuit used in a drive circuit device for a power semiconductor switching element in the inverter is shown below.
A conventional signal transmission circuit includes a transformer having a primary winding and a secondary winding, a drive circuit connected to the upstream side of the primary winding, and a pulse connected to the secondary winding and driven from the secondary winding. And a latch circuit that is connected to the downstream side of the selection circuit and prevents transfer of pulses input under the set conditions. The drive circuit converts each of the input signals into two or more edge signals and transmits them to the primary winding in response to the rising or falling change of the input signal. The selection circuit is composed of two comparators, each of which is assigned a different reference voltage and separates the pulses from the secondary winding according to the assignment. The latch circuit compares the pulses separated by the selection circuit, and when different pulses are generated continuously in a short time, the latch circuit masks the pulses to prevent transfer (for example, Patent Document 1).

US Pat. No. 6,720,816 B2 (FIG. 3, FIG. 4)

  Since the conventional signal transmission circuit is configured as described above, the reliability of signal transmission is improved by transmitting a plurality of edge signals to the primary winding of the transformer in response to changes in the logical value of the input signal. It is increasing. However, since two comparators having different reference voltages are provided on the secondary side of the transformer and two types of signals input to the latch circuit are generated, the circuit configuration can be simplified and the circuit area can be reduced. Has a limit and cost reduction is difficult. Furthermore, if noise occurs in the reference voltage of the comparator, the comparator may malfunction.

  The present invention has been made to solve the above problems, and can transmit signals with high reliability, promotes simplification of the circuit configuration and reduction of the circuit area, and further improves noise resistance. An object of the present invention is to provide an improved low-cost signal transmission circuit and a power conversion device including the same.

The signal transmission circuit according to the present invention includes an insulating transformer having a first coil and a second coil, and the first coil connected to the first coil in response to a change in the logical value of the input first signal. A first circuit that generates and outputs a transmission signal to one end and a second end, and a second signal that is connected to the second coil and that corresponds to the first signal input to the first circuit. And a second circuit for outputting. The transmission signal to the first end and the second end of the first coil is composed of a plurality of pulses generated alternately and continuously for each change in the logical value of the first signal. The second circuit includes a comparator that has two input terminals connected to the first and second ends of the second coil, and compares the voltage signals generated at the first and second ends. An SR latch circuit that receives the signal and the reset signal and outputs the second signal, and the set signal and the reset signal by partially masking the reference set signal and the reference reset signal based on the output signal of the comparator, respectively. The signal generation circuit generates the set signal by masking the reference set signal in a first continuous period set in advance from the timing based on the rising edge of the reset signal, and the signal generation circuit generates the set signal. at a preset second consecutive period from the timing based on the rising edge of the set signal by masking the reference reset signal which generates the reset signal A.

  The power conversion device according to the present invention includes a power semiconductor switching element, a drive circuit that drives the power semiconductor switching element, a control unit that generates a control signal for controlling the power semiconductor switching element, and the signal transmission circuit. The signal transmission circuit is connected between the control unit and the drive circuit, insulates the control unit from the drive circuit, and uses the control signal from the control unit as the first signal. The second signal that is input and generated is output to the drive circuit.

Since the signal transmission circuit according to the present invention is configured as described above, it is possible to transmit signals with high reliability, improve noise resistance, and further reduce the cost by simplifying the circuit configuration and reducing the circuit area. Can provide a simple signal transmission circuit.
In addition, since the power conversion device according to the present invention is configured as described above, the signal transmission circuit that transmits the control signal from the control unit to the drive circuit insulated from the control unit can transmit the signal with high reliability and noise. It can be realized with a simple and small circuit configuration with improved tolerance, and it is possible to promote downsizing and cost reduction of a power conversion device with high reliability of signal transmission of control signals and improved noise tolerance.

It is a figure which shows the circuit structure of the signal transmission circuit by Embodiment 1 of this invention. It is the block diagram which applied the power converter device by Embodiment 1 of this invention to motor control. It is a figure which shows the operation | movement waveform of the signal transmission circuit by Embodiment 1 of this invention. It is a figure which shows the circuit structure of the 1st circuit by Embodiment 1 of this invention. It is a figure which shows the operation | movement waveform of the 1st circuit by Embodiment 1 of this invention. It is a figure which shows the circuit structure of the rising edge detection circuit by Embodiment 1 of this invention. It is a figure which shows the operation | movement waveform of the rising edge detection circuit by Embodiment 1 of this invention. It is a figure which shows the circuit structure of the falling edge detection circuit by Embodiment 1 of this invention. It is a figure which shows the operation | movement waveform of the falling edge detection circuit by Embodiment 1 of this invention. It is a figure which shows the operation | movement waveform at the time of noise generation in the signal transmission circuit by Embodiment 1 of this invention. It is a figure which shows the circuit structure of the 1st circuit by another example of Embodiment 1 of this invention. It is a figure which shows the operation | movement waveform of the 1st circuit by another example of Embodiment 1 of this invention. It is a figure which shows the circuit structure of the signal transmission circuit by Embodiment 2 of this invention. It is a figure which shows the operation | movement waveform of the signal transmission circuit by Embodiment 2 of this invention. It is a figure which shows the circuit structure of the 1st circuit by Embodiment 2 of this invention. It is a figure which shows the operation | movement waveform of the 1st circuit by Embodiment 2 of this invention. It is a figure which shows the circuit structure of the 1st circuit by another example of Embodiment 2 of this invention. It is a figure which shows the operation | movement waveform of the 1st circuit by another example of Embodiment 2 of this invention. It is a figure which shows the circuit structure of the signal transmission circuit by Embodiment 3 of this invention. It is a figure which shows the operation | movement waveform of the signal transmission circuit by Embodiment 3 of this invention. It is a figure which shows the circuit structure of the signal transmission circuit by Embodiment 4 of this invention. It is a figure which shows the operation | movement waveform of the signal transmission circuit by Embodiment 4 of this invention. It is the block diagram which applied the power converter device by Embodiment 5 of this invention to motor control. It is the block diagram which applied the power converter device by another example of Embodiment 5 of this invention to motor control. It is the block diagram which applied the power converter device by another example of Embodiment 5 of this invention to motor control.

Embodiment 1 FIG.
Hereinafter, a signal transmission circuit according to a first embodiment of the present invention will be described with reference to the drawings. In addition, in each following embodiment, the same code | symbol is attached | subjected about the same component.
FIG. 1 is a diagram showing a circuit configuration of a signal transmission circuit 1000 according to the first embodiment of the present invention. As shown in FIG. 1, the signal transmission circuit 1000 is connected to the insulating transformer 10 having the first coil 11 and the second coil 12, the first circuit 100 connected to the first coil 11, and the second coil 12. A second circuit 200 for transmitting an input signal IN, which is a first signal input from the input terminal 101 to the first circuit 100, via the isolation transformer 10, and a second signal from the output terminal 201 of the second circuit 200. An output signal OUT that is a signal is output. By this signal transmission, the output signal OUT becomes a signal corresponding to the input signal IN.

  The first circuit 100 includes a first pulse conversion circuit 120. The first pulse conversion circuit 120 generates and outputs transmission signals VS and VR to the first coil 11 in accordance with changes in the logical value of the input signal IN input from the input terminal 101. In the first pulse conversion circuit 120, when the input signal IN that is input changes from low to high, a pulse having a predetermined period width is output to the first end of the first coil 11, and the first pulse conversion circuit 120 continuously outputs the first pulse. A pulse having a predetermined period width is output to the second end of the coil 11. When the input signal IN changes from high to low, a pulse having a predetermined period width is output to the second end of the first coil 11, and continuously, to the first end of the first coil 11 for a predetermined period. A pulse with a width of is output. That is, in the first pulse conversion circuit 120, when the logic value of the input signal IN changes, a plurality of pulses are output alternately and continuously to the first end and the second end of the first coil 11.

The second circuit 200 has two input terminals connected to the first and second ends of the second coil 12, and receives and compares the voltage signals VRX + and VRX- generated at the first and second ends. The comparator 220 includes an SR latch circuit 270 that receives a set signal VS2 and a reset signal VR2 and outputs a signal VQ that is an output signal OUT, and a signal generation circuit 210.
The comparator 220 receives the signal from the second coil 12, demodulates it into a binary signal VO having a logical value, and outputs it. The signal generation circuit 210 generates the reference set signal VS1 and the reference reset signal VR1 based on the output signal VO of the comparator 220, and then partially masks them to generate the set signal VS2 and the reset signal VR2, respectively. Output to the circuit 270.

The signal generation circuit 210 includes a rising edge detection circuit 230 as a first edge detection circuit, a falling edge detection circuit 240 as a second edge detection circuit, a first mask circuit 250, and a second mask circuit 260. .
The rising edge detection circuit 230 detects a change in the rising edge of the output signal VO of the comparator 220, and outputs a reference set signal VS1 having a pulse width of a predetermined period τ3. The falling edge detection circuit 240 detects a change in the falling edge of the output signal VO of the comparator 220 and outputs a reference reset signal VR1 having a pulse width of a predetermined period τ3.

The first mask circuit 250 includes a rising edge detection circuit 252, a NOT circuit 253, and an AND circuit 251.
The output signal VQB from the inverting output terminal QB of the SR latch circuit 270 is input to the rising edge detection circuit 252, and the output of the rising edge detection circuit 252 is input to the NOT circuit 253. In the AND circuit 251, the reference set signal VS <b> 1 from the rising edge detection circuit 230 is input to the first terminal of the AND circuit 251, and the mask signal VSM that is the output of the NOT circuit 253 is input to the second terminal of the AND circuit 251. . Then, the output of the AND circuit 251 is input to the set terminal S of the SR latch circuit 270 as the set signal VS2. The output signal VQB from the inverted output terminal QB of the SR latch circuit 270 is an inverted signal of the signal VQ and is referred to as an output inverted signal VQB of the SR latch circuit 270.
The first mask circuit 250 masks an unnecessary signal of the reference set signal VS1 output from the rising edge detection circuit 230 for a predetermined period, that is, partially, and demodulates a signal corresponding to the input signal IN by the SR latch circuit 270. Therefore, only the set signal VS2 necessary for the purpose is output.

The second mask circuit 260 includes a rising edge detection circuit 262, a NOT circuit 263, and an AND circuit 261.
The output signal VQ from the output terminal Q of the SR latch circuit 270 is input to the rising edge detection circuit 262, and the output of the rising edge detection circuit 262 is input to the NOT circuit 263. In the AND circuit 261, the reference reset signal VR <b> 1 from the falling edge detection circuit 240 is input to the first terminal of the AND circuit 261, and the mask signal VRM that is the output of the NOT circuit 263 is input to the second terminal of the AND circuit 261. The Then, the output of the AND circuit 261 is input to the reset terminal R of the SR latch circuit 270 as the reset signal VR2.
The second mask circuit 260 masks an unnecessary signal of the reference reset signal VR1 output from the falling edge detection circuit 240 for a predetermined period, that is, partially, and demodulates the signal corresponding to the input signal IN by the SR latch circuit 270. Only the reset signal VR2 that is necessary for this is output.

  The SR latch circuit 270 outputs a signal VQ, which is the output signal OUT of the signal transmission circuit 1000, from the output terminal Q. In the SR latch circuit 270, the set signal VS2 generated by the first mask circuit 250 is input to the set terminal S, and the reset signal VR2 generated by the second mask circuit 260 is input to the reset terminal R. Then, the output signal VQ from the output terminal Q is raised from low to high in accordance with the logical change of the set signal VS2. The high state of the output signal VQ is maintained, and the output signal VQ from the output terminal Q falls from high to low in accordance with the logic change of the reset signal VR2. Further, the inverted output signal VQB is output from the inverted output terminal QB of the SR latch circuit 270.

Such a signal transmission circuit 1000 is applied to transmission of a control signal for driving and controlling the power semiconductor switching element 2 in the power conversion device 20, for example, as shown in FIG.
As shown in FIG. 2, a power conversion device 20 that controls a motor 1 used in a hybrid vehicle, an electric vehicle, or the like includes a power semiconductor switching element 2 and a driver unit 3 as a drive circuit that drives the power semiconductor switching element 2. The control unit 4 generates a control signal for controlling the power semiconductor switching element 2, and the signal transmission circuit 1000 transmits the control signal from the control unit 4 to the driver unit 3.
The signal transmission circuit 1000 is connected between the control unit 4 and the driver unit 3 and insulates the control unit 4 from a device controlled by a high voltage, such as the driver unit 3, the power semiconductor switching element 2, and the motor 1, A control signal from the control unit 4 is input as an input signal IN, and an output signal OUT corresponding to the control signal is generated and output to the driver unit 3.

FIG. 3 is a diagram showing operation waveforms of the signal transmission circuit 1000 according to the first embodiment.
FIG. 3 shows an input signal IN input to the signal transmission circuit 1000, transmission signals VS and VR transmitted from the first circuit 100 to the first end and the second end of the first coil 11, respectively, and the second coil. 12, which are generated at the first end and the second end and received by the second circuit 200, the output signal VO of the comparator 220, and the rising edge that detects the rising edge of the output signal VO of the comparator 220. The output signal (reference set signal) VS1 of the edge detection circuit 230, the output signal (reference reset signal) VR1 of the falling edge detection circuit 240 that detects the falling edge of the output signal VO of the comparator 220, and the signal transmission circuit 1000 The output signal VQ of the SR latch circuit 270, the inverted output signal VQB of the SR latch circuit 270, and the output of the falling edge signal A mask signal VRM for masking the reference reset signal VR1 from the detection circuit 240 for a predetermined period τ4 and a reference set signal VS1 generated in the first mask circuit 250 and masked from the rising edge detection circuit 230 for a predetermined period τ4. Operation waveforms of the mask signal VSM for performing the above operation, the set signal VS2 input to the set terminal S of the SR latch circuit 270, and the reset signal VR2 input to the reset terminal R of the SR latch circuit 270 are shown.

Hereinafter, the detailed configuration and operation of each part of the signal transmission circuit 1000 will be described.
FIG. 4 shows the configuration of the first pulse conversion circuit 120 constituting the first circuit 100 of the signal transmission circuit 1000, and FIG. The configuration of the first pulse conversion circuit 120 shown in FIG. 4 is an example and is not limited.
As shown in FIG. 4, the first pulse conversion circuit 120 includes a transmission circuit 120 a and two OR circuits 130 and 131. The transmission circuit 120a includes a rising edge detection circuit 127 and three falling edge detection circuits 128a to 128c. The input signal IN input to the transmission circuit 120a is input to the rising edge detection circuit 127 and the falling edge detection circuit 128a. The output VA of the rising edge detection circuit 127 is input to the falling edge detection circuit 128 b and the first end of the OR circuit 130. The output VB of the falling edge detection circuit 128 a is input to the falling edge detection circuit 128 c and the second end of the OR circuit 131. The output VC of the falling edge detection circuit 128 b is input to the first end of the OR circuit 131, and the output VD of the falling edge detection circuit 128 c is input to the second end of the OR circuit 130.

As shown in FIG. 5, in the first pulse conversion circuit 120, when the logical value of the input signal IN changes from low to high, the rising edge detection circuit 127 responds to a pulse (signal) having a width of a predetermined period τ1. VA) is output. Further, when the signal VA changes from high to low, the falling edge detection circuit 128b outputs a pulse (signal VC) having a width of a predetermined period τ2 accordingly.
In the first pulse conversion circuit 120, when the logical value of the input signal IN changes from high to low, the falling edge detection circuit 128a outputs a pulse (signal VB) having a width of a predetermined period τ1 accordingly. To do. Further, when the signal VB changes from high to low, the falling edge detection circuit 128c outputs a pulse (signal VD) having a width of a predetermined period τ2 accordingly. The OR circuit 130 receives the signal VA and the signal VD and outputs a signal VS that is the output of the first pulse conversion circuit 120. The OR circuit 131 receives the signal VB and the signal VC and outputs a signal VR that is an output of the first pulse conversion circuit 120.

  The predetermined period τ1 of the rising edge detection circuit 127 and the predetermined period τ1 of the falling edge detection circuit 128a are preferably the same, but this is not restrictive. Further, it is desirable that the predetermined period τ2 of the falling edge detection circuit 128b and the predetermined period τ2 of the falling edge detection circuit 128c are the same, but this is not restrictive.

FIG. 6 is a circuit diagram showing a configuration of the rising edge detection circuit 127, and FIG. 7 shows its operation waveform. Note that the configuration of the rising edge detection circuit 127 shown in FIG. 6 is an example and is not limited.
As shown in FIG. 6, the rising edge detection circuit 127 includes a delay circuit 127a, a NOT circuit 127b, and an AND circuit 127c. The signal DIN1 input to the rising edge detection circuit 127 is input to the delay circuit 127a and the first end of the AND circuit 127c. The signal DIN1 input to the delay circuit 127a is delayed by a predetermined period (in this case, indicated by τ) and input to the second end of the AND circuit 127c via the NOT circuit 127b. The AND circuit 127c outputs a signal DOUT1 that is an output of the rising edge detection circuit 127.
As shown in FIG. 7, the rising edge detection circuit 127 outputs a signal DOUT1 having a width of a predetermined period τ when the input signal DIN1 changes from low to high.

  The above-described configuration of the rising edge detection circuit 127 individually sets the predetermined time τ to be delayed in the other rising edge detection circuits 230, 252 and 262 used in the second circuit 200 of the signal transmission circuit 1000. Applicable in things.

FIG. 8 is a circuit diagram showing a configuration of the falling edge detection circuit 128a, and FIG. 9 shows its operation waveform. The configuration of the falling edge detection 128a shown in FIG. 8 is an example and is not limited.
As shown in FIG. 8, the falling edge detection circuit 128a includes a delay circuit 128d, a NOT circuit 128e, and an AND circuit 128f. The signal DIN2 input to the falling edge detection circuit 128a is input to the delay circuit 128d and input to the first end of the AND circuit 128f via the NOT circuit 128e. The signal DIN2 input to the delay circuit 128d is delayed by a predetermined period (in this case, indicated by τ) and input to the second end of the AND circuit 128f. The AND circuit 128f outputs a signal DOUT2 that is an output of the falling edge detection circuit 128a.
As shown in FIG. 9, when the input signal DIN2 changes from high to low, the falling edge detection circuit 128a outputs a signal DOUT2 having a width of a predetermined period τ.

  Note that the configuration of the falling edge detection circuit 128a described above is a predetermined delay that is also delayed by the other falling edge detection circuits 128b, 128c, and 240 used in the first circuit 100 and the second circuit 200 of the signal transmission circuit 1000. It can be applied by setting the time τ individually.

  Next, the overall operation of the signal transmission circuit 1000 will be described with reference to FIG. As described above, the signal transmission circuit 1000 includes the insulating transformer 10 having the first coil 11 and the second coil 12, the first circuit 100 connected to the first coil 11, and the first circuit connected to the second coil 12. 2 circuit 200, the input signal IN input to the first circuit 100 is transmitted through the isolation transformer 10, and the output signal OUT is output from the second circuit 200.

At time t1, the input signal IN input to the first pulse conversion circuit 120 of the first circuit 100 changes from low to high. When the input signal IN changes from low to high, the first pulse conversion circuit 120 outputs a pulse (signal VS) having a width of a predetermined period τ 1 to the first end of the first coil 11. When the signal VS changes from low to high, a current change occurs in the first coil 11 and is induced by the current change. Bipolar induced voltage signals VRX + and VRX− are generated at the first and second ends of the second coil 12. Is output. The bipolar induced voltage signals VRX + and VRX− are input to the comparator 220, and the output signal VO of the comparator 220 changes from low to high.
When the output signal VO of the comparator 220 changes from low to high, the rising edge detection circuit 230 outputs a pulse (reference set signal VS1) having a width of a predetermined period τ3. The pulse width (predetermined period τ3) of the reference set signal VS1 is a period (τ3 <τ1) shorter than the pulse width (predetermined period τ1) of the output signal VS from the first pulse conversion circuit 120.

In the first mask circuit 250, when the pulse of the reference set signal VS1 is input from the rising edge detection circuit 230, the set signal VS2 to the SR latch circuit 270 is generated according to the logic of the mask signal VSM (continues high state). The Then, the output signal VQ of the SR latch circuit 270 changes from low to high and is output as the output signal OUT of the signal transmission circuit 1000. At this time, the output inversion signal VQB of the SR latch circuit 270 changes from high to low.
When the output signal VQ of the SR latch circuit 270 changes from low to high, the second mask circuit 260 generates an off pulse (mask signal VRM) having a width of a predetermined period τ4. In the second mask circuit 260, the reference reset signal VR1 from the falling edge detection circuit 240 is masked by the mask signal VRM for a predetermined period τ4, and during that period, the reset signal VR2 that is low is generated to generate the reset terminal of the SR latch circuit 270. Output to R. That is, the second mask circuit 260 masks the reference reset signal VR1 in a predetermined period τ4 that is a continuous period from the rising timing of the output signal OUT.

  At time t2, in the first pulse conversion circuit 120, the pulse (signal VS) having a width of the predetermined period τ1 generated at time t1 is turned off, and the pulse (signal VR) having the width of the predetermined period τ2 is continuously generated. Output to the second end of one coil 11. The relationship between the predetermined period τ1 of the output signal VS of the first pulse conversion circuit 120 and the predetermined period τ2 of the output signal VR may be τ1 = τ2, and the magnitude relationship is not particularly specified. When the signal VR changes from low to high, a current change occurs in the first coil 11, which is induced by the current change, and is opposite to the induced voltage signal at the time t1 at the first and second ends of the second coil 12. Directional bipolar induced voltage signals VRX + and VRX− are output. The bipolar induced voltage signals VRX + and VRX− are input to the comparator 220, and the output signal VO of the comparator 220 changes from high to low.

  When the output signal VO of the comparator 220 changes from high to low, the falling edge detection circuit 240 outputs a pulse (reference reset signal VR1) having a width of a predetermined period τ3. The pulse width (predetermined period τ3) of the reference reset signal VR1 is a period (τ3 <τ2) shorter than the pulse width (predetermined period τ2) of the output signal VR from the first pulse conversion circuit 120. Further, it is desirable that the pulse width τ3 of the reference reset signal VR1 and the pulse width τ3 of the reference set signal VS1 are the same, but the magnitude relationship is not particularly specified.

In the second mask circuit 260, when the pulse of the reference reset signal VR1 is input from the falling edge detection circuit 240, the reset signal VR2 to the SR latch circuit 270 is generated according to the logic of the mask signal VRM. That is, the pulse (reference reset signal VR1) of the predetermined period τ3 is masked by the off pulse (mask signal VRM) of the predetermined period τ4, and the reset signal VR2 maintains the low state. As a result, the output signal VQ of the SR latch circuit 270 continues to be in the high state and is output as the output signal OUT of the signal transmission circuit 1000. At this time, the output inversion signal VQB of the SR latch circuit 270 continues to be in the low state.
The predetermined period τ4 of the mask signal VRM generated by the second mask circuit 260 is set to be longer than the period obtained by adding the predetermined period τ1 of the output signal VS of the first pulse conversion circuit 120 and the predetermined period τ3 of the reference reset signal VR1 ( τ4> τ1 + τ3). The mask signal VRM is in the low state for a predetermined period τ4 from the rising timing of the output signal OUT, and returns to the high level before the falling timing of the output signal OUT. In this case, it returns to high before time t3.

At time t3, in the first pulse conversion circuit 120, when the pulse (signal VR) having a width of the predetermined period τ2 generated at time t2 is turned off, that is, when the signal VR is changed from high to low, a current change occurs in the first coil 11. Occurring and induced by the current change, bipolar induced voltage signals VRX + and VRX− in opposite directions to the induced voltage signal at time t2 are output to the first end and the second end of the second coil 12. The bipolar induced voltage signals VRX + and VRX− are input to the comparator 220, and the output signal VO of the comparator 220 changes from low to high.
When the output signal VO of the comparator 220 changes from low to high, the rising edge detection circuit 230 outputs a pulse (reference set signal VS1) having a width of a predetermined period τ3.

  In the first mask circuit 250, when the pulse of the reference set signal VS1 is input from the rising edge detection circuit 230, the set signal VS2 to the SR latch circuit 270 is generated according to the logic of the mask signal VSM (continues high state). The The output signal VQ of the SR latch circuit 270 continues to be in the high state and is output as the output signal OUT of the signal transmission circuit 1000. At this time, the output inversion signal VQB of the SR latch circuit 270 continues to be in the low state.

At time t4, the input signal IN input to the first pulse conversion circuit 120 changes from high to low. When the input signal IN changes from high to low, the first pulse conversion circuit 120 outputs a pulse (signal VR) having a width of a predetermined period τ1 to the second end of the first coil 11. When the signal VR changes from low to high, a current change occurs in the first coil 11, which is induced by the current change, and is opposite to the induced voltage signal at time t3 at the first and second ends of the second coil 12. Directional bipolar induced voltage signals VRX + and VRX− are output. The bipolar induced voltage signals VRX + and VRX− are input to the comparator 220, and the output signal VO of the comparator 220 changes from high to low.
When the output signal VO of the comparator 220 changes from high to low, the falling edge detection circuit 240 outputs a pulse (reference reset signal VR1) having a width of a predetermined period τ3.

In the second mask circuit 260, when the pulse of the reference reset signal VR1 is input from the falling edge detection circuit 240, the reset signal VR2 to the SR latch circuit 270 is generated according to the logic of the mask signal VRM (continues high state). Is done. Then, the output signal VQ of the SR latch circuit 270 changes from high to low and is output as the output signal OUT of the signal transmission circuit 1000. At this time, the output inversion signal VQB of the SR latch circuit 270 changes from low to high.
When the output inversion signal VQB of the SR latch circuit 270 changes from low to high, the first mask circuit 250 generates an off pulse (mask signal VSM) having a width of a predetermined period τ4. In the first mask circuit 250, the reference set signal VS1 from the rising edge detection circuit 230 is masked for a predetermined period τ4 by the mask signal VSM, and during that period, a set signal VS2 that is low is generated to generate the set terminal S of the SR latch circuit 270. Output to. That is, the first mask circuit 250 masks the reference set signal VS1 in a predetermined period τ4 that is a continuous period from the falling timing of the output signal OUT.

  At time t5, in the first pulse conversion circuit 120, the pulse (signal VR) having a width of the predetermined period τ1 generated at time t4 is turned off, and the pulse having the width of the predetermined period τ2 (signal VS) is continuously generated. Output to the first end of one coil 11. The relationship between the predetermined period τ1 of the output signal VR of the first pulse conversion circuit 120 and the predetermined period τ2 of the output signal VS may be τ1 = τ2, and the magnitude relationship is not particularly specified. When the signal VS changes from low to high, a current change occurs in the first coil 11 and is induced by the current change, and is opposite to the induced voltage signal at the time t4 at the first and second ends of the second coil 12. Directional bipolar induced voltage signals VRX + and VRX− are output. The bipolar induced voltage signals VRX + and VRX− are input to the comparator 220, and the output signal VO of the comparator 220 changes from low to high.

  When the output signal VO of the comparator 220 changes from low to high, the rising edge detection circuit 230 outputs a pulse (reference set signal VS1) having a width of a predetermined period τ3. The pulse width (predetermined period τ3) of the reference set signal VS1 is a period (τ3 <τ2) shorter than the pulse width (predetermined period τ2) of the output signal VS from the first pulse conversion circuit 120.

  In the first mask circuit 250, when the pulse of the reference set signal VS1 is input from the rising edge detection circuit 230, the set signal VS2 to the SR latch circuit 270 is generated according to the logic of the mask signal VSM. That is, the pulse (reference set signal VS1) of the predetermined period τ3 is masked by the off pulse (mask signal VSM) of the predetermined period τ4, and the set signal VS2 maintains the low state. As a result, the output signal VQ of the SR latch circuit 270 continues to be in the low state and is output as the output signal OUT of the signal transmission circuit 1000. At this time, the output inversion signal VQB of the SR latch circuit 270 continues to be in the high state.

  The predetermined period τ4 of the mask signal VSM generated by the first mask circuit 250 is set to be longer than the period obtained by adding the predetermined period τ1 of the output signal VR of the first pulse conversion circuit 120 and the predetermined period τ3 of the reference set signal VS1 ( τ4> τ1 + τ3), which is preferably the same as the predetermined period τ4 of the mask signal VRM generated by the second mask circuit 260. The mask signal VSM is in a low state for a predetermined period τ4 from the falling timing of the output signal OUT, and returns to the high level before the rising timing of the output signal OUT.

At time t6, in the first pulse conversion circuit 120, when the pulse (signal VS) having a width of the predetermined period τ2 generated at time t5 is turned off, that is, when the signal VS changes from high to low, a current change occurs in the first coil 11. Occurring and induced by the current change, bipolar induced voltage signals VRX + and VRX− in opposite directions to the induced voltage signal at time t5 are output to the first end and the second end of the second coil 12. The bipolar induced voltage signals VRX + and VRX− are input to the comparator 220, and the output signal VO of the comparator 220 changes from high to low.
When the output signal VO of the comparator 220 changes from high to low, the falling edge detection circuit 240 outputs a pulse (reference reset signal VR1) having a width of a predetermined period τ3.

  In the second mask circuit 260, when the pulse of the reference reset signal VR1 is input from the falling edge detection circuit 240, the reset signal VR2 to the SR latch circuit 270 is generated according to the logic of the mask signal VRM (continues high state). Is done. The output signal VQ of the SR latch circuit 270 continues to be in the low state and is output as the output signal OUT of the signal transmission circuit 1000. At this time, the output inversion signal VQB of the SR latch circuit 270 continues to be in the high state.

Next, the overall operation when common-mode noise occurs in the signal transmission circuit 1000 will be described. FIG. 10 shows an operation waveform when the common mode noise 5 exceeding the operation region A of the comparator 220 is generated in the second coil 12 of the isolation transformer 10.
At time t1, the input signal IN input to the first pulse conversion circuit 120 of the first circuit 100 changes from low to high. In the first pulse conversion circuit 120, when the first input signal IN changes from low to high, the pulse signal VS having a width of a predetermined period τ1 is output to the first end of the first coil 11. When the input signal IN changes from low to high, the first pulse conversion circuit 120 outputs a pulse (signal VS) having a width of a predetermined period τ 1 to the first end of the first coil 11. When the signal VS changes from low to high, a current change occurs in the first coil 11 and is induced by the current change. Bipolar induced voltage signals VRX + and VRX− are generated at the first and second ends of the second coil 12. Is output.

  The signals VRX + and VRX− output to the first end and the second end of the second coil 12 are input to the comparator 220. At this time, as shown in the figure, the signals VRX + and VRX− Assume that in-phase noise 5 exceeding the operation region A occurs. For this reason, the comparator 220 does not operate, and the output signal VO of the comparator 220 continues to be in the low state. The reference set signal VS1 from the rising edge detection circuit 230 at the subsequent stage of the comparator 220 is also in the low state, and the SR latch circuit 270 does not operate and the output signal OUT is maintained in the low state.

At time t2, in the first pulse conversion circuit 120, the pulse (signal VS) having a width of the predetermined period τ1 generated at time t1 is turned off, and the pulse (signal VR) having the width of the predetermined period τ2 is continuously generated. Output to the second end of one coil 11. When the signal VR changes from low to high, a current change occurs in the first coil 11, which is induced by the current change, and is opposite to the induced voltage signal at the time t1 at the first and second ends of the second coil 12. Directional bipolar induced voltage signals VRX + and VRX− are output. Bipolar induced voltage signals VRX + and VRX− are input to the comparator 220.
At this time, the signals VRX + and VRX− input to the comparator 220 are within the operation region of the comparator 220 because the common-mode noise 5 at the time t1 is reduced. The output signal VO of the comparator 220 continues to be in the low state due to the common mode noise 5 at the time t1, and the signals VRX + and VRX− from the first end and the second end of the second coil 12 are input to the comparator 220. Then, the low state is further continued by the normal operation of the comparator 220. The reference set signal VS1 from the rising edge detection circuit 230 at the subsequent stage of the comparator 220 is also in the low state, and the SR latch circuit 270 does not operate and the output signal OUT is maintained in the low state.

At time t3, in the first pulse conversion circuit 120, when the pulse (signal VR) having a width of the predetermined period τ2 generated at time t2 is turned off, that is, when the signal VR is changed from high to low, a current change occurs in the first coil 11. Occurring and induced by the current change, bipolar induced voltage signals VRX + and VRX− in opposite directions to the induced voltage signal at time t2 are output to the first end and the second end of the second coil 12. Bipolar induced voltage signals VRX + and VRX− are input to the comparator 220.
At this time, the signals VRX + and VRX− input to the comparator 220 are within the operation region of the comparator 220 because the common mode noise 5 at the time t1 is further reduced, and the output signal VO of the comparator 220 is low to high. become. When the output signal VO of the comparator 220 changes from low to high, the rising edge detection circuit 230 outputs a pulse (reference set signal VS1) having a width of a predetermined period τ3.

In the first mask circuit 250, when the pulse of the reference set signal VS1 is input from the rising edge detection circuit 230, the set signal VS2 to the SR latch circuit 270 is generated according to the logic of the mask signal VSM (continues high state). The Then, the output signal VQ of the SR latch circuit 270 changes from low to high and is output as the output signal OUT of the signal transmission circuit 1000. At this time, the output inversion signal VQB of the SR latch circuit 270 changes from high to low.
When the output signal VQ of the SR latch circuit 270 changes from low to high, the second mask circuit 260 generates an off pulse (mask signal VRM) having a width of a predetermined period τ4. In the second mask circuit 260, the reference reset signal VR1 from the falling edge detection circuit 240 is masked by the mask signal VRM for a predetermined period τ4, and during that period, the reset signal VR2 that is low is generated to generate the reset terminal of the SR latch circuit 270. Output to R. That is, the second mask circuit 260 masks the reference reset signal VR1 in a predetermined period τ4 that is a continuous period from the rising timing of the output signal OUT.
The operation after time t4 is the same as the operation based on FIG.

In this embodiment, the first pulse conversion circuit 120 of the first circuit 100 has a plurality of consecutively alternating first and second ends of the first coil 11 for each change of the logical value of the input signal IN. Pulses (signals VS and VR) are output. Each pulse (signals VS and VR) is transmitted to the first coil 11 of the insulating transformer 10 to induce voltage signals VRX + and VRX− in the second coil 12, and these signals VRX + and VRX− are supplied to the comparator 220. Input to two input terminals.
In the operation shown in FIG. 10, the input signal IN changes from low to high at time t1, and the first pulse conversion circuit 120 alternately outputs two pulses to the first end and the second end of the first coil 11 alternately. (Signals VS and VR at times t1 and t2) are output. The comparator 220 cannot process the signals VRX + and VRX− generated at the first end and the second end of the second coil 12 due to the common-mode noise 5 generated at time t1, and a malfunction occurs. However, when the common-mode noise 5 decreases, the comparator 220 processes signals VRX + and VRX− generated at the first end and the second end of the second coil 12 by the second pulse (signal VR) at time t2. . Thereby, the output signal VO of the comparator 220 and the operation of the entire second circuit 200 can be returned to the normal state at time t3.

As described above, the signal transmission circuit 1000 according to the first embodiment has a plurality of pulses (signals) alternately and continuously to the first end and the second end of the first coil 11 for each change in the logical value of the input signal IN. (VS, VR) is output, so that even if the comparator 220 cannot process the input signal due to noise and malfunctions, it can quickly recover and transmit the signal with high reliability.
In addition, since the signals VRX + and VRX− at the first end and the second end of the second coil 12 are input to the two input terminals of the comparator 220, the comparator 220 connected to the second coil 12 has a reference voltage. In addition, the two signals VRX + and VRX− are processed by only one comparator 220 and converted into a binary signal VO. Therefore, the circuit configuration of the signal transmission circuit 1000 can be simplified, and the circuit area can be reduced and the cost can be reduced. Further, the comparator 220 does not have a problem that the reference voltage is affected by noise and causes a malfunction, and noise tolerance is improved and the reliability of signal transmission is further improved.

Further, based on the output signal VO of the comparator 220, the rising edge detection circuit 230 generates the reference set signal VS1, and the falling edge detection circuit 240 generates the reference reset signal VR1. Further, the first mask circuit 250 and the second mask circuit 260 mask the reference set signal VS1 and the reference reset signal VR1 for a predetermined period τ4, and remove unnecessary portions by masking the set signal VS2 input to the SR latch circuit 270 and reset. A signal VR2 is generated. The output signal VQ from the SR latch circuit 270 is used as the output signal OUT of the signal transmission circuit 1000.
As a result, the set signal VS2 and the reset signal VR2 input to the SR latch circuit 270 are easily and reliably generated from only one output signal VO of the comparator 220, and the output signal OUT corresponding to the input signal IN is generated. Can be obtained.

  The first mask circuit 250 masks the reference set signal VS1 for a predetermined period τ4 from the rising timing of the output inversion signal VQB of the SR latch circuit 270 to generate the set signal VS2. The second mask circuit 260 masks the reference reset signal VR1 for a predetermined period τ4 from the rising timing of the output signal VQ of the SR latch circuit 270 to generate the reset signal VR2. For this reason, it is possible to reliably remove the unnecessary portions of the reference set signal VS1 and the reference reset signal VR1 and generate the set signal VS2 and the reset signal VR2 input to the SR latch circuit 270 with high reliability.

  Further, since the power conversion device 20 includes such a signal transmission circuit 1000, the noise resistance of the signal transmission for transmitting the control signal from the control unit 4 to the driver unit 3 is improved and the reliability is improved. 20 can be reduced in size and cost.

In the above embodiment, the first pulse conversion circuit 120 constituting the first circuit 100 is the circuit shown in FIG. 4, but another example is shown below.
11 shows a circuit configuration different from FIG. 4 of the first pulse conversion circuit 120 constituting the first circuit 100 of the signal transmission circuit 1000, and FIG. Note that the waveforms of the output signals VS and VR of the first pulse conversion circuit 120 are the same regardless of the circuit configuration of the first pulse conversion circuit 120.

  As illustrated in FIG. 11, the first pulse conversion circuit 120 includes a transmission circuit 120 b and two OR circuits 130 and 131. The transmission circuit 120b includes two delay circuits 121 and 122, four NOT circuits 123a, 123b, 124a, and 124b, and four AND circuits 125a, 125b, 126c, and 126c. The input signal IN input to the transmission circuit 120b is input to the delay circuit 121, the first end of the AND circuit 125a, and the second end of the AND circuit 126b via the NOT circuit 124b. The output VE of the delay circuit 121 is input to the delay circuit 122, the second ends of the AND circuits 125a and 125b, and the first ends of the AND circuits 126a and 126b via the NOT circuits 123a and 123b. The The output VF of the delay circuit 122 is input to the first end of the AND circuit 125b and the second end of the AND circuit 126a via the NOT circuit 124a.

  As shown in FIG. 12, in the first pulse conversion circuit 120, when the logical value of the input signal IN changes, the delay circuit 121 outputs a signal VE delayed by a predetermined period τ1 in response to this, and further, the delay circuit When the logic value of the output signal VE 121 changes, the delay circuit 122 outputs a signal VF delayed by a predetermined period τ2 accordingly. Based on the input signal IN, the output signal VE of the delay circuit 121, and the output signal VF of the delay circuit 122, the four NOT circuits 123a, 123b, 126a, 126b and the four AND circuits 125a, 125b, 126a, 126b. Are used to generate signals VG and VH input to the OR circuit 130 and signals VI and VJ input to the OR circuit 131. The OR circuits 130 and 131 generate signals VS and VR and output them from the first pulse conversion circuit 120.

  Also in this case, a plurality of pulses (signals VS, VR) can be reliably output to the first end and the second end of the first coil 11 alternately in accordance with the change in the logical value of the input signal IN. The effect obtained can be obtained similarly. In this case, in the first pulse conversion circuit 120, the circuit scale can be reduced by sharing the circuit blocks, and a circuit configuration suitable for downsizing can be provided.

Embodiment 2. FIG.
Next, a signal transmission circuit according to a second embodiment of the present invention will be described with reference to the drawings.
FIG. 13 is a diagram showing a circuit configuration of a signal transmission circuit 2000 according to the second embodiment of the present invention, and its operation waveform is shown in FIG.
In the second embodiment, the configuration of the first circuit 100a of the signal transmission circuit 2000 is different from that of the first embodiment. The first circuit 100a includes a second pulse conversion circuit 140, and the configuration of the second pulse conversion circuit 140 is shown in FIG. The operation waveform of the second pulse conversion circuit 140 is shown in FIG. Other configurations are the same as those of the first embodiment.
The configuration of the second pulse conversion circuit 140 shown in FIG. 15 is an example and is not limited.

  As shown in FIG. 13, the signal transmission circuit 2000 includes an insulating transformer 10 having a first coil 11 and a second coil 12, and a first circuit 100 a connected to the first coil 11, as in the first embodiment. And a second circuit 200 connected to the second coil 12, and transmits an input signal IN, which is a first signal input from the input terminal 101 to the first circuit 100a, via the insulating transformer 10, The output signal OUT which is the second signal is output from the output terminal 201 of the circuit 200. By this signal transmission, the output signal OUT becomes a signal corresponding to the input signal IN.

The second pulse conversion circuit 140 generates and outputs transmission signals VS and VR to the first coil 11 in accordance with changes in the logical value of the input signal IN input from the input terminal 101.
In the second pulse conversion circuit 140, when the input signal IN that is input changes from low to high, a pulse having a width of a predetermined period τ1 is output to the first end of the first coil 11, and further, A pulse having a width of a predetermined period τ2 is output to the second end of one coil 11, and further, a pulse having a width of a predetermined period τ1a and τ2a is alternately and continuously connected to the first end and the second end of the first coil 11. And a total of 4 pulses are output continuously. Further, when the input signal IN changes from high to low, a pulse having a width of a predetermined period τ1 is output to the second end of the first coil 11, and continuously, the predetermined value is applied to the first end of the first coil 11. A pulse having a width of the period τ2 is output, and further, pulses having a width of a predetermined period τ1a and τ2a are output alternately and continuously to the second end and the first end of the first coil 11, for a total of four pulses. Are output continuously.

As shown in FIG. 15, the second pulse conversion circuit 140 includes a transmission circuit 140 a and two OR circuits 143 and 144. The transmission circuit 140a includes a rising edge detection circuit 141 and seven falling edge detection circuits 142a to 142g. The input signal IN input to the transmission circuit 140a is input to the rising edge detection circuit 141 and the falling edge detection circuit 142a. The output VA of the rising edge detection circuit 141 is input to the falling edge detection circuit 142b and the first end of the OR circuit 143. The output VB of the falling edge detection circuit 142a is input to the falling edge detection circuit 142c and the first end of the OR circuit 144. The output VC of the falling edge detection circuit 142b is input to the falling edge detection 142d and the second end of the OR circuit 144. The output VD of the falling edge detection circuit 142c is input to the second end of the OR circuit 143 and the falling edge detection circuit 142e. The output VE of the falling edge detection circuit 142d is input to the falling edge detection circuit 142f and the third end of the OR circuit 143. The output VF of the falling edge detection circuit 142e is input to the falling edge detection circuit 142g and the third end of the OR circuit 144. The output VG of the falling edge detection circuit 142f is input to the fourth end of the OR circuit 144. The output VH of the falling edge detection circuit 142g is input to the fourth end of the OR circuit 143.
The OR circuit 143 receives the signals VA, VD, VE, and VH, and outputs a signal VS that is the output of the second pulse conversion circuit 140. The OR circuit 144 receives the signals VB, VC, VF, and VG and outputs a signal VR that is an output of the second pulse conversion circuit 140.

  The rising edge detection circuit 141 uses the same circuit as shown in FIGS. 6 and 7 of the first embodiment, and the falling edge detection circuits 142a to 142g are the same as those in the first embodiment shown in FIGS. However, the present invention is not limited to this.

  As shown in FIG. 16, in the second pulse conversion circuit 140, when the logical value of the input signal IN changes from low to high, the rising edge detection circuit 141 responds accordingly to a pulse (signal) having a width of a predetermined period τ1. VA) is output. Thereafter, when the signal VA changes from high to low, the falling edge detection circuit 142b outputs a pulse (signal VC) having a width of a predetermined period τ2 accordingly. Thereafter, when the signal VC changes from high to low, the falling edge detection circuit 142d outputs a pulse (signal VE) having a width of a predetermined period τ1a. Thereafter, when the signal VE changes from high to low, the falling edge detection circuit 142f outputs a pulse (signal VG) having a width of a predetermined period τ2a.

In the second pulse conversion circuit 140, when the logical value of the input signal IN changes from high to low, the falling edge detection circuit 142a outputs a pulse (signal VB) having a width of a predetermined period τ1 accordingly. To do. Thereafter, when the signal VB changes from high to low, the falling edge detection circuit 142c outputs a pulse (signal VD) having a width of a predetermined period τ2 accordingly. Thereafter, when the signal VD changes from high to low, the falling edge detection circuit 142e outputs a pulse (signal VF) having a width of a predetermined period τ1a. Thereafter, when the signal VF changes from high to low, the falling edge detection circuit 142g outputs a pulse (signal VH) having a width of a predetermined period τ2a.
The signals VA, VD, VE, and VH are input to the OR circuit 143, and the OR circuit 143 outputs the signal VS that is the output of the second pulse conversion circuit 140. The signals VB, VC, VF, and VG are input to the OR circuit 144, and the OR circuit 144 outputs the signal VR that is the output of the second pulse conversion circuit 140.

Next, the overall operation of the signal transmission circuit 2000 will be described with reference to FIG.
At time t1, the input signal IN input to the second pulse conversion circuit 140 of the first circuit 100a changes from low to high. When the input signal IN changes from low to high, the second pulse conversion circuit 140 outputs a pulse (signal VS) having a width of a predetermined period τ1 to the first end of the first coil 11. When the signal VS changes from low to high, a current change occurs in the first coil 11 and is induced by the current change. Bipolar induced voltage signals VRX + and VRX− are generated at the first and second ends of the second coil 12. Is output. The bipolar induced voltage signals VRX + and VRX− are input to the comparator 220, and the output signal VO of the comparator 220 changes from low to high.
When the output signal VO of the comparator 220 changes from low to high, the rising edge detection circuit 230 outputs a pulse (reference set signal VS1) having a width of a predetermined period τ3. The pulse width (predetermined period τ3) of the reference set signal VS1 is a period (τ3 <τ1) shorter than the pulse width (predetermined period τ1) of the output signal VS from the second pulse conversion circuit 140.

In the first mask circuit 250, when the pulse of the reference set signal VS1 is input from the rising edge detection circuit 230, the set signal VS2 to the SR latch circuit 270 is generated according to the logic of the mask signal VSM (continues high state). The Then, the output signal VQ of the SR latch circuit 270 changes from low to high and is output as the output signal OUT of the signal transmission circuit 2000. At this time, the output inversion signal VQB of the SR latch circuit 270 changes from high to low.
When the output signal VQ of the SR latch circuit 270 changes from low to high, the second mask circuit 260 generates an off pulse (mask signal VRM) having a width of a predetermined period τ4a. In the second mask circuit 260, the reference reset signal VR1 from the falling edge detection circuit 240 is masked for a predetermined period τ4a by the mask signal VRM, and during that period, the reset signal VR2 that is low is generated to generate the reset terminal of the SR latch circuit 270. Output to R. That is, the second mask circuit 260 masks the reference reset signal VR1 in a predetermined period τ4a that is a continuous period from the rising timing of the output signal OUT.

  At time t2, the second pulse conversion circuit 140 turns off the pulse (signal VS) having the width of the predetermined period τ1 generated at time t1, and continuously applies the pulse (signal VR) having the width of the predetermined period τ2. Output to the second end of one coil 11. When the signal VR changes from low to high, a current change occurs in the first coil 11, which is induced by the current change, and is opposite to the induced voltage signal at the time t1 at the first and second ends of the second coil 12. Directional bipolar induced voltage signals VRX + and VRX− are output. The bipolar induced voltage signals VRX + and VRX− are input to the comparator 220, and the output signal VO of the comparator 220 changes from high to low.

  When the output signal VO of the comparator 220 changes from high to low, the falling edge detection circuit 240 outputs a pulse (reference reset signal VR1) having a width of a predetermined period τ3. The pulse width (predetermined period τ3) of the reference reset signal VR1 is a period (τ3 <τ2) shorter than the pulse width (predetermined period τ2) of the output signal VR from the second pulse conversion circuit 140. Further, it is desirable that the pulse width τ3 of the reference reset signal VR1 and the pulse width τ3 of the reference set signal VS1 are the same, but the magnitude relationship is not particularly specified.

  In the second mask circuit 260, when the pulse of the reference reset signal VR1 is input from the falling edge detection circuit 240, the reset signal VR2 to the SR latch circuit 270 is generated according to the logic of the mask signal VRM. That is, the pulse (reference reset signal VR1) of the predetermined period τ3 is masked by the off pulse (mask signal VRM) of the predetermined period τ4a, and the reset signal VR2 maintains the low state. As a result, the output signal VQ of the SR latch circuit 270 continues to be in the high state and is output as the output signal OUT of the signal transmission circuit 2000. At this time, the output inversion signal VQB of the SR latch circuit 270 continues to be in the low state.

At time t3, the second pulse conversion circuit 140 turns off the pulse having the width of the predetermined period τ2 (signal VR) generated at time t2, and continuously outputs the pulse having the width of the predetermined period τ1a (signal VS). Output to the first end of one coil 11. When the signal VS changes from low to high, a current change occurs in the first coil 11 and is induced by the current change, and is opposite to the induced voltage signal at the time t2 at the first end and the second end of the second coil 12. Directional bipolar induced voltage signals VRX + and VRX− are output. The bipolar induced voltage signals VRX + and VRX− are input to the comparator 220, and the output signal VO of the comparator 220 changes from low to high.
When the output signal VO of the comparator 220 changes from low to high, the rising edge detection circuit 230 outputs a pulse (reference set signal VS1) having a width of a predetermined period τ3.
The pulse width (predetermined period τ3) of the reference set signal VS1 is a period (τ3 <τ1a) shorter than the pulse width (predetermined period τ1a) of the output signal VS from the second pulse conversion circuit 140.

  In the first mask circuit 250, when the pulse of the reference set signal VS1 is input from the rising edge detection circuit 230, the set signal VS2 to the SR latch circuit 270 is generated according to the logic of the mask signal VSM (continues high state). The The output signal VQ of the SR latch circuit 270 continues to be in the high state and is output as the output signal OUT of the signal transmission circuit 2000. At this time, the output inversion signal VQB of the SR latch circuit 270 continues to be in the low state.

At time t4, the second pulse conversion circuit 140 turns off the pulse (signal VS) having a width of the predetermined period τ1a generated at time t3, and continuously applies pulses (signal VR) having the width of the predetermined period τ2a. Output to the second end of one coil 11. When the signal VR changes from low to high, a current change occurs in the first coil 11, which is induced by the current change, and is opposite to the induced voltage signal at time t3 at the first and second ends of the second coil 12. Directional bipolar induced voltage signals VRX + and VRX− are output. The bipolar induced voltage signals VRX + and VRX− are input to the comparator 220, and the output signal VO of the comparator 220 changes from high to low.
When the output signal VO of the comparator 220 changes from high to low, the falling edge detection circuit 240 outputs a pulse (reference reset signal VR1) having a width of a predetermined period τ3. The pulse width (predetermined period τ3) of the reference reset signal VR1 is a period (τ3 <τ2a) shorter than the pulse width (predetermined period τ2a) of the output signal VR from the second pulse conversion circuit 140.

In the second mask circuit 260, when the pulse of the reference reset signal VR1 is input from the falling edge detection circuit 240, the reset signal VR2 to the SR latch circuit 270 is generated according to the logic of the mask signal VRM. That is, the pulse (reference reset signal VR1) of the predetermined period τ3 is masked by the off pulse (mask signal VRM) of the predetermined period τ4a, and the reset signal VR2 maintains the low state. As a result, the output signal VQ of the SR latch circuit 270 continues to be in the high state and is output as the output signal OUT of the signal transmission circuit 2000. At this time, the output inversion signal VQB of the SR latch circuit 270 continues to be in the low state.
The predetermined period τ4a of the mask signal VRM generated by the second mask circuit 260 is longer than the period obtained by adding the period from time t1 to time t4 and the predetermined period τ3 of the reference set signal VR1, that is, (τ4a> τ1 + τ2 + τ1a + τ3). Is set to be
The mask signal VRM is in a low state for a predetermined period τ4a from the rising timing of the output signal OUT, and returns to the high level before the falling timing of the output signal OUT. In this case, it returns to high before time t5.

At time t5, in the second pulse conversion circuit 140, when the pulse (signal VR) having a predetermined period τ2a generated at time t4 is turned off, that is, when the signal VR changes from high to low, a current change occurs in the first coil 11. Occurring and induced by the current change, bipolar induced voltage signals VRX + and VRX− in opposite directions to the induced voltage signal at time t4 are output to the first end and the second end of the second coil 12. The bipolar induced voltage signals VRX + and VRX− are input to the comparator 220, and the output signal VO of the comparator 220 changes from low to high.
When the output signal VO of the comparator 220 changes from low to high, the rising edge detection circuit 230 outputs a pulse (reference set signal VS1) having a width of a predetermined period τ3.

  In the first mask circuit 250, when the pulse of the reference set signal VS1 is input from the rising edge detection circuit 230, the set signal VS2 to the SR latch circuit 270 is generated according to the logic of the mask signal VSM (continues high state). The The output signal VQ of the SR latch circuit 270 continues to be in the high state and is output as the output signal OUT of the signal transmission circuit 2000. At this time, the output inversion signal VQB of the SR latch circuit 270 continues to be in the low state.

At time t6, the input signal IN input to the second pulse conversion circuit 140 changes from high to low. When the input signal IN changes from high to low, the second pulse conversion circuit 140 outputs a pulse (signal VR) having a width of a predetermined period τ1 to the second end of the first coil 11. When the signal VR changes from low to high, a current change occurs in the first coil 11, which is induced by the current change, and is opposite to the induced voltage signal at the time t5 at the first end and the second end of the second coil 12. Directional bipolar induced voltage signals VRX + and VRX− are output. The bipolar induced voltage signals VRX + and VRX− are input to the comparator 220, and the output signal VO of the comparator 220 changes from high to low.
When the output signal VO of the comparator 220 changes from high to low, the falling edge detection circuit 240 outputs a pulse (reference reset signal VR1) having a width of a predetermined period τ3.

In the second mask circuit 260, when the pulse of the reference reset signal VR1 is input from the falling edge detection circuit 240, the reset signal VR2 to the SR latch circuit 270 is generated according to the logic of the mask signal VRM (continues high state). Is done. Then, the output signal VQ of the SR latch circuit 270 changes from high to low and is output as the output signal OUT of the signal transmission circuit 2000. At this time, the output inversion signal VQB of the SR latch circuit 270 changes from low to high.
When the output inversion signal VQB of the SR latch circuit 270 changes from low to high, the first mask circuit 250 generates an off pulse (mask signal VSM) having a width of a predetermined period τ4a. In the first mask circuit 250, the reference set signal VS1 from the rising edge detection circuit 230 is masked for a predetermined period τ4a by the mask signal VSM, and during that period, a set signal VS2 that is low is generated to generate the set terminal S of the SR latch circuit 270. Output to. That is, the first mask circuit 250 masks the reference set signal VS1 in a predetermined period τ4a that is a continuous period from the falling timing of the output signal OUT.

  At time t7, the second pulse conversion circuit 140 turns off the pulse having the width of the predetermined period τ1 (signal VR) generated at time t6 and continuously applies the pulse having the width of the predetermined period τ2 (signal VS). Output to the first end of one coil 11. When the signal VS changes from low to high, a current change occurs in the first coil 11 and is induced by the current change, and is opposite to the induced voltage signal at the time t6 at the first and second ends of the second coil 12. Directional bipolar induced voltage signals VRX + and VRX− are output. The bipolar induced voltage signals VRX + and VRX− are input to the comparator 220, and the output signal VO of the comparator 220 changes from low to high.

  When the output signal VO of the comparator 220 changes from low to high, the rising edge detection circuit 230 outputs a pulse (reference set signal VS1) having a width of a predetermined period τ3. The pulse width (predetermined period τ3) of the reference set signal VS1 is a period (τ3 <τ2) shorter than the pulse width (predetermined period τ2) of the output signal VS from the second pulse conversion circuit 140.

  In the first mask circuit 250, when the pulse of the reference set signal VS1 is input from the rising edge detection circuit 230, the set signal VS2 to the SR latch circuit 270 is generated according to the logic of the mask signal VSM. That is, the pulse (reference set signal VS1) of the predetermined period τ3 is masked by the off pulse (mask signal VSM) of the predetermined period τ4a, and the set signal VS2 maintains the low state. As a result, the output signal VQ of the SR latch circuit 270 continues to be in the low state and is output as the output signal OUT of the signal transmission circuit 2000. At this time, the output inversion signal VQB of the SR latch circuit 270 continues to be in the high state.

At time t8, the second pulse conversion circuit 140 turns off the pulse (signal VS) having the width of the predetermined period τ2 generated at time t7, and continuously outputs the pulse (signal VR) having the width of the predetermined period τ1a. Output to the first end of one coil 11. When the signal VR changes from low to high, a current change occurs in the first coil 11, which is induced by the current change, and is opposite to the induced voltage signal at the time t7 at the first end and the second end of the second coil 12. Directional bipolar induced voltage signals VRX + and VRX− are output. The bipolar induced voltage signals VRX + and VRX− are input to the comparator 220, and the output signal VO of the comparator 220 changes from high to low.
When the output signal VO of the comparator 220 changes from high to low, the falling edge detection circuit 240 outputs a pulse (reference reset signal VR1) having a width of a predetermined period τ3.
The pulse width (predetermined period τ3) of the reference reset signal VR1 is a period (τ3 <τ1a) shorter than the pulse width (predetermined period τ1a) of the output signal VR from the second pulse conversion circuit 140.

  In the second mask circuit 260, when the pulse of the reference reset signal VR1 is input from the falling edge detection circuit 240, the reset signal VR2 to the SR latch circuit 270 is generated according to the logic of the mask signal VRM (continues high state). Is done. The output signal VQ of the SR latch circuit 270 continues to be in the low state and is output as the output signal OUT of the signal transmission circuit 2000. At this time, the output inversion signal VQB of the SR latch circuit 270 continues to be in the high state.

At time t9, the second pulse conversion circuit 140 turns off the pulse (signal VR) having the width of the predetermined period τ1a generated at time t8, and continuously applies the pulse (signal VS) having the width of the predetermined period τ2a. Output to the second end of one coil 11. When the signal VS changes from low to high, a current change occurs in the first coil 11 and is induced by the current change, and is opposite to the induced voltage signal at the time t8 at the first end and the second end of the second coil 12. Directional bipolar induced voltage signals VRX + and VRX− are output. The bipolar induced voltage signals VRX + and VRX− are input to the comparator 220, and the output signal VO of the comparator 220 changes from low to high.
When the output signal VO of the comparator 220 changes from low to high, the rising edge detection circuit 230 outputs a pulse (reference set signal VS1) having a width of a predetermined period τ3. The pulse width (predetermined period τ3) of the reference set signal VS1 is a period (τ3 <τ2a) shorter than the pulse width (predetermined period τ2a) of the output signal VS from the second pulse conversion circuit 140.

In the first mask circuit 250, when the pulse of the reference set signal VS1 is input from the rising edge detection circuit 230, the reset signal VS2 to the SR latch circuit 270 is generated according to the logic of the mask signal VSM. That is, the pulse (reference set signal VS1) of the predetermined period τ3 is masked by the off pulse (mask signal VSM) of the predetermined period τ4a, and the set signal VS2 maintains the low state. As a result, the output signal VQ of the SR latch circuit 270 continues to be in the low state and is output as the output signal OUT of the signal transmission circuit 2000. At this time, the output inversion signal VQB of the SR latch circuit 270 continues to be in the high state.
The predetermined period τ4a of the mask signal VSM generated by the first mask circuit 250 is longer than the period obtained by adding the period from time t6 to time t9 and the predetermined period τ3 of the reference set signal VS1, that is, (τ4a> τ1 + τ2 + τ1a + τ3). Is set to be
The mask signal VSM is in a low state for a predetermined period τ4a from the falling timing of the output signal OUT, and returns to the high level before the rising timing of the output signal OUT. In this case, it returns to high before time t10.

At time t10, in the second pulse conversion circuit 140, when the pulse (signal VS) having a width of the predetermined period τ2a generated at time t9 is turned off, that is, when the signal VS changes from high to low, a current change occurs in the first coil 11. Occurring and induced by the current change, bipolar induced voltage signals VRX + and VRX− in opposite directions to the induced voltage signal at time t9 are output to the first end and the second end of the second coil 12. The bipolar induced voltage signals VRX + and VRX− are input to the comparator 220, and the output signal VO of the comparator 220 changes from high to low.
When the output signal VO of the comparator 220 changes from high to low, the falling edge detection circuit 240 outputs a pulse (reference reset signal VR1) having a width of a predetermined period τ3.

  In the second mask circuit 260, when the pulse of the reference reset signal VR1 is input from the falling edge detection circuit 240, the reset signal VR2 to the SR latch circuit 270 is generated according to the logic of the mask signal VRM (continues high state). Is done. The output signal VQ of the SR latch circuit 270 continues to be in the low state and is output as the output signal OUT of the signal transmission circuit 2000. At this time, the output inversion signal VQB of the SR latch circuit 270 continues to be in the high state.

  As described above, the signal transmission circuit 2000 according to the second embodiment has a total of four in succession alternately to the first end and the second end of the first coil 11 for each change in the logical value of the input signal IN. Pulses (signals VS and VR) are output. As a result, in-phase noise is generated in the second coil 12 of the insulating transformer 10, and even when the comparator 220 cannot process the input signal and malfunctions, it can quickly recover and transmit the signal with high reliability. In this case, since there are three opportunities for the comparator 220 to change the logic value to the normal value for each change in the logic value of the input signal IN, the output signal can be output even when it takes time for the common-mode noise to return to the steady state. OUT can be returned to a normal state, and noise tolerance and reliability can be further improved.

  For each change in the logical value of the input signal IN, a total of 6 or more 2N pulses (signals VS, VR) are output alternately to the first end and the second end of the first coil 11. The output signal OUT can be returned to a normal state even with a larger or longer noise period. In that case, the predetermined period of the mask signals VSM and VRM generated by the first mask circuit 250 and the second mask circuit 260 is a period during which (2N−1) pulses (signals VS and VR) are continuously generated and the reference set signal. It is set longer than a period obtained by adding a predetermined period τ3 of VS1 (or reference reset signal VR1).

  Further, since the power conversion device 20 includes such a signal transmission circuit 2000, noise resistance and reliability of signal transmission for transmitting the control signal from the control unit 4 to the driver unit 3 are further improved, and the power conversion device 20 can be reduced in size and cost.

In the second embodiment, the second pulse conversion circuit 140 constituting the first circuit 100a is the circuit shown in FIG. 15, but another example is shown below.
FIG. 17 shows a circuit configuration different from that of FIG. 15 of the second pulse conversion circuit 140 constituting the first circuit 100a of the signal transmission circuit 2000, and FIG. Note that the waveforms of the output signals VS and VR of the second pulse conversion circuit 140 are the same regardless of the circuit configuration of the second pulse conversion circuit 140.

  As shown in FIG. 17, the second pulse conversion circuit 140 includes a transmission circuit 140 b and two OR circuits 143 and 144. The transmission circuit 140b includes four delay circuits 145 to 148, eight NOT circuits 149a to 149d and 150a to 150d, and eight AND circuits 151a to 151d and 152a to 152d. The input signal IN input to the transmission circuit 140b is input to the delay circuit 145, the first end of the AND circuit 151a, and the second end of the AND circuit 152b via the NOT circuit 150b. The output VA1 of the delay circuit 145 includes the delay circuit 146, the second end of the AND circuit 151a via the NOT circuit 149a, the second end of the AND circuit 151b via the NOT circuit 149b, and the first end of the AND circuit 152a. And the first end of the AND circuit 152b.

  The output VB1 of the delay circuit 146 includes the first end of the AND circuit 151b, the second end of the AND circuit 152a via the NOT circuit 150a, the first end of the AND circuit 151c, the delay circuit 147, and the NOT circuit 150d. To the second end of the AND circuit 152d. The output VC1 of the delay circuit 147 is connected to the second end of the AND circuit 151c via the NOT circuit 149c, the second end of the AND circuit 151d via the NOT circuit 149d, the delay circuit 148, and the first end of the AND circuit 152c. And the first end of the AND circuit 152d. The output VD1 of the delay circuit 148 is input to the first end of the AND circuit 151d and the second end of the AND circuit 152c via the NOT circuit 150c. The output of the NOT circuit 149a is input to the second end of the AND circuit 151a.

At the first end, the second end, the third end, and the fourth end of the OR circuit 143, the output VE1 of the AND circuit 151a, the output VF1 of the AND circuit 151b, the output VG1 of the AND circuit 151c, and the output VH1 of the AND circuit 151d, respectively. And the OR circuit 143 generates the signal VS and outputs it from the second pulse conversion circuit 140.
The first end, the second end, the third end, and the fourth end of the OR circuit 144 are the output VI1 of the AND circuit 152a, the output VJ1 of the AND circuit 152b, the output VK1 of the AND circuit 152c, and the output VL1 of the AND circuit 152d, respectively. And the OR circuit 144 generates a signal VR and outputs it from the second pulse conversion circuit 140.

As shown in FIG. 18, in the second pulse conversion circuit 140, when the logical value of the input signal IN changes, the delay circuit 145 outputs the output signal VA1 obtained by delaying the input signal IN by a predetermined period τ1. The delay circuit 146 outputs an output signal VB1 obtained by delaying the output signal VA1 of the delay circuit 145 by a predetermined period τ2. The delay circuit 147 outputs an output signal VC1 obtained by delaying the output signal VB1 of the delay circuit 146 by a predetermined period τ1a. The delay circuit 148 outputs an output signal VD1 obtained by delaying the output signal VC1 of the delay circuit by a predetermined period τ2a.
Based on the input signal IN and the output signals VA1 to VD1 of the four delay circuits 145 to 148, the eight NOT circuits 149a to 149d and 150a to 150d and the eight AND circuits 151a to 151d and 152a to 152d are provided. Are used to generate signals VE1 to VH1 input to the OR circuit 143 and signals VI1 to VL1 input to the OR circuit 144. The OR circuits 143 and 144 generate the signals VS and VR and output them from the second pulse conversion circuit 140.

  In this case as well, a total of four pulses (signals VS and VR) can be reliably output to the first end and the second end of the first coil 11 alternately according to the change in the logical value of the input signal IN. The effects described above can be obtained similarly. In this case, in the second pulse conversion circuit 140, the circuit scale can be reduced by sharing the circuit blocks, and a circuit configuration suitable for downsizing can be provided.

Embodiment 3 FIG.
Next, a signal transmission circuit according to a third embodiment of the present invention will be described with reference to the drawings.
FIG. 19 is a diagram showing a circuit configuration of a signal transmission circuit 3000 according to the third embodiment of the present invention, and its operation waveform is shown in FIG.
In the third embodiment, the configuration of the second circuit 200a of the signal transmission circuit 3000 is different from that of the first embodiment, and the other configurations are the same as those of the first embodiment.
As shown in FIG. 19, the signal transmission circuit 3000 includes the insulating transformer 10 having the first coil 11 and the second coil 12 and the first circuit 100 connected to the first coil 11, as in the first embodiment. And a second circuit 200a connected to the second coil 12, an input signal IN which is a first signal input from the input terminal 101 to the first circuit 100 is transmitted via the isolation transformer 10, and a second The output signal OUT which is the second signal is output from the output terminal 201 of the circuit 200a. By this signal transmission, the output signal OUT becomes a signal corresponding to the input signal IN.

The second circuit 200a has two input terminals connected to the first and second ends of the second coil 12, and receives and compares the voltage signals VRX + and VRX− generated at the first and second ends. The comparator 220 includes an SR latch circuit 270a that receives a set signal VS2 and a reset signal VR2 and outputs a signal VQ that is an output signal OUT, and a signal generation circuit 280.
The comparator 220 receives the signal from the second coil 12, demodulates it into a binary signal VO having a logical value, and outputs it. The signal generation circuit 280 generates a set signal VS2 and a reset signal VR2 by partially masking the output signal VO of the comparator 220 as a reference set signal VS1 and an inverted signal thereof as a reference reset signal VR1, respectively. Output to the circuit 270a.

The signal generation circuit 280 includes a delay circuit 281, a third mask circuit 250 a, and a fourth mask circuit 260 a.
The delay circuit 281 outputs a signal Vd1 obtained by delaying the output signal VO of the comparator 220 by a predetermined period τ5.
The third mask circuit 250a includes a NOT circuit 283 and an AND circuit 284. The output signal VO of the comparator 220 is input to the first terminal of the AND circuit 284 as the reference set signal VS1, and the output signal Vd1 of the delay circuit 281 is input to the second terminal of the AND circuit 284 via the NOT circuit 283. The output of the AND circuit 284 is input to the set terminal S of the SR latch circuit 270a as the set signal VS2.
The third mask circuit 250a partially masks the reference set signal VS1, which is the output signal VO of the comparator 220, using the inverted signal of the output signal Vd1 of the delay circuit 281 as a mask signal. Then, only the set signal VS2 necessary for demodulating the signal corresponding to the input signal IN by the SR latch circuit 270a is output.

The fourth mask circuit 260a includes a NOT circuit 282 and an AND circuit 285. The output signal VO of the comparator 220 is input to the first terminal of the AND circuit 285 via the NOT circuit 282, and the output signal Vd1 of the delay circuit 281 is input to the second terminal of the AND circuit 285. The output of the AND circuit 285 is input to the reset terminal R of the SR latch circuit 270a as the reset signal VR2.
The fourth mask circuit 260a uses the inverted signal of the output signal VO of the comparator 220 as a reference reset signal VR1, and partially masks the reference reset signal VR1 using the output signal Vd1 of the delay circuit 281 as a mask signal. Then, only the reset signal VR2 necessary for demodulating the signal corresponding to the input signal IN by the SR latch circuit 270a is output.

  The SR latch circuit 270a outputs a signal VQ, which is the output signal OUT of the signal transmission circuit 3000, from the output terminal Q. In the SR latch circuit 270a, the set signal VS2 generated by the third mask circuit 250a is input to the set terminal S, and the reset signal VR2 generated by the fourth mask circuit 260a is input to the reset terminal R. Then, the output signal VQ from the output terminal Q is raised from low to high in accordance with the logical change of the set signal VS2. Then, the high state of the output signal VQ is maintained, the output signal VQ from the output terminal Q is lowered from high to low in accordance with the logic change of the reset signal VR2, and the low state is maintained.

Next, the overall operation of the signal transmission circuit 3000 will be described with reference to FIG.
In FIG. 20, the input signal IN input to the signal transmission circuit 3000, the transmission signals VS and VR transmitted from the first circuit 100 to the first end and the second end of the first coil 11, respectively, and the second coil 12 using the signals VRX + and VRX− generated at the first and second ends and received by the second circuit 200a, the output signal VO (reference set signal VS1) of the comparator 220, and the delay circuit 281. 220, a signal Vd1 obtained by delaying the output signal VO, a set signal VS2 input to the set terminal S of the SR latch circuit 270a, a reset signal VR2 input to the reset terminal R of the SR latch circuit 270a, and a signal transmission circuit An operation waveform of the output signal VQ of the SR latch circuit 270a, which becomes the output signal OUT of 3000, is shown.

  As shown in FIG. 20, the transmission signals VS and VR transmitted from the first circuit 100 to the first end and the second end of the first coil 11 are the same as those in the first embodiment, and the delay circuit 281 delays. The predetermined period τ5 is set to be longer than the continuous generation period (τ1 + τ2) of two pulses output when the logical value of the input signal IN changes.

  At time t1, the input signal IN input to the first pulse conversion circuit 120 of the first circuit 100 changes from low to high. When the input signal IN changes from low to high, the first pulse conversion circuit 120 outputs a pulse (signal VS) having a width of a predetermined period τ 1 to the first end of the first coil 11. When the signal VS changes from low to high, a current change occurs in the first coil 11 and is induced by the current change. Bipolar induced voltage signals VRX + and VRX− are generated at the first and second ends of the second coil 12. Is output. The bipolar induced voltage signals VRX + and VRX− are input to the comparator 220, and the output signal VO (reference set signal VS1) of the comparator 220 changes from low to high. The output signal VO of the comparator 220 is input to the signal generation circuit 280.

  Since the delay circuit 281 in the signal generation circuit 280 outputs the signal Vd1 obtained by delaying the output signal VO of the comparator 220 by a predetermined time τ5, the signal Vd1 continues to be in the low state, and the output of the AND circuit 285 (reset signal VR2). ) Goes low. At this time, the inverted signal (not shown) of the output signal Vd1 is in a high state, and when the signal VO (reference set signal VS1) changes from low to high, the output of the AND circuit 284 (set signal VS2) changes from low to high. The set signal VS2 is input to the SR latch circuit 270a, and the output signal VQ of the SR latch circuit 270a changes from low to high and is output as the output signal OUT of the signal transmission circuit 3000.

  At time t2, in the first pulse conversion circuit 120, the pulse (signal VS) having a width of the predetermined period τ1 generated at time t1 is turned off, and the pulse (signal VR) having the width of the predetermined period τ2 is continuously generated. Output to the second end of one coil 11. When the signal VR changes from low to high, a current change occurs in the first coil 11, which is induced by the current change, and is opposite to the induced voltage signal at the time t1 at the first and second ends of the second coil 12. Directional bipolar induced voltage signals VRX + and VRX− are output. The bipolar induced voltage signals VRX + and VRX− are input to the comparator 220, and the output signal VO (reference set signal VS1) of the comparator 220 changes from high to low. The output signal VO of the comparator 220 is input to the signal generation circuit 280.

  The output signal Vd1 of the delay circuit 281 in the signal generation circuit 280 continues to be in the low state, and the output of the AND circuit 285 (reset signal VR2) continues to be in the low state. At this time, the inverted signal (not shown) of the output signal Vd1 is in a high state, but when the signal VO (reference set signal VS1) changes from high to low, the output of the AND circuit 284 (set signal VS2) changes from high to low. Become. Since the reset signal VR2 continues to be in the low state, the output signal VQ of the SR latch circuit 270a continues to be in the high state and is output as the output signal OUT of the signal transmission circuit 3000.

  At time t3, in the first pulse conversion circuit 120, when the pulse (signal VR) having a width of the predetermined period τ2 generated at time t2 is turned off, that is, when the signal VR is changed from high to low, a current change occurs in the first coil 11. Occurring and induced by the current change, bipolar induced voltage signals VRX + and VRX− in opposite directions to the induced voltage signal at time t2 are output to the first end and the second end of the second coil 12. The bipolar induced voltage signals VRX + and VRX− are input to the comparator 220, and the output signal VO of the comparator 220 changes from low to high. The output signal VO of the comparator 220 is input to the signal generation circuit 280.

  The output signal Vd1 of the delay circuit 281 in the signal generation circuit 280 continues to be in the low state, and the output of the AND circuit 285 (reset signal VR2) continues to be in the low state. At this time, the inverted signal (not shown) of the output signal Vd1 is in a high state, and when the signal VO (reference set signal VS1) changes from low to high, the output of the AND circuit 284 (set signal VS2) changes from low to high. . Since the reset signal VR2 continues to be in the low state, the output signal VQ of the SR latch circuit 270a continues to be in the high state and is output as the output signal OUT of the signal transmission circuit 3000.

At time t4, the output signal Vd1 of the delay circuit 281, that is, the signal Vd1 obtained by delaying the output signal VO of the comparator 220 by a predetermined period τ5 changes from low to high. At this time, since the first pulse conversion circuit 120 of the first circuit 100 does not operate, no current change occurs in the first coil 11 and no induced voltage signal is generated in the second coil 12. The output signal VO of the comparator 220 continues to be in the high state and is input to the signal generation circuit 280.
In the signal generation circuit 280, the reference reset signal VR1 (not shown) that is an inverted signal of the output signal VO of the comparator 220 is in the low state, and the output signal Vd1 of the delay circuit 281 changes from low to high, but the AND circuit 285. Output (reset signal VR2) continues to be low. At this time, the signal VO (reference set signal VS1) is in the high state, but the inverted signal of the output signal Vd1 changes from high to low, and the output of the AND circuit 284 (set signal VS2) changes from high to low. Since the reset signal VR2 continues to be in the low state, the output signal VQ of the SR latch circuit 270a continues to be in the high state and is output as the output signal OUT of the signal transmission circuit 3000.

At time t5, the output signal Vd1 of the delay circuit 281 changes from high to low. At this time, since the first pulse conversion circuit 120 of the first circuit 100 does not operate, no current change occurs in the first coil 11 and no induced voltage signal is generated in the second coil 12. The output signal VO of the comparator 220 continues to be in the high state and is input to the signal generation circuit 280.
In the signal generation circuit 280, the reference reset signal VR1 that is an inverted signal of the output signal VO of the comparator 220 is in a low state, and the output signal Vd1 of the delay circuit 281 is also changed from high to low. The signal VR2) remains in the low state. At this time, the signal VO (reference set signal VS1) is in a high state, the inverted signal of the output signal Vd1 changes from low to high, and the output of the AND circuit 284 (set signal VS2) changes from low to high. Since the reset signal VR2 continues to be in the low state, the output signal VQ of the SR latch circuit 270a continues to be in the high state and is output as the output signal OUT of the signal transmission circuit 3000.

At time t6, the output signal Vd1 of the delay circuit 281 changes from low to high. At this time, since the first pulse conversion circuit 120 of the first circuit 100 does not operate, no current change occurs in the first coil 11 and no induced voltage signal is generated in the second coil 12. The output signal VO of the comparator 220 continues to be in the high state and is input to the signal generation circuit 280.
In the signal generation circuit 280, the reference reset signal VR1, which is an inverted signal of the output signal VO of the comparator 220, is in the low state, and the output signal Vd1 of the delay circuit 281 changes from low to high, but the output (reset) of the AND circuit 285 The signal VR2) remains in the low state. At this time, the signal VO (reference set signal VS1) is in the high state, but the inverted signal of the output signal Vd1 changes from high to low, and the output of the AND circuit 284 (set signal VS2) changes from high to low. Since the reset signal VR2 continues to be in the low state, the output signal VQ of the SR latch circuit 270a continues to be in the high state and is output as the output signal OUT of the signal transmission circuit 3000.

  At time t7, the input signal IN input to the first pulse conversion circuit 120 changes from high to low. When the input signal IN changes from high to low, the first pulse conversion circuit 120 outputs a pulse (signal VR) having a width of a predetermined period τ1 to the second end of the first coil 11. When the signal VR changes from low to high, a current change occurs in the first coil 11, which is induced by the current change, and is opposite to the induced voltage signal at time t3 at the first and second ends of the second coil 12. Directional bipolar induced voltage signals VRX + and VRX− are output. The bipolar induced voltage signals VRX + and VRX− are input to the comparator 220, and the output signal VO of the comparator 220 changes from high to low. The output signal VO of the comparator 220 is input to the signal generation circuit 280.

  In the signal generation circuit 280, the reference reset signal VR1, which is an inverted signal of the output signal VO of the comparator 220, goes from low to high. Further, since the delay circuit 281 outputs the signal Vd1 obtained by delaying the output signal VO of the comparator 220 by the predetermined period τ5, the signal Vd1 continues to be in the high state, and the output (reset signal VR2) of the AND circuit 285 is changed from low to high. become. At this time, since the inverted signal of the output signal Vd1 is in the low state and the signal VO (reference set signal VS1) changes from high to low, the output of the AND circuit 284 (set signal VS2) continues to be in the low state. Since the reset signal VR2 changes from low to high, the output signal VQ of the SR latch circuit 270a changes from high to low and is output as the output signal OUT of the signal transmission circuit 3000.

  At time t8, in the first pulse conversion circuit 120, the pulse (signal VR) having a width of the predetermined period τ1 generated at time t7 is turned off, and the pulse having the width of the predetermined period τ2 (signal VS) is continuously generated. Output to the second end of one coil 11. When the signal VS changes from low to high, a current change occurs in the first coil 11 and is induced by the current change, and is opposite to the induced voltage signal at the time t7 at the first end and the second end of the second coil 12. Directional bipolar induced voltage signals VRX + and VRX− are output. The bipolar induced voltage signals VRX + and VRX− are input to the comparator 220, and the output signal VO of the comparator 220 changes from low to high. The output signal VO of the comparator 220 is input to the signal generation circuit 280.

  Although the output signal Vd1 of the delay circuit 281 in the signal generation circuit 280 continues to be in the high state, the reference reset signal VR1, which is an inverted signal of the output signal VO of the comparator 220, changes from high to low, so that the output of the AND circuit 285 (Reset signal VR2) changes from high to low. At this time, the inverted signal of the output signal Vd1 is in the low state, and the output (set signal VS2) of the AND circuit 284 continues to be in the low state. Since the set signal VS2 continues in the low state, the output signal VQ of the SR latch circuit 270a continues in the low state and is output as the output signal OUT of the signal transmission circuit 3000.

  At time t9, in the first pulse conversion circuit 120, when the pulse (signal VS) having a width of the predetermined period τ2 generated at time t8 is turned off, that is, when the signal VS is changed from high to low, a current change occurs in the first coil 11. Occurring and induced by the current change, bipolar induced voltage signals VRX + and VRX− in opposite directions to the induced voltage signal at time t8 are output to the first end and the second end of the second coil 12. The bipolar induced voltage signals VRX + and VRX− are input to the comparator 220, and the output signal VO of the comparator 220 changes from high to low. The output signal VO of the comparator 220 is input to the signal generation circuit 280.

  Since the output signal Vd1 of the delay circuit 281 in the signal generation circuit 280 continues to be in a high state, and the reference reset signal VR1 that is an inverted signal of the output signal VO of the comparator 220 changes from low to high, the output of the AND circuit 285 ( The reset signal VR2) goes from low to high. At this time, the inverted signal of the output signal Vd1 is in the low state, and the output (set signal VS2) of the AND circuit 284 continues to be in the low state. Since the set signal VS2 continues in the low state, the output signal VQ of the SR latch circuit 270a continues in the low state and is output as the output signal OUT of the signal transmission circuit 3000.

At time t10, the output signal Vd1 of the delay circuit 281, that is, the signal Vd1 obtained by delaying the output signal VO of the comparator 220 by a predetermined period τ5 changes from high to low. At this time, since the first pulse conversion circuit 120 of the first circuit 100 does not operate, no current change occurs in the first coil 11 and no induced voltage signal is generated in the second coil 12. The output signal VO of the comparator 220 continues to be in the low state and is input to the signal generation circuit 280.
In the signal generation circuit 280, the output signal Vd1 of the delay circuit 281 changes from high to low, and the reference reset signal VR1 that is the inverted signal of the output signal VO of the comparator 220 continues to be in the high state, but the output ( The reset signal VR2) goes from high to low. At this time, the inverted signal of the output signal Vd1 changes from low to high, but the signal VO (reference set signal VS1) is in the low state, and the output of the AND circuit 284 (set signal VS2) continues to be in the low state. Since the set signal VS2 continues in the low state, the output signal VQ of the SR latch circuit 270a continues in the low state and is output as the output signal OUT of the signal transmission circuit 3000.

At time t11, the output signal Vd1 of the delay circuit 281 changes from low to high. At this time, since the first pulse conversion circuit 120 of the first circuit 100 does not operate, no current change occurs in the first coil 11 and no induced voltage signal is generated in the second coil 12. The output signal VO of the comparator 220 continues to be in the low state and is input to the signal generation circuit 280.
In the signal generation circuit 280, the output signal Vd1 of the delay circuit 281 changes from low to high, and the reference reset signal VR1 that is the inverted signal of the output signal VO of the comparator 220 continues to be in the high state. The reset signal VR2) goes from low to high. At this time, the inverted signal of the output signal Vd1 changes from high to low, the signal VO (reference set signal VS1) is in the low state, and the output of the AND circuit 284 (set signal VS2) continues to be in the low state. Since the set signal VS2 continues in the low state, the output signal VQ of the SR latch circuit 270a continues in the low state and is output as the output signal OUT of the signal transmission circuit 3000.

At time t12, the output signal Vd1 of the delay circuit 281 changes from high to low. At this time, since the first pulse conversion circuit 120 of the first circuit 100 does not operate, no current change occurs in the first coil 11 and no induced voltage signal is generated in the second coil 12. The output signal VO of the comparator 220 continues to be in the low state and is input to the signal generation circuit 280.
In the signal generation circuit 280, the output signal Vd1 of the delay circuit 281 changes from high to low, and the reference reset signal VR1 that is the inverted signal of the output signal VO of the comparator 220 continues to be in the high state, but the output ( The reset signal VR2) goes from high to low. At this time, the inverted signal of the output signal Vd1 changes from low to high, but the signal VO (reference set signal VS1) is in the low state, and the output of the AND circuit 284 (set signal VS2) continues to be in the low state. Since the set signal VS2 continues in the low state, the output signal VQ of the SR latch circuit 270a continues in the low state and is output as the output signal OUT of the signal transmission circuit 3000.

As described above, also in the third embodiment, in the same manner as in the first embodiment, each change in the logical value of the input signal IN alternately continues to the first end and the second end of the first coil 11. Since a plurality of pulses (signals VS and VR) are output, even when the comparator 220 cannot process the input signal due to noise and malfunctions, it can return quickly and transmit the signal with high reliability.
In addition, since the signals VRX + and VRX− at the first end and the second end of the second coil 12 are input to the two input terminals of the comparator 220, the comparator 220 connected to the second coil 12 has a reference voltage. In addition, the two signals VRX + and VRX− are processed by only one comparator 220 and converted into a binary signal VO. Therefore, the circuit configuration of the signal transmission circuit 3000 can be simplified, and the circuit area can be reduced and the cost can be reduced. Further, the comparator 220 does not have a problem that the reference voltage is affected by noise and causes a malfunction, and noise tolerance is improved and the reliability of signal transmission is further improved.

Further, based on the output signal VO of the comparator 220, a reference set signal VS1 and a reference reset signal VR1 are generated, and the third mask circuit 250a and the fourth mask circuit 260a respectively generate the reference set signal VS1 and the reference reset signal VR1. By masking and removing unnecessary portions, a set signal VS2 and a reset signal VR2 input to the SR latch circuit 270a are generated. The output signal VQ from the SR latch circuit 270a is used as the output signal OUT of the signal transmission circuit 3000.
Thus, the set signal VS2 and the reset signal VR2 input to the SR latch circuit 270a are easily and reliably generated from only one output signal VO of the comparator 220, and the output signal OUT corresponding to the input signal IN is generated. Can be obtained.

In this embodiment, the signal generation circuit 280 that generates the set signal VS2 and the reset signal VR2 input to the SR latch circuit 270a includes the delay circuit 281 that delays the output signal VO of the comparator 220, and the third mask circuit. 250a and a fourth mask circuit 260a. The third mask circuit 250a sets the output signal VO of the comparator 281 as the reference set signal VS1, masks a part of the reference set signal VS1 using the output inverted signal of the delay circuit 281 and removes an unnecessary portion, and sets the set signal. VS2 is generated. The fourth mask circuit 260a uses the output inverted signal of the comparator 281 as the reference reset signal VR1, masks a part of the reference reset signal VR1 using the output signal Vd1 of the delay circuit 281 and removes an unnecessary portion, and reset signal VR2 is generated. In this case, the third mask circuit 250a and the fourth mask circuit 260a are configured by one NOT circuit 283, 282 and AND circuits 284, 285, respectively.
As a result, the signal generation circuit 280 can have a simple circuit configuration, the circuit configuration of the signal transmission circuit 3000 can be further simplified, and the reduction in circuit area and cost can be further promoted.

  In addition, since the power conversion device 20 includes such a signal transmission circuit 3000, noise resistance of signal transmission for transmitting a control signal from the control unit 4 to the driver unit 3 is improved and reliability is improved. 20 can be further reduced in size and cost.

Embodiment 4 FIG.
Next, a signal transmission circuit according to a fourth embodiment of the present invention will be described with reference to the drawings.
FIG. 21 is a diagram showing a circuit configuration of a signal transmission circuit 4000 according to the fourth embodiment of the present invention, and its operation waveform is shown in FIG.
In the fourth embodiment, the configuration of the second circuit 200b of the signal transmission circuit 4000 is different from that of the first embodiment, and other configurations are the same as those of the first embodiment.
As shown in FIG. 21, the signal transmission circuit 4000 includes the insulating transformer 10 having the first coil 11 and the second coil 12 and the first circuit 100 connected to the first coil 11, as in the first embodiment. And a second circuit 200b connected to the second coil 12, and transmits an input signal IN, which is a first signal input from the input terminal 101 to the first circuit 100, via the isolation transformer 10; The output signal OUT which is the second signal is output from the output terminal 201 of the circuit 200b. By this signal transmission, the output signal OUT becomes a signal corresponding to the input signal IN.

The second circuit 200b has two input terminals connected to the first and second ends of the second coil 12, and receives and compares the voltage signals VRX + and VRX− generated at the first and second ends. The comparator 220 includes an SR latch circuit 270a that receives a set signal VS2 and a reset signal VR2 and outputs a signal VQ that is an output signal OUT, and a signal generation circuit 290.
The comparator 220 receives the signal from the second coil 12, demodulates it into a binary signal VO having a logical value, and outputs it. The signal generation circuit 290 generates the reference set signal VS1 and the reference reset signal VR1 based on the output signal VO of the comparator 220, and then partially masks them to generate the set signal VS2 and the reset signal VR2, respectively. Output to the circuit 270a.

The signal generation circuit 290 includes a rising edge detection circuit 230 as a first edge detection circuit, a falling edge detection circuit 240 as a second edge detection circuit, a first mask circuit 250b, and a second mask circuit 260b. .
The rising edge detection circuit 230 detects a change in the rising edge of the output signal VO of the comparator 220, and outputs a reference set signal VS1 having a pulse width of a predetermined period τ3. The falling edge detection circuit 240 detects a change in the falling edge of the output signal VO of the comparator 220 and outputs a reference reset signal VR1 having a pulse width of a predetermined period τ3.

The first mask circuit 250b includes a one-shot multivibrator 252b, a NOT circuit 253b, and a NOR circuit 251b.
The reset signal VR2 output from the second mask circuit 260b is input to the one-shot multivibrator 252b. The one-shot multivibrator 252b outputs an output signal having a width of a predetermined period τ6 using a change in the input signal as a trigger. In the NOR circuit 251b, the reference set signal VS1 from the rising edge detection circuit 230 is input to the first end of the NOR circuit 251b via the NOT circuit 253b, and the mask signal VSM which is the output of the one-shot multivibrator 252b is the NOR circuit. It is input to the second end of 251b. The output of the NOR circuit 251b is input to the set terminal S of the SR latch circuit 270a as the set signal VS2.
The first mask circuit 250b is necessary for masking the reference set signal VS1 output from the rising edge detection circuit 230 for a predetermined period, that is, partially, and demodulating the signal corresponding to the input signal IN by the SR latch circuit 270a. Only the set signal VS2 is output.

The second mask circuit 260b includes a one-shot multivibrator 262b, a NOT circuit 263b, and a NOR circuit 261b.
The set signal VS2 output from the first mask circuit 250b is input to the one-shot multivibrator 262b. The one-shot multivibrator 262b outputs an output signal having a width of a predetermined period τ6 using a change in the input signal as a trigger. In the NOR circuit 261b, the reference reset signal VR1 from the falling edge detection circuit 240 is input to the first terminal of the NOR circuit 261b via the NOT circuit 263b, and the mask signal VRM that is the output of the one-shot multivibrator 262b is NOR. The signal is input to the second terminal of the circuit 261b. The output of the NOR circuit 261b is input to the reset terminal R of the SR latch circuit 270a as the reset signal VR2.
The second mask circuit 260b is necessary for masking the reference reset signal VR1 output from the falling edge detection circuit 240 for a predetermined period, that is, partially, and demodulating the signal corresponding to the input signal IN by the SR latch circuit 270a. Only the reset signal VR2 is output.

  The SR latch circuit 270a outputs a signal VQ, which is the output signal OUT of the signal transmission circuit 4000, from the output terminal Q. In the SR latch circuit 270a, the set signal VS2 generated by the first mask circuit 250b is input to the set terminal S, and the reset signal VR2 generated by the second mask circuit 260b is input to the reset terminal R. Then, the output signal VQ from the output terminal Q is raised from low to high in accordance with the logical change of the set signal VS2. Then, the high state of the output signal VQ is maintained, the output signal VQ from the output terminal Q is lowered from high to low in accordance with the logic change of the reset signal VR2, and the low state is maintained.

Next, the overall operation of the signal transmission circuit 4000 will be described with reference to FIG.
In FIG. 22, the input signal IN input to the signal transmission circuit 4000, the transmission signals VS and VR transmitted from the first circuit 100 to the first end and the second end of the first coil 11, respectively, and the second coil 12, signals VRX + and VRX− generated at the first and second ends and received by the second circuit 200 b, the output signal VO of the comparator 220, and the rising edge of the rising edge of the output signal VO of the comparator 220 are detected. The output signal (reference set signal) VS1 of the edge detection circuit 230, the output signal (reference reset signal) VR1 of the falling edge detection circuit 240 for detecting the falling edge of the output signal VO of the comparator 220, and the SR latch circuit 270a. In the second mask circuit 260b, the set signal VS2 input to the set terminal S, the reset signal VR2 input to the reset terminal R of the SR latch circuit 270a, and the second mask circuit 260b. The mask signal VRM generated and masked in the first mask circuit 250b for masking the reference reset signal VR1 from the falling edge detection circuit 240 for a predetermined period, and the reference set signal VS1 from the rising edge detection circuit 230 as a predetermined The operation waveforms of the mask signal VSM for masking the period and the output signal VQ of the SR latch circuit 270a that becomes the output signal OUT of the signal transmission circuit 4000 are shown.

In the first to third embodiments, the reference set signal VS1 and the reference reset signal VR1 are masked when the mask signal is low. However, in the fourth embodiment, when the mask signals VSM and VRM are high. Mask unnecessary portions of the reference set signal VS1 and the reference reset signal VR1.
Further, transmission signals VS and VR transmitted to the first end and the second end of the first coil 11, signals VRX + and VRX− generated at the first end and the second end of the second coil 12, and the comparator 220, respectively. The output signal VO, the reference set signal VS1, the reference reset signal VR1, the set signal VS2, and the reset signal VR2 are the same as those shown in FIG. 3 of the first embodiment, and the same operation as that of the first embodiment is performed. The description will be omitted as appropriate. Note that t1 to t14 in FIG. 22 are different from those shown in FIG.

At time t1, the input signal IN input to the first pulse conversion circuit 120 of the first circuit 100 changes from low to high. In the first pulse conversion circuit 120, a pulse (signal VS) having a width of a predetermined period τ 1 is output to the first coil 11, induced by a current change in the first coil 11, and the first end of the second coil 12. Bipolar induced voltage signals VRX + and VRX− are output to the second end. As a result, the output signal VO of the comparator 220 changes from low to high, and the rising edge detection circuit 230 outputs a pulse (reference set signal VS1) having a width of a predetermined period τ3.
In the first mask circuit 250b, the reset signal VR2 (low state) is input to the one-shot multivibrator 252b, and the output (mask signal VSM) of the one-shot multivibrator 252b continues to be in the low state. When the pulse of the reference set signal VS1 is input from the rising edge detection circuit 230 to the first mask circuit 250b, the output of the first mask circuit 250b (set signal VS2) changes from low to high according to the logic of the mask signal VSM. Become. Then, the output signal VQ of the SR latch circuit 270a changes from low to high and is output as the output signal OUT of the signal transmission circuit 4000.

  When the output (set signal VS2) of the first mask circuit 250b changes from low to high, the one-shot multivibrator 262b of the second mask circuit 260b generates a pulse (mask signal VRM) having a width of a predetermined period τ6. Generate. In the second mask circuit 260b, the reference reset signal VR1 from the falling edge detection circuit 240 is masked for a predetermined period τ6 by the mask signal VRM, and during that period, the reset signal VR2 that is low is generated to reset the SR latch circuit 270a. Output to R. That is, the second mask circuit 260b masks the reference reset signal VR1 in a predetermined period τ6 that is a continuous period from the rising timing of the set signal VS2.

At time t2, the reference set signal VS1 and the set signal VS2 change from high to low.
At time t3, the first pulse conversion circuit 120 turns off the pulse (signal VS) generated at time t1, and continuously outputs a pulse (signal VR) having a width of a predetermined period τ2 to the first coil 11. . Induced by the current change of the first coil 11, induced voltage signals VRX + and VRX− are output to the first end and the second end of the second coil 12, and the output signal VO of the comparator 220 changes to low. The falling edge detection circuit 240 outputs a pulse (reference reset signal VR1) having a width of a predetermined period τ3.
The pulse (reference reset signal VR1) in the predetermined period τ3 is masked by the pulse (mask signal VRM) in the predetermined period τ6, and the reset signal VR2 maintains the low state. As a result, the output signal VQ of the SR latch circuit 270a continues to be in the high state and is output as the output signal OUT of the signal transmission circuit 4000.

At time t4, the reference reset signal VR1 changes from high to low, and then the mask signal VRM changes from high to low.
The predetermined period τ6 of the mask signal VRM that is the output of the one-shot multivibrator 262b is equal to the predetermined period τ1 of the output signal VS at the time t1 of the first pulse conversion circuit 120 of the first circuit 100 and the falling edge detection. It is set longer than a period obtained by adding the predetermined period τ3 of the circuit 240 (τ6> τ1 + τ3). The mask signal VRM becomes high only for a predetermined period τ6 from the rising timing of the set signal VS2, and then returns to low before the set signal VS2 becomes high, that is, before time t5.

At time t5, in the first pulse conversion circuit 120, the pulse (signal VR) having a width of the predetermined period τ2 generated at time t3 is turned off, and is induced by the current change of the first coil 11, and the first pulse of the second coil 12 is detected. The induced voltage signals VRX + and VRX− are output to the end and the second end, and the output signal VO of the comparator 220 changes to high. The rising edge detection circuit 230 outputs a pulse (reference set signal VS1) having a width of a predetermined period τ3.
In the first mask circuit 250b, the reset signal VR2 (low state) is input to the one-shot multivibrator 252b, and the output (mask signal VSM) of the one-shot multivibrator 252b continues to be in the low state. When the pulse of the reference set signal VS1 is input from the rising edge detection circuit 230 to the first mask circuit 250b, the output of the first mask circuit 250b (set signal VS2) changes from low to high according to the logic of the mask signal VSM. Become.

When the output (set signal VS2) of the first mask circuit 250b changes from low to high, the one-shot multivibrator 262b of the second mask circuit 260b generates a pulse (mask signal VRM) having a width of a predetermined period τ6. Generate. Since the reference reset signal VR1 is in the low state and in the second mask circuit 260b, the reset signal VR2 continues in the low state, the output signal VQ of the SR latch circuit 270a continues in the high state, and the output of the signal transmission circuit 4000 Output as signal OUT.
At time t6, the reference set signal VS1 and the set signal VS2 change from high to low.
At time t7, the mask signal VRM changes from high to low.

At time t8, the input signal IN input to the first pulse conversion circuit 120 of the first circuit 100 changes from high to low. In the first pulse conversion circuit 120, a pulse (signal VR) having a width of a predetermined period τ 1 is output to the first coil 11, induced by a current change in the first coil 11, and the first end of the second coil 12 and Bipolar induced voltage signals VRX + and VRX− are output to the second end. As a result, the output signal VO of the comparator 220 changes from high to low, and the falling edge detection circuit 240 outputs a pulse (reference reset signal VR1) having a width of a predetermined period τ3.
In the second mask circuit 260b, the set signal VS2 (low state) is input to the one-shot multivibrator 262b, and the output (mask signal VRM) of the one-shot multivibrator 262b continues to be in the low state. When the pulse of the reference reset signal VR1 is input from the falling edge detection circuit 240 to the second mask circuit 260b, the output (reset signal VR2) of the second mask circuit 260b is changed from low to high according to the logic of the mask signal VRM. become. Then, the output signal VQ of the SR latch circuit 270a changes from high to low and is output as the output signal OUT of the signal transmission circuit 4000.

  When the output of the second mask circuit 260b (reset signal VR2) changes from low to high, the one-shot multivibrator 252b of the first mask circuit 250b generates a pulse (mask signal VSM) having a width of a predetermined period τ6. Generate. In the first mask circuit 250b, the reference set signal VS1 from the rising edge detection circuit 230 is masked by the mask signal VSM for a predetermined period τ6, and during that period, the reset signal VS2 that is low is generated to generate the set terminal S of the SR latch circuit 270a. Output to. That is, the first mask circuit 250b masks the reference set signal VS1 in a predetermined period τ6 that is a continuous period from the rising timing of the reset signal VR2.

At time t9, the reference reset signal VR1 and the reset signal VR2 change from high to low.
At time t10, the first pulse conversion circuit 120 turns off the pulse (signal VR) generated at time t8, and continuously outputs a pulse (signal VS) having a width of a predetermined period τ2 to the first coil 11. . Induced by the current change of the first coil 11, induced voltage signals VRX + and VRX− are output to the first end and the second end of the second coil 12, and the output signal VO of the comparator 220 changes to high. The rising edge detection circuit 230 outputs a pulse (reference set signal VS1) having a width of a predetermined period τ3.
The pulse (reference set signal VS1) of the predetermined period τ3 is masked by the pulse (mask signal VSM) of the predetermined period τ6, and the set signal VS2 maintains the low state. As a result, the output signal VQ of the SR latch circuit 270a continues to be in the low state and is output as the output signal OUT of the signal transmission circuit 4000.

At time t11, the reference set signal VS1 changes from high to low, and then the mask signal VSM changes from high to low.
The predetermined period τ6 of the mask signal VSM that is the output of the one-shot multivibrator 252b is longer than the period obtained by adding the predetermined period τ1 of the output signal VR at time t8 and the predetermined period τ3 of the rising edge detection circuit 230. It is set (τ6> τ1 + τ3). The mask signal VSM becomes high only for a predetermined period τ6 from the rising timing of the reset signal VR2, and then returns to low before the set signal VR2 becomes high, that is, before time t12.

At time t12, in the first pulse conversion circuit 120, the pulse (signal VS) having a width of the predetermined period τ2 generated at time t10 is turned off, and is induced by the current change of the first coil 11, and the first pulse 12 The induced voltage signals VRX + and VRX− are output to the end and the second end, and the output signal VO of the comparator 220 changes to low. The falling edge detection circuit 240 outputs a pulse (reference reset signal VR1) having a width of a predetermined period τ3.
In the second mask circuit 260b, the set signal VS2 (low state) is input to the one-shot multivibrator 262b, and the output (mask signal VRM) of the one-shot multivibrator 262b continues to be in the low state. When the pulse of the reference reset signal VR1 is input from the falling edge detection circuit 240 to the second mask circuit 260b, the output (reset signal VR2) of the second mask circuit 260b is changed from low to high according to the logic of the mask signal VRM. become.

When the output of the second mask circuit 260b (reset signal VR2) changes from low to high, the one-shot multivibrator 252b of the first mask circuit 250b generates a pulse (mask signal VSM) having a width of a predetermined period τ6. Generate. Since the reference set signal VS1 is in the low state and in the first mask circuit 250b, the set signal VS2 continues in the low state, the output signal VQ of the SR latch circuit 270a continues in the low state, and the output of the signal transmission circuit 4000 Output as signal OUT.
At time t13, the reference reset signal VR1 and the reset signal VR2 change from high to low.
At time t14, the mask signal VSM changes from high to low.

As described above, also in the fourth embodiment, as in the first embodiment, each change in the logical value of the input signal IN alternately continues to the first end and the second end of the first coil 11. Since a plurality of pulses (signals VS and VR) are output, even when the comparator 220 cannot process the input signal due to noise and malfunctions, it can return quickly and transmit the signal with high reliability.
In addition, since the signals VRX + and VRX− at the first end and the second end of the second coil 12 are input to the two input terminals of the comparator 220, the comparator 220 connected to the second coil 12 has a reference voltage. In addition, the two signals VRX + and VRX− are processed by only one comparator 220 and converted into a binary signal VO. Therefore, the circuit configuration of the signal transmission circuit 4000 can be simplified, and the circuit area can be reduced and the cost can be reduced. Further, the comparator 220 does not have a problem that the reference voltage is affected by noise and causes a malfunction, and noise tolerance is improved and the reliability of signal transmission is further improved.

Further, based on the output signal VO of the comparator 220, the rising edge detection circuit 230 generates the reference set signal VS1, and the falling edge detection circuit 240 generates the reference reset signal VR1. Further, the first mask circuit 250b and the second mask circuit 260b mask the reference set signal VS1 and the reference reset signal VR1 for a predetermined period to remove unnecessary portions, thereby setting the set signal VS2 and the reset signal input to the SR latch circuit 270a. VR2 is generated. The output signal VQ from the SR latch circuit 270a is used as the output signal OUT of the signal transmission circuit 4000.
Thus, the set signal VS2 and the reset signal VR2 input to the SR latch circuit 270a are easily and reliably generated from only one output signal VO of the comparator 220, and the output signal OUT corresponding to the input signal IN is generated. Can be obtained.

  Further, the first mask circuit 250b uses the one-shot multivibrator 252b to generate the set signal VS2 by masking the reference set signal VS1 for a predetermined period τ6 from the rising timing of the reset signal VR2. The second mask circuit 260b uses the one-shot multivibrator 262b to mask the reference reset signal VR1 for a predetermined period τ6 from the rising timing of the set signal VS2 to generate the reset signal VR2. For this reason, it is possible to reliably remove the unnecessary portions of the reference set signal VS1 and the reference reset signal VR1, and to generate the set signal VS2 and the reset signal VR2 input to the SR latch circuit 270a with high reliability.

  Further, since the power conversion device 20 includes such a signal transmission circuit 4000, the noise resistance of the signal transmission for transmitting the control signal from the control unit 4 to the driver unit 3 is improved and the reliability is improved. 20 can be reduced in size and cost.

Embodiment 5. FIG.
FIG. 23 is a configuration diagram in which a power conversion apparatus according to Embodiment 5 of the present invention is applied to motor control. Here, although shown about the power converter device 20a provided with the signal transmission circuit 1000 by the said Embodiment 1, it is the same also when it has the signal transmission circuits 2000-4000 by Embodiment 2-4.
As shown in FIG. 23, a power converter 20a that controls a motor 1 used in a hybrid vehicle, an electric vehicle, or the like is configured by sealing one or more power semiconductor switching elements 2 and a driver unit 3 together with resin. A power module 2a, a control unit 4 that generates a control signal for controlling the power semiconductor switching element 2, and a signal transmission circuit 1000 that transmits the control signal from the control unit 4 to the driver unit 3.

The signal transmission circuit 1000 is connected between the control unit 4 and the driver unit 3 and insulates the control unit 4 from a device controlled by a high voltage, such as the driver unit 3, the power semiconductor switching element 2, and the motor 1, A control signal from the control unit 4 is input as an input signal IN and output as an output signal OUT.
In this embodiment, the power conversion device 20a improves the signal transmission accuracy, further simplifies the circuit configuration, reduces the circuit area, and promotes the suppression of malfunction caused by noise. In addition, since the power module 2a including the power semiconductor switching element 2 and the driver unit 3 is provided, the power conversion device 20a can be further reduced in size and cost.

In addition, as shown in FIG. 24, you may use the power converter device 20b provided with the power module 2b comprised by resin-sealing together the power semiconductor switching element 2, the driver part 3, and the signal transmission circuit 1000, Similar effects can be obtained.
Further, as shown in FIG. 25, a power conversion device 20c including a power module 2c configured by resin-sealing the power semiconductor switching element 2, the driver unit 3, the signal transmission circuit 1000, and the control unit 4 together. You may use, and the same effect is acquired.

  It should be noted that within the scope of the present invention, the embodiments can be freely combined, or the embodiments can be appropriately modified or omitted.

Claims (14)

An insulation transformer having a first coil and a second coil, and transmission to the first end and the second end of the first coil in response to a change in the logical value of the first signal input to the first coil. A first circuit that generates and outputs a signal; and a second circuit that is connected to the second coil and generates and outputs a second signal corresponding to the first signal input to the first circuit. ,
The transmission signal to the first end and the second end of the first coil is composed of a plurality of pulses generated alternately and continuously for each change of the logical value of the first signal,
The second circuit has two input terminals connected to the first end and the second end of the second coil and compares each voltage signal generated at the first end and the second end, a set signal, An SR latch circuit that receives the reset signal and outputs the second signal, and a reference set signal and a reference reset signal based on the output signal of the comparator are partially masked to generate the set signal and the reset signal, respectively. and a signal generation circuit for,
The signal generation circuit generates the set signal by masking the reference set signal in a first continuous period set in advance from the timing based on the rising edge of the reset signal, and is preset from the timing based on the rising edge of the set signal. Masking the reference reset signal in the second continuous period generated to generate the reset signal;
Signal transmission circuit. The signal generation circuit detects a rising edge of the output signal of the comparator and outputs the reference set signal; and detects a falling edge of the output signal of the comparator and resets the reference A second edge detection circuit for outputting a signal; a first mask circuit for masking a part of the reference set signal to generate the set signal of the SR latch circuit; and a part of the reference reset signal being masked. The signal transmission circuit according to claim 1, further comprising a second mask circuit that generates the reset signal of the SR latch circuit. The first mask circuit and the second mask circuit obtain the change in the logical value of the second signal and the inverted signal of the second signal from the SR latch circuit, respectively, and generate the set signal and the reset signal. The signal transmission circuit according to claim 2. The first mask circuit masks the reference set signal in the first continuous period from the rising timing of the inverted signal of the second signal, which is timing based on the rising edge of the reset signal ,
4. The signal transmission circuit according to claim 3, wherein the second mask circuit masks the reference reset signal in the second continuous period from a rising timing of the second signal, which is a timing based on a rising edge of the set signal . The first mask circuit acquires the reset signal from the second mask circuit, masks a part of the reference set signal, and generates the set signal of the SR latch circuit,
3. The signal transmission according to claim 2, wherein the second mask circuit acquires the set signal from the first mask circuit and masks a part of the reference reset signal to generate the reset signal of the SR latch circuit. circuit. The first mask circuit masks the reference set signal in the first continuous period from the rising timing of the reset signal,
6. The signal transmission circuit according to claim 5, wherein the second mask circuit masks the reference reset signal in the second continuous period from the rising timing of the set signal. The signal generation circuit includes a delay circuit that delays an output signal of the comparator, an output signal of the comparator as the reference set signal, and a part of the reference set signal by using an output inverted signal of the delay circuit. A third mask circuit for generating the set signal of the SR latch circuit by masking, and using the output inverted signal of the comparator as the reference reset signal, and using the output signal of the delay circuit as a part of the reference reset signal And a fourth mask circuit for generating the reset signal of the SR latch circuit by masking the signal. 8. The signal transmission circuit according to claim 7, wherein the delay circuit delays the output signal of the comparator by a period longer than a continuous generation period of the plurality of pulses in the transmission signal. 9. The signal transmission circuit according to claim 1, wherein the transmission signal has 2N of the plurality of pulses per change in the logical value of the first signal. 10. The signal transmission circuit is connected between the control unit of the power semiconductor switching element and the drive circuit, insulates the control unit and the drive circuit, and inputs the control signal from the control unit as the first signal. The signal transmission circuit according to claim 1, wherein the generated second signal is output to the drive circuit. A power semiconductor switching element; a drive circuit that drives the power semiconductor switching element; a control unit that generates a control signal for controlling the power semiconductor switching element; and a signal transmission circuit.
The signal transmission circuit is
An insulation transformer having a first coil and a second coil, and transmission to the first end and the second end of the first coil in response to a change in the logical value of the first signal input to the first coil. A first circuit that generates and outputs a signal; and a second circuit that is connected to the second coil and generates and outputs a second signal corresponding to the first signal input to the first circuit. ,
The transmission signal to the first end and the second end of the first coil is composed of a plurality of pulses generated alternately and continuously for each change of the logical value of the first signal,
The second circuit has two input terminals connected to the first end and the second end of the second coil and compares each voltage signal generated at the first end and the second end, a set signal, An SR latch circuit that receives the reset signal and outputs the second signal, and a reference set signal and a reference reset signal based on the output signal of the comparator are partially masked to generate the set signal and the reset signal, respectively. And a signal generation circuit that
The signal generation circuit generates the set signal by masking the reference set signal in a first continuous period set in advance from the timing based on the rising edge of the reset signal, and is preset from the timing based on the rising edge of the set signal. Masking the reference reset signal in the second continuous period generated to generate the reset signal,
The signal transmission circuit is connected between the control unit and the drive circuit, insulates the control unit and the drive circuit, and inputs the control signal from the control unit as the first signal, A power converter that generates the second signal and outputs the second signal to the drive circuit. The power conversion device according to claim 11, comprising a power module including the drive circuit and the power semiconductor switching element. The power conversion device according to claim 11, further comprising a power module including the signal transmission circuit, the drive circuit, and the power semiconductor switching element. The power conversion device according to claim 11, comprising a power module including the control unit, the signal transmission circuit, the drive circuit, and the power semiconductor switching element.

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