JP6006528B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly, to a connection between a wiring on a flexible film and a semiconductor integrated circuit in a semiconductor device in which a semiconductor integrated circuit made of a semiconductor element is mounted on a flexible film.

  Currently, thin image display devices using thin image display panels such as liquid crystal display panels, plasma image display panels, and EL (Electro-Luminescence) image display panels have been put into practical use. As a method of mounting a semiconductor device for driving such an image display panel, COF (Chip On Film) in which a semiconductor chip made of LSI or the like is mounted on a film substrate is used.

  In the case of COF, protruding electrodes (pads) are installed on the periphery of a semiconductor chip at a predetermined wiring pitch, and the protruding electrodes and the inner leads supported by the film substrate are connected to each other. Are joined.

  In recent years, with the development of miniaturization technology, multi-output has been promoted by increasing the number of protruding electrodes of a semiconductor chip. On the other hand, downsizing of semiconductor chips has been promoted due to the demand for downsizing of semiconductor devices. In order to realize such a large number of colors and a reduction in the size of the semiconductor chip, it is necessary to advance the fine pitch of the protruding electrodes on the semiconductor chip.

  Also, the shape of the semiconductor chip has a shorter and shorter shape in order to further reduce the mounting area, and it is necessary to increase the number of protruding electrodes installed on the long side of the chip. is there.

  Specifically, the protruding electrodes are arranged at a high density along the periphery of the semiconductor chip, and a fine pitch is achieved so that the semiconductor chip size does not increase even if the number of protruding electrodes is increased. In order to arrange the protruding electrodes at high density, it is necessary to narrow the space between the protruding electrodes, reduce the area occupied by the protruding electrodes (at least reduce the width of the protruding electrodes), and increase the number of protruding electrodes.

  In Patent Document 1, in response to a demand for an increase in the number of outputs (number of bumps) per unit length of a semiconductor chip, the first bump row and the second bump row are arranged every other bump without arranging each bump on the same row. It describes that the bump electrodes are arranged in a so-called zigzag pattern divided into two bump rows. Thereby, for example, as shown in FIG. 39, the protruding electrodes 31 are arranged in a staggered manner, and a semiconductor chip in which the inner leads 32 are individually connected to the protruding electrodes can be realized, and a fine pitch can be achieved.

  In Patent Document 2, similarly to Patent Document 1, the protruding electrodes are arranged separately in the first bump row and the second bump row, and further, for example, as shown in FIG. I am trying.

  As described above, in products that require a fine pitch, it is the mainstream to arrange the protruding electrodes separately in the first bump row and the second bump row.

  In Patent Document 3, when projecting electrodes are arranged separately in a first bump row and a second bump row, the projecting electrodes arranged on the inner bump row farther from the end of the semiconductor chip are arranged on the end of the semiconductor chip. It is described that the mounting position accuracy of the semiconductor chip on the substrate is relaxed by making the width wider than the bump electrode arranged in the bump row on the part side.

JP 2004-134471 A JP 2004-193223 A JP 2004-342993 A

  As described above, with the reduction in the area of the semiconductor chip, the width of the protruding electrodes is reduced and the distance between the protruding electrodes is reduced to reduce the pitch of the protruding electrodes. However, in order to advance such fine pitches, it is necessary to solve the problem of displacement of the joint position between the protruding electrode and the inner lead.

  In order to avoid such misalignment of the bonding position between the protruding electrode and the inner lead, first, the pattern accuracy of the film substrate and the protruding electrode and the mounting accuracy of the bonding apparatus for bonding the film substrate and the semiconductor chip are increased. It is necessary to increase. However, such misalignment of the joining position does not occur only due to these pattern accuracy and mounting accuracy. In some cases, it is not possible to avoid displacement of the bonding position between the protruding electrode and the inner lead simply by increasing the pattern accuracy and the mounting accuracy. This will be described below.

  The protruding electrode on the semiconductor chip is bonded to the inner lead on the film substrate by thermocompression bonding. For this reason, the position of the inner lead on the film substrate varies due to the thermal expansion of the film substrate, and the inner lead on the film substrate formed so as to correspond to the protruding electrode formed on the semiconductor chip is thermally expanded. May be displaced from the position where the corresponding protruding electrode is formed. As a result, the contact area between the inner lead and the protruding electrode is reduced. Alternatively, the inner lead comes into contact with the protruding electrode other than the protruding electrode to be originally bonded, thereby causing a leakage defect or a short circuit defect.

  FIG. 41 shows a situation where a displacement of the joining position of the inner leads occurs in the layout of the protruding electrodes 31 and the inner leads 32 shown in FIG.

  When no misalignment occurs, as shown in FIG. 41A, the protruding electrode 31 and the inner lead 32 are disposed with a sufficient distance X1 therebetween, so that no leak failure or short circuit failure occurs.

  On the other hand, when the joining position shift occurs, as shown in FIG. 41B, a sufficient separation distance cannot be secured between the protruding electrode and the inner lead, and the contact area between the inner lead and the protruding electrode is reduced. To do. In the worst case, as shown in FIG. 41C, a short circuit failure is caused.

  For this reason, it is necessary to set the value of the separation distance X1 in consideration of the positional deviation of the inner leads so that no leak failure or short-circuit failure occurs even if the positional deviation of the inner lead occurs.

  Furthermore, due to the variation in the thickness of the semiconductor chip and the variation in the height of the protruding electrode, the inner lead on the film substrate may be displaced from the position of the corresponding protruding electrode during thermocompression bonding. This occurs when non-uniform pressure is applied at the time of pressure bonding between the film substrate and the semiconductor chip, and the protruding electrode side slides from the initial alignment position of the inner lead and protruding electrode.

  FIG. 42 shows an example of an apparatus for thermocompression bonding a semiconductor chip to a film substrate. A film substrate (here, polyimide) 34 placed on the bonding stage 33 is arranged so that the inner lead 32 and the protruding electrode 31 face the semiconductor chip 30 that is vacuum-sucked by the bonding tool 35 through the vacuum suction hole 36. Is positioned. By lowering the bonding tool 35, the inner lead and the protruding electrode are crimped and connected.

  Here, FIG. 43 shows a state of thermocompression bonding between the semiconductor chip 30 and the film substrate 34 when there is a variation in the thickness of the semiconductor chip and a variation in the height of the protruding electrode. In FIG. 43, the thickness of the semiconductor chip varies, and the height of the protruding electrode decreases toward the right side of the figure.

  Thus, when the height of the protruding electrode is different, when the bonding tool is lowered and crimped, the inner lead and the protruding electrode first come into contact first from the left in FIG. FIG. 44 shows an enlarged view of the semiconductor chip 30 and the film substrate 34 in this state. If the bonding tool is further lowered in this state, excessive pressure is applied to the inner lead and the protruding electrode on the left side of the drawing, and the protruding electrode slides down from the inner lead as shown in FIG. It will fit into the gap. As a result, misalignment occurs in the connection between the inner lead and the protruding electrode, causing a short circuit or a leak.

  For this reason, considering the misalignment between the inner lead and the protruding electrode during thermocompression bonding, it is necessary to expand the space between the protruding electrode and the inner lead beyond the value determined from the pattern accuracy and mounting accuracy described above, and further fine pitch It was an obstacle.

  In other words, when fine pitch is used at present, if the space between the protruding electrode and the inner lead is narrowed, a problem of misalignment of the bonding position occurs. Therefore, the space between the protruding electrode and the inner lead is maintained and the protruding electrode or inner lead is maintained. Therefore, it is necessary to reduce the width of the pitch and make it fine pitch. However, in that case, the bonding area between the protruding electrode and the inner lead is reduced, and there is a concern that the bonding reliability may be lowered.

  In view of the above situation, an object of the present invention is to provide a semiconductor device that can reduce the joining position deviation between the inner lead and the protruding electrode and can easily make the fine pitch between the inner lead and the protruding electrode.

In order to achieve the above object, a semiconductor device according to the present invention includes a plurality of first protruding electrodes disposed on a peripheral portion of a semiconductor chip, and a plurality of first lead wires formed on a film substrate. In the semiconductor device in which each of the one protruding electrode is connected to the first lead wiring and connected to the internal circuit of the semiconductor chip,
A second lead wiring group consisting of one or a plurality of second lead wirings is disposed in a region on the film substrate corresponding to a predetermined region sandwiched between the first protruding electrodes;
In at least one specific second lead wiring of the second lead wiring constituting the second lead wiring group, the specific second lead wiring and the first protrusion disposed adjacent to the second lead wiring A separation distance from a second protruding electrode arranged adjacent to the second lead wire separately from the electrode or the first protruding electrode is connected to the first lead wire and the first lead wire. The first feature is that the distance is shorter than the distance from the first protruding electrode adjacent to the protruding electrode.

  In the semiconductor device according to the first aspect of the present invention, the specific second lead wiring is further sandwiched between the two second projecting electrodes, or the first projecting electrode and the second projecting electrode. Arrangement is a second feature.

  The semiconductor device according to the second aspect of the present invention is further characterized in that the specific second lead wiring is disposed so as to be sandwiched between the two second protruding electrodes.

  The semiconductor device according to the third aspect of the present invention is further arranged such that each of the second lead wires constituting the second lead wire group is sandwiched between the second protruding electrodes. This is the fourth feature.

  In the semiconductor device according to the present invention having any one of the first to fourth characteristics, it is preferable that the specific second lead wiring is a dummy wiring.

  In the semiconductor device according to the present invention having any one of the first to fourth characteristics, it is preferable that the specific second lead wire is a wire electrically connected to the first lead wire.

  At this time, if the specific second lead wiring is a wiring electrically connected to the first lead wiring, the first protruding electrode (the second lead wiring is electrically connected to the specific second lead wiring). The second lead wiring, or a protruding electrode different from the first protruding electrode, is disposed at a position opposite to the first protruding electrode to be electrically connected.

  In the semiconductor device according to the present invention having any one of the first to fourth characteristics, it is preferable that the second protruding electrode is a dummy protruding electrode.

The semiconductor device according to the present invention having any one of the first to fourth features is further provided.
The second projecting electrode is disposed at a position farther from the first distance than the outer second projecting electrode disposed at a first distance from the end of the semiconductor chip, and the distance from the end of the semiconductor chip. Including two types of inner second protruding electrodes,
A fifth feature is that the specific second lead wiring is disposed along a gap between the outer second protruding electrode and the inner second protruding electrode. In this case, it is preferable that the outer second protruding electrodes and the inner second protruding electrodes are arranged in a staggered manner.

  The semiconductor device according to the present invention of the fifth feature further includes the specific second lead wiring and the outer second projecting electrode or the inner second projecting electrode disposed adjacent to the specific second lead wiring. Is preferably shorter than the separation distance between the first lead wiring and the first protruding electrode adjacent to the first protruding electrode connected to the first lead wiring.

  In the semiconductor device according to the present invention having any one of the first to fifth features, it is further preferable that the second lead wiring group is provided in a central portion of the side edge of the semiconductor chip. Features.

  In the semiconductor device according to the present invention having any one of the first to sixth features, it is preferable that a plurality of the second lead wiring groups are further provided on the peripheral edge of the semiconductor chip at a constant interval.

  In the semiconductor device according to the present invention having any one of the first to sixth features, it is preferable that the first protruding electrodes are further arranged in a staggered pattern.

  According to the semiconductor device of the present invention having the above characteristics, at least one second lead wiring is disposed in a predetermined misalignment prevention region at the periphery of the semiconductor chip, or the second protruding electrode is sandwiched between the lead wirings. In order to prevent misalignment, a misalignment prevention pattern is provided. As a result, the displacement of the bonding position between the first lead wiring (inner lead) and the first protruding electrode caused by the variation in the thickness of the semiconductor chip and the height of the protruding electrode is reduced, while avoiding short-circuit defects and leak defects. Thus, a semiconductor device in which the fine pitch of the protruding electrodes can be easily realized.

  Here, unlike the first lead wiring and the first protruding electrode, the second lead wiring and the second protruding electrode are basically a dummy wiring and a dummy protruding electrode that are not used for connection to the semiconductor circuit on the chip. It is. For example, by disposing a dummy pattern formed including at least one second lead wiring between the first lead wirings, the bonding position shift at the time of thermocompression bonding is reduced in the thickness of the semiconductor chip and the height of the protruding electrode. It can be limited to a predetermined amount or less regardless of variations. However, as shown in various embodiments described later, depending on the configuration, the second lead wiring and the second protruding electrode may be used for connection to a semiconductor circuit on the chip.

  In one embodiment, the second lead wiring is fitted into the gap between the two second protruding electrodes by arranging the second lead wiring so as to be sandwiched between the second protruding electrodes. As a result, as a result of the variation in the thickness of the semiconductor chip and the height of the protruding electrode, the second bonding position shift is caused even by the slip generated due to the non-uniform pressure during the pressure bonding between the semiconductor chip and the film substrate. When the lead wire comes into contact with the side surface of the second protruding electrode, it can be stopped, and the displacement of the joining position can be suppressed within the distance between the second lead wire and the second protruding electrode. In another embodiment, by increasing the width of the contact portion of the second lead wiring with the second protruding electrode, the bonding area between the second protruding electrode and the second lead wiring is increased, and the bonding position is shifted. Can be reduced.

  As a result, cost increases associated with increased device prices and connection failure rates due to higher accuracy of the bonding device in the mounting process, and increased costs due to reduced variations in semiconductor chip thickness and bump electrode height. It is possible to promote the fine pitch of the inner lead wiring while suppressing.

  In the present invention, a separate space for arranging the second lead wiring or the second protruding electrode is required in the misalignment prevention region, but the amount of bonding position shift between the first lead wiring and the first protruding electrode is reduced. As a result, it is possible to arrange the first lead wires with a smaller interval than in the prior art. As a result, a fine pitch can be easily achieved. In particular, in a multi-output semiconductor chip having a large number of first protruding electrodes, the chip size can be reduced.

In the semiconductor device according to the first embodiment of the present invention, a layout diagram showing the arrangement of lead wires and protruding electrodes Sectional drawing which shows the joining state of the lead wiring and protrusion electrode after thermocompression bonding the semiconductor chip and the film board | substrate in the semiconductor device which concerns on 1st Embodiment of this invention. The figure which shows arrangement | positioning of the lead wiring and protrusion electrode in a conventional structure for the comparison with this invention In the semiconductor device according to the first embodiment of the present invention, a layout diagram showing the arrangement of lead wires and protruding electrodes when a bonding position shift occurs. In the semiconductor device according to the first embodiment of the present invention, a layout diagram showing a bonding state between a lead wiring and a protruding electrode when a bonding position shift occurs. In the semiconductor device according to the first embodiment of the present invention, a layout diagram showing the arrangement of lead wires and protruding electrodes Sectional drawing which shows the joining state of the lead wiring and protrusion electrode after thermocompression bonding the semiconductor chip and the film board | substrate in the semiconductor device which concerns on 1st Embodiment of this invention. Another example showing the layout of lead wires and protruding electrodes in the semiconductor device according to the first embodiment of the present invention. Another example showing the layout of lead wires and protruding electrodes in the semiconductor device according to the first embodiment of the present invention. Another example showing the layout of lead wires and protruding electrodes in the semiconductor device according to the first embodiment of the present invention. Another example showing the layout of lead wires and protruding electrodes in the semiconductor device according to the first embodiment of the present invention. FIG. 6 is a layout diagram showing the arrangement of lead wires and protruding electrodes in a semiconductor device according to a second embodiment of the present invention. Another example showing a layout showing the arrangement of lead wires and protruding electrodes in a semiconductor device according to the second embodiment of the present invention Another example showing a layout showing the arrangement of lead wires and protruding electrodes in a semiconductor device according to the second embodiment of the present invention Another example showing a layout showing the arrangement of lead wires and protruding electrodes in a semiconductor device according to the second embodiment of the present invention FIG. 6 is a layout diagram showing the arrangement of lead wires and protruding electrodes in a semiconductor device according to a third embodiment of the present invention. Sectional drawing which shows the joining state of the lead wiring and protrusion electrode after thermocompression-bonding a semiconductor chip and a film substrate in the semiconductor device which concerns on 3rd Embodiment of this invention. Another example showing a layout showing the arrangement of lead wires and protruding electrodes in a semiconductor device according to the third embodiment of the present invention Another example showing a layout showing the arrangement of lead wires and protruding electrodes in a semiconductor device according to the third embodiment of the present invention Another example showing a layout showing the arrangement of lead wires and protruding electrodes in a semiconductor device according to the third embodiment of the present invention Another example showing a layout showing the arrangement of lead wires and protruding electrodes in a semiconductor device according to the third embodiment of the present invention Another example showing a layout showing the arrangement of lead wires and protruding electrodes in a semiconductor device according to the third embodiment of the present invention Another example showing a layout showing the arrangement of lead wires and protruding electrodes in a semiconductor device according to the third embodiment of the present invention Another example showing a layout showing the arrangement of lead wires and protruding electrodes in a semiconductor device according to the third embodiment of the present invention FIG. 9 is a layout diagram showing the arrangement of lead wires and protruding electrodes in a semiconductor device according to a fourth embodiment of the present invention. Sectional drawing which shows the joining state of the lead wiring and protrusion electrode after thermocompression-bonding a semiconductor chip and a film substrate in the semiconductor device which concerns on 4th Embodiment of this invention. Another example showing a layout showing the arrangement of lead wires and protruding electrodes in a semiconductor device according to the fourth embodiment of the present invention Another example showing a layout showing the arrangement of lead wires and protruding electrodes in a semiconductor device according to the fourth embodiment of the present invention Another example showing a layout showing the arrangement of lead wires and protruding electrodes in a semiconductor device according to the fourth embodiment of the present invention Another example showing a layout showing the arrangement of lead wires and protruding electrodes in a semiconductor device according to the fourth embodiment of the present invention Another example showing a layout showing the arrangement of lead wires and protruding electrodes in a semiconductor device according to the fourth embodiment of the present invention FIG. 10 is a layout diagram showing the arrangement of lead wires and protruding electrodes in a semiconductor device according to a fifth embodiment of the present invention; Sectional drawing which shows the joining state of the lead wiring and protrusion electrode after thermocompression-bonding a semiconductor chip and a film substrate in the semiconductor device which concerns on 5th Embodiment of this invention. Another example showing a layout showing the arrangement of lead wires and protruding electrodes in a semiconductor device according to the fourth embodiment of the present invention Another example showing a layout showing the arrangement of lead wires and protruding electrodes in a semiconductor device according to the fourth embodiment of the present invention Another example showing a layout showing the arrangement of lead wires and protruding electrodes in a semiconductor device according to the fourth embodiment of the present invention The figure which shows an example of the arrangement | positioning location of a position shift prevention area | region in the semiconductor device which concerns on this invention. The figure which shows an example of the arrangement | positioning location of a position shift prevention area | region in the semiconductor device which concerns on this invention. Layout diagram showing the layout of lead wires and protruding electrodes in the conventional configuration Layout diagram showing the layout of lead wires and protruding electrodes in the conventional configuration Layout diagram of the layout of lead wires and protruding electrodes showing how the bonding position shift occurs in a conventional semiconductor device The figure which shows an example of the apparatus which heat-presses a semiconductor chip and a film substrate The figure which shows the mode of the thermocompression bonding of the semiconductor chip and the film substrate when the thickness of the semiconductor chip and the height of the protruding electrode vary. Enlarged view showing the state of thermocompression bonding between the semiconductor chip and the film substrate when there is variation in the thickness of the semiconductor chip and the height of the protruding electrode Enlarged view showing the state of thermocompression bonding between the semiconductor chip and the film substrate when there is variation in the thickness of the semiconductor chip and the height of the protruding electrode

  An embodiment of the present invention will be described below with reference to FIGS. In the drawings shown below, for the convenience of explanation, the main parts are emphasized and the dimensional ratios such as the thicknesses and lengths of the constituent members may not necessarily match the actual dimensional ratios.

<First Embodiment>
FIG. 1 is a layout diagram showing the arrangement of lead wires and protruding electrodes in a semiconductor device according to an embodiment of the present invention (hereinafter referred to as “present invention device 1” as appropriate). FIG. 2 shows a cross-sectional view after thermocompression bonding in the AA ′ direction of FIG. FIG. 1 is an arrangement layout of lead wirings and protruding electrodes when the present invention is applied to FIG. 3 which is the prior art.

  As shown in FIG. 1 and FIG. 2, a plurality of first protruding electrodes 11 are arranged on the periphery of the semiconductor chip 20, and each of the first protruding electrodes 11 is formed on a film substrate 21. The first lead wires 12 extending inward of the semiconductor chip 20 beyond 22 are connected separately. The film substrate 21 is made of, for example, a polyimide tape. The first protruding electrode 11 is connected to the internal circuit of the semiconductor chip 20, and thereby the electrical connection between the first lead wiring 12 and the internal circuit of the semiconductor chip 20 is made.

  On the other hand, the second lead wiring 14 is disposed on the film substrate 21 in a predetermined region (a misalignment prevention region) 23 in the peripheral portion of the semiconductor chip 20 sandwiched between the first electrodes 11. Further, the second lead wiring 14 is arranged so as to be sandwiched between two second protruding electrodes 13 arranged on the peripheral edge of the semiconductor chip 20. In the present embodiment, the second protruding electrode 13 and the second lead wiring 14 are dummy protruding electrodes and lead wirings that are not connected to the internal circuit of the semiconductor chip 20.

  The first protruding electrode 11 and the second protruding electrode 13 are made of, for example, gold, and the first lead wiring 12 and the second lead wiring 14 are made of, for example, a copper foil plated with tin. . When the first protruding electrode 11 and the first lead wiring 12 are joined by thermocompression bonding, the first lead wiring 12 is formed in the first protruding electrode 11 because the protruding electrode is made of a softer material than the lead wiring. Is done. At this time, a gold-tin metal junction is formed between the first protruding electrode 11 and the first lead wiring 12, and thereby the first protruding electrode 11 and the first lead wiring 12 are electrically connected. Considering the joining position shift at the time of thermocompression bonding of the first protruding electrode 11 and the first lead wiring 12, the first lead wiring 12 of the first protruding electrode 11 is prevented from being disconnected or short-circuited due to the bonding position deviation. The width in the direction perpendicular to the extending direction is secured wider than that of the first lead wiring 12.

  On the other hand, since the second lead wiring 14 is disposed so as to be sandwiched between the second protruding electrodes 13, the second lead wiring 14 is just fitted into the gap between the second protruding electrodes 13 as a result of thermocompression bonding. It is formed to get stuck.

  For this reason, even when the bonding position shift occurs between the first protruding electrode 11 and the first lead wiring 12 due to the variation in the thickness of the semiconductor chip and the height of the protruding electrode, the bonding position shift is the first. It stops when the two-lead wiring 14 comes into contact with the side surface of the second protruding electrode 13, and the joining position shift does not proceed any further. FIG. 4 shows the arrangement of the lead wire and the protruding electrode in a state in which the joining position shift occurs in the device 1 of the present invention and the protruding electrodes 11 and 13 slide to the right in FIG. Indicates. FIG. 5 shows a cross-sectional view after thermocompression bonding in the A-A ′ direction of FIG. 4.

  As shown in FIGS. 4 and 5, in the device 1 of the present invention, the arrangement of the second protruding electrode 13 and the second lead wiring 14 makes it possible to reduce the thickness of the semiconductor chip and the height of the protruding electrode during thermocompression bonding. It is possible to forcibly suppress the bonding position shift to be equal to or less than the separation distance X2 between the second lead wire 14 and the second protruding electrode 13 adjacent to the second lead wire.

  In FIG. 1 and FIG. 3, for example, the interval (pitch) between the first protruding electrodes 11 is 20 μm, the interval (pitch) between the first lead wires 12 is 20 μm, the width of the first protruding electrode 11 is 16 μm, The width of the lead wiring 12 is 8 μm. In this case, since the separation distance X1 between the first lead wire 12 and the first bump electrode 11 adjacent to the first bump electrode 11 connected to the first lead wire is 8 μm, a short circuit occurs when the bonding position shift is 8 μm or more. Leads to failure.

  In the case of the arrangement layout of the conventional method (FIG. 3), the alignment accuracy in consideration of the variation in the thickness of the semiconductor chip and the height of the protruding electrode is 7.8 μm, and the separation distance X1 is 8 μm. I'm satisfied with the conditions that don't happen. However, since the alignment accuracy has almost no margin for the separation distance X1, if the temperature factor or the variation factor of the thickness of the semiconductor chip or the height of the protruding electrode exceeds the assumption, the displacement of the bonding position more than expected will occur. As a result, there is a risk of causing a short circuit failure between the first protruding electrode 11 and the first lead wiring 12.

  On the other hand, in FIG. 1, since the maximum misalignment of the joining position occurs only in the above-mentioned separation distance X2, the first protrusion electrode 11 and the first lead are set by setting the separation distance X2 smaller than the separation distance X1. The distance between the wirings 12 can be maintained at a predetermined distance (X1-X2) or more, and a short circuit failure can be prevented.

  For example, in FIG. 1, the distance between the two second protruding electrodes 13 is 8 μm, and the width of the second lead wiring 14 is 4 μm. Since the pattern accuracy of the first and second protruding electrodes and the mounting accuracy of the bonding device for bonding the film substrate 21 and the semiconductor chip 20 can be controlled with high accuracy, the second lead wiring is mounted in a state where the pressure bonding device is mounted. The separation distance X2 between 14 and the second protruding electrode 13 can be set to 2 μm.

  In this case, even when a force that causes the first lead wiring 12 to deviate from the first protruding electrode due to thermal expansion, chip height variation, or the like during thermocompression bonding, a bonding position shift of 2 μm or more does not occur. For this reason, as long as the separation distance X1 is set to a value larger than 2 μm, the intervals between the first protruding electrodes 11 and the intervals between the first lead wires 12 can be arranged close to each other, and a fine pitch can be achieved. Is easily possible.

  In the device 1 of the present invention, a space (position displacement prevention region 23) for disposing the second protruding electrode 13 and the second lead wiring 14 is required, but the bonding position displacement amount can be limited to the separation distance X2 or less. The interval between the first lead wires 12 can be arranged narrower than the prior art. As a result, especially in a multi-output semiconductor chip having a large number of first protruding electrodes, the spacing between the first lead wires 12 can be narrowed rather than the increase in chip mounting area accompanying the provision of the misalignment prevention region 23. The effect of reducing the area is great, and the chip size can be reduced.

  In the device 1 of the present invention, the displacement of the bonding position is limited to a predetermined value or less by arranging the two second protruding electrodes 13 and the second lead wiring 14, but the present invention is not limited to this. . By using at least one second lead wiring 14, it is possible to limit the joining position shift.

  In the semiconductor device shown in the arrangement layout of FIG. 6 (hereinafter referred to as “present invention device 2” as appropriate), the second lead wire 14 is a predetermined region (position) of the periphery of the semiconductor chip 20 sandwiched between the first lead wires 12. Displacement prevention region) 23 is disposed on film substrate 21. The second lead wiring 14 is a dummy lead wiring that is not connected to the internal circuit of the semiconductor chip 20. FIG. 7 shows a cross-sectional view after thermocompression bonding in the A-A ′ direction of FIG. 6.

  In FIG. 6, the second lead wires 14 are arranged so as to be sandwiched between the first protruding electrodes 11 respectively connected to the adjacent first lead wires 12. As a result, the second lead wiring 14 is formed so as to fit into the gap between the first protruding electrodes 11 as shown in FIG.

  For this reason, even when the bonding position shift occurs between the first protruding electrode 11 and the first lead wiring 12 due to the variation in the thickness of the semiconductor chip and the height of the protruding electrode, the bonding position shift is the first. The two-lead wiring 14 stops when it contacts the side surface of the first protruding electrode 11, and the joining position shift does not proceed any further. Further, since the second lead wiring 14 is a dummy lead wiring, even if it comes into contact with the first protruding electrode 11, there is no problem of a circuit short circuit.

  That is, in the device 2 of the present invention, due to the arrangement of the second lead wiring 14, the bonding position shift at the time of thermocompression bonding due to the variation in the thickness of the semiconductor chip and the height of the protruding electrode is forcibly changed from the second lead wiring 14. It is possible to suppress the distance X3 or less from the first protruding electrode 11 adjacent to the second lead wiring 14. Then, the separation distance X3 is set to be smaller than the separation distance X1 between the first lead wire 12 and the first protrusion electrode 11 adjacent to the first protrusion electrode 11 connected to the first lead wire. The distance between the protruding electrode 11 and the first lead wiring 12 can be maintained at a predetermined distance (X1-X3) or more, and a short circuit failure can be prevented.

  In addition, a plurality of second lead wirings 14 can be arranged in the misalignment prevention region 23. FIG. 8 shows an example of an arrangement layout of the device 1 of the present invention when there are two second lead wires 14 and FIG. 9 shows three second lead wires 14.

  In FIG. 8, a second lead wiring group consisting of two second lead wirings 14 (14a, 14b) is arranged in the misregistration prevention region 23 sandwiched between the first electrodes 11, and the second lead wiring group on the left side of the figure is arranged. The two lead wirings 14a are arranged so as to be sandwiched between the first projecting electrodes 11 and the second projecting electrodes 13, and the second lead wiring 14b on the right side of the figure is sandwiched between the two second projecting electrodes 13. Are arranged as follows. With such a configuration, the first projecting electrode adjacent to the second lead wiring 14a and the second lead wiring 14a can be prevented from shifting the bonding position during thermocompression bonding due to variations in the thickness of the semiconductor chip and the height of the projecting electrode. 11 and a distance X2 or less between the second lead wirings 14a and 14b and the second protruding electrode 13 adjacent to each of the second lead wirings can be reliably suppressed.

  In FIG. 9, a second lead wiring group composed of a plurality (three) of second lead wirings 14 is disposed in the misalignment prevention region 23 sandwiched between the first electrodes 11, and each of the second lead wirings 14 is The second protruding electrodes 13 are arranged so as to be sandwiched between them. With this configuration, the bonding position shift at the time of thermocompression bonding due to the variation in the thickness of the semiconductor chip and the height of the protruding electrode can be reduced by the second protruding electrode adjacent to the second lead wiring 14 and the second lead wiring. 13 can be reliably suppressed to a distance X2 or less.

  Further, as shown in the layout of FIG. 10, the second lead wiring 14 may be wider than the first lead wiring 12. By making the width of the second lead wiring 14 wide, it is possible to prevent the second lead wiring from being peeled off due to the stress generated when the positional deviation is suppressed, and to reliably suppress the positional deviation of the bonding at the time of thermocompression bonding.

  In the above embodiment, the second lead wiring 14 is a dummy lead wiring that is not connected to the internal circuit of the semiconductor chip 20. The second lead wiring 14 does not come into contact with the first protruding electrode 11 or the second protruding electrode 13 as long as the joining position does not shift. Here, regarding the method of configuring the dummy wiring, the present invention is not limited to the above configuration, and the second lead wiring 14 is located inside the end 22 of the semiconductor chip 20 as shown in the layout of FIG. The lead wires may be separated by forming an isolated lead wire, or may be divided outside the end of the semiconductor chip 20 to form an isolated lead wire. Even if the second lead wiring 14 is connected to a circuit outside the semiconductor chip 20, no other problem occurs as long as it is not connected to the internal circuit of the semiconductor chip 20.

Second Embodiment
In the first embodiment, the second lead wiring is a dummy lead wiring that is not connected to the internal circuit of the semiconductor chip 20. However, a configuration in which the second lead wiring is connected to the first lead wiring 12 is also conceivable. In the semiconductor device shown in the layout of FIG. 12 (hereinafter, referred to as “the device 3 of the present invention” as appropriate), the second lead wiring 14 is located on the periphery of the semiconductor chip 20 sandwiched between the first lead wirings 12 (12a, 12b). The second lead wiring 14 is arranged in a predetermined region (positional displacement prevention region) 23, and the second lead wiring 14 is connected to one adjacent first lead wiring 12a. Therefore, the second lead wiring 14 and the internal circuit of the semiconductor chip 20 are connected via the first protruding electrode 11a connected to the first lead wiring 12a.

  However, since the second lead wiring 14 is disposed so as to be sandwiched between the second protruding electrodes 13 (13a, 13b), bonding at the time of thermocompression bonding due to variations in the thickness of the semiconductor chip and the height of the protruding electrodes. The positional shift can be suppressed to a distance X2 or less between the second lead wire 14 and the second protruding electrodes 13a and 13b adjacent to the second lead wire 14. Further, since the second protruding electrodes 13a and 13b are dummy protruding electrodes, the second lead wiring 14 comes into contact with the side surfaces of the second protruding electrodes 13a and 13b, and as a result, the first lead wiring 12a becomes the second protruding electrode 13a. , 13b does not cause a problem of short circuit.

  In this case, as shown in the layout of FIG. 13, the second protruding electrode 13a may be omitted and the second lead wiring 14 may be sandwiched between the first protruding electrode 11a and the second protruding electrode 13b. I do not care. However, in FIG. 12, since the second lead wiring 14 is connected to the first lead wiring 12a, there is a risk that the first lead wiring 12a and the first lead wiring 12b are short-circuited via the second lead wiring 14. The arrangement of the second protruding electrode 13b is omitted, and the same configuration as that of the semiconductor device 2 shown in FIG. That is, in the arrangement layout shown in FIG. 12, the second lead wiring 14 is connected with the second lead wiring 14 sandwiched so that the second lead wiring 14 and the first protruding electrode 11b do not come into contact with each other due to the displacement of the bonding position. The second protruding electrode or another second lead wiring needs to be disposed at a position facing the first protruding electrode 11a connected to the first lead wiring 12a.

  In the arrangement layout of FIG. 14, two second lead wires 14a and 14b are arranged in the misalignment prevention region 23 at the periphery of the semiconductor chip 20, and the second lead wire 14a includes the first lead wire 12a and the second lead wire. 14b is connected to the first lead wiring 12b. In this case, the second lead wiring 14a and the second lead wiring 14b are formed separately and are not electrically connected, so that the first lead wiring 12a and the first lead wiring 12b are short-circuited without providing the second protruding electrode 13. There is no danger of doing. The joining position shift at the time of thermocompression bonding can be suppressed to a distance X3 or less regardless of whether the protruding electrode slides to the right or to the left in FIG.

  Further, the layout shown in FIG. 15 is such that the second lead wiring 14b connected to the first lead wiring 12b in FIG. 14 is an isolated wiring that is not connected to the first lead wiring 12b.

<Third Embodiment>
Hereinafter, an example in which the present invention is applied to a semiconductor chip (see FIG. 39) in which the first protruding electrodes are arranged in a staggered manner will be described. FIG. 16 is a layout diagram showing the arrangement of lead wires and protruding electrodes in a semiconductor device according to an embodiment of the present invention (hereinafter referred to as “present invention device 4” as appropriate). FIG. 17 is a cross-sectional view after thermocompression bonding in the AA ′ direction and the BB ′ direction in FIG.

  As shown in FIGS. 16 and 17, a plurality of first protruding electrodes 15, 16 are arranged on the periphery of the semiconductor chip 20, and each of the first protruding electrodes 15, 16 is formed on the film substrate 21. The first lead wires 12 extending inward of the semiconductor chip 20 beyond the semiconductor chip end 22 are connected separately. Here, the first protruding electrode is disposed at a position where the distance from the end portion 22 of the semiconductor chip 20 is relatively short, the outer first protruding electrode 15 positioned relatively outside, and the end portion of the semiconductor chip 20. The inner first protruding electrode 16 is arranged at a relatively far position from the inner side 22 and is relatively inward. The outer first protruding electrodes 15 and the inner first protruding electrodes 16 are arranged in a staggered manner along the circumferential direction of the semiconductor chip 20, that is, alternately. Each of the outer first protruding electrode 15 and the inner first protruding electrode 16 is connected to the internal circuit of the semiconductor chip 20, and thereby, the first lead wiring 12 and the internal circuit of the semiconductor chip 20 are electrically connected. .

  On the other hand, the second lead wiring 14 is arranged on the film substrate 21 in a predetermined region (a misalignment prevention region) 23 on the peripheral edge of the semiconductor chip 20 sandwiched between the first protruding electrodes 11. Further, the second lead wiring 14 is disposed so as to be sandwiched between the second protruding electrodes 17 and 18. In the present embodiment, the second protruding electrodes 17 and 18 and the second lead wiring 14 are dummy protruding electrodes and lead wirings that are not connected to the internal circuit of the semiconductor chip 20.

  Here, the second protruding electrode is disposed at a position where the distance from the end portion 22 of the semiconductor chip 20 is relatively short, the outer second protruding electrode 17 positioned relatively outside, and the end portion of the semiconductor chip 20. The inner second protruding electrode 18 is arranged at a relatively far position from the inner side 22 and is relatively inward. That is, the second protruding electrode includes the outer second protruding electrode 17 arranged at a first distance from the end 22 of the semiconductor chip 20 and the outer second protruding electrode at a position farther than the first distance. The inner second projecting electrode 18 is arranged inside the semiconductor chip 20 relative to the electrode 17, and the outer second projecting electrode 17 and the inner second projecting electrode 18 are staggered along the circumferential direction of the semiconductor chip 20. Arranged.

  In this way, the second lead wiring 14 is arranged in a bifurcated fork shape along the gap between the adjacent three outer second protruding electrodes 17 arranged in a staggered manner and the two adjacent inner second protruding electrodes 18. ing. The distance between the outer second protruding electrode 17 and the second lead wiring 14 and the distance between the inner second protruding electrode 18 and the second lead wiring 14 are the same at X2.

  As described above, since the second lead wiring 14 is disposed so as to be sandwiched between the outer second projecting electrode 17 and the inner second projecting electrode 18, as a result of thermocompression bonding, as shown in FIG. The wiring 14 is formed so as to fit exactly in the gap between the outer second protruding electrodes 17 and the gap between the inner second protruding electrodes 18.

  As a result, due to variations in the thickness of the semiconductor chip and the height of the protruding electrodes, a displacement of the bonding position between the outer first protruding electrode 15 or the inner first protruding electrode 16 and the first lead wiring 12 occurs during thermocompression bonding. Even if it occurs, the joining position shift stops when the second lead wiring 14 contacts either side surface of the outer second projecting electrode 17 and the inner second projecting electrode 18, and the joining position shift further proceeds. There is no.

  That is, in the device 4 of the present invention, due to the arrangement pattern composed of the outer second protruding electrode 17, the inner second protruding electrode 18, and the second lead wiring 14, it is caused by variations in the thickness of the semiconductor chip and the height of the protruding electrode. It is possible to forcibly suppress the displacement of the bonding position during thermocompression bonding to a distance X2 or less between the second lead wiring 14 and the outer second protruding electrode 17 or the inner second protruding electrode 18 adjacent to the second lead wiring. It becomes.

The separation distance X2 is defined as the separation distance between the first lead wiring 12 and the inner first projection electrode 16 adjacent to the outer first projection electrode 15 connected to the first lead wiring 12, and the first lead wiring 12. The distance between the outer first protruding electrode 15 adjacent to the inner first protruding electrode 16 connected to the first lead wiring 12 (X1 in this embodiment) is set to be smaller than the outer first Both the distance between the protruding electrode 15 and the first lead wiring 12 and the distance between the inner first protruding electrode 16 and the first lead wiring 12 can be maintained at a predetermined distance (X1-X2) or more, thereby causing a short circuit defect. Can be prevented.

  In the layout shown in FIG. 18, the second lead wiring 14 is triangulated so as to be along a gap sandwiched between four adjacent outer second protruding electrodes 17 and three adjacent inner second protruding electrodes 18. It is an example formed in the fork shape.

  In the arrangement layout shown in FIG. 19, the second lead wiring 14 is quadrangular so as to follow a gap sandwiched between the five adjacent outer second protruding electrodes 17 and the four adjacent inner second protruding electrodes 18. It is an example formed in the fork shape.

  In FIGS. 18 and 19, by increasing the area of the region sandwiched between the outer second protruding electrode 17 or the inner second protruding electrode 18 of the second lead wiring 14, the displacement of the bonding position at the time of thermocompression bonding can be effectively reduced. It is possible to suppress the distance between the two-lead wiring 14 and the outer second protruding electrode 17 or the inner second protruding electrode 18 to less than or equal to X2.

  In FIG. 16, FIG. 18, and FIG. 19, the second lead wiring 14 extends from the outside of the semiconductor chip to the inside of the chip beyond the end 22 of the semiconductor chip. For example, FIG. Thus, it is good also as an isolated 2nd lead wiring arrange | positioned only to the area | region on a semiconductor chip. Note that FIG. 20 shows the arrangement of the second lead wiring 14 only in the region on the semiconductor chip in the arrangement layout of FIG.

  Further, as shown in FIGS. 21 and 22, a plurality of second lead wires are arranged along the gap with the outer second projecting electrode 17 or the inner second projecting electrode 18, and a part of the second lead wires is connected to the first lead wire. It does not matter if they are connected. In the arrangement layout shown in FIG. 19, the second lead wiring arranged in the misalignment prevention region 23 is a second lead wiring group including the second lead wirings 14c to 14e, and the second lead wiring 14c is the first lead wiring 14c. This is connected to the lead wiring 12c. The first lead wiring 12c and the second lead wiring 14c are integrally formed.

  FIG. 22 shows that in the layout shown in FIG. 19, the second lead wiring arranged in the misalignment prevention region 23 is a second lead wiring group composed of the second lead wirings 14f to 14h, and the second lead wiring 14f is the first lead wiring. The lead wiring 12c and the second lead wiring 14h are connected to the first lead wiring 12d. The first lead wiring 12c and the second lead wiring 14f, and the first lead wiring 12d and the second lead wiring 14h are integrally formed, respectively.

  21 and 22, the outer second protruding electrode 17 or the inner second protruding electrode 18 is a dummy protruding electrode, and the second lead wiring 14c (14f) is in contact with the side surfaces of the inner second protruding electrodes 18a and 18b. As a result, even if the first lead wiring 12c is connected to the inner second protruding electrodes 18a and 18b, the problem of a circuit short circuit does not occur. Similarly, in FIG. 22, the second lead wiring 14h contacts the side surfaces of the inner second protruding electrodes 18c and 18d, and as a result, the first lead wiring 12d is connected to the inner second protruding electrodes 18c and 18d. However, the problem of short circuit does not occur.

  Further, in FIGS. 23 and 24, the first protruding electrodes (the outer first protruding electrode 15 and the inner first protruding electrode 16) are arranged in an irregular staggered manner, and the first lead wiring 11 is bent and arranged. This is an example of applying the present invention to a semiconductor chip (see FIG. 40). The second lead wiring 14 is disposed along a gap sandwiched between the outer second projecting electrode 17 and the inner second projecting electrode 18, and the misalignment of the joining position during the thermocompression bonding with the second lead wiring 14 and the outer second projecting electrode 18. The distance between the two protruding electrodes 17 or the inner second protruding electrode 18 can be suppressed to less than or equal to X2.

  According to the above-described present invention devices 1 to 4 and the modification thereof, the thickness of the semiconductor chip and the protruding electrode are determined by the pattern constituted by the second lead wiring 14 and the second protruding electrode arranged in the misalignment prevention region 23. The misalignment of the bonding position due to the height variation can be limited to a predetermined amount or less, thereby realizing a semiconductor device that can easily achieve fine pitch and can easily reduce the chip size.

<Fourth embodiment>
FIG. 25 is a layout diagram showing the arrangement of lead wirings and protruding electrodes in a semiconductor device according to an embodiment of the present invention (hereinafter referred to as “present invention device 5” as appropriate). FIG. 26 shows a cross-sectional view after thermocompression bonding in the AA ′ direction of FIG.

  In the device 5 of the present invention shown in FIG. 25, the first protruding electrode (outer first protruding electrode 15) is located at a position where the distance from the end 22 of the semiconductor chip 20 is relatively close to the peripheral edge of the semiconductor chip 20. Several are arranged. The outer first protruding electrodes 15 are separately connected to the first lead wires 12 formed on the film substrate 21 and extending inward of the semiconductor chip 20 beyond the semiconductor chip end 22. As a result, the first lead wiring 12 and the internal circuit of the semiconductor chip 20 are electrically connected.

  Here, a part of the first lead wiring 12 extends inward of the chip 20 from the outer first protruding electrode 15, and the distance from the end 22 of the semiconductor chip 20 is longer than the outer first protruding electrode 15. It is sandwiched between the inner second protruding electrodes 18 arranged at a distant position. The inner second protruding electrode 18 is a dummy protruding electrode that is not connected to the internal circuit of the semiconductor chip 20.

  In other words, the device 5 of the present invention provides the misalignment prevention region 23 in the region inside the peripheral edge of the semiconductor chip 20, and arranges the second lead wiring 14 in the misalignment prevention region 23, while the second lead wiring. 14 is configured to be connected to the adjacent first lead wiring. By disposing the second lead wiring 14 between the inner second projecting electrodes 18, the displacement of the joining position during thermocompression bonding is separated from the distance between the second lead wiring 14 and the inner second projecting electrode 18. X2 or less can be suppressed. The second lead wiring 14 is electrically connected to the outer first projecting electrode 15, but the inner second projecting electrode 18 is a dummy projecting electrode, so that the problem of short circuit does not occur.

  The separation distance X2 is set to be smaller than the separation distance X1 between the first lead wiring 12 and the outer first projection electrode 15 adjacent to the outer first projection electrode 15 connected to the first lead wiring 12. In addition, the distance between the outer first protruding electrode 15 and the first lead wiring 12 can be maintained at a predetermined distance (X1-X2) or more, and a short circuit failure can be prevented.

  By configuring in this way, since the second lead wiring is not arranged between the first protruding electrodes (outer first protruding electrodes 15) as compared with the above-described embodiments, the number of first protruding electrodes (that is, It is possible to suppress misalignment without reducing the number of input / output terminals of the chip.

  Here, since the protruding electrode (at least the outer first protruding electrode 15) is formed so as to be connected to the uppermost layer wiring, wiring other than the uppermost layer wiring can be arranged under the protruding electrode. Therefore, even if the inner second protruding electrode 18 is provided on the chip inner side than the outer first protruding electrode 15, the influence on the integration degree of the internal circuit is small.

  Further, the outer first protruding electrode 15 is connected to the uppermost wiring layer of the internal circuit which is an integrated circuit, but the inner second protruding electrode 18 does not need to be electrically connected to the internal circuit. It is not always necessary to connect to the uppermost wiring layer. If there is no problem in the adhesion strength with the inner second projecting electrode 18, the second projecting electrode can be disposed on the protective film of the uppermost wiring layer of the internal integrated circuit. As described above, by disposing the inner second protruding electrode 18 on the protective film, the uppermost layer wiring can be freely disposed below the inner second protruding electrode 18, and the degree of integration of the internal circuit is increased. The influence of can be eliminated.

  In FIG. 25, the second lead wiring 14 is connected to the first lead wiring 12, but it may be an isolated wiring that is not connected to the first lead wiring 12 as in the layout shown in FIG. .

  Further, as shown in the layout of FIGS. 28 and 29, another second lead wiring 14i may be disposed in a region where the inner second protruding electrodes 18 face each other. The second lead wiring 14i may be connected to the first lead wiring 12e as shown in FIG. 28, or may be an isolated wiring as shown in FIG.

  In addition, as shown in the layout of FIG. 30, the second lead wiring 14 is not connected to the first lead wiring 12 (that is, not connected to the outer first protruding electrode 15 via the first lead wiring 12). Further, it may be a dummy wiring extending beyond the semiconductor chip end 22 to the outside of the semiconductor chip 20. 30 shows the arrangement layout of the device 1 of the present invention shown in FIG. 1 described above, and the second lead electrode 12 and the second lead wire 12 are arranged by arranging the second bump electrode 13 inside the chip with respect to the first bump electrode 11. This corresponds to a configuration in which the distance from the lead wiring 14 is narrowed.

  Further, as shown in the layout of FIG. 31, a part of the first lead wiring 12 is extended to the inside of the semiconductor chip 20 and disposed at a position where the distance from the end 22 of the semiconductor chip 20 is relatively far. A position where the distance from the end 22 of the semiconductor chip 20 is closer to the inner first protruding electrode 16 so as to be connected to the inner first protruding electrode 16 and sandwich the lead wiring connected to the inner first protruding electrode 16. It is also possible to arrange the second projecting electrode (outer second projecting electrode 17). In other words, FIG. 31 shows that the second lead wiring 14 extends inward of the semiconductor chip 20 beyond the semiconductor chip end 22 and is connected to the first lead wiring 12f disposed inside the end 22 of the semiconductor chip. Thus, a configuration is shown in which the second lead wiring 14 is electrically connected to the inner first protruding electrode 16 via the first lead wiring 12f. FIG. 31 shows the arrangement layout of the device 1 of the present invention shown in FIG. 1 described above, in which the second lead wiring 14 extends to the inner side of the semiconductor chip 20 and is electrically connected to the inner first protruding electrode 16. It corresponds to what you did.

  According to the device 5 of the present invention and the modification thereof, the thickness of the semiconductor chip and the height of the protruding electrode are determined by the pattern composed of the second lead wiring 14 and the second protruding electrode arranged in the misalignment prevention region 23. The bonding position shift at the time of thermocompression bonding due to the variation in the thickness can be limited to a predetermined amount or less, thereby realizing a semiconductor device in which a fine pitch can be easily formed and a chip size can be easily reduced.

<Fifth Embodiment>
FIG. 32 is a layout diagram showing the arrangement of lead wirings and protruding electrodes in a semiconductor device according to an embodiment of the present invention (hereinafter referred to as “present invention device 6” as appropriate). FIG. 33 is a cross-sectional view after thermocompression bonding in the AA ′ direction and the BB ′ direction in FIG.

  In the device 6 of the present invention shown in FIGS. 32 and 33, the first protruding electrode (outer first protruding electrode 15) is relatively close to the peripheral edge of the semiconductor chip 20 from the end 22 of the semiconductor chip 20. A plurality of positions are arranged. The outer first protruding electrodes 15 are separately connected to the first lead wires 12 formed on the film substrate 21 and extending inward of the semiconductor chip 20 beyond the semiconductor chip end 22. As a result, the first lead wiring 12 and the internal circuit of the semiconductor chip 20 are electrically connected.

  On the other hand, a plurality of second projecting electrodes (inner second projecting electrodes 18) are arranged on the periphery of the semiconductor chip 20 at positions relatively far from the end 22 of the semiconductor chip 20. The inner second protruding electrodes 18 are separately connected to the second lead wirings 14 formed on the film substrate 21 and extending inward of the semiconductor chip 20 beyond the semiconductor chip end 22. That is, in the device 6 of the present invention, the outer first protruding electrode 15 is disposed at a first distance from the end 22 of the semiconductor chip 20, and the inner second protruding electrode 18 is located at a position farther than the first distance. The outer first protruding electrodes 15 are arranged inside the semiconductor chip 20, and the outer first protruding electrodes 15 and the inner second protruding electrodes 18 are arranged in a staggered manner.

  Here, the width of the second lead wiring 14 is wider than that of the first lead wiring 12 in the contact area with the inner second protruding electrode 18. In the present embodiment, the width of the second lead wire 14 in the contact region is wider than the width of the inner second protruding electrode 18 in the direction perpendicular to the extending direction of the second lead wire 14, and the second lead The wiring 14 is disposed so as to cover the inner second protruding electrode 18.

  As described above, in the misalignment prevention region 23 provided in the inner region of the peripheral edge of the semiconductor chip 20, the width of the contact region of the second lead wire 14 with the second protruding electrode is wider than that of the first lead wire 12. By increasing the contact area between the second lead wiring 14 and the inner second projecting electrode 18, the outer first projecting electrode 15 slides from the first lead wiring 12, and the inner second projecting electrode 18 second lead. It is possible to suppress sliding movement from the wiring 14 and to make it difficult to cause a joining position shift.

  In particular, the width of the contact area of the second lead wiring 14 with the second protruding electrode is made wider than the width of the inner second protruding electrode 18 in the direction perpendicular to the extending direction of the second lead wiring 14, thereby The width of the two protruding electrodes 18 is the width of the contact area with the inner second protruding electrode 18. Furthermore, by arranging the second lead wiring 14 so as to cover the inner second protruding electrode 18, the area of the inner second protruding electrode 18 becomes the contact area with the inner second protruding electrode 18, and the contact area is maximized. The

  In this case, in order to increase the contact area between the second lead wiring 14 and the inner second protruding electrode 18, the area of the inner second protruding electrode 18 may be set large. Preferably, the area of the inner second protruding electrode 18 is set to be larger than the area of the outer first protruding electrode 15.

  In the device 6 of the present invention, since the first lead wiring 12 does not extend to the inside of the chip where the inner second protruding electrode 18 is located, the direction perpendicular to the extending direction of the second lead wiring 14 of the inner second protruding electrode 18 Is wider than the outer first protruding electrode 15 and the area of the inner second protruding electrode 18 is easily larger than that of the outer first protruding electrode 15. By increasing the area of the inner second protruding electrode 18, the contact area with the second lead wiring 14 is increased, and the effect of preventing the first lead wiring 12 and the second lead wiring 14 from sliding off the protruding electrode is improved. To do.

  In the device 6 of the present invention, the inner second protruding electrode 18 is connected to the internal circuit of the semiconductor chip 20. The second lead wiring 14 is connected to an external circuit, and is connected to the internal circuit of the chip 20 via the inner second protruding electrode 18. In other words, the second lead wiring 14 and the inner second protruding electrode 18 can be a non-dummy wiring and a protruding electrode, respectively.

  However, the at least one inner second protruding electrode 18 may be a dummy protruding electrode that is not connected to the internal circuit of the semiconductor chip 20.

  The arrangement layout shown in FIG. 34 is obtained by combining the arrangement layout of the device 6 of the present invention with the arrangement layout of the device 2 of the present invention shown in FIG. 4 so as to be covered by at least one second lead wiring 14j. The inner second projecting electrode 18e disposed in the region is used as a dummy wiring and projecting electrode that are not connected to the internal circuit of the semiconductor chip 20. At this time, it is preferable to design the separation distance between the second lead wiring 14 j and the first lead wiring 12 to be shorter than the separation distance between the other second lead wiring 14 and the first lead wiring 12.

  By adopting such a configuration, it is possible to suppress the joining position deviation at the time of thermocompression bonding by the contact area between the second lead wirings 14 and 14j and the inner second projecting electrodes 18 and 18e, and to prevent the joining position deviation from occurring in the second lead wiring. 14j is stopped when it contacts the side surfaces of the outer first protruding electrodes 15a and 15b adjacent thereto, and the amount of displacement of the bonding position is within the distance X3 between the second lead wiring 14j and the adjacent outer first protruding electrodes 15a and 15b. Can be suppressed.

  35 is a combination of the layout of the device 6 of the present invention with the layout of the device 1 of the present invention shown in FIG. 1, and is sandwiched between at least one second lead wiring 14k. The protruding electrodes 17a and 17b as dummy protruding electrodes that are not connected to the internal circuit of the semiconductor chip 20 are arranged on the outer side where the distance from the end 22 of the semiconductor chip 20 is relatively shorter than the inner second protruding electrode 18. Yes. By adopting such a configuration, it is possible to suppress the joining position shift at the time of thermocompression bonding by the contact area between the second lead wirings 14 and 14k and the inner second projecting electrode 18, and to prevent the joining position deviation from the second lead wiring 14k. It stops when it contacts the side surfaces of the adjacent projecting electrodes 17a and 17b, and the amount of displacement of the joining position can be suppressed within the distance X2 between the second lead wiring 14k and the outer second projecting electrodes 17a and 17b adjacent thereto. . In this case, since the protruding electrodes 17a and 17b are dummy protruding electrodes, the second lead wiring 14k and the inner second protruding electrode 18 in contact with the second lead wiring 14k are connected to the internal circuit of the semiconductor chip 20. Can be used as wiring and electrodes. However, the inner second protruding electrode 18 in contact with the second lead wiring 14k may be a dummy protruding electrode that is not connected to the internal circuit of the semiconductor chip 20, and the second lead wiring 14k may be a dummy wiring.

  Furthermore, a semiconductor device according to an embodiment of the present invention shown in the layout of FIG. 36 (hereinafter referred to as “present invention device 7” as appropriate) is connected to the first protruding electrode (outer first protruding electrode 15). A part of one lead wiring is connected to the second lead wiring 14 extending inward of the semiconductor chip 20, and the second lead wiring has a larger area than the outer first protruding electrode 15, and The distance from the end portion 22 is in contact with the inner second protruding electrode 18 located on the inner side farther than the outer first protruding electrode 15. The inner second protruding electrode 18 is a dummy protruding electrode that is not connected to the internal circuit of the semiconductor chip 20. In other words, the device 7 of the present invention is different from the device 5 of the present invention shown in FIG. 25 in that the second lead wiring 14 is disposed so as to be sandwiched between the inner second projecting electrodes 18, and the inner second projecting electrode 18 having a large area is arranged. It arrange | positions so that may be covered, and the joining position shift at the time of thermocompression bonding is suppressed.

  Here, the inner second projecting electrode 18 is connected to the inner first projecting electrode 15 that is electrically connected to the inner second projecting electrode 18 via the second lead wiring 14 if the connection destination is the same connection node. Even if connected to the internal circuit of the semiconductor chip 20, there is no possibility of a circuit short-circuit, and the operation of the internal circuit is not affected.

  According to the devices 6 and 7 of the present invention and the modifications thereof, the contact between the second protruding electrode and the second lead wiring is achieved by making the width of the second lead wiring wider than the width of the first lead wiring. Increases the area and suppresses the lead wires from sliding off the protruding electrodes even when the pressure during thermocompression is uneven due to variations in the thickness of the semiconductor chip or the height of the protruding electrodes. It is possible to realize a semiconductor device in which fine pitch is easy and chip size can be easily reduced.

<Sixth Embodiment>
Below, the place where the misalignment prevention region 23 in which the second lead wiring 14 or the second protruding electrode is arranged in each of the above embodiments will be described.

  FIG. 37 shows an example of the arrangement of the protruding electrodes on the semiconductor chip 20 and the arrangement of the misalignment prevention region 23. Generally, as for the arrangement of the protruding electrodes on the semiconductor chip 20, as shown in FIG. 37A, the protruding electrodes are arranged in one step on the long side of the semiconductor chip 20, and as shown in FIG. In general, the protruding electrodes are arranged in a staggered manner in two steps on the long side of the semiconductor chip 20.

  In this case, it is preferable to provide the misalignment prevention region 23 in the central portion of the long side of the semiconductor chip 20 in the peripheral portion of the semiconductor chip 20. Furthermore, it is more preferable to provide the misregistration prevention region 23 in each of the center portions of the two long sides. By providing the misalignment prevention region 23 at the center, the function of suppressing the misalignment of the second lead wiring 14 or the second protruding electrode 13 (17, 18) is exerted equally on the left and right sides, and fewer second lead wirings are provided. The effect can be exhibited by 14 and the second protruding electrode.

  However, when the side of the semiconductor chip 20 is long, it is effective to provide the misalignment prevention region 23 in addition to the central portion. In this case, as shown in FIG. 38, it is preferable to arrange a plurality of misregistration prevention regions 23 on each long side at substantially constant intervals. Thereby, the second lead wiring 14 or the second protruding electrode disperses the function of suppressing the bonding position deviation, and efficiently exhibits the function of suppressing the bonding position deviation even when the side of the semiconductor chip 20 is long. Can do.

<Seventh embodiment>
Below, the result of having evaluated the joining position shift at the time of thermocompression bonding with respect to said apparatus of this invention is shown.

  First, in the conventional configuration, in the configuration in which the protruding electrodes (first protruding electrodes) 31 shown in FIG. 39 are arranged in a staggered manner, the interval between the protruding electrodes 31 (the arrangement direction of the inner leads (first lead wiring) 32) The distance between the protruding electrodes 31 arranged on the inner side and the end side of the chip in the chip is 20 μm, the distance between the inner leads 32 is 20 μm, the width of the protruding electrodes 31 is 16 μm, and the width of the inner leads 32 is 8 μm. The maximum displacement of the bonding position between the protruding electrode 31 and the inner lead 32 was 7.8 μm.

  On the other hand, in the configuration in which the misalignment prevention region 23 is provided in the central portion of the semiconductor chip 20 and the second protruding electrode 13 and the second lead wiring 14 are arranged in the arrangement layout shown in FIG. When the distance is 32 μm, the distance between the second protruding electrodes 13 is 16 μm, the width of the second lead wiring 14 is 8 μm, and the distance X2 between the second protruding electrode 13 and the second lead wiring 14 is 4 μm, the bonding position shifts. Occurred only 4 μm at the maximum.

  Further, a misalignment prevention region 23 is provided in the central portion of the semiconductor chip 20, and the outer second protruding electrode 17, the inner second protruding electrode 18, and the second lead wiring 14 are arranged in a four-fork-shaped layout shown in FIG. In the configuration in which the outer second protruding electrode 17 and the inner second protruding electrode 18 have a width of 16 μm, the distance between the second lead wire 14 and the outer second protruding electrode 17 or the inner second protruding electrode 18 is 16 μm. When X2 was 4 μm, the displacement of the bonding position occurred only 4 μm at the maximum.

  Further, in the case of the configuration in which the misalignment prevention region 23 is provided in the central portion of the semiconductor chip 20 and the inner second projecting electrode 18 and the second lead wiring 14 are disposed in the layout shown in FIG. 25, the inner second projecting electrode. When the width of 18 is 16 μm, the width of the second lead wiring 14 is 8 μm, and the separation distance X2 between the second lead wiring 14 and the inner second projecting electrode 18 is 4 μm, the misalignment of the bonding position is only 4 μm at the maximum. .

  Further, in the configuration in which the second lead wiring 14 is disposed so as to cover the inner second protruding electrode 18 in the layout shown in FIG. 32, the inner second protruding electrode 18 has a width of 22 μm, and the second lead wiring 14 When the width in the contact area with the inner second protruding electrode 18 was 29 μm, the bonding position deviation occurred only 4 μm at the maximum.

  Therefore, according to the present invention, by disposing a misregistration prevention pattern including the second lead wiring 14 or the second protruding electrode 13 (17, 18) in a predetermined region of the semiconductor chip peripheral portion, the semiconductor The displacement of the bonding position between the first lead wiring and the first protruding electrode at the time of thermocompression that is caused by the variation in the thickness of the chip and the height of the protruding electrode is reduced. Fine pitch becomes easy.

<Another embodiment>
Another embodiment will be described below.

  <1> The present invention relates to the layout of lead wires and protruding electrodes when a semiconductor chip is mounted on a film substrate, and its implementation is not limited at all by the configuration of the mounted semiconductor chip. For example, the present invention is not limited by the material of the protruding electrode and the first lead wiring.

  <2> In the above-described embodiment, a representative case has been exemplified for the arrangement pattern of the second protruding electrodes 13 (17, 18) and the second lead wirings 14 of the present invention. The present invention is not limited to such an exemplified configuration, and it goes without saying that various design changes can be made in accordance with the actual arrangement pattern of the protruding electrodes. It is possible to design an arrangement pattern in which two or more arrangement patterns described in the above embodiments are appropriately combined as necessary.

  <3> In the fourth and fifth embodiments (FIGS. 25 to 30 and FIGS. 32 to 36), the first protruding electrode is disposed at a position where the distance from the end 22 of the semiconductor chip 20 is relatively short. The outer first protrusion electrode 15 is described, and the second protrusion electrode is described as the inner second protrusion electrode 18 disposed at a position relatively far from the end 22 of the semiconductor chip 20. . However, in these embodiments, the arrangement layout of the protruding electrodes and the lead wirings in the vicinity of the misregistration prevention region 23 on the semiconductor chip 20 is illustrated and separated from the misregistration prevention region 23 at the peripheral portion of the semiconductor chip 20. In the region, the first protruding electrode (inner first protruding electrode 16) may be disposed at a position where the distance from the end 22 of the semiconductor chip 20 is relatively long. At this time, the outer first protruding electrode 15 and the inner first protruding electrode 16 can be preferably arranged in a staggered pattern.

  <4> In the above embodiment, when the second protruding electrode is a dummy protruding electrode, the dummy protruding electrode is described as a protruding electrode that is not connected to the internal circuit of the semiconductor chip 20. However, in the present invention, the dummy protruding electrode means an electrode that does not affect the operation of the internal circuit of the semiconductor chip 20 and is not necessarily limited to being insulated from the internal circuit of the semiconductor chip 20. .

  For example, a second lead wiring corresponding to the second protruding electrode which is the dummy protruding electrode (a second protruding wiring which is arranged adjacent to the dummy protruding electrode and contacts the dummy protruding electrode when a bonding position shift occurs) In the configuration in which the lead wiring) is connected to the lead wiring (first lead wiring) connected to the internal circuit, when a displacement of the joining position occurs, the first protruding electrode connected to the first lead wiring and the dummy protruding electrode And may be electrically connected. However, if the connection node of the internal circuit of the semiconductor chip 20 of the dummy protrusion electrode is made to coincide with the connection node of the first protrusion electrode, the dummy protrusion electrode and the first protrusion electrode are electrically connected as a result of the displacement of the bonding position. However, there is no possibility of a circuit short-circuit, and it is considered that the operation of the internal circuit of the semiconductor chip 20 is not affected.

  In addition, when the corresponding second lead wiring is not connected to a circuit outside the semiconductor chip 20 with respect to the dummy protruding electrode, the dummy protruding electrode is connected to the internal circuit of the semiconductor chip 20. However, it is considered that the operation of the internal circuit of the semiconductor chip 20 is not affected.

  <5> Similarly, in the above embodiment, when the second lead wiring is a dummy lead wiring, the dummy lead wiring is described as a wiring that is not connected to the internal circuit of the semiconductor chip 20. However, in the present invention, the dummy lead wiring means a wiring that does not affect the operation of the internal circuit of the semiconductor chip 20, and is not necessarily limited to the case where it is insulated from the internal circuit of the semiconductor chip 20. Absent. For example, if the dummy lead wiring is insulated from a signal applied from the outside of the chip, it is considered that the operation is not affected even if the dummy lead wiring is connected to the internal circuit of the chip. That is, the dummy lead wiring is a floating wiring that is not fixed to a specific potential via the internal circuit of the chip.

  For example, in the case where the dummy lead wiring (second lead wiring) is adjacent to the first or second projecting electrode connected to the internal circuit, the dummy lead wiring and the projecting when the bonding position shift occurs. The electrode contacts. At this time, if a signal is given to the dummy lead wiring from the outside of the chip, a leakage current or the like is generated between the dummy lead wiring and the protruding electrode, which may affect the operation of the internal circuit. . In this case, the second lead wiring, which is a dummy lead wiring, is preferably insulated so that no signal is applied from the outside of the chip. Alternatively, if the dummy lead wire is adjacent to the first protruding electrode, the dummy lead wire can be provided with the same signal as the first lead wire connected to the first protruding electrode. Even if the wiring is connected to the first protruding electrode as a result of the displacement of the bonding position, it is considered that the operation of the internal circuit of the semiconductor chip 20 is not affected.

  The isolated wiring shown in the above embodiment is a form of dummy lead wiring because it is insulated from both the internal circuit and the outside of the semiconductor chip 20. That is, the dummy lead wiring includes isolated wiring.

  The present invention can be used for mounting a semiconductor device by COF.

1 to 7: Semiconductor device according to one embodiment of the present invention (device of the present invention)
11, 11a, 11b: 1st protruding electrode 12, 12a-12f: 1st lead wiring 13, 13a, 13b: 2nd protruding electrode 14, 14a-14k: 2nd lead wiring 15, 15a, 15b: outside 1st protrusion Electrode 16: Inner first protruding electrode 17, 17a, 17b: Outer second protruding electrode 18, 18a to 18e: Inner second protruding electrode 20, 30: Semiconductor chip 21, 34: Film substrate 22: Semiconductor chip end 23: Position Deviation prevention area 31: Protruding electrode 32: Inner lead 33: Bonding stage 35: Bonding tool 36: Vacuum suction hole X1: Separation distance from the second lead wiring to the adjacent second protruding electrode X2: Adjacent from the first lead wiring Separation distance to first projection electrode X3: Separation distance from second lead wiring to adjacent first projection electrode

Claims (13)

A plurality of first protruding electrodes disposed on the peripheral edge of the semiconductor chip and a plurality of first lead wirings formed on the film substrate, each of the first protruding electrodes being connected to the first lead wiring separately. In a semiconductor device connected to an internal circuit of the semiconductor chip,
In the region of the film on the substrate corresponding to a predetermined displacement prevention region sandwiched between the first protruding electrodes, one or more second lead wiring is arranged,
In at least one specific second lead wiring among the second lead wirings,
Said specified second lead wires, the distance between the specific second the first protrusion electrodes disposed adjacent to the lead wires, the first connecting said first lead wire, with the first lead wire Shorter than the distance from the first protruding electrode adjacent to one protruding electrode, and
The specific second lead wiring is a dummy wiring or a wiring electrically connected to the first lead wiring connected to the first protruding electrode disposed adjacent to the specific second lead wiring. There is a semiconductor device. The specific second lead wires, a prior SL first projecting electrodes, that are arranged so as to be sandwiched between the second protruding electrode disposed adjacent to the separate second lead wires with the first protruding electrode The semiconductor device according to claim 1. 3. The semiconductor device according to claim 2 , wherein at least one of the second lead wires excluding the specific second lead wire is disposed so as to be sandwiched between the second protruding electrodes. The specific second lead wiring is a wiring electrically connected to the first lead wiring;
Separately from the second lead wiring or the first projecting electrode, the second projecting electrode is disposed at a position facing the first projecting electrode connected to the first lead wiring with the specific second lead wiring interposed therebetween . the semiconductor device according to any one of claim 1 to 3, characterized in that the second protrusion electrodes disposed adjacent to the lead wires are disposed. A plurality of first protruding electrodes disposed on the peripheral edge of the semiconductor chip and a plurality of first lead wirings formed on the film substrate, each of the first protruding electrodes being connected to the first lead wiring separately. In a semiconductor device connected to an internal circuit of the semiconductor chip,
One or a plurality of second lead wires are disposed in a region on the film substrate corresponding to a predetermined misalignment prevention region sandwiched between the first protruding electrodes,
In at least one specific second lead wiring among the second lead wirings, the specific second lead wiring and the first protruding electrode or the first protruding electrode arranged adjacent to the specific second lead wiring Separately, a separation distance from a second protruding electrode disposed adjacent to the second lead wiring is such that the first lead wiring and the first protruding electrode connected to the first lead wiring are adjacent to the first protruding electrode. Shorter than the distance from one protruding electrode,
The second projecting electrode is disposed at a position farther from the first distance than the outer second projecting electrode disposed at a first distance from the end of the semiconductor chip, and the distance from the end of the semiconductor chip. Including two types of inner second protruding electrodes,
The specific second lead wires, characterized in that it is disposed along the gap between the outer second protruding electrode and the inner second protruding electrode semiconductors devices. 6. The semiconductor device according to claim 5 , wherein the outer second protruding electrodes and the inner second protruding electrodes are arranged in a staggered manner.   A separation distance between the specific second lead wiring and the outer second protruding electrode or the inner second protruding electrode disposed adjacent to the specific second lead wiring is determined by the first lead wiring and the first second wiring. 7. The semiconductor device according to claim 5, wherein the semiconductor device is shorter than a distance from the first protruding electrode adjacent to the first protruding electrode connected to the lead wiring. 8. The semiconductor device according to claim 1 , wherein the specific second lead wiring is a dummy wiring. The semiconductor device according to claim 2 , wherein the second protruding electrode is a dummy protruding electrode. A plurality of first protruding electrodes disposed on the peripheral edge of the semiconductor chip and a plurality of first lead wirings formed on the film substrate, each of the first protruding electrodes being connected to the first lead wiring separately. In a semiconductor device connected to an internal circuit of the semiconductor chip,
One or a plurality of second lead wires are disposed in a region on the film substrate corresponding to a predetermined misalignment prevention region sandwiched between the first protruding electrodes,
In at least one specific second lead wiring of the second lead wirings, a second protruding electrode disposed adjacent to the second lead wiring separately from the specific second lead wiring and the first protruding electrode Is shorter than the separation distance between the first lead wiring and the first protruding electrode adjacent to the first protruding electrode connected to the first lead wiring,
The second protruding electrode is a dummy protruding electrode;
The specific second lead wiring is disposed so as to be sandwiched between the two second projecting electrodes, and the projecting electrode is disposed at a position farther from the end of the semiconductor chip than the second projecting electrode. A semiconductor device, wherein the semiconductor device is electrically connected to an internal circuit of the semiconductor chip. The semiconductor device according to claim 1, wherein the misalignment prevention region is provided in a central portion of a side edge of the semiconductor chip. 12. The semiconductor device according to claim 1, wherein a plurality of the misregistration prevention regions are provided at a peripheral portion of the semiconductor chip at regular intervals. The semiconductor device according to claim 1, wherein the first protruding electrodes are arranged in a staggered manner.

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