JP5999597B2 - Oscillator - Google Patents

Description

The present invention relates to an oscillator that does not use a terminal dedicated to a test mode.

Along with the downsizing and cost reduction of oscillators using crystal resonators, SAW resonators, etc., IC chips on which the oscillators are formed are also required to be downsized. Such an oscillator is usually subjected to a product test before shipment to eliminate defective products.
In order to perform a test mode operation that operates only when performing a shipping test on an oscillator, it is common to prepare a terminal dedicated to the test mode and input a test mode control signal to perform a shipping test. . However, the reduction of the chip size of the IC chip for the oscillator increases the ratio of the pad (PAD) size to the chip size, and as a result, the presence of the test mode dedicated terminal significantly hinders the chip size reduction. become. Furthermore, since the differential output (eg, LV-PECL, LVDS, etc.) used for the high frequency signal requires two output terminals, the ratio of PAD to the chip size becomes larger.
Here, the main items to be tested using the test mode are the high output voltage (VOH) and low output voltage (VOL) of the output signal. The test target circuit (circuit under test) includes, for example, a level adjustment circuit (Output buffer).

The case where the test mode dedicated terminal is used has been described above, but there are the following examples of test methods that do not use the test mode dedicated terminal.
(1) A method in which an AC signal is input from a transducer input connection terminal (XIN) and a transducer output terminal (XOUT) attached to the IC chip, and the output waveform is directly monitored by a measuring instrument such as an oscilloscope. This is usually used with a differential output oscillator.
(2) The low output voltage VOL of the output signal measures the low output voltage immediately after the oscillator (IC) is started, and the high output voltage VOH is obtained from the vibrator input connection terminal (XIN) or the vibrator output connection terminal (XOUT). In this method, the AC signal is input and the voltage measured by smoothing the output signal is correlated with the actual VOH. This is mainly used in CMOS output oscillators.
(3) The test mode is activated by applying a voltage equal to or higher than the power supply voltage Vdd to the Enable / Disable control terminal (OE terminal), and VOH and VOL output by DC output are monitored. This is usually used for both differential output oscillators and CMOS output oscillators.

However, these methods have the following problems.
In the method (1), since the differential signal output by the AC output is highly sensitive to power supply noise, it is easily affected by the parasitic components of the evaluation system such as a tester, a test board, and a probe needle. Difficult to build and maintain. In addition, since a high-accuracy oscilloscope is required, it is difficult to reduce the cost of the tester and the test time by simultaneous measurement.
In the method (2), since the smoothed voltage is measured by a multimeter in a DC manner, the measurement system as in (1) is not difficult and simultaneous measurement is possible. However, in the case of differential output, VOH Since VOL is a voltage specific to the signal standard, measurement by smoothing cannot be performed. Since the output of the CMOS output oscillator is VOH at the Vdd level and VOL is at the Vss (0 V) level, the test can be performed by correlating the smoothed voltage with the actual VOH.

In the method (3), it is possible to operate the test mode regardless of the output signal standard, but since a voltage higher than Vdd is applied to the OE terminal, it is smaller and consumes less power using a fine process with low breakdown voltage. Products that are suitable for power (power supply voltage) operation may become unusable.
As a means for solving this problem, the inventors have proposed a test circuit system in which a test mode is activated by inputting an OE terminal and a vibrator input connection terminal (XIN) to an NAND (or AND) logic circuit. .

In this test method, the OE terminal is set to a disabled state, and the test mode is set when a high voltage is input to the input terminal (XIN) of the oscillation circuit. Then, by applying a High or Low (OPEN) voltage to the output terminal (XOUT) of the oscillation circuit, the DC output High-Low from the output terminals OUT and OUTN of the oscillator is switched to perform the VOH and VOL tests. It is a configuration.
In this test method, it is not necessary to apply a voltage equal to or higher than the power supply voltage (Vdd) to the OE terminal and the XIN terminal in the DC measurement test, so even a product using a fine process with a low withstand voltage regardless of the output signal standard. The test mode can be started, and the simultaneous measurement environment can be easily constructed.

  However, in this test method, the NMOS transistor of the oscillation amplifier is turned on in the test mode, and then when a high voltage is applied to the XOUT terminal, an overcurrent flows inside the IC chip, and a desired test is performed due to the IC chip failure or voltage drop. The problem that it becomes impossible to perform occurs. Further, since the threshold value Vth of the test signal input circuit used in the test method varies depending on the power supply voltage, there is a problem that a large current is required to make the test mode function when the power supply voltage increases. This problem occurs mainly when a high-frequency oscillation circuit for a triple wave having a small feedback resistance or an NMOS transistor having a low threshold Vth for small-sized, high-frequency, low-voltage operation is used for an oscillation amplifier.

  Patent Document 1 discloses a semiconductor integrated circuit that can supply an operation clock having a stable amplitude. The semiconductor integrated circuit includes an oscillation circuit, an amplitude correction circuit, and a test enable signal generation circuit. The amplitude correction circuit includes a second transmission circuit, a third transmission circuit, an inverter circuit for driving a high-speed operation clock, an inverter circuit for driving a normal operation clock, and a power supply voltage supply circuit. Since a constant power supply voltage is supplied to the clock drive inverter circuit from the power supply voltage supply circuit, the amplitude of the input clock signal is maintained at a predetermined value by the clock drive inverter circuit.

Patent Document 2 discloses a semiconductor integrated circuit device capable of finely adjusting a high voltage with few variations of a high voltage for switching an operation mode with respect to manufacturing variations of MOS transistors. In this semiconductor integrated circuit device, a higher voltage than the normal working voltage is used as a control voltage for controlling the mode switching signal. The operation mode switching circuit includes an NMOS transistor and a PMOS transistor. The gate and drain of the NMOS transistor are connected to the external input terminal. The source of the PMOS transistor is connected to the source of the NMOS transistor, and the PMOS transistor outputs a mode switching signal from the drain based on a control voltage applied to the gate. A control voltage is applied to the gate of the PMOS transistor so that the NMOS and PMOS transistors are turned on when a voltage higher than the normal operating voltage is applied to the external input terminal.

JP 2008-282833 A

Japanese Patent Application Laid-Open No. 07-073062

The conventional test method using the DC output described in (3) has the above-described problem, and the test method proposed by the inventors as a means for solving this problem is as described above. In testing by DC measurement, it is not necessary to apply a voltage higher than the power supply voltage (Vdd) to the OE terminal and XIN terminal, so the test mode can be activated even for products that use a fine process with low withstand voltage regardless of the output signal standard. It is possible to construct a simultaneous measurement environment easily. However, such a method causes various problems as described above.
The present invention has been made under such circumstances. Even when a high voltage is applied to the output terminal (XOUT terminal) of the oscillation circuit, a desired test cannot be performed due to a voltage drop due to the influence of contact resistance. Provided is an oscillator capable of miniaturization in which the problem is reduced and the threshold voltage Vth of the test circuit varies depending on the power supply voltage, so that the high power supply voltage reduces the failure of the test mode itself.

  One aspect of the oscillator of the present invention is an oscillation circuit, a test circuit for testing a circuit under test that constitutes the oscillation circuit, and the oscillation circuit to which an activation signal is input and a resonator output terminal is connected in a test mode An output terminal of the oscillation circuit to which a test voltage is input and the input terminal of the vibrator is connected in the test mode, and an output signal of the circuit under test corresponding to the test voltage is output. 1 and a second output terminal, and the test circuit fixes an initial stage inverter to which an input signal from the vibrator output terminal is input, and fixes a potential of the input terminal of the inverter during normal operation, and a through current of the inverter. The inverter is characterized in that the threshold voltage of the inverter is made smaller than ½ of the power supply voltage. The inverter may include a resistor and an NMOS transistor. A load resistor having one end grounded as the input potential fixing means may be attached to the gate of the NMOS transistor.

  In the oscillator of the present invention, even when a high voltage is applied to the transducer output connection terminal (XOUT terminal), problems such as a desired test cannot be performed due to a voltage drop are reduced, and a dedicated test terminal becomes unnecessary. The IC chip can be miniaturized. In addition, by making the CMOS inverter whose threshold is determined as a percentage of the power supply voltage into a resistance load type inverter determined by the threshold (fixed value) of the transistor, the threshold voltage is lowered and fluctuation of the threshold voltage due to the power supply voltage is eliminated. Thus, the high voltage input from the XOUT terminal can be lowered, and the risk of overcurrent alleviation and malfunction of the test mode can be reduced.

1 is a circuit diagram of an oscillator according to Embodiment 1. FIG. FIG. 3 is a diagram illustrating the operation of the terminal illustrated in FIG. 1. FIG. 3 is a characteristic diagram (a) and a circuit diagram (b) for explaining the relationship between the IC chip and the probe during the test in Example 1. FIG. FIG. 5 is a characteristic diagram illustrating a test state in the first embodiment.

    Hereinafter, embodiments of the invention will be described with reference to examples.

Embodiment 1 will be described with reference to FIGS.
FIG. 1 shows a circuit configuration of an oscillator according to the first embodiment. The oscillator has an output terminal connected to the oscillation circuit 2 formed on the semiconductor chip 10 such as silicon, and a vibrator input connection terminal XIN formed on the semiconductor chip, and an input terminal connected to the vibrator output connection terminal XOUT. And a piezoelectric vibrator (not shown) such as a quartz crystal.
In addition to the terminals (XIN terminal, XOUT terminal) described above, the semiconductor chip 10 includes a test circuit for testing the oscillator, an Enable / Disable control terminal OE (hereinafter referred to as OE terminal) for starting the test mode, and a first output. A terminal (hereinafter referred to as OUT terminal) and a second output terminal (hereinafter referred to as OUTN terminal) are provided. The semiconductor chip 10 is further provided with an output circuit that transmits a signal from the oscillation circuit 2 to an output terminal. The semiconductor chip 10 shown in FIG. 1 is provided with an oscillation detection circuit 21, a frequency dividing circuit or waveform shaping circuit 23, a single-differential conversion circuit 24, an output buffer 25, and the like as output circuits.

  In this oscillator, the OE terminal and the XIN terminal are input to a logic circuit such as a NAND that activates the test mode. The test method for the oscillator is configured such that the test mode is set when the OE terminal is set to the Disable state and a high voltage (H) is input to the XIN terminal. Then, by applying a high or low (OPEN) voltage (H, L) to the XOUT terminal, the DC voltage output from the OUT and OUTN terminals is switched between high and low, and the output is tested for H and L. Do.

  FIG. 4 is a characteristic diagram for explaining the quality of output in the test method. The vertical axis represents output (V), and the horizontal axis represents time (t). A represents a normal output signal line. The normal output signal line A has a high voltage portion (VOH) and a low voltage portion (VOL). The area a surrounded by a dotted line indicates that the range is normal if VOH is included in this range, and the area b surrounded by the dotted line indicates that it is normal if VOL is included in this range. Yes. The output signal lines X, Y, and Z are defective products that do not enter any region.

  The oscillation circuit 2 formed in the semiconductor chip 10 has an oscillation amplifier 20 having an input terminal connected to the XIN terminal and an output terminal connected to the XOUT terminal, and one end connected to the input terminal of the oscillation amplifier 20, and the output A feedback resistor Rf having the other end connected to the other end, a capacitor C constituting the oscillation amplifier 20 and having a source connected to the power supply voltage Vdd, connected to the gate of the PMOS transistor P1, and one end grounded and the other end connected to the XIN terminal And a capacitor Cd having one end grounded and the other end connected to the XOUT terminal.

The output of the oscillation circuit 2 (output of the oscillation amplifier 20) is finally output from the OUT terminal and the OUTN terminal via the level adjustment circuit (output buffer) 25. Between the oscillation circuit and the output terminal (OUT terminal, OUTN terminal), an oscillation detection circuit 21, a logic circuit (NAND) 22, a frequency divider or waveform shaping circuit 23, a single-differential conversion circuit 24, and an output buffer 25 are provided. It is interposed as an output circuit.
The oscillation detection circuit 21 inputs the output of the oscillation amplifier 20 and inputs the output to the first input terminal of the NAND circuit 22. In the NAND circuit 22, a signal obtained by inverting the signal from the OE terminal by the inverter 11 is input to the second input terminal, and the output is input to the frequency dividing circuit or the waveform shaping circuit 23 and the single-differential conversion circuit 24. The The frequency divider or waveform shaping circuit 23 receives the output of the NAND circuit 22 and the signal from the XOUT terminal and outputs the signal to the single-differential conversion circuit 24. The single-differential conversion circuit 24 inputs the output of the NAND circuit 22 together with the output of the frequency divider or waveform shaping circuit 23 and inputs the output signal and the inverted signal to the output buffer 25.

Next, the test circuit will be described.
The test circuit 1 includes an inverter 12, a logic circuit (NAND) 13, and a logic circuit (NAND) 14. In the NAND circuit 13, the test signal sent from the OE terminal is inverted by the inverter 11 and inputted to the first input terminal, the test signal sent from the XIN terminal is inputted to the second input terminal, and the output is the NAND circuit 14. To the second input terminal. The inverter 12 receives the test signal from the XOUT terminal, and the output terminal is connected to the output terminal and the inverting output terminal of the single-differential conversion circuit 24. The output of the inverter 12 is input to the output buffer 25. In the NAND circuit 14, the output of the oscillation detection circuit 21 is input to the first input terminal, and the output of the NAND circuit 13 is input to the second input terminal. The output signal of the NAND circuit is input to the output buffer 25 which is a circuit under test.

A transmission gate (Transmission gate) is connected between the XIN terminal and the second input terminal of the NAND circuit 13.
Gate SW) is provided. The switch SW1 uses a signal obtained by inverting the signal from the OE terminal by the inverter 11 as a control signal. This control signal and the control signal inverted by the inverter 15 are input to both gates to turn on / off the switch SW1. A resistor R1 having one end grounded is connected between the switch SW1 and the second input end of the NAND circuit 13. Further, a resistor R2 having one end connected to the drain of the NMOS transistor N2 is connected between the resistor R1 and the second input terminal of the NAND circuit 13. The source of the NMOS transistor N2 is grounded, and the gate is connected to the output side of the NAND circuit 13.
A switch SW2 composed of a transmission gate is provided between the XOUT terminal and the inverter 12. The switch SW2 uses the output signal from the NAND circuit 13 as a control signal. This control signal and the control signal inverted by the inverter 16 are input to both gates to turn on / off the switch SW2.

A switch SW3 including a transmission gate is provided between the inverter 12 and the output terminal of the single-differential conversion circuit 24 and the input terminal of the output buffer 25. The switch SW3 uses an output signal from the NAND circuit 13 as a control signal. This control signal and the control signal inverted by the inverter 18 are input to both gates to turn on / off the switch SW3.
A switch SW4 including a transmission gate is provided between the inverter 12 and the inverting output terminal of the single-differential conversion circuit 24 and the input terminal of the output buffer 25. The output signal of the inverter 12 is inverted by the inverter 17 and input to the SW4. The switch SW4 uses the output signal from the NAND circuit 13 as a control signal. This control signal and the control signal inverted by the inverter 19 are input to both gates to turn on / off the switch SW4.

Next, the operation of the test circuit will be described.
In this test method, a low voltage (L) is applied to the OE terminal to place the terminal in a disabled state, and a high voltage (H) is input to the XIN terminal to enter the test mode. In this mode, by applying a high or low (OPEN) voltage to the XOUT terminal, the DC voltage output from the OUT terminal and OUTN terminal is switched between high and low, and the VOH and VOL tests are performed (see FIG. 2). . FIG. 2 shows the voltage levels of the terminals in the enable state and the disable state in the test mode (TEST).
First, a low voltage (L) is applied to the OE terminal to place the OE terminal in a disabled state. The switch SW1 for setting the test circuit 1 in the test mode turns on a signal obtained by inverting the test signal (L) from the OE terminal by the inverter 11 using the control signal (H). Accordingly, the test signal (H) applied to the XIN terminal passes through the switch SW1 and is input to the second input terminal of the NAND circuit 13, and the test signal from the OE terminal inverted by the inverter 11 is (H ), Input to the first input terminal of the NAND circuit 13. Since both inputs of the NAND circuit 13 are the high voltage (H), the low voltage (L) is output to the output terminal.

The output signal (L) of the NAND circuit 13 is input to the second input terminal of the NAND circuit 14. On the other hand, the signal (H) is input from the oscillation detection circuit to the first input terminal. This oscillation detection circuit outputs a signal (H) except when oscillation is detected in normal operation. At this time, the output signal (H) of the NAND circuit 14 is input to an input terminal for controlling Enable / Disable of the output buffer 25. When the high voltage (H) is input to the input terminal, the output buffer 25 is enabled and can be tested. However, when the low voltage (L) is input to the input terminal, the output buffer 25 is disabled and cannot be tested. .
However, when the OE terminal is L and the XIN terminal is H, since the L signal is always input to the second input terminal of the NAND circuit 14, a high voltage (H) is input to the first input terminal. However, even if the low voltage (L) is input, the output is the high voltage (H), which is always in the test mode.

In this test mode, the frequency dividing circuit or waveform shaping circuit 23, the single-differential conversion circuit 24, and the like constituting the output circuit are controlled by a logic circuit (NAND) 22. The NAND circuit 22 inputs the output signal (H) of the oscillation detection circuit 21 to the first input terminal, inputs the inverted signal (H) of the output signal of the OE terminal to the second input terminal, and outputs the output signal (L ) This output signal is input to the input terminals for controlling Enable / Disable of the circuits 23 and 24 constituting the output circuit, and these circuits are set to the Disable state.

At this time, in the test circuit 1, the test signal (H) from the XOUT terminal passes through the ON switch SW2 and is input to the inverter 12, where it is inverted, and one signal (L) is in the ON state. The signal is input to the first input terminal of the output buffer 25 through the switch SW3. The other signal is inverted by the inverter 17 and input to the second input terminal of the output buffer 25 as an inverted signal (H).
The test circuit 1 tests the shape of the signal input to the output buffer 25 from the first and second input terminals of the output buffer 25 to the output terminals OUT and OUTN of the oscillation circuit 2. A specific test method is as described in FIG.

Next, the inverter 12 of the test circuit 1 will be described.
As described above, in this test method, it is not necessary to apply a voltage equal to or higher than the power supply voltage (Vdd) to the OE terminal and the XIN terminal in the DC measurement test. It is possible to start the test mode even for products that use, and the simultaneous measurement environment can be easily constructed.
However, in this test method, the NMOS transistor of the oscillation amplifier is turned on in the test mode, and then when a high voltage is applied to the XOUT terminal, an overcurrent flows inside the IC chip, and a desired test is performed due to the IC chip failure or voltage drop. The problem that it becomes impossible to perform occurs. Further, since the threshold value Vth of the test circuit used in the test method varies depending on the power supply voltage, there is a problem that the test mode itself does not function when the power supply voltage increases.

FIG. 3 is a characteristic diagram and circuit diagram for explaining the relationship between the IC chip and the probe during the test. Pads (PAD) such as an OE terminal, an XIN terminal, and an XOUT terminal are formed on the IC chip on which the test circuit and the oscillation circuit are formed. When the characteristic is measured by probing the IC chip with a tester, the probe is applied to the PAD (FIG. 3A). At this time, the contact resistance between the probe and the PAD is easily attached, and the L component of the probe needle is also attached (FIG. 3B). Such L component and R component cause a voltage drop, which causes a problem that a desired test cannot be performed.

As means for solving such a problem, in this embodiment, first, a CMOS inverter which has been conventionally used is replaced with a resistance load type inverter.
The inverter 12 used in this embodiment has a resistor R4 whose one end is connected to the power supply voltage Vdd and an NMOS transistor N3 whose drain is connected to the other end of the resistor R4 and whose source is grounded. In order to pull down the input and prevent the consumption / standby current from flowing, a resistor R3 having one end grounded can be connected to the gate of the NMOS transistor N3. At this time, the threshold voltage Vth of the inverter is made smaller than ½ of the power supply voltage Vdd.

The threshold voltage Vth is lowered by making the CMOS inverter whose threshold voltage Vth is determined by the percentage with respect to the power supply voltage Vdd into a resistance load type inverter determined by the threshold voltage Vth (fixed value) of the transistor, and the threshold voltage Vth by the power supply voltage Vdd is reduced. By eliminating this variation, the input high voltage input from the XOUT terminal can be lowered, and the risk of overcurrent mitigation and malfunction of the test mode can be reduced.
In this embodiment, a resistance load type inverter is used, but a CMOS inverter can also be used. However, in this method, it is necessary to change the structure of both the PMOS and NMOS transistors so that the threshold voltage of the inverter is smaller than ½ of the power supply voltage, which complicates the manufacturing process.

  In the test method described in this embodiment, it is not necessary to apply a voltage equal to or higher than the power supply voltage (Vdd) to the OE terminal and the XIN terminal in the test by DC measurement. It is possible to start the test mode even for products that use, and the simultaneous measurement environment can be easily constructed. Further, since the test dedicated terminal is not used, the IC chip can be miniaturized.

DESCRIPTION OF SYMBOLS 1 ... Test circuit 2 ... Oscillation circuit 10 ... IC chip 11, 12, 15, 16, 17, 18, 19 ... Inverter 13, 14, 22 ... Logic circuit (NAND)
DESCRIPTION OF SYMBOLS 20 ... Oscillation amplifier 21 ... Oscillation detection circuit 23 ... Dividing circuit or waveform shaping circuit 24 ... Single-Differential conversion circuit 25 ... Test circuit, level adjustment circuit (output buffer)

Claims (3)

An oscillation circuit; a test circuit for testing a circuit under test that constitutes the oscillation circuit; an input terminal of the oscillation circuit to which an activation signal is input and a resonator output terminal is connected in the test mode; and in the test mode An output terminal of the oscillation circuit to which a test voltage is input and an input terminal of the vibrator is connected, and first and second output terminals to which an output signal of the circuit under test corresponding to the test voltage is output The test circuit includes an initial stage inverter to which an input signal from the output terminal is input, and an input potential fixing means for fixing a potential of the input terminal of the inverter and preventing a through-current during normal operation, The said inverter makes the threshold voltage of the said inverter smaller than 1/2 of a power supply voltage, The oscillator characterized by the above-mentioned. The oscillator according to claim 1, wherein the inverter is a resistance load type inverter having a resistor and an NMOS transistor. 3. The oscillator according to claim 2, wherein a load resistor having one end grounded as the input potential fixing means is provided at the gate of the NMOS transistor.

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