JP5997535B2 - Charge pump - Google Patents

Description

  The present invention relates to a polarity inversion type charge pump having a boosting factor that is not an integral multiple.

  In a polarity inversion type (negative output type) charge pump, a boost factor (−1.5 times, −2.5 times, etc.) that is not an integral multiple may be used in order to increase power efficiency. For example, when generating an output voltage of −6V from an input voltage of + 5V, the boosted voltage (−1.5 times higher than generating −6V by adjusting the voltage of −2 times boosted voltage (= −10V) ( = −7.5V) to adjust the voltage to generate −6V can improve the power efficiency.

  FIG. 7 is a circuit diagram showing a conventional example of a negative charge pump, and FIG. 8 is a diagram for explaining a -1.5 times boosting operation by the negative charge pump. The negative charge pump of this conventional example includes a period A in which the flying capacitors C1 to C3 are connected between the application terminal of the input voltage Vin (for example, + 4V) and the application terminal of the reference voltage Vss (for example, 0V), and the flying capacitors C1 to C3. Switches SW301 to SW310 that are turned on / off to alternately switch between the period B in which C3 is connected between the application terminal of the reference voltage Vss (for example, 0V) and the application terminal of the output voltage Vout (for example, −6V). Have. Among these switches, the switches SW305 to SW308 are connected between the flying capacitors C1 to C3 between the period A and the period B so as to obtain a boosting factor that is not an integral multiple (here, -1.5). Is equivalent to a series-parallel switching switch for switching between serial and parallel, and a CMOS switch in which a PMOS switch and an NMOS switch are complementarily combined is generally used.

  As an example of the related art related to the above, Patent Document 1 can be cited.

JP 2007-159356 A

  The voltages V32 to V36 applied to both ends of the switches SW305 to SW308 are voltages from the input voltage Vin (for example, +4 V) to the reference voltage Vss (for example, 0 V) in the period A, and the reference voltage Vss (for example, 0 V) in the period B. To an output voltage Vout (for example, −6 V). Based on this, in the conventional negative charge pump, the on / off control signal (gate signal) of the switches SW305 to SW308 is pulse-driven between the input voltage Vin (for example, + 4V) and the output voltage Vout (for example, -6V). It was.

  In this case, a maximum difference voltage (for example, 10 V) between the input voltage Vin and the output voltage Vout is applied to the switches SW305 to SW308. Therefore, in the conventional negative charge pump, even if the input voltage Vin and the output voltage Vout are both equal to or lower than the withstand voltage (for example, 6.5 V) of the medium withstand voltage element, the switches SW305 to SW308 have the input voltage Vin and the output voltage Vout. Therefore, it is necessary to use a high breakdown voltage element (for example, a breakdown voltage of 28 V) that can withstand the voltage difference between the two.

  In general, a high voltage element has a larger area and a higher on-resistance than a medium voltage element. For this reason, in order to obtain a current capability equivalent to that of the medium withstand voltage element using the high withstand voltage element, it is necessary to increase the size of the switch, resulting in an increase in circuit area. Further, when the size of the switch is increased, the parasitic capacitance of the gate is increased, so that a charge / discharge current for turning on / off the switch is increased and power efficiency is lowered.

  In view of the above-mentioned problems found by the inventors of the present application, the present invention realizes downsizing of a polarity inversion type charge pump having a boosting factor that is not an integral multiple, improving current capability, or improving power efficiency. The purpose is to do.

  In order to achieve the above object, a charge pump according to the present invention includes a first period in which a plurality of flying capacitors are connected between an application terminal for an input voltage and an application terminal for a reference voltage; A polarity inversion type charge pump having a plurality of switches that are turned on / off alternately to switch between a second period connected between a reference voltage application terminal and an output voltage application terminal. Among the switches, the series-parallel switch for switching the connection relationship between the flying capacitors in series / parallel between the first period and the second period so as to obtain a boosting factor that is not an integer multiple is described above. The switch turned on in the first period is a PMOS switch, the switch turned on in the second period is an NMOS switch, and the series-parallel switch The gates of the exchange switch is the both configurations the reference voltage is fixedly applied (first configuration).

  In the charge pump having the first configuration, each of the series-parallel changeover switches is not a high withstand voltage element that can withstand a voltage difference between the input voltage and the output voltage, but the input voltage and the reference voltage. It is preferable to adopt a configuration (second configuration) that is a medium withstand voltage element that can withstand a voltage difference of 1 or a voltage difference between the reference voltage and the output voltage.

  In the charge pump having the second configuration, the reference voltage may be a ground voltage (third configuration).

  In addition, the charge pump having the third configuration may be configured (fourth configuration) to perform -1.5 times boosting using the first to third flying capacitors.

  In addition, the charge pump having the fourth configuration includes, as the plurality of switches, a first switch that conducts / cuts off between the application terminal of the reference voltage and the first terminal of the third flying capacitor, and the reference voltage A second switch for conducting / cutting off between the application terminal of the first flying capacitor and the first terminal of the first flying capacitor; and conducting / cutting off between the application terminal of the output voltage and the first terminal of the second flying capacitor. A third switch; a fourth switch that conducts / cuts off between the output voltage application terminal and the first terminal of the first flying capacitor; a second terminal of the first flying capacitor; and a second terminal of the second flying capacitor. A fifth switch for conducting / interrupting between the first end and a sixth switch for conducting / interrupting between the second end of the second flying capacitor and the first end of the third flying capacitor; A seventh switch for conducting / interrupting between the second end of the first flying capacitor and the first end of the third flying capacitor, the second end of the second flying capacitor, and the third flying An eighth switch for conducting / interrupting between the second end of the capacitor, a ninth switch for conducting / interrupting between the application end of the input voltage and the second end of the third flying capacitor, and the reference voltage And a tenth switch for conducting / interrupting between the application terminal of the third flying capacitor and the second terminal of the third flying capacitor, and the fifth to eighth switches connected between the first to third flying capacitors. Is a configuration (fifth configuration) corresponding to the series-parallel switch.

  In the charge pump having the fifth configuration, in the first period, the first switch, the second switch, the fifth switch, the eighth switch, and the ninth switch are turned on, The third switch, the fourth switch, the sixth switch, the seventh switch, and the tenth switch are turned off, and in the second period, the first switch, the second switch, the fifth switch, A configuration in which the eighth switch and the ninth switch are turned off and the third switch, the fourth switch, the sixth switch, the seventh switch, and the tenth switch are turned on (sixth Configuration).

  In addition, the charge pump having the third configuration may be configured (seventh configuration) to perform -2.5 times boosting using the first to fourth flying capacitors.

  In addition, the charge pump having the seventh configuration includes, as the plurality of switches, a first switch that conducts / cuts off between a reference voltage application terminal and a first terminal of the fourth flying capacitor, and the reference voltage A second switch for conducting / interrupting between the application terminal of the first flying capacitor and the first terminal of the third flying capacitor; and conducting / interrupting between the application terminal of the reference voltage and the first terminal of the first flying capacitor. A third switch; a fourth switch that conducts / cuts off between the application terminal of the output voltage and the first terminal of the second flying capacitor; and an application terminal of the output voltage and the first terminal of the first flying capacitor. A fifth switch for conducting / interrupting between the first flying capacitor, a sixth switch for conducting / interrupting between the second end of the first flying capacitor and the first end of the second flying capacitor, A seventh switch that conducts / cuts off between a second end of the flying capacitor and a first end of the third flying capacitor; a second end of the first flying capacitor; and a first end of the third flying capacitor. An eighth switch for conducting / cutting off between the second flying capacitor, a ninth switch for conducting / cutting off between the second end of the third flying capacitor and the first end of the fourth flying capacitor, and a third switch of the third flying capacitor. A tenth switch for conducting / interrupting between two ends and the second end of the fourth flying capacitor; and conducting / blocking between a second end of the second flying capacitor and a second end of the fourth flying capacitor. An eleventh switch for cutting off, a twelfth switch for conducting / cutting off between the application terminal of the input voltage and the second terminal of the fourth flying capacitor, and the reference voltage A sixteenth to eleventh switch connected between the first to fourth flying capacitors, and a thirteenth switch for conducting / cutting off between the application terminal of the first flying capacitor and the second end of the fourth flying capacitor May be configured (eighth configuration) corresponding to the series-parallel switch.

  The charge pump having the eighth configuration may be configured such that, in the first period, the first to third switches, the sixth switch, and the tenth to twelfth switches are turned on, the fourth switch, The fifth switch, the seventh to ninth switches, and the thirteenth switch are turned off. In the second period, the first to third switches, the sixth switch, and the tenth to twelfth switches. It is preferable that the fourth switch, the fifth switch, the seventh to ninth switches, and the thirteenth switch are turned on (a ninth configuration) when the switch is turned off.

  The liquid crystal drive device according to the present invention includes a charge pump having any one of the first to ninth configurations, and a driver that generates a drive signal for the liquid crystal display panel using the output voltage of the charge pump. (Tenth configuration).

  The liquid crystal display device according to the present invention has a configuration (an eleventh configuration) including a liquid crystal display panel and a liquid crystal driving device having a tenth configuration for generating a driving signal for the liquid crystal display panel. .

  Further, the electronic apparatus according to the present invention has a configuration (a twelfth configuration) having a liquid crystal display device having the eleventh configuration.

  According to the present invention, it is possible to reduce the size of a polarity inversion charge pump having a boosting factor that is not an integral multiple, improve the current capability, or improve the power efficiency.

Block diagram showing one configuration example of a liquid crystal display device Circuit diagram showing a first configuration example of the negative charge pump 11 Diagram for explaining -1.5 times boosting operation Circuit diagram showing a second configuration example of the negative charge pump 11 Diagram for explaining −2.5 times boosting operation External view showing one configuration example of an electronic apparatus provided with a liquid crystal display device Circuit diagram showing a conventional example of a negative charge pump Diagram for explaining -1.5 times boosting operation

<Liquid crystal display device>
FIG. 1 is a block diagram illustrating a configuration example of a liquid crystal display device. The liquid crystal display device 1 of this configuration example includes a liquid crystal driving device 10 and a liquid crystal display panel 20.

  The liquid crystal driving device 10 is a monolithic semiconductor integrated circuit device (so-called liquid crystal driver IC) that generates a driving signal (for example, a gate driving signal SG) of the liquid crystal display panel 20, and includes a negative charge pump 11, a positive charge pump 12, and a gate. And a driver 13.

  The negative charge pump 11 is connected between the application terminal of the input voltage Vin and the application terminal of the reference voltage Vss. The negative charge pump 11 reverses the polarity of the input voltage Vin with reference to the reference voltage Vss, and is a predetermined boost factor that is not an integral multiple. To generate a negative output voltage VoutN. The circuit configuration and operation of the negative charge pump 11 will be described in detail later.

  The positive charge pump 12 is connected between the application terminal of the input voltage Vin and the application terminal of the reference voltage Vss, and generates the positive output voltage VoutP by boosting the input voltage Vin at a predetermined boosting factor. .

  The gate driver 13 generates a gate drive signal (vertical scanning signal) SG of the liquid crystal display panel 20 using the output voltages VoutP and VoutN.

  Note that voltage adjustment circuits (regulators) that adjust the voltage values of the output voltages VoutP and VoutN may be provided on the power supply paths from the negative charge pump 11 and the positive charge pump 12 to the gate driver 13, respectively.

  Although not explicitly shown in FIG. 2, the liquid crystal drive device 10 may incorporate a source driver that generates a source drive signal (video signal) SS of the liquid crystal display panel 20.

  The liquid crystal display panel 20 outputs images, characters, and the like based on the gate drive signal SG and the source drive signal SS input from the liquid crystal drive device 10.

<Negative charge pump>
FIG. 2 is a circuit diagram showing a first configuration example of the negative charge pump 11. The negative charge pump 11 of the first configuration example is a circuit block that generates an output voltage VoutN (−6 V) by boosting the input voltage Vin (+4 V) by −1.5 times, and includes switches SW101 to SW110, a flying capacitor C1-C3 and output capacitor Cout are included. The switches SW101 to SW110 are semiconductor elements integrated in the liquid crystal driving device 10, and the flying capacitors C1 to C3 and the output capacitor Cout are discrete elements externally attached to the liquid crystal driving device 10.

  The switch SW101 is a PMOS switch whose source and back gate are connected to the application terminal of the reference voltage Vss (0V) and whose drain is connected to the first terminal (V15) of the flying capacitor C3. The switch SW101 corresponds to a first switch that conducts / cuts off between the application terminal of the reference voltage Vss (0 V) and the first terminal of the flying capacitor C3.

  The switch SW102 is a PMOS switch whose source and back gate are connected to the application terminal of the reference voltage Vss (0V) and whose drain is connected to the first terminal (V11) of the flying capacitor C1. The switch SW102 corresponds to a second switch that conducts / cuts off between the application terminal of the reference voltage Vss (0V) and the first terminal of the flying capacitor C1.

  The switch SW103 is an NMOS switch whose source and back gate are connected to the application terminal of the output voltage VoutN (−6V) and whose drain is connected to the first terminal (V13) of the flying capacitor C2. The switch SW103 corresponds to a third switch that conducts / cuts off between the application terminal of the output voltage VoutN (−6 V) and the first terminal of the flying capacitor C2.

  The switch SW104 is an NMOS switch whose source and back gate are connected to the application terminal of the output voltage VoutN (−6V) and whose drain is connected to the first terminal of the flying capacitor C1. The switch SW104 corresponds to a fourth switch that conducts / cuts off between the application terminal of the output voltage VoutN (−6V) and the first terminal of the flying capacitor C1.

  The switch SW105 is a PMOS switch whose source and back gate are connected to the second end (V12) of the flying capacitor C1, and whose drain is connected to the first end of the flying capacitor C2. The switch SW105 corresponds to a fifth switch that conducts / cuts off between the second end of the flying capacitor C1 and the first end of the flying capacitor C2.

  The switch SW106 is an NMOS switch whose drain is connected to the second end (V14) of the flying capacitor C2, and whose source and back gate are connected to the first end of the flying capacitor C3. The switch SW106 corresponds to a sixth switch that conducts / cuts off between the second end of the flying capacitor C2 and the first end of the flying capacitor C3.

  The switch SW107 is an NMOS switch whose drain is connected to the second end of the flying capacitor C1, and whose source and back gate are connected to the first end of the flying capacitor C3. The switch SW107 corresponds to a seventh switch that conducts / cuts off between the second end of the flying capacitor C1 and the first end of the flying capacitor C3.

  The switch SW108 is a PMOS switch whose drain is connected to the second end of the flying capacitor C2, and whose source and back gate are connected to the second end (V16) of the flying capacitor C3. The switch SW108 corresponds to an eighth switch that conducts / cuts off between the second end of the flying capacitor C2 and the second end of the flying capacitor C3.

  The switch SW109 is a PMOS switch whose source and back gate are connected to the application terminal of the input voltage Vin (+ 4V) and whose drain is connected to the second terminal of the flying capacitor C3. The switch SW109 corresponds to a ninth switch that conducts / cuts off between the application terminal of the input voltage Vin (+4 V) and the second terminal of the flying capacitor C3.

  The switch SW110 is an NMOS switch whose source and back gate are connected to the application terminal of the reference voltage Vss (0V) and whose drain is connected to the second terminal of the flying capacitor C3. The switch SW110 corresponds to a tenth switch that conducts / cuts off between the application terminal of the reference voltage Vss (0 V) and the second terminal of the flying capacitor C3.

  The output capacitor Cout is connected between the application terminal of the output voltage VoutN (−6 V) and the application terminal of the reference voltage Vss (0 V), and smoothes the output voltage VoutN.

  In the charge pump 11 of the first configuration example, the flying capacitor C1 to C3 is connected between the application terminal of the input voltage Vin (+ 4V) and the application terminal of the reference voltage Vss (0V), and the flying capacitors C1 to C3. ON / OFF control of the switches SW101 to SW110 is performed so as to alternately switch between the period B in which is connected between the application terminal of the reference voltage Vss (0V) and the application terminal of the output voltage VoutN (−6V). . Period A corresponds to a period in which the flying capacitors C1 to C3 are charged using the input voltage Vin, and period B is an output voltage obtained by charging the output capacitor Cout using charges stored in the flying capacitors C1 to C3. This corresponds to a period during which VoutN is output.

  FIG. 3 is a diagram for explaining the -1.5-fold voltage boosting operation. From the top, the connection relationship of the flying capacitors C1 to C3, the on / off states of the switches SW101 to SW110, and the negative charge pump 11 are illustrated. The node voltages V11 to V16 of each part are depicted for each of period A (left side of the paper) and period B (right side of the paper).

  In the period A, the switch SW101, the switch SW102, the switch SW105, the switch SW108, and the switch SW109 are turned on, and the switch SW103, the switch SW104, the switch SW106, the switch SW107, and the switch SW110 are turned off. As a result, the flying capacitors C1 and C2 are connected in series between the application terminal of the input voltage Vin and the application terminal of the reference voltage Vss, while the flying capacitor C3 is connected in parallel to these. Become. At this time, the voltage across the flying capacitors C1 and C2 is Vin / 2, and the voltage across the flying capacitor C3 is Vin (both are based on Vss).

  On the other hand, in the period B, the switch SW101, the switch SW102, the switch SW105, the switch SW108, and the switch SW109 are turned off, and the switch SW103, the switch SW104, the switch SW106, the switch SW107, and the switch SW110 are turned on. As a result, the flying capacitors C1 and C2 are connected in parallel between the application terminal of the input voltage Vin and the application terminal of the reference voltage Vss, while the flying capacitor C3 is connected in series to these. Become. At this time, since the voltages across the flying capacitors C1 to C3 are respectively held at the voltage values in the period A, the output voltage VoutN is −1.5 × Vin (Vss reference), and the boosting operation is −1.5 times. Is realized.

  Thus, in order to obtain a boosting factor (-1.5 times) that is not an integral multiple, serial-parallel switching is performed in which the connection relationship between the flying capacitors C1 to C3 is switched in series / parallel between the period A and the period B. A switch is required. In the negative charge pump 11 of the first configuration example, among the switches SW101 to SW110, the switches SW105 to SW108 connected between the flying capacitors C1 to C3 correspond to the series-parallel changeover switch.

  Here, a first difference different from the conventional configuration is that switches SW105 to SW108 are not used as CMOS switches in which PMOS switches and NMOS switches are complementarily combined, but as switches SW105 and SW108 that are turned on in period A. While using the PMOS switch, NMOS switches are used as the switches SW106 and SW107 that are turned on in the period B. The second difference is that the gate signals of the switches SW105 to SW108 are not pulse-driven between the input voltage Vin (+4 V) and the output voltage VoutN (-6 V), but the reference voltage Vss for each gate. This is a point where (0V) is fixedly applied. Hereinafter, the effect will be described in detail while paying attention to these differences.

  In the period A, when the switch SW101, the switch SW102, and the switch SW109 are turned on and the switch SW103, the switch SW104, and the switch SW110 are turned off, the respective nodes of the negative charge pump 11 (sources or drains of the switches SW105 to SW108). Are applied with the reference voltage Vss or node voltages V11 to V16 higher than the reference voltage Vss. Accordingly, the switches SW105 and SW108 that are PMOS switches are turned on, and the switches SW106 and SW107 that are NMOS switches are turned off.

  On the other hand, in the period B, when the switch SW101, the switch SW102, and the switch SW109 are turned off and the switch SW103, the switch SW104, and the switch SW110 are turned on, the respective nodes of the negative charge pump 11 (sources of the switches SW105 to SW108). To the reference voltage Vss or node voltages V11 to V16 lower than the reference voltage Vss. Accordingly, the switches SW105 and SW108 that are PMOS switches are turned off, and the switches SW106 and SW107 that are NMOS switches are turned on.

  As described above, in the negative charge pump 11 of the first configuration example, the gate signals of the switches SW105 to SW108 are not pulse-driven between the input voltage Vin (+4 V) and the output voltage VoutN (−6 V). Since the switches SW105 to SW108 can be appropriately controlled to be turned on / off, it is possible to reduce the withstand voltage of the switches SW105 to SW108.

  Specifically, the switches SW105 to SW108 are not high breakdown voltage elements that can withstand the voltage difference (10V) between the input voltage Vin and the output voltage VoutN, but the voltage difference (4V) between the input voltage Vin and the reference voltage Vss. Alternatively, it is possible to use a medium withstand voltage element (for example, withstand voltage 6.5 V) that can withstand a voltage difference (6 V) between the reference voltage Vss and the output voltage VoutN.

  That is, if the input voltage Vin and the output voltage VoutN are both equal to or lower than the withstand voltage of the medium withstand voltage element, the voltage difference between the gates, drains, and sources of the switches SW105 to SW108 is also equal to or less than the withstand voltage of the medium withstand voltage element. It is possible to use medium withstand voltage elements instead of high withstand voltage elements as .about.SW108.

  As described above, in the negative charge pump 11 of the first configuration example, since the medium withstand voltage element can be used as the switches SW105 to SW108, it is possible to reduce the circuit area and improve the current capability.

  Also, with the negative charge pump 11 of the first configuration example, appropriate on / off control can be realized while the gate signals of the switches SW105 to SW108 are fixed to the reference voltage Vss. Charging / discharging current for turning on / off is not necessary, and power efficiency can be improved.

  Note that for the switch SW101, the switch SW102, and the switch SW104, each gate signal may be pulse-driven between the reference voltage Vss (0 V) and the output voltage VoutN (−6 V). For the switches SW109 and SW110, each gate signal may be pulse-driven between the input voltage Vin (+4 V) and the reference voltage Vss (0 V). By performing such gate driving, the voltage applied to each switch can be kept low, so that a medium withstand voltage element can be used as each switch.

  On the other hand, since a voltage (8 V) exceeding the withstand voltage of the medium withstand voltage element is applied between the source and drain of the switch SW103, it is necessary to use a high withstand voltage element (for example, withstand voltage of 28 V). Therefore, the switch SW103 may be pulse-driven with the gate signal between the input voltage Vin (+4 V) and the output voltage VoutN (−6 V). By performing such gate driving, the on-resistance value of the switch SW103 can be reduced as compared with the case where the high level of the gate signal is set to the reference voltage Vss (0 V). And power efficiency can be improved.

  FIG. 4 is a circuit diagram showing a second configuration example of the negative charge pump 11. The negative charge pump 11 of the second configuration example is a circuit block that generates the output voltage VoutN (−6.25 V) by boosting the input voltage Vin (+2.5 V) by −2.5 times, and switches SW201 to SW213. And flying capacitors C1 to C4 and an output capacitor Cout. The switches SW201 to SW213 are semiconductor elements integrated in the liquid crystal driving device 10, and the flying capacitors C1 to C4 and the output capacitor Cout are discrete elements externally attached to the liquid crystal driving device 10.

  The switch SW201 is a PMOS switch whose source and back gate are connected to the application terminal of the reference voltage Vss (0V) and whose drain is connected to the first terminal (V27) of the flying capacitor C4. The switch SW201 corresponds to a first switch that conducts / cuts off between the application terminal of the reference voltage Vss (0V) and the first terminal of the flying capacitor C4.

  The switch SW202 is a PMOS switch whose source and back gate are connected to the application terminal of the reference voltage Vss (0V) and whose drain is connected to the first terminal (V25) of the flying capacitor C3. The switch SW202 corresponds to a second switch that conducts / cuts off between the application terminal of the reference voltage Vss (0 V) and the first terminal of the flying capacitor C3.

  The switch SW203 is a PMOS switch whose source and back gate are connected to the application terminal of the reference voltage Vss (0V) and whose drain is connected to the first terminal (V21) of the flying capacitor C1. The switch SW203 corresponds to a third switch that conducts / cuts off between the application terminal of the reference voltage Vss (0V) and the first terminal of the flying capacitor C1.

  The switch SW204 is an NMOS switch whose source and back gate are connected to the application terminal of the output voltage VoutN (−6.25 V) and whose drain is connected to the first terminal (V23) of the flying capacitor C2. The switch SW204 corresponds to a fourth switch that conducts / cuts off between the application terminal of the output voltage VoutN (−6.25V) and the first terminal of the flying capacitor C2.

  The switch SW205 is an NMOS switch whose source and back gate are connected to the application terminal of the output voltage VoutN (−6.25V) and whose drain is connected to the first terminal of the flying capacitor C1. The switch SW205 corresponds to a fifth switch that conducts / cuts off between the application terminal of the output voltage VoutN (−6.25V) and the first terminal of the flying capacitor C1.

  The switch SW206 is a PMOS switch whose source and back gate are connected to the second end (V22) of the flying capacitor C1, and whose drain is connected to the first end of the flying capacitor C2. The switch SW206 corresponds to a sixth switch that conducts / cuts off between the second end of the flying capacitor C1 and the first end of the flying capacitor C2.

  The switch SW207 is an NMOS switch whose drain is connected to the second end (V24) of the flying capacitor C2, and whose source and back gate are connected to the first end of the flying capacitor C3. The switch SW207 corresponds to a seventh switch that conducts / cuts off between the second end of the flying capacitor C2 and the first end of the flying capacitor C3.

  The switch SW208 is an NMOS switch whose drain is connected to the second end of the flying capacitor C1, and whose source and back gate are connected to the first end of the flying capacitor C3. The switch SW208 corresponds to an eighth switch that conducts / cuts off between the second end of the flying capacitor C1 and the first end of the flying capacitor C3.

  The switch SW209 is an NMOS switch whose drain is connected to the second end (V26) of the flying capacitor C3, and whose source and back gate are connected to the first end of the flying capacitor C4. The switch SW209 corresponds to a ninth switch that conducts / cuts off between the second end of the flying capacitor C3 and the first end of the flying capacitor C4.

  The switch SW210 is a PMOS switch whose drain is connected to the second end of the flying capacitor C3 and whose source and back gate are connected to the second end (V28) of the flying capacitor C4. The switch SW210 corresponds to a tenth switch that conducts / cuts off between the second end of the flying capacitor C3 and the second end of the flying capacitor C4.

  The switch SW211 is a PMOS switch whose drain is connected to the second end of the flying capacitor C2, and whose source and back gate are connected to the second end of the flying capacitor C4. The switch SW211 corresponds to an eleventh switch that conducts / cuts off between the second end of the flying capacitor C2 and the second end of the flying capacitor C4.

  The switch SW212 is a PMOS switch whose source and back gate are connected to the application terminal of the input voltage Vin (+ 2.5V) and whose drain is connected to the second terminal of the flying capacitor C4. The switch SW212 corresponds to a twelfth switch that conducts / cuts off between the application terminal of the input voltage Vin (+2.5 V) and the second terminal of the flying capacitor C4.

  The switch SW213 is an NMOS switch whose source and back gate are connected to the application terminal of the reference voltage Vss (0 V) and whose drain is connected to the second terminal of the flying capacitor C4. The switch SW213 corresponds to a thirteenth switch that conducts / cuts off between the application terminal of the reference voltage Vss (0 V) and the second terminal of the flying capacitor C4.

  The output capacitor Cout is connected between the application terminal of the output voltage VoutN (−6.25 V) and the application terminal of the reference voltage Vss (0 V), and smoothes the output voltage VoutN.

  In the charge pump 11 of the second configuration example, a period A in which the flying capacitors C1 to C4 are connected between the application terminal of the input voltage Vin (+2.5 V) and the application terminal of the reference voltage Vss (0 V), and the flying capacitor C1 ON / OFF control of the switches SW201 to SW213 so that the period B in which .about.C4 is connected between the application terminal of the reference voltage Vss (0 V) and the application terminal of the output voltage VoutN (−6.25 V) is alternately switched. Is done. The period A corresponds to a period in which the flying capacitors C1 to C4 are charged using the input voltage Vin, and the period B is an output voltage obtained by charging the output capacitor Cout using the charges stored in the flying capacitors C1 to C4. This corresponds to a period during which VoutN is output.

  FIG. 5 is a diagram for explaining a -2.5 times boosting operation. From the top, the connection relationship of the flying capacitors C1 to C4, the on / off states of the switches SW201 to SW213, and the voltages V21 to V28 are illustrated. Are depicted for each of period A (left side of the paper) and period B (right side of the paper).

  In the period A, the switches SW201 to SW203, the switch SW206, and the switches SW210 to SW212 are turned on, and the switch SW204, the switch SW205, the switches SW207 to SW209, and the switch SW213 are turned off. As a result, the flying capacitors C1 and C2 are connected in series between the application terminal of the input voltage Vin and the application terminal of the reference voltage Vss, while the flying capacitors C3 and C4 are connected in parallel to these. It becomes a state. At this time, the voltage across the flying capacitors C1 and C2 is Vin / 2, and the voltage across the flying capacitors C3 and C4 is Vin (both are based on Vss).

  On the other hand, in the period B, the switches SW201 to SW203, the switch SW206, and the switches SW210 to SW212 are turned off, and the switch SW204, the switch SW205, the switches SW207 to SW209, and the switch SW213 are turned on. As a result, the flying capacitors C1 and C2 are connected in parallel between the application terminal of the input voltage Vin and the application terminal of the reference voltage Vss, while the flying capacitors C3 and C4 are connected in series to these. It becomes a state. At this time, since the voltages across the flying capacitors C1 to C4 are held at the voltage values in the period A, the output voltage VoutN is −2.5 × Vin (Vss reference), and the boosting operation is −2.5 times. Is realized.

  In this way, in order to obtain a boosting factor (−2.5 times) that is not an integral multiple, serial-parallel switching that switches the connection relationship between the flying capacitors C1 to C4 between the period A and the period B in series / parallel. A switch is required. In the negative charge pump 11 of the second configuration example, among the switches SW201 to SW213, the switches SW206 to SW211 connected between the flying capacitors C1 to C4 correspond to the series-parallel changeover switch.

  Here, the first difference from the conventional configuration is that the switches SW206 to SW211 do not use CMOS switches in which PMOS switches and NMOS switches are complementarily combined, but are switches SW206 and SW210 that are turned on in the period A. In addition, a PMOS switch is used as the switch SW211 and an NMOS switch is used as the switches SW207 to SW209 that are turned on in the period B. The second difference is that the gate signals of the switches SW206 to SW211 are not pulse-driven between the input voltage Vin (+2.5 V) and the output voltage VoutN (−6.25 V), but to each gate. The reference voltage Vss (0 V) is fixedly applied. Hereinafter, the effects will be described in detail while paying attention to these differences.

  In the period A, when the switches SW201 to SW203 and the switch SW212 are turned on and the switches SW204, SW205 and SW213 are turned off, the respective nodes of the negative charge pump 11 (sources or drains of the switches SW206 to SW211 are switched). In addition, the reference voltage Vss or node voltages V21 to V28 higher than the reference voltage Vss are applied. Accordingly, the switches SW206, SW210, and SW211 that are PMOS switches are turned on, and the switches SW207 to SW209 that are NMOS switches are turned off.

  On the other hand, in the period B, when the switches SW201 to SW203 and the switch SW212 are turned off and the switch SW204, the switch SW205 and the switch SW213 are turned on, the respective nodes of the negative charge pump 11 (sources or switches of the switches SW206 to SW211). The node voltage V21 to V28 is applied to the reference voltage Vss or lower than the reference voltage Vss. Accordingly, the switches SW206, SW210, and SW211 that are PMOS switches are turned off, and the switches SW207 to SW209 that are NMOS switches are turned on.

  Thus, in the negative charge pump 11 of the second configuration example, the gate signals of the switches SW206 to SW211 are pulse-driven between the input voltage Vin (+2.5 V) and the output voltage VoutN (−6.25 V). Even if not, the switches SW206 to SW211 can be appropriately turned on / off, so that the switches SW206 to SW211 can be reduced in breakdown voltage.

  Specifically, the switches SW206 to SW211 are not high withstand voltage elements that can withstand the voltage difference (8.75 V) between the input voltage Vin and the output voltage VoutN, but the voltage difference between the input voltage Vin and the reference voltage Vss ( 2.5V) or a medium withstand voltage element (for example, withstand voltage 6.5V) that can withstand a voltage difference (6.25V) between the reference voltage Vss and the output voltage VoutN can be used.

  That is, if the input voltage Vin and the output voltage VoutN are both equal to or lower than the withstand voltage of the medium withstand voltage element, the voltage difference between the gates, drains, and sources of the switches SW206 to SW211 is also equal to or less than the withstand voltage of the medium withstand voltage element. It is possible to use medium withstand voltage elements instead of high withstand voltage elements as .about.SW211.

  Thus, in the case of the negative charge pump 11 of the second configuration example, the medium withstand voltage element can be used as the switches SW206 to SW211. Therefore, the circuit area can be reduced and the current capability can be improved.

  In the negative charge pump 11 of the second configuration example, appropriate on / off control can be realized while fixing the gate signals of the switches SW206 to SW211 to the reference voltage Vss. Charging / discharging current for turning on / off is not necessary, and power efficiency can be improved.

  For the switches SW201 to SW203 and the switch SW205, each gate signal may be pulse-driven between the reference voltage Vss (0 V) and the output voltage VoutN (−6.25 V). For the switches SW212 and SW213, each gate signal may be pulse-driven between the input voltage Vin (+2.5 V) and the reference voltage Vss (0 V). By performing such gate driving, the voltage applied to each switch can be kept low, so that a medium withstand voltage element can be used as each switch.

  On the other hand, since a voltage (7.5 V) exceeding the withstand voltage of the medium withstand voltage element is applied between the source and drain of the switch SW204, it is necessary to use a high withstand voltage element (for example, withstand voltage of 28 V). Therefore, the switch SW204 may be pulse-driven with its gate signal between the input voltage Vin (+2.5 V) and the output voltage VoutN (−6.25 V). By performing such gate driving, the on-resistance value of the switch SW204 can be reduced as compared with the case where the high level of the gate signal is set to the reference voltage Vss (0 V). And power efficiency can be improved.

<Application to electronic devices>
FIG. 6 is an external view of a mobile phone (smart phone) provided with the above-described liquid crystal display device 1. The mobile phone (smart phone) X is a specific example of an electronic device that can be mounted on the liquid crystal display device 1. In terms of appearance, the imaging unit X1 mounted on the front surface or the back surface of the main body and an operation for accepting a user operation It has a part X2 (such as various buttons) and a display part X3 that displays characters and video. The large display unit X3 is equipped with a touch panel function for accepting a user's touch operation.

  By providing the above-described liquid crystal display device 1 as the display unit X3, the mobile phone (smartphone) X can be reduced in size and weight, or the battery life can be improved.

<Other variations>
In the above embodiment, the detailed description has been given by taking the configuration in which the present invention is applied to the negative charge pump for the liquid crystal driving device as an example. However, the application target of the present invention is not limited to this. The present invention can be widely applied to all polarity inversion type charge pumps having a step-up ratio that is not an integral multiple.

  Various technical features disclosed in the present specification can be variously modified within the scope of the technical creation in addition to the above-described embodiment.

  For example, in the above-described embodiment, the reference voltage Vss has been described as an example of a configuration in which the reference voltage Vss is 0 V (ground voltage). It doesn't matter.

  Further, in the above-described embodiment, the first configuration example of the −1.5 times boost type (see FIGS. 2 and 3) and the second configuration example of the −2.5 times boost type (see FIGS. 4 and 5). However, the step-up ratio is not limited to this, and it goes without saying that a circuit configuration similar to the above can also be adopted for charge pumps having other step-up ratios. .

  That is, the above-described embodiment is to be considered in all respects as illustrative and not restrictive, and the technical scope of the present invention is indicated not by the description of the above-described embodiment but by the scope of the claims. It should be understood that all modifications that fall within the meaning and range equivalent to the terms of the claims are included.

  The present invention can be used to reduce the size of a polarity inversion type charge pump having a step-up ratio that is not an integral multiple, improve current capability, or improve power efficiency.

DESCRIPTION OF SYMBOLS 1 Liquid crystal display device 10 Liquid crystal drive device 11 Negative charge pump 12 Positive charge pump 13 Gate driver 20 Liquid crystal display panel SW101-110 switch (SW105-108: Series parallel switch)
SW201 to 213 switches (SW206 to 211: Series-parallel switch)
C1-C4 Flying capacitor Cout Output capacitor X Mobile phone (smartphone)
X1 imaging unit X2 operation unit X3 display unit

Claims (12)

A first period in which a plurality of flying capacitors are connected between an input end of an input voltage and an application end of a reference voltage; and a plurality of flying capacitors are connected between an end of application of the reference voltage and an application end of an output voltage A polarity inversion type charge pump having a plurality of switches that are turned on / off to alternately switch between the second period and
Of the plurality of switches, a series-parallel switch that switches the connection relationship between the flying capacitors in series / parallel between the first period and the second period so as to obtain a boosting factor that is not an integral multiple. The switch that is turned on in the first period is a PMOS switch, the switch that is turned on in the second period is an NMOS switch, and each of the gates of the series-parallel changeover switch has the reference A charge pump in which a voltage is fixedly applied.   Each of the series-parallel changeover switches is not a high withstand voltage element that can withstand a voltage difference between the input voltage and the output voltage, but a voltage difference between the input voltage and the reference voltage, or the reference voltage and the output The charge pump according to claim 1, wherein the charge pump is a medium withstand voltage element capable of withstanding a voltage difference from the voltage.   The charge pump according to claim 2, wherein the reference voltage is a ground voltage.   4. The charge pump according to claim 3, wherein the boosting is performed by -1.5 times using the first to third flying capacitors. As the plurality of switches,
A first switch for conducting / cutting off between the application terminal of the reference voltage and the first terminal of the third flying capacitor;
A second switch for conducting / cutting off between the application terminal of the reference voltage and the first terminal of the first flying capacitor;
A third switch for conducting / cutting off between the application terminal of the output voltage and the first terminal of the second flying capacitor;
A fourth switch for conducting / cutting off between the application terminal of the output voltage and the first terminal of the first flying capacitor;
A fifth switch for conducting / interrupting between the second end of the first flying capacitor and the first end of the second flying capacitor;
A sixth switch for conducting / blocking between a second end of the second flying capacitor and a first end of the third flying capacitor;
A seventh switch for conducting / blocking between the second end of the first flying capacitor and the first end of the third flying capacitor;
An eighth switch that conducts / cuts off between the second end of the second flying capacitor and the second end of the third flying capacitor;
A ninth switch that conducts / cuts off between the application terminal of the input voltage and the second terminal of the third flying capacitor;
A tenth switch that conducts / cuts off between the application terminal of the reference voltage and the second terminal of the third flying capacitor;
Including
5. The charge pump according to claim 4 , wherein the fifth to eighth switches connected between the first to third flying capacitors correspond to the series-parallel changeover switch.   In the first period, the first switch, the second switch, the fifth switch, the eighth switch, and the ninth switch are turned on, and the third switch, the fourth switch, and the sixth switch are turned on. The switch, the seventh switch, and the tenth switch are turned off. In the second period, the first switch, the second switch, the fifth switch, the eighth switch, and the ninth switch are 6. The charge pump according to claim 5, wherein the charge pump is turned off, and the third switch, the fourth switch, the sixth switch, the seventh switch, and the tenth switch are turned on.   4. The charge pump according to claim 3, wherein the boosting is performed by -2.5 times using the first to fourth flying capacitors. As the plurality of switches,
A first switch that conducts / cuts off between the application terminal of the reference voltage and the first terminal of the fourth flying capacitor;
A second switch for conducting / cutting off between the application terminal of the reference voltage and the first terminal of the third flying capacitor;
A third switch for conducting / interrupting between the application terminal of the reference voltage and the first terminal of the first flying capacitor;
A fourth switch for conducting / cutting off between the application terminal of the output voltage and the first terminal of the second flying capacitor;
A fifth switch for conducting / cutting off between the application terminal of the output voltage and the first terminal of the first flying capacitor;
A sixth switch that conducts / cuts off between the second end of the first flying capacitor and the first end of the second flying capacitor;
A seventh switch for conducting / interrupting between the second end of the second flying capacitor and the first end of the third flying capacitor;
An eighth switch for conducting / blocking between the second end of the first flying capacitor and the first end of the third flying capacitor;
A ninth switch that conducts / cuts off between the second end of the third flying capacitor and the first end of the fourth flying capacitor;
A tenth switch for conducting / blocking between a second end of the third flying capacitor and a second end of the fourth flying capacitor;
An eleventh switch for conducting / blocking between a second end of the second flying capacitor and a second end of the fourth flying capacitor;
A twelfth switch that conducts / cuts off between the application terminal of the input voltage and the second terminal of the fourth flying capacitor;
A thirteenth switch for conducting / cutting off between the application terminal of the reference voltage and the second terminal of the fourth flying capacitor;
Including
8. The charge pump according to claim 7, wherein the sixth to eleventh switches connected between the first to fourth flying capacitors correspond to the series-parallel changeover switch.   In the first period, the first to third switches, the sixth switch, and the tenth to twelfth switches are turned on, and the fourth switch, the fifth switch, and the seventh to ninth switches And the thirteenth switch is turned off, and in the second period, the first to third switches, the sixth switch, and the tenth to twelfth switches are turned off, and the fourth switch, 9. The charge pump according to claim 8, wherein the fifth switch, the seventh to ninth switches, and the thirteenth switch are turned on.   10. A liquid crystal drive device comprising: the charge pump according to claim 1; and a driver that generates a drive signal for a liquid crystal display panel using an output voltage of the charge pump. .   A liquid crystal display device comprising: a liquid crystal display panel; and the liquid crystal driving device according to claim 10 which generates a driving signal for the liquid crystal display panel.   An electronic apparatus comprising the liquid crystal display device according to claim 11.

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