JP2007049809A - Boosting circuit and camera module using the boosting circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a boosting circuit small in chip area, reduced in output resistance and low in cost, and a camera module using the boosting circuit. <P>SOLUTION: The boosting circuit comprises: a first charge pump circuit 55 that outputs a voltage that is stepped down a half time as large as an input voltage; a second charge pump circuit 56 that outputs a voltage boosted twice as large as the input voltage; and a bypass capacitor 57 that is arranged between the earth and a connecting point 62 that connects the output end of the first charge pump circuit 55 and the input end of the second charge pump circuit 56. More suitably, a one-and-a-half-time charge pump circuit connected to the earth at its clock-buffer output end position is employed as the first charge pump circuit 55, and a two-time charge pump circuit is employed as the second charge pump circuit 56. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a booster circuit and a camera module using the booster circuit.

  FIG. 5 is a typical block diagram of a CCD camera module mounted on a conventional camera-equipped mobile phone. An optical image of a subject is formed on the CCD image sensor 1 by the imaging lens 2, and the CCD image sensor 1 photoelectrically converts the image data of this optical image, and the captured image data is output from the CCD image sensor 1 as an electrical signal. .

  The electrical signal output from the CCD image sensor 1 is subjected to signal processing by an analog front end (AFE) 3 and finally converted from an analog signal to a digital signal, and a digital signal processor (DSP) 4 which is a digital image processing LSI. Is output.

  Since the AFE 3 is an analog circuit and requires a dynamic range, it often requires a power supply voltage VDD of about 2.9 V and several tens of mA. Further, since the DSP 4 is a complete logic LSI, it is manufactured by a miniaturized process such as a 0.13 μm rule, and its power supply voltage is often about 1.5V. Since the power supply voltage VDSP (1.5 V) for the DSP 4 is also used in the baseband in the mobile phone which is the main body of the device, it is generated and supplied by the power circuit 5 of the mobile phone main body, and the DSP 4 is also supplied to the main body device side. Often provided.

  On the other hand, in order to drive the CCD image sensor 1, an H electrode driver (HDR) 6 is used for driving the H electrode (transfer electrode for horizontal register) and a V electrode is used for driving the V electrode (transfer electrode for vertical register). A driver (VDR) 7 is required.

  The HDR 6 for driving the CCD image sensor 1 is a driver for transferring and driving the horizontal register of the CCD image sensor 1, and a necessary voltage is determined by the CCD image sensor 1, but a power supply of about 10 mA at 3.2V. The voltage VCC is often required.

  Further, since the vertical register needs to be driven with three values of VH, VM, and VL, the three power supply voltages are required. However, since VM is generally used at 0V, the power supply required for VDR7 is required. As voltages, VH (+15 V, about several mA) and VL (−7.5 V, about several mA) are required. This power supply voltage VH is also supplied to an amplifier provided in the horizontal register output stage.

  Of the above components, the DSP 4 does not necessarily have to be in the vicinity of the CCD image sensor 1 as a camera module. However, since the AFE3, HDR6 and VDR7 are disposed in the vicinity of the CCD image sensor 1 as a camera module component, Usually, a dedicated power supply (PWR) 8 is provided.

  This PWR 8 receives the battery voltage VBAT (about 3.2 V to 4.3 V) from the battery 9 attached to the apparatus body, and VH (+15 V), VL (−7.5 V), VDD (2.9 V) described above. , VCC (3.2 V) is generated and supplied to each component device of the camera module.

  FIG. 6 is a block diagram of the PWR8. The PWR 8 receives the battery voltage VBAT and outputs a VDD voltage of 2.9 V, the first series regulator 11, the first charge pump circuit 12 that takes in the output voltage of the first series regulator 11 and boosts it six times, The second series regulator 13 that takes in the output voltage (2.9V × 6 = 17.4V) of the one charge pump circuit 12 and outputs + 15V that is the VH voltage, and the output voltage of the first series regulator 11 takes in and is tripled The second charge pump circuit 14 that boosts the voltage and the third series that takes in the output voltage (2.9 V × (−3) = − 8.7 V) of the second charge pump circuit 14 and outputs −7.5 V that is the VL voltage The third charge pump circuit 1 that takes in the output voltage of the regulator 15 and the first series regulator 11 and boosts it by 1.5 times 6 and a fourth series regulator 17 that takes in the output voltage of the third charge pump circuit 16 (2.9 V × (1.5) = 4.35 V) and outputs the VCC voltage of 3.2 V.

  Since the power supply voltage VDD (= 2.9 V) required by the AFE 3 is always lower than the battery voltage VBAT, it can be generated by the first series regulator 11, but other power supply voltages VH, VL, VCC are Since the voltage is equal to or higher than the VBAT voltage, the booster circuits 12, 14, and 16 and the series regulators 13, 15, and 17 are combined.

  A switching power supply using a transformer or a coil may be used as the booster circuit. However, as described in Patent Document 1 below, when a high voltage is required in a cellular phone or the like, a switching regulator using a coil has a magnetic flux around it. Therefore, a charge pump circuit that can be realized with a capacitor is often used as a booster circuit.

  The voltage VBAT supplied from the battery 9 is input to the first series regulator 11 to generate 2.9 V, which is supplied to the AFE 3. On the other hand, this 2.9V is input to each charge pump circuit 12, 14, 16 and after boosting, the voltage is dropped by the series regulators 13, 15, 17 to obtain desired power supply voltages VH, VL, VCC. can get.

  Since the charge pump circuits 12, 14, and 16 generate ripples in the output voltage due to fluctuations in the output voltage due to the load and clock operation, if the series regulators 13, 15, and 17 are provided in the subsequent stage, the ripples are removed, and the power supply voltage VH, HL and VCC can be stabilized.

  The reason why the battery voltage VBAT is not directly input to the charge pump circuits 12, 14, and 16 is because the breakdown voltage of the MOS transistor used in the charge pump circuits 12, 14, and 16 is taken into consideration. In the charge pump circuits 12, 14, and 16, a voltage twice as large as the input voltage is applied to each transistor. However, in a conventional CMOS process, a withstand voltage of about 6V is often set, and the maximum voltage of the battery is set. When 4.3V is input, a voltage exceeding the rated voltage is applied to the MOS transistor, and thus a regulated voltage is required.

On the other hand, the amount of voltage drop generated in a general series regulator is about 0.2 to 0.3V, and the output of the first series regulator 11 is set to 2.9V in view of the balance between the two. The number of stages of the charge pump circuit is the voltage drop (ΔVcp) determined by the output voltage (Vout) of the regulator connected thereto, the input / output voltage difference (ΔVsr) in the regulator, and the output resistance and load current of the charge pump circuit. By
VDD × n> Vout + ΔVcp + ΔVsr
It is determined to be.

  When the difference between the right side and the left side (VDD × n−Vout−ΔVcp−ΔVsr) increases, the difference becomes a power loss, and therefore it is necessary to select an optimum value for n.

  FIG. 7 is a typical circuit diagram of a charge pump circuit that doubles an input voltage for output. A charge pump circuit developed by Dixon and using a diode as a rectifying element is well known, but a MOS transistor is generally used instead of a diode in order to increase the boosting efficiency.

  The charge pump circuit shown in FIG. 7 basically has rectifying transistors 23 and 24 functioning as two rectifying elements arranged in series between an input voltage terminal 21 and an output voltage terminal 22, and both transistors 23, One end of a capacitor 26 for charge pump is connected to 24 connection points 25, and the output end of the clock buffer 27 is connected to the other end of the capacitor 26. 7 are transistors that set the operating points of the transistors 23 and 24, respectively.

  When a voltage VDD is applied to the input voltage terminal 21 and a clock having a VDD amplitude is applied to the input terminal of the clock buffer 27 in the charge pump circuit having such a configuration, the voltage applied to the input voltage terminal 21 is applied to the output voltage terminal 22. A voltage [2 × VDD] in which the voltage VDD corresponding to the clock amplitude is superimposed on VDD appears. By multiplying such double charge pump circuits in multiple stages, an output n * VDD of an arbitrary integer multiple can be obtained.

  Since the voltages VH and VL consume little current, even if n is an integer, the loss can be ignored. However, regarding the horizontal register drive voltage (VHD) through which a large current flows, if it is multiplied by an integer, the power loss becomes so large that it cannot be ignored. Therefore, conventionally, as described in Patent Document 2, it is common to use a 1.5 times charge pump circuit whose equivalent circuit is shown in FIG.

  In the 1.5 times charge pump circuit of FIG. 8, two rectifying transistors 33 and 34 are connected in series between an input terminal 31 to which a voltage VDD is applied and an output terminal 32, and both transistors 33 and 34 are connected. Two capacitors 37 and 38 for charge pumps are connected in series via a changeover switch 39 between a connection point 35 of the signal and a clock buffer 36 to which a clock having a voltage amplitude VDD is input, and the changeover switch connected in series. The selector switch 40 that short-circuits the capacitor 39 and the capacitor 37 and the selector switch 41 that short-circuits the selector switch 39 and the capacitor 38 connected in series are provided.

  In the 1.5 × charge pump circuit having such a configuration, as shown in the left diagram of FIG. 9, when the output of the clock buffer 36 becomes 0 V, the switch 39 is “closed” and the switches 40 and 41 are “open”. Then, the potential difference between both ends of each of the capacitors 37 and 38 is VDD / 2. Next, when the output of the clock buffer 36 becomes high level, the switch 39 is opened and the switches 40 and 41 are closed, so that both capacitors 37 and 38 are connected in parallel as shown in the right diagram of FIG. The voltage difference VDD / 2 across the capacitors 37 and 38 is superimposed on the voltage VDD applied to the input terminal 31 and rectified by the rectifying transistor 34. As a result, VDD + VDD / 2 = 1.5 VDD is output from the output terminal 32.

JP 2001-231249 A JP 2001-169537 A

  As described above, the power loss is improved by using a 1.5 times booster circuit instead of 2 times as a booster circuit for driving the horizontal register. However, the number of pixels of recent camera modules has increased to millions of pixels. As the number of pixels increases in this way, the current consumed by the CCD image sensor 1 also increases. In particular, with regard to the H electrode of the horizontal register, a higher frame rate is required when the number of pixels increases, resulting in an increase in current consumption. Therefore, an extremely low output resistance is required for the 1.5 times charge pump circuit.

  For this reason, the size of the charge pump circuit 16 (see FIG. 6) for generating the power supply voltage VHD for driving the horizontal register is increased, which causes a high manufacturing cost of the chip on which the CCD image sensor is mounted.

  Generally, the charge pump circuit is not suitable for an application that takes out a large current (several tens of mA or more). Conventionally, the number of pixels of a CCD image sensor for a cellular phone is small and the current consumption is less than that of a digital camera. Therefore, the charge pump circuit 16 shown in FIG. In order to achieve this, a 1.5 times charge pump circuit is required to have an extremely low output resistance, which is becoming difficult to realize.

  However, in the case of the charge pump circuit disclosed in Patent Document 2, since the pumping capacitors 37 and 38 are rearranged by the switches 39, 40, and 41, the on-resistance of the switches 39 to 41 becomes a problem. That is, in a charge pump circuit that requires a large current, its output resistance needs to be lowered. To that end, the series resistance of the path from the pumping clock buffer 36 to the output needs to be sufficiently low.

  That is, not only the output resistance of the clock buffer 36 is lowered, but also the switches 39 to 41 for recombination are required to have a low on-resistance. The switches 39, 40, and 41 are implemented using MOS transistors. However, in order to reduce the on-resistance, it is necessary to increase the area of the MOS transistor, which causes a problem that the chip cost increases.

  An object of the present invention is to provide a low-cost booster circuit having a small chip area and a small output resistance, and a camera module using the booster circuit.

  The booster circuit according to the present invention includes a DC voltage input terminal to which a first voltage is applied, and a clock input terminal to which a clock signal that swings between a second voltage and a ground potential is input. In the booster circuit that outputs a voltage obtained by superimposing the second voltage and the second voltage, the first voltage is set lower than the second voltage.

  According to the camera module of the present invention, in the camera module attached to the apparatus main body, the power supply circuit on the apparatus main body side generates a first voltage lower than the voltage of the apparatus power supply from the apparatus power supply. To generate a second voltage lower than the apparatus power supply and higher than the first voltage, and each of the second voltages is input to the booster circuit.

  The first voltage of the camera module of the present invention is generated by a switching power supply circuit.

  The second voltage of the camera module of the present invention is generated by a series regulator type power supply circuit.

  The step-up circuit according to the present invention includes a step-down means for generating and outputting a fourth voltage lower than the third voltage from the input third voltage, and between the output terminal of the step-down means and the ground potential. Provided with a bypass capacitor, a DC voltage input terminal to which the fourth voltage is applied, and a clock input terminal to which a clock signal that swings between the second voltage and the ground potential is input, A voltage obtained by superimposing the fourth voltage and the second voltage is output.

  In the booster circuit of the present invention, the second voltage and the third voltage are the same, and the fourth voltage is 0.5 times the second voltage or the third voltage. 2 or 1.5 times the third voltage is obtained.

  The step-down means of the step-up circuit of the present invention is characterized by using a capacitor and a switch.

  The camera module of the present invention is a power supply that maximizes power consumption among the constituent circuits of a camera module-side power supply device that generates a plurality of power supply voltages required for driving the camera module in a camera module attached to the apparatus body. The step-up circuit described above is used as a constituent circuit for generating a voltage.

  The imaging device of the camera module of the present invention is a CCD image sensor, and the power source maximizing power consumption is a power source for driving a horizontal transfer register of the CCD.

  According to the present invention, the output impedance can be lowered by using the bypass capacitor even if the MOS transistor constituting the switch or the like has a small area, so that the output resistance can be lowered.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a block configuration diagram around a camera module of the camera module mounting apparatus according to the first embodiment of the present invention. Since the basic configuration in the CCD camera module of the present embodiment is the same as the conventional configuration described in FIG. 5, detailed description thereof will be omitted, and only different portions will be described.

  In the camera module mounting apparatus of the present embodiment, the main body power supply circuit 50 provided on the apparatus main body side generates the voltage VDSP (1.5 V), and this voltage 1.5 V is used as the camera module power supply apparatus (PWR) 51. It is also configured to supply.

  The camera module power supply (PWR) 51 receives the supply of the battery voltage VBAT from the battery 9 as described in FIG. 6, and the first series regulator 11 generates the power supply voltage VDD (2.9 V) from the battery voltage. The power supply voltages VH (+15 V) and VL (−7.5 V) are generated from the voltage VDD. In the power supply device 51 of this embodiment, the power supply voltage VCC (3.2 V) supplied to the H electrode of the horizontal register is generated. ) Is generated by a booster circuit 52 and a series regulator 17 which will be described later.

  FIG. 3 is a detailed circuit diagram of the booster circuit 52 shown in FIG. The configuration of the booster circuit 52 is the same as that of the double charge pump circuit described in FIG. For this reason, the same reference numerals are given to the same circuit elements, and the description thereof is omitted.

  The booster circuit 52 of the present embodiment generates a voltage approximately 1.5 times the voltage VDD from the voltage VDD generated by the first series regulator 11 and the voltage VDSP supplied from the main body power supply circuit 50.

  That is, in this embodiment, a voltage of 1.5 V (voltage generated by the main body power supply circuit 20 for the DSP 4) is applied to the input voltage terminal 21 shown in FIG. Apply.

  As a result, a voltage of 1.5 V + VDD (= 2.9 V) = 4.4 V is output from the output terminal 22, which is stepped down to 3.2 V by the series regulator 17 shown in FIG. 2, and HDR 6 (see FIG. 1). To be supplied.

  Now, the output of the clock buffer (clock driver) 27 is CLK1, the clock applied to the gate of the transfer transistor 23 is CLK2, and the clock applied to the gate of the transfer transistor 24 is CLK3.

  When CLK1 is set to 0V, CLK2 is set to 0V, and CLK3 is set to VDD, that is, 2.9V with 1.5V applied to the input terminal 21, the transistor 23 is turned on and the capacitor 26 is charged.

  In this case, since the CLK1, that is, the output of the clock buffer 27 is 0V, the voltage difference between both ends of the capacitor 26 is 1.5V. In addition, the operating point setting transistor 28 is in an OFF state because 1.5 V is applied to the source and 1.5 V is also applied to the gate.

  Further, paying attention to the operating point setting transistor 29 and the transistor 24, since CLK1 is 0 V, the operating point setting transistor 29 is on, and the gate and the source of the transistor 24 have the same potential. Is turned off, the charge from the input is stored only in the capacitor 26, and the backflow of the charge from the output side is prevented.

  Next, CLK1 is changed from 0V to 2.9V, CLK2 is also changed from 0V to 2.9V, and CLK3 is changed from 2.9V to 0V. Since CLKl becomes 2.9V, the source of the transistor 23 connected to the capacitor 26, the drain of the transistor 24, and the source of the operating point setting transistor 28 become 4.4V (VDD + VDSP).

  Here, paying attention to the transistor 24, since CLK3 becomes 0V, the transistor 24 is turned on, and 4.4V (2.9V + 1.5V) is output to the output terminal 22. If attention is paid to the operating point setting transistor 28, the source is 4.4V and the gate voltage is 1.5V, so that the ON state is set. For this reason, the gate and the source of the transistor 23 are at the same potential, and the transistor 23 is turned off. Thereby, the backflow of electric charge is prevented.

  Since the booster circuit of this embodiment does not have a selector switch as compared with the 1.5 times charge pump circuit shown in FIG. 8, it is not necessary to increase the area of the MOS transistor for the selector switch, and the chip area can be reduced.

(Second Embodiment)
FIG. 4 is a configuration diagram of the booster circuit 52 according to the second embodiment of the present invention. The booster circuit 52 of the present embodiment includes a first circuit unit 55, a second circuit unit 56, and a connection point between both circuit units 55 and 56 (an output terminal of the first circuit unit 55, and also a second circuit unit 56. And a bypass capacitor 57 connected between the input terminal) and ground.

  The first circuit section 55 is connected in series between two transistors 63 and 64 connected in series between the input terminal 61 and the output terminal 62, and between a connection point 65 of both transistors 63 and 64 and the ground. A capacitor 66, a changeover switch 67, a capacitor 68, a changeover switch 69 that short-circuits the capacitor 66 and the switch 67 connected in series, and a changeover switch 70 that short-circuits the switch 67 and the capacitor 68 connected in series. .

  The second circuit unit 56 includes two transfer transistors 72 and 73 connected in series between the input terminal 62 and the output terminal 71, a connection point 74 between the transistors 72 and 73, and an output terminal of the clock buffer 75. And a charging capacitor 76 provided between them, and a clock having a VDD amplitude is input to the clock buffer 75. The illustrated transistor 77 is a transistor that sets the operating point of the transfer transistor 72, the transistor 78 is a transistor that sets the operating point of the transistor 77, and the transistor 79 is a transistor that sets the operating point of the transfer transistor 73.

  The first circuit unit 55 has a circuit configuration similar to that of the 1.5 × charge pump circuit described in FIG. 8, but the clock buffer 36 of FIG. 8 is not provided and this position is grounded. .Has a function to make 5 times. The first circuit unit 55 is composed of a switched capacitor and has a large output impedance, but the impedance can be lowered by the bypass capacitor 57. For this reason, even if the on-resistance of the switch is large, it is only necessary to supply necessary electric charges.

  The second circuit unit 56 has a circuit configuration similar to the double charge pump circuit described with reference to FIG. 7 except that a transistor 78 that determines the operating point of the transistor 77 is added. The output voltage of the clock buffer 75 is added to the applied voltage 62 and supplied to the output terminal 71. Unlike the first circuit unit 55, the second circuit unit 56 does not have a changeover switch, and therefore only the on-resistance of the clock buffer 75 needs to be minimized.

  In the booster circuit 52 of the present embodiment, the power supply voltage VDD (2.9 V) is applied to the input terminal 61 of the first circuit unit 55. The clock applied to the gate of the transfer transistor 63 is CLK10, and the clock applied to the gate of the transfer transistor 64 is CLK11.

  CLK10 is set to 0V, CLK11 is set to 2.9V, the switch 67 is turned on, the switches 69 and 70 are turned off, and the two capacitors 66 and 68 are connected in series. The capacitors 66 and 68 connected in series are charged by the 2.9V power supply. In this case, the same amount of current flows through the two capacitors 66 and 68, so the charges stored in the capacitors 66 and 68 are As a result, the respective inter-terminal voltages of the capacitors 66 and 68 are equally 1.45V.

  Next, when CLK10 and CLK11 are set to 2.9 V, the two transfer transistors 63 and 64 are turned off, the switch 67 is turned off, and the switches 69 and 70 are turned on, the capacitors 66 and 68 are connected in parallel. The node of the source of the transfer transistor 63 and the drain of the transfer transistor 64 is 1.45V. Finally, when CLK10 is set to 2.9V and CLK11 is set to 0V, the transfer transistor 64 is turned on, and 1.45V is output to the output terminal 62 of the first circuit section 55 (input terminal of the second circuit section 56).

  In the voltage down-conversion by the first circuit unit 55, each node voltage does not exceed the power supply voltage 2.9V, so that an operating point setting transistor is not necessary. The voltage of 1.45V output from the voltage down converter (first circuit unit 55) becomes the input voltage of the next-stage charge pump circuit (second circuit unit 56).

  Since the operation of the second circuit unit 56 is the same as that of the first embodiment, the description thereof is omitted. As a result, the output voltage of the first circuit unit 55 is 1.45V and the input clock voltage of the clock buffer 75 is A voltage of 4,35V (1.45V + 2.9V) on which VDD is superimposed is output to the output terminal 71.

  In the booster circuit 52 of the present embodiment, since the bypass capacitor 57 is added between the first circuit unit 55 and the second circuit unit 56, the output impedance of the first circuit unit 55 becomes small enough to be ignored. High efficiency can be achieved as compared with the conventional 1.5 times charge pump circuit described with reference to FIG. 7, and it is not necessary to increase the chip area.

  Further, while the first embodiment supplies two types of voltages from the main body power supply circuit 50, in the present embodiment, only one type of voltage VBAT needs to be obtained from the main body power supply circuit 50. Easy connection.

  Since the booster circuit according to the present invention can provide a low-cost booster circuit having a small chip area and a small output resistance, it is useful to be mounted on a camera module having a large number of pixels.

It is a principal part block block diagram of the camera module mounting apparatus which concerns on the 1st Embodiment of this invention. It is a block block diagram of the camera module side power supply device shown in FIG. FIG. 3 is a circuit diagram of a booster circuit used in the camera module side power supply device according to the first embodiment of the present invention. It is a circuit diagram of the booster circuit used with the camera module side power supply device which concerns on the 2nd Embodiment of this invention. It is a principal block block diagram of the conventional camera module mounting apparatus. It is a block block diagram of the camera module type power supply device shown in FIG. It is a circuit diagram of a general double charge pump circuit. It is a circuit diagram of the conventional 1.5 times charge pump circuit. It is operation | movement explanatory drawing of the 1.5 times charge pump circuit shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 CCD image sensor 50 Main body side power supply circuit 51 Camera module side power supply device 52 Booster circuit 55 1st circuit part 56 2nd circuit part 57 Bypass capacitor

Claims (9)

  A DC voltage input terminal to which a first voltage is applied; and a clock input terminal to which a clock signal that swings between the second voltage and a ground potential is input. The first voltage and the second voltage A booster circuit that outputs a voltage on which a voltage is superimposed, wherein the first voltage is set lower than the second voltage.   In the camera module attached to the apparatus main body, the power supply circuit on the apparatus main body side generates a first voltage lower than the voltage of the apparatus power supply from the apparatus power supply, and the power supply circuit on the camera module side is lower than the apparatus power supply from the apparatus power supply. 2. The camera module using a booster circuit according to claim 1, wherein a second voltage higher than the first voltage is generated, and each of the second voltages is input to the booster circuit.   The camera module according to claim 2, wherein the first voltage is generated by a switching power supply circuit.   The camera module according to claim 2, wherein the second voltage is generated by a series regulator type power supply circuit.   Step-down means for generating and outputting a fourth voltage lower than the third voltage from the inputted third voltage, and a bypass capacitor provided between the output terminal of the step-down means and the ground potential; A DC voltage input terminal to which the fourth voltage is applied, and a clock input terminal to which a clock signal having an amplitude between the second voltage and the ground potential is input, and the fourth voltage and the first voltage A voltage booster circuit that outputs a voltage on which the voltage of 2 is superimposed.   By making the second voltage and the third voltage the same, and making the fourth voltage 0.5 times the second or the third voltage, the second or the third voltage The booster circuit according to claim 5, wherein an output voltage that is 1.5 times as large as the output voltage is obtained.   The step-up circuit according to claim 5 or 6, wherein the step-down means comprises a capacitor and a switch.   In the camera module attached to the apparatus main body, among the constituent circuits of the camera module side power supply apparatus that generates a plurality of power supply voltages required for driving the camera module, the constituent circuit that generates the power supply voltage that maximizes the power consumption A camera module using the booster circuit according to claim 1.   9. The camera module according to claim 8, wherein the image pickup device of the camera module is a CCD image sensor, and a power source maximizing power consumption is a power source for driving a horizontal transfer register of the CCD.

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