JP5993197B2 - Transmission system, transmission apparatus, and jitter compensation method - Google Patents

Description

  The present invention relates to a transmission system, a transmission apparatus, and a jitter compensation method including a transmission apparatus that transmits a high-speed data signal through a plurality of transmission lines and a reception apparatus that receives the high-speed data signal.

  Conventionally, a jitter tolerance test system for measuring jitter tolerance of a device to be tested such as a semiconductor circuit is known. In the conventional jitter tolerance test system, random jitter, periodic jitter, and data-dependent jitter can be accurately generated. In the probe card of this jitter tolerance test system, the input terminal of the coaxial cable and the probe terminal are connected by a microstrip line in order to reduce the transmission loss of the high-speed signal.

  By the way, in recent jitter tolerance test apparatuses, as the probe terminals are densified, the distance between the microstrip lines becomes narrow, and jitter due to crosstalk generated in the probe card becomes a problem. For example, crosstalk occurs between microstrip lines arranged in parallel like a data bus. Crosstalk received between adjacent microstrip lines affects the rise or fall timing of the transmission signal. This effect becomes crosstalk-induced jitter (CIJ).

  CIJ varies depending on the relationship of signals transmitted through a transmission line, for example. For example, in a transmission line with low impedance, the timing of the transmission signal is faster when the signal relationship is in the differential (Odd) mode, and the timing of the transmission signal is delayed in the in-phase (Even) mode.

  Conventionally, the influence of jitter caused by crosstalk has been canceled by inserting a delay element in the transmission line to increase the delay time in the odd mode and decrease the delay time in the even mode. For example, in Patent Document 1, the drive current of the transmission output buffer is changed according to the signal mode between the three transmission lines, and the jitter caused by the crosstalk between the transmission lines is canceled by the amount of change in the delay time of the output buffer. The technology to do is described.

JP 2011-10118 A

  However, the conventional technique does not consider the optimum value of the delay time when canceling CIJ. Further, in the above conventional technique, for example, when a large number of transmission lines are arranged in parallel, it is difficult to set the delay time to an optimum value because there is an influence of a transmission line adjacent to the adjacent transmission line. It is.

  Furthermore, in the above conventional technique, the input line of the mode detection unit for detecting the signal mode between the three transmission lines becomes complicated, and it is difficult to adjust the timing of mode detection. Further, the above-described conventional technique is compatible only with signal transmission by the single-end system, and does not show CIJ cancellation in the case of transmitting a signal by the differential system.

  The disclosed technique has been made in view of the above points, and aims to provide a transmission system, a transmission apparatus, and a jitter compensation method capable of reducing jitter due to crosstalk with a simple configuration. Yes.

The disclosed technology is a transmission system including a transmission device that transmits a high-speed data signal via a plurality of transmission lines and a reception device that receives the high-speed data signal, and the reception device includes the plurality of transmission lines. A mode detection unit for detecting whether the mode between the adjacent high-speed data signals is a differential mode or a common mode, and a differential phase comparison unit or a common phase depending on the detected mode One of the comparison units is enabled, and the transmission device detects the phase difference of the high-speed data signal output from the adjacent transmission line in the plurality of transmission lines below a predetermined value and transmits the detection signal to the transmission device anda phase comparator for outputting to the transmission device, for each of the high-speed data signals corresponding to said plurality of transmission lines, an output of the delay device provided in the receiving apparatus Possess the input side of the delay device which is provided to the input side, and a delay control unit that sets to the delay device to delay time of the delay device when receiving the detection signal from the receiving apparatus, the delay control The delay time set in the delay device on the output side of the first high-speed data signal corresponding to the first transmission line is calculated based on the second high-speed data signal adjacent to one of the first high-speed data signals. The delay time set in the delay device on the output side and set in the delay device on the input side of the first high-speed data signal is input to the third high-speed data signal adjacent to the other of the first high-speed data signal. Set to the side delay device.

  It can also be set as the method of making a computer perform the said each part as a procedure.

  According to the disclosed technique, jitter due to crosstalk can be reduced with a simple configuration.

It is a figure explaining a jitter tolerance test system. It is a figure explaining CIJ compensation. It is a 1st figure explaining CIJ which arises between microstrip transmission lines. It is a 2nd figure explaining CIJ which arises between microstrip transmission lines. It is a figure explaining the function structure of the signal generation unit with CIJ compensation. It is a figure explaining the circuit structure of the signal generation unit with CIJ compensation. It is a figure explaining the structure of LSI for CIJ compensation. It is a figure explaining the 1st setting procedure of delay time. It is a flowchart explaining the 1st setting process of delay time. It is a figure explaining the 2nd setting procedure of delay time. It is a flowchart explaining the 2nd setting process of delay time. It is a figure explaining the 3rd setting procedure of delay time. It is a flowchart explaining the 3rd setting procedure of delay time. It is a figure explaining a simulation model. It is a 1st figure explaining a simulation result. It is a 2nd figure explaining a simulation result. It is a 3rd figure explaining a simulation result.

  Embodiments will be described below with reference to the drawings. FIG. 1 is a diagram for explaining a jitter tolerance test system.

  The jitter tolerance test system 100 of this embodiment includes a jitter tolerance test apparatus 200, a probe card 300, and a probe card adapter 400.

  The jitter tolerance test apparatus 200 includes a signal generation unit 210 with crosstalk-induced jitter (CIJ) compensation, a control unit 220, and an analysis unit 230. The CIJ-compensated signal generation unit 210 outputs a test signal (pseudo random bit sequence signal; PRBS signal) for performing a jitter tolerance test to the probe card 300. The test signal of this embodiment is a signal that has undergone CIJ compensation by the signal generation unit 210 with CIJ compensation. Details of the CIJ compensated signal generation unit 210 will be described later. The control unit 220 controls the signal generating unit 210 with CIJ compensation. The analysis unit 230 analyzes the status signal as a result of the jitter tolerance test output from the probe card 300.

  The probe card 300 is connected to a signal generating unit with CIJ compensation 210 via a coaxial cable 310 and a microstrip transmission line (hereinafter simply referred to as a transmission line) 320 to 329, and the signal generating unit with CIJ compensation 210. The test signal from is input. The probe card 300 also has probe terminals 340 and 350 connected to the device under test.

  The probe terminal 340 transmits a test signal transmitted via the transmission lines 320 to 329 to the device under test. The test signal of this embodiment is a high-speed data signal. One end of the probe terminal 350 is connected to the coaxial cable 350, and transmits a status signal output from the device under test to the analysis unit 230. The status signal of this embodiment is a signal that is slower than the test signal.

  The probe card adapter 400 includes a CIJ compensation LSI (Large Scale Integration) 410. The CIJ compensation LSI 410 has a probe connection terminal 420 connected to the probe terminals 340 and 350.

  The probe card adapter 400 of this embodiment is connected to the probe card 300 when performing CIJ compensation. In the present embodiment, after the probe card 300 and the CIJ compensation LSI 410 of the probe card adapter 400 are connected and CIJ compensation is performed, the test target device is connected to the probe card 300 and a jitter tolerance test is performed.

  Thus, in this embodiment, since the jitter tolerance test of the device under test is performed after performing CIJ compensation, the jitter tolerance test can be performed with the CIJ of the signals output from the transmission lines 320 to 329 reduced. .

  In this embodiment, the jitter tolerance test system 100 is used, but the present invention is not limited to this. CIJ compensation described later can be applied to a transmission system that transmits high-speed data signals via a microstrip transmission line. In this case, the jitter tolerance test apparatus 200 corresponds to a transmission apparatus that transmits a high-speed data signal, and the CIJ compensation LSI 410 corresponds to a high-speed data signal reception apparatus.

  Next, CIJ compensation of this embodiment will be described.

  FIG. 2 is a diagram for explaining CIJ compensation.

  In the present embodiment, a CIJ compensation signal generation unit 210 and a CIJ compensation LSI 410 are connected via transmission lines 320 to 329.

  In this embodiment, the CIJ-compensated signal generation unit 210 has a delay device for performing CIJ compensation, and is generated on the transmission lines 320 to 329 of the probe card 300 while transmitting the test signal to the CIJ compensation LSI 410. An optimum delay time is adjusted to cancel CIJ. The adjusted optimum delay time is set in the delay device of the CIJ compensated signal generation unit 210.

  Specifically, the CIJ compensation LSI 410 converts the phase difference between adjacent channels into a control voltage (delay control signal) and feeds it back to the signal generation unit 210 with CIJ compensation. In this embodiment, a DLL (Delay Locked Loop) is formed by this feedback. The CIJ compensated signal generation unit 210 receives the delay control signal and controls the delay time of the delay device.

  The CIJ compensation LSI 410 of this embodiment outputs a lock signal to the CIJ compensated signal generation unit 210 when the phase difference between adjacent channels in the DLL formed here becomes a predetermined value or less. That is, when the lock signal is output, the delay device is set with a delay time in which the phase difference between adjacent channels is equal to or less than a predetermined value. In this embodiment, when the lock signal is output for all channels, the delay time adjustment of the delay device is completed, and the delay time for CIJ compensation is set in the delay device.

  The transmission lines 320 to 329 of the present embodiment have the same wiring length so that the propagation times are the same in all transmission lines, and the meander wiring that aligns the wiring lengths is coaxially connected to the coaxial cable 310 with the minimum length. Arranged near the connector. Further, in the transmission lines 320 to 329 of this embodiment, the intervals between the wirings are made equal.

  Next, CIJ generated between transmission lines will be described. FIG. 3 is a first diagram illustrating CIJ that occurs between microstrip transmission lines. FIG. 3 shows a case where there are two transmission lines. FIG. 3A is a schematic diagram of a transmission line, and FIG. 3B shows a change in CIJ that occurs.

  In FIG. 3A, a signal is transmitted from the signal source 1 through the transmission line 1, and a signal is transmitted from the signal source 2 through the transmission line 2. Here, CIJ varies depending on the polarity of signals output from the signal sources 1 and 2.

  For example, when the polarity of the signal output from the signal source 1 and the polarity of the signal output from the signal source 2 are the same, the mode between the transmission line 1 and the transmission line 2 is an Even mode that handles signals having the same phase. Become. Further, when the polarity of the signal output from the signal source 1 and the polarity of the signal output from the signal source 2 are different, the mode between the transmission line 1 and the transmission line 2 is Odd (differential) that handles signals whose phases are different by 180 degrees. ) Mode.

  When the mode between the transmission lines 1 and 2 is the Even mode, CIJ generated at the far end of the transmission line 1 and CIJ generated at the far end of the transmission line 2 are both + te. When the mode between the transmission lines 1 and 2 is the odd mode, the CIJ generated at the far end of the transmission line 1 and the CIJ generated at the far end of the transmission line 2 are both -to. Note that + te and -to are time deviations in each mode with respect to the propagation time when the signal is propagated without crosstalk, and te = to.

  That is, in the example of FIG. 3, when the mode between the two transmission lines is the Even mode, the signal is transmitted at a timing that is te later (+ te) than the propagation time when no crosstalk is received. Therefore, in order to cancel this time deviation, the delay time may be set so that this propagation time is advanced by te (-te). When the mode between the two transmission lines is the odd mode, the signal is transmitted at a timing that is earlier (-to) than the propagation time when no crosstalk is received. Therefore, in order to cancel this time deviation, the delay time may be set so as to delay the propagation time to (+ to).

  FIG. 4 is a second diagram for explaining CIJ occurring between the microstrip transmission lines. FIG. 4 shows a case where there are three transmission lines. FIG. 4A is a schematic diagram of a transmission line, and FIG. 4B shows a change in CIJ that occurs.

  In FIG. 4A, a signal is transmitted from the signal source 1 through the transmission line 1, a signal is transmitted from the signal source 2 through the transmission line 2, and a signal is transmitted from the signal source 3 through the transmission line 3.

  In the example of FIG. 4, the transmission line 2 is affected by both of the adjacent transmission lines 1 and 3. Therefore, the change of CIJ is different from the case of two transmission lines.

  In FIG. 4, when the polarity of the signal output from the signal source 1 and the polarity of the signal output from the signal source 2 are the same, the mode between the transmission line 1 and the transmission line 2 is the Even mode. When the polarity of the signal output from the signal source 2 and the polarity of the signal output from the signal source 3 are the same, the mode between the transmission line 2 and the transmission line 3 is the Even mode. In the present embodiment, this case is referred to as an even-even mode.

  In the case of the Even-Even mode, the CIJ of the transmission line 1 and the transmission line 3 is + te. The CIJ of the transmission line 2 is approximately + 2te because of the influence from the transmission lines 1 and 3.

  In this embodiment, when the mode between the transmission line 1 and the transmission line 2 is the Even mode, and the mode between the transmission line 2 and the transmission line 3 is the Odd mode, it is called an Even-Odd mode. In the case of the Even-Odd mode, the CIJ of the transmission line 2 is + te, and the influence received from the transmission line 3 is −to because the influence received from the transmission line 1 is −to. Similarly, when the mode between the transmission line 1 and the transmission line 2 is the odd mode and the mode between the transmission line 2 and the transmission line 3 is the even mode, the CIJ of the transmission line 2 is 0. .

  When the transmission line 1 and the transmission line 2 are in the odd mode, and the transmission line 2 and the transmission line 3 are also in the odd mode, the CIJ of the transmission line 2 is -2to.

  According to the example of FIG. 4B, when the transmission line is arranged on both sides like the transmission line 2, the transmission line 2 is affected by the crosstalk between the transmission lines on both sides, so the time deviation becomes large. I understand that.

  In this embodiment, paying attention to the change in CIJ corresponding to the mode between the transmission lines, CIJ is reduced by setting an optimal delay time to cancel this CIJ.

  Next, the configuration of the CIJ compensated signal generation unit 210 will be described. FIG. 5 is a diagram for explaining the functional configuration of the CIJ-compensated signal generation unit.

  The CIJ-compensated signal generation unit 210 according to this embodiment includes a clock generation unit 211, a compensation unit 212, and a DDJ (Data Dependent Jitter) filter 213. The clock generation unit 211 of this embodiment includes a Gaussian Noise Generator (hereinafter, random jitter generation unit) 221, a coupler 222, a Signal / Function Generator (hereinafter, periodic jitter generation unit) 223, and a pulse generation unit 224. The random jitter generator 221 generates random jitter. The random jitter is output to the coupler 222. The periodic jitter generator 223 generates periodic jitter. The periodic jitter is input to the pulse generator 224. The pulse generator 224 outputs a pulse signal on which periodic jitter is superimposed. The pulse signal output from the pulse generator 224 is superimposed with random jitter in the coupler 222 and output to the compensator 212.

  The DDJ filter 213 generates data-dependent jitter in the signal output from the compensation unit 212.

  The circuit configuration of the CIJ compensated signal generation unit 210 of this embodiment will be described below with reference to FIG. FIG. 6 is a diagram for explaining the circuit configuration of the CIJ-compensated signal generation unit.

  The CIJ-compensated signal generating unit 210 according to the present embodiment adds in advance a time deviation corresponding to the reverse sign of CIJ shown in FIG. 4 to the test signal before being input to the probe card 300. In this embodiment, this configuration cancels CIJ of signals output from the transmission lines 320 to 329 of the probe card 300. In the present embodiment, CIJ is canceled in units of three for the ten transmission lines 320 to 329. That is, in the present embodiment, the influence of the adjacent lines is canceled in each of the transmission lines 320 to 329.

  The CIJ-compensated signal generation unit 210 of this embodiment includes input buffer amplifiers CB11, CB12, CB21, CB22, CB31, CB32, CB41, CB42, CB51, and CB52 to which the reference clock output from the clock generation unit 211 is input. Have. In the CIJ-compensated signal generation unit 210 of this embodiment, delay devices 241, 251, 242, and 252 for delaying a reference clock input from the input buffer amplifier are provided corresponding to each input buffer amplifier. The delay devices 241 and 251 are output side delay devices provided on the output side, and the delay devices 242 and 252 are input side delay devices provided on the input side. The delay devices 241 and 242 are set with a delay time when the Even signal of the mode detection unit described later becomes valid. The delay devices 251 and 252 enable the Odd signal of the mode detection unit described later. The delay time is set when

  In the delay devices 241, 251, 242, and 252 of this embodiment, a CIJ compensation delay time for compensating CIJ generated in the probe card 300 in advance is set. The delay time is varied by the control voltage or changed by a switch or the like. The control voltage is given by a delay control signal output from the CIJ compensation LSI 410. The delay devices 241, 251, 242, and 252 of the present embodiment are, for example, a method in which logic devices such as inverters are connected in a daisy chain and an output tap is switched according to a control voltage, or a delay device that changes a drive current. Realized.

  The delay devices 241, 251, 242, and 252 of the present embodiment can be varied up to + to_max and −te_max indicating the maximum value of CIJ compensation with the delay time Td as a reference value (center value) by setting the control voltage. Can do.

  In this embodiment, when the time deviation by CIJ when any two adjacent channels of the signals output from transmission lines 320 to 329 are in the Even mode is + te, CIJ compensation corresponding to this time deviation is performed. The delay time tcomp for use is -tce. Similarly, when the time deviation by CIJ when any two adjacent two channels of signals output from transmission lines 320 to 329 are in the odd mode is −to, CIJ compensation corresponding to this time deviation The delay time tcomp for use is + tco.

  The CIJ-compensated signal generation unit 210 according to the present embodiment includes pattern generation units PG11, PG12, PG21, PG22, PG31, PG32, PG41, PG42, PG51, and PG52. Each pattern generation unit generates a random data pattern signal in synchronization with the reference clock generated by the clock generation unit 211.

  The CIJ-compensated signal generation unit 210 according to the present embodiment includes mode detection units MD12, MD21, MD22, MD31, MD32, MD41, MD42, MD51, and MD52. Each mode detection unit detects a mode of a data pattern signal between two adjacent channels.

  Further, the CIJ-compensated signal generation unit 210 of this embodiment includes delay control units 243, 253, 244, and 254. The delay control units 243 and 253 set the delay times of the delay devices 241 and 251 provided on the output side. The delay control units 244 and 254 set the delay time of the delay devices 242 and 252 provided on the input side. In other words, the delay control units 243 and 244 of this embodiment control the delay times of the delay devices 241 and 242 when the Even signal of the mode detection unit becomes valid. The delay control units 253 and 254 according to the present embodiment control the delay times of the delay devices 251 and 252 when the odd signal of the mode detection unit becomes valid.

  Further, the CIJ-compensated signal generation unit 210 of this embodiment has a flip-flop 271. The flip-flop 271 latches the data pattern signal generated by each pattern generation unit, and is provided corresponding to each input buffer amplifier.

  Each mode detection unit MD of this embodiment detects a mode by comparing signal polarities between two adjacent channels, and sends a mode signal (Even signal, Odd signal) indicating the detected mode to the delay control units 243, 253 or The data is output to the delay control units 244 and 254.

  A case where signals between two adjacent channels are, for example, a data pattern signal generated by the pattern generation unit PG11 and a data pattern signal generated by the pattern generation unit PG12 will be described.

  In this case, the mode detection unit MD12 performs mode detection. If the detected mode is the Even mode (Even signal active), the delay control unit 243 controls the delay device 241 so that the delay time for CIJ compensation is Td-tce. If the detected mode is the Odd mode (Odd signal active), the delay control unit 253 controls the delay device 251 so that the delay time for CIJ compensation is Td + tco. Further, if the detected mode is neither the Even mode nor the Odd mode (Even signal and Odd signal are not active), the delay control units 243 and 253 set the CIJ compensation delay time to the reference value Td. The delay devices 241 and 251 are controlled. The delay control units 243 and 253 simultaneously control the delay devices of two adjacent transmission lines in the same mode. That is, the delay control units 243 and 253 simultaneously set a delay time for CIJ compensation for the delay devices 241 and 251 corresponding to the input buffer amplifier CB12.

  A case will be described in which signals between two adjacent channels are, for example, a data pattern signal generated by the pattern generation unit PG12 and a data pattern signal generated by the pattern generation unit PG21.

  In this case, the mode detection unit MD21 performs mode detection. If the detected mode is the Even mode, the delay control unit 244 controls the delay device 242 so that the delay time for CIJ compensation is Td-tce. If the detected mode is the Odd mode (Odd signal active), the delay control unit 254 controls the delay device 252 so that the delay time for CIJ compensation is Td + tco. Further, if the detected mode is neither the Even mode nor the Odd mode (Even signal and Odd signal are not active), the delay control units 244 and 254 set the delay time for CIJ compensation to the reference value Td. The delay devices 242 and 252 are controlled. Note that the delay control units 244 and 254 simultaneously control delay devices of two adjacent transmission lines in the same mode. That is, the delay control units 244 and 254 simultaneously set the CIJ compensation delay time for the delay devices 242 and 252 corresponding to the input buffer amplifier CB21.

  The reference clock generated by the clock generation unit 211 is output to the flip-flop 271 with a delay time for CIJ compensation via the delay devices 241, 251, 242, and 252. The output of the flip-flop 271 is sent to the transmission line 320 of the probe card 300 via the output buffer amplifier TXO11. The output buffer amplifier TXO11 corresponds to the input buffer amplifier CB11, and an output buffer amplifier corresponding to another input buffer amplifier is provided.

  As described above, the CIJ-compensated signal generation unit 210 of this embodiment includes the delay devices 242 and 252 provided on the input side and the delay devices 241 and 251 provided on the output side for each channel. The CIJ-compensated signal generation unit 210 also includes delay control units 244 and 254 that control delay devices 242 and 252 provided on the input side, and a delay control unit 243 that controls delay devices 241 and 251 provided on the output side. H.253. The delay control units 244 and 254 set delay times for the adjacent two-channel delay devices 242 and 252 and control the delay times at the same timing. The delay control units 243 and 253 set delay times for the delay devices 241 and 251 of two adjacent channels, and control the delay times at the same timing.

  That is, in the present embodiment, even when the number of channels is increased, the configuration of each channel is made the same, and a delay control unit that controls two adjacent channels and a mode detection unit corresponding to the delay control unit are provided. it can. Therefore, in this embodiment, the delay time for CIJ compensation can be set with a simple configuration, and it is possible to easily cope with the addition of channels.

  Next, the CIJ compensation LSI 410 of this embodiment will be described with reference to FIG. FIG. 7 is a diagram illustrating the configuration of the CIJ compensation LSI.

  The CIJ generated in the wiring of the CIJ compensation LSI 410 is very small compared to the CIJ generated in the probe card 300 and can be ignored.

  In the CIJ compensation LSI 410, the test signal received from the probe terminal 340 of the probe card 300 is input to the input buffer amplifier. The CIJ compensation LSI 410 according to this embodiment includes ten input buffer amplifiers RXI11, RXI12, RXI21, RXI22, RXI31, RXI32, RXI41, RXI42, RXI51, and RXI52 corresponding to the ten transmission lines 320 to 329.

  The output of the input buffer amplifier RXI11 is input to a data regenerator (Data Regen.) 412 and a CDR (Clock Data Recovery) 413, and the data regenerator 412 uses the clock regenerated by the CDR 413 to receive data from the received test signal. Play. The reproduced data that has been reproduced is input to the mode detector 431 together with the reproduced data of the adjacent channels, and the signal mode between the adjacent channels is detected.

  The output of the input buffer amplifier RXI11 is input to phase comparators 432 and 433. The output from the input buffer amplifier RXI12 is also input to the phase comparators 432 and 433. The phase comparators 432 and 433 compare the phase of the edge of the test signal between two adjacent channels. The phase difference signals resulting from the comparison by the phase comparators 432 and 433 pass through the filters (LPF) 434 and 435, and are supplied to the delay control units 436 and 437. In this embodiment, the phase comparator 432 is an Odd mode phase comparator, and the phase comparator 433 is an Even mode phase comparator. In this embodiment, the Even mode phase comparator and the Odd mode phase comparator are independent of each other. When the mode detection unit 431 detects the Even mode, the Even mode phase comparator 433 is enabled, Compare the phase of the edge of the test signal in Even mode. Similarly, in the Odd mode, the Odd mode phase comparator 432 is enabled to compare the phase of the edge of the test signal in the Odd mode. The Odd mode phase comparator 432 compares the phases of two input signals with a phase difference of 180 degrees as a reference.

  Outputs of the filters 434 and 435 are converted into delay control signals corresponding to control voltages by delay control units 436 and 437. This delay control signal is sent to the delay control units 243 and 253 of the CIJ compensated signal generation unit 210. That is, in this embodiment, low-speed data communication is performed between the delay control units 436 and 437 and the delay control units 243 and 253.

  The lock detectors 438 and 439 output a lock signal LockE_1112 and a lock signal LockO_1112, respectively, when the phase difference compared by the phase comparators 432 and 433 is equal to or less than a specified value. The lock signal LockE_1112 and the lock signal LockO_1112 are sent to the control unit 220 of the signal generation unit 210 with CIJ compensation.

  In FIG. 7, the channel corresponding to each input buffer amplifier other than the input buffer amplifier RXI11 has the same configuration.

  Next, setting of the delay time for CIJ compensation in this embodiment will be described. In this embodiment, the control unit 220 performs control to set the delay time for each channel of the CIJ compensation-added signal generation unit 210 based on the signal received from the CIJ compensation LSI 410.

  In this embodiment, the delay time is set in three steps. First, the first procedure will be described with reference to FIG. FIG. 8 is a diagram for explaining a first setting procedure of the delay time.

  In this embodiment, the output side delay devices 241 and 251 for delaying the signal output from the output buffer amplifier TXO11 are fixed to the reference value Td, and the data pattern signals output from the pattern generation units PG11 and PG12 are differentially transmitted. The delay time of the delay devices 242 and 252 on the input side is set as follows.

  Here, the signal output from the output buffer amplifier TXO11 is a signal in which the adjacent transmission line is only on one side. That is, in this embodiment, the delay of all the delay devices 242 and 252 on the input side is based on the delay time set in the delay devices 242 and 252 on the input side provided in the transmission line adjacent to the transmission line on only one side. Set the time.

  In this embodiment, when signals corresponding to the transmission lines 320 to 329 are detected in the mode of three signals, mode detection between two adjacent signals is performed. In this embodiment, the delay time of the delay device is set using differential transmission in which the mode of two adjacent signals is always the odd mode.

  FIG. 9 is a flowchart for explaining the first delay time setting process. The control unit 220 of the present embodiment performs initial setting (step S901). Specifically, the control unit 220 sets the delay time of all the delay devices of the CIJ compensated signal generation unit 210 to the reference value Td by the delay control signal. All delay devices are delay devices 241, 251, 242, and 252 provided corresponding to the respective input buffer amplifiers. Further, the control unit 220 enables the mode detection by enabling the mode detection units MD21, MD31, MD41, and MD51 used for setting the delay time of the delay devices 242 and 252 on the input side according to the mode control signal. In addition, the control unit 220 invalidates the mode detection units MD12, MD22, MD32, MD42, and MD52 used for setting the delay time of the delay devices 241 and 251 on the output side. In this embodiment, the delay time when mode detection is not performed is the reference value Td.

  In addition, the control unit 220 controls the generation of the data pattern signal by the pattern generation unit according to the pattern control signal. In the present embodiment, the control unit 220 generates the data pattern signal so that the data pattern signal output from the pattern generation units PG11 and PG12 and the data pattern signal output from the pattern generation units PG21 and PG22 are always in the odd mode. Let The control unit 220 always outputs the data pattern signal output from the pattern generation units PG31 and PG32, the data pattern signal output from the pattern generation units PG41 and PG42, and the data pattern signal output from the pattern generation units PG51 and PG52. A data pattern signal is generated so as to be in the mode.

  That is, the control unit 220 always sets the data pattern signal used for controlling the delay time of the output side delay devices 241 and 251 to the odd mode. In this embodiment, the delay times of the output-side delay devices 241 and 251 are fixed to the reference value Td while the delay-time setting processing of the input-side delay devices 242 and 252 is performed.

  Subsequently, the control unit 220 causes a pattern data signal to be randomly output from each pattern generation unit in response to the pattern control signal (step S902). In step S902, a data pattern signal used for controlling the delay time of the delay devices 242 and 252 on the input side is randomly output.

  Subsequently, the control unit 220 enables only the mode detection unit MD21 by the mode control signal (step S903). Subsequently, the control unit 220 validates only the Even signal of the mode detection unit MD21 (step S904).

  In step S904, the signal output from the output buffer amplifier TXO11 and the signal output from the output buffer amplifier TXO12 are output to the CIJ compensation LSI 410 via the transmission line 320 and the transmission line 321. When the output signal of the transmission line 320 is the signal TLO11 and the output signal of the transmission line 321 is the signal TLO12 (see FIG. 2), the CIJ compensation LSI 410 compares the phase difference between the signal TLO11 and the signal TLO12. Then, the CIJ compensation LSI 410 outputs a lock signal LockE_1112 to the control unit 220 when the phase difference between the signal TLO11 and the signal TLO12 becomes a predetermined value or less. The predetermined value is the minimum value that can be taken by the phase difference between the signal TLO11 and the signal TLO12, and is a preset value.

  The control unit 220 determines whether or not the lock signal LockE_1112 has been detected (step S905). If not detected in step S905, the process proceeds to step S918 described later.

  When detected in step S905, the delay time set in the delay device 242 corresponding to the input buffer amplifier CB12 is a delay time in which the phase difference between the signal TLO11 and the signal TLO12 is a minimum value. The control unit 220 temporarily stores delay control data corresponding to the delay time set here in the delay device 242 in a buffer memory or the like in the delay control unit 244 corresponding to the mode detection unit MD21 by the delay control signal ( Step S906).

  Here, the control unit 220 returns the delay time of the delay device 242 corresponding to the input buffer amplifier CB12 to the reference value Td by the delay control signal (step S907). At this time, the control unit 220 also returns the delay time of the delay device 242 that delays the signal corresponding to the input buffer amplifier CB21 to the reference value Td. Subsequently, the control unit 220 validates only the odd signal of the mode detection unit MD21 (step S908).

  In step S 908, the signal output from the output buffer amplifier TXO 11 and the signal output from the output buffer amplifier TXO 12 are output to the CIJ compensation LSI 410 via the transmission line 320 and the transmission line 321. The CIJ compensation LSI 410 compares the phase difference between the signal TLO11 and the signal TLO12. Then, the CIJ compensation LSI 410 outputs a lock signal LockO_1112 to the control unit 220 when the phase difference between the signal TLO11 and the signal TLO12 becomes a predetermined value or less.

  The control unit 220 determines whether or not the lock signal LockO_1112 has been detected (step S909). If not detected in step S909, the process proceeds to step S918 described later. When detected in step S909, the delay time set in the delay device 252 corresponding to the input buffer amplifier CB12 is a delay time in which the phase difference between the signal TLO11 and the signal TLO12 is the minimum value. Based on the delay control signal, the control unit 220 stores delay control data corresponding to the delay time set in the delay device 252 in the delay time setting register in the delay control unit 254 corresponding to the mode detection unit MD21 ( Step S910). In this embodiment, in step S910, the delay time of the delay device 252 is set.

  Subsequently, in response to the delay control signal, the control unit 220 stores the delay control data temporarily stored in the buffer memory or the like in the delay control unit 244 in step S906 in the delay time setting register in the delay control unit 244 (step S911). ). In this embodiment, the delay time of the delay device 242 is set in step S911.

  Subsequently, the control unit 220 determines whether or not the lock signal LockE_1112 and the lock signal LockO_1112 are detected from the CIJ compensation LSI 410 (step S912). If not detected in step S912, the process proceeds to step S918 described later.

  When detected in step S912, the phase difference between the signal TLO11 and the signal TLO12 is minimized. That is, this state is a state in which the CIJ generated between the transmission line 320 and the transmission line 321 is reduced to almost the minimum. In this embodiment, the delay devices 242 and 252 corresponding to the input buffer amplifier CB21 are set to the delay times similar to those of the delay devices 242 and 252 corresponding to the input buffer amplifier CB12. Therefore, the signal TLO11 and the signal TLO21 are set. The phase difference between and is minimized.

  If detected in step S912, the control unit 220 enables the mode detection unit MD31 and performs phase comparison between the signal TLO21 output from the transmission line 322 and the signal TLO22 output from the transmission line 323. (Step S913). Specifically, the control unit 220 performs processing similar to the processing in steps S904 to S912, and sets the delay times of the delay devices 242 and 252 corresponding to the input buffer amplifier CB22 and the input buffer amplifier CB31. This delay time is a delay time for canceling CIJ occurring in the transmission line 323 and the transmission line 324.

  Subsequently, the control unit 220 performs a phase comparison between the signal TLO31 output from the transmission line 324 and the signal TLO32 output from the transmission line 325. (Step S914). Specifically, the control unit 220 performs processing similar to the processing in steps S904 to S912, and sets the delay times of the delay devices 242 and 252 corresponding to the input buffer amplifier CB32 and the input buffer amplifier CB41. This delay time is a delay time for canceling CIJ occurring in the transmission line 325 and the transmission line 326.

  Subsequently, the control unit 220 performs a phase comparison between the signal TLO41 output from the transmission line 326 and the signal TLO42 output from the transmission line 327. (Step S915). Specifically, the control unit 220 performs processing similar to the processing in steps S904 to S912, and sets the delay times of the delay devices 242 and 252 corresponding to the input buffer amplifier CB42 and the input buffer amplifier CB51. This delay time is a delay time for canceling CIJ occurring in the transmission line 327 and the transmission line 328.

  Subsequently, the control unit 220 determines whether or not the lock signal LockE_5152 and the lock signal LockO_5152 are detected (step S916).

  If not detected in step S916, the process proceeds to step S918 described later. When detected in step S916, it indicates that the phase difference between the signal TLO51 output from the transmission line 328 and the signal TLO52 output from the transmission line 329 is equal to or less than a predetermined value. That is, the CIJ generated between adjacent transmission lines in the transmission lines 320 to 329 is reduced.

  If detected in step S916, the control unit 220 determines whether all lock signals have been detected (step S917). Note that all lock signals indicate all lock signals of the lock signals LockO_1112, LockE_1112 to Lock signals LockO_5152, LockE_5152 in FIG.

  If all lock signals are not detected in step S917, the control unit 220 changes the sensitivity setting in all lock detection units of the CIJ compensation LSI 410 by the lock control signal (step S918). Specifically, the control unit 220 changes a predetermined value of the phase difference that is a threshold value for detecting lock.

  When all lock signals are detected in step S917, the control unit 220 ends the first delay time setting process.

  In the example of FIG. 9, the transmission line 320 that transmits the signal corresponding to the input buffer amplifier CB11 is first used as the transmission line adjacent to the transmission line only on one side, but the transmission corresponding to the input buffer amplifier CB52 is transmitted. The track 329 may be used. When the CIJ accompanying differential transmission is compensated, only the first setting procedure shown in FIG. 8 is necessary. To compensate for CIJ accompanying single-ended transmission, the following second setting procedure and third procedure are used. The setting procedure is necessary.

  Next, a second procedure for setting the delay time according to this embodiment will be described. FIG. 10 is a diagram for explaining a second procedure for setting the delay time.

  In the first delay time setting procedure, the delay times of the input delay devices 242 and 252 are set with the delay time of the output delay devices 241 and 251 of the CIJ compensated signal generation unit 210 as the reference value Td.

  In the second delay time setting procedure of the present embodiment, the difference is made with reference to the delay devices 242 and 252 on the input side other than the delay devices 242 and 252 corresponding to the input buffer amplifiers CB11 and CB52 (hereinafter referred to as outer channels). The delay devices 241 and 251 on the output side are set by dynamic transmission.

  In the second delay time setting procedure, with reference to the delay time of the delay device on the input side of each channel (the delay time set in FIG. 9), the delay on the output side as shown in FIG. Set device delay time. In the state after the second setting procedure is executed, the delay time of the delay device corresponding to the outer channel is the reference value Td.

  FIG. 11 is a flowchart for explaining the second delay time setting process. The control unit 220 of the present embodiment performs initial setting of the delay time second setting process (step S1101). Specifically, the control unit 220 enables all the mode detection units by the mode control signal. Further, the control unit 220 always sets the mode of the pattern data signal output from the pattern generation units PG12 and PG21 and the mode of the pattern data signal output from the pattern generation units PG22 and PG31 to the Odd mode according to the pattern control signal. . Similarly, the control unit 220 always sets the mode of the pattern data signal output from the pattern generation units PG32 and PG41 and the mode of the pattern data signal output from the pattern generation units PG42 and PG51 to the Odd mode. That is, the control unit 220 always sets the data pattern signal used for controlling the delay time of the delay devices 242 and 252 on the input side to the odd mode.

  Subsequently, the control unit 220 randomly outputs pattern data signals from all the pattern generation units in response to the pattern control signal (step S1102). Subsequently, the control unit 220 outputs a delay control signal to the delay control units 244 and 245, and causes the delay control unit 244 to set the delay time of the delay device (step S1103).

  Specifically, the control unit 220 uses the delay control units 244 and 254 to set the delay times of the delay devices 242 and 252 on the input side corresponding to the input buffer amplifiers CB12, CB22, CB32, and CB42 to the delay times adjusted in FIG. Set to. The delay time adjusted in FIG. 9 is stored in the delay time setting registers in the delay control units 244 and 254. The control unit 220 sets the delay times of the output-side delay devices 241 and 251 corresponding to the input buffer amplifiers CB21, CB31, CB41, and CB51 with reference to the input-side delay devices 242 and 252 described above.

  Further, the control unit 220 corresponds to the delay times of the delay devices 242 and 252 on the input side corresponding to the input buffer amplifiers CB21, CB31, CB41, and CB51 and the input buffer amplifiers CB12, CB22, CB32, and CB42. The delay time of the delay devices 241 and 251 on the output side is set as the reference Td.

  Subsequently, the control unit 220 validates only the Even signal for all the mode detection units by the mode control signal (step S1104). In step S1104, the control unit 220 performs control by DLL control so that the phase difference between the signal TLO12 and the signal TLO21 and the phase difference between the signal TLO22 and the signal TLO31 are minimized. In step S1104, the control unit 220 performs control by DLL control so that the phase difference between the signal TLO32 and the signal TLO41 and the phase difference between the signal TLO42 and the signal TLO51 are minimized.

  Subsequently, the control unit 220 determines whether or not the lock signal LockE_1221, the lock signal LockE_2231, the lock signal LockE_3241, and the lock signal LockE_4251 have been detected (step S1105). If not detected in step S1105, the process proceeds to step S1117 described later.

  When detected in step S1105, the phase difference between the signal TLO12 and the signal TLO21, the phase difference between the signal TLO22 and the signal TLO31, the phase difference between the signal TLO32 and the signal TLO41, and the phase difference between the signal TLO42 and the signal TLO51 are minimized. The delay time is set for each delay device.

  Therefore, the control unit 220 temporarily stores delay control data corresponding to the delay time set in the delay device 241 corresponding to the output buffer amplifier TX21 that outputs the signal TLO21 in a buffer memory or the like in the corresponding delay control unit 243. Similarly, the delay device 241 corresponding to the output buffer amplifier TX31, the delay device 241 corresponding to the output buffer amplifier TX41, and the delay control data corresponding to the delay time set in the delay device 241 corresponding to the output buffer amplifier TX51 are also temporarily stored. (Step S1106).

  Subsequently, the control unit 220 returns the delay time of the delay devices other than the delay device 241 corresponding to the input buffer amplifier CB11 and the input buffer amplifier CB52 to the reference value Td by the delay control signal (step S1107).

  Subsequently, the control unit 220 validates only the Odd signal for all the mode detection units by the mode control signal (step S1108). Since the process of step S1108 is the same as the process of step S1104, description thereof is omitted.

  Subsequently, the control unit 220 determines whether or not the lock signal LockO_1221, the lock signal LockO_2231, the lock signal LockO_3241, and the lock signal LockO_4251 have been detected (step S1109). If not detected in step S1109, the process proceeds to step S1117 described later. If detected in step S1109, the phase difference between the signal TLO12 and the signal TLO21, the phase difference between the signal TLO22 and the signal TLO31, the phase difference between the signal TLO32 and the signal TLO41, and the delay that minimizes the phase difference between the signal TLO42 and the signal TLO51. Time is set for the delay device. In this embodiment, the delay time that minimizes the phase difference between the signals of two adjacent channels is called the optimum value of the delay time.

  Therefore, the control unit 220 sets the delay time in the delay control unit 253 corresponding to the delay control data corresponding to the delay time set in the delay device 251 corresponding to the output buffer amplifier TXO 21 that outputs the signal TLO 21 by the delay control signal. Save to register. Similarly, the control unit 220 performs delay control corresponding to the delay time to the delay device 251 corresponding to the output buffer amplifier TXO31, the delay device 251 corresponding to the output buffer amplifier TXO41, and the delay device 251 corresponding to the output buffer amplifier TXO51. The data is stored in the delay time setting register in the corresponding delay control unit 253 (step S1110).

  Subsequently, the control unit 220 uses the delay control signal, and the control unit 220 uses the delay control signal to transfer the delay control data temporarily stored in the delay control unit 243 in step S1106 to the delay time setting register in the delay control unit 243. save. Similarly, the control unit 220 includes a delay device 241 corresponding to the output buffer amplifier TXO31, a delay device 241 corresponding to the output buffer amplifier TXO41, and a delay control unit 243 corresponding to the delay device 241 corresponding to the output buffer amplifier TXO51. The delay control data is stored in the delay time setting register (step S1111).

  In this embodiment, the delay time of the delay device on the output side excluding the outer delay device is set in steps S1110 and S1111.

  Subsequently, the control unit 220 validates both the Even signal and the Odd signal in all the mode detection units by the mode control signal (step S1112). Subsequently, the control unit 220 determines whether the lock signal LockE_1221, the lock signal LockE_2231, the lock signal LockE_3241, the lock signal LockE_4251, the lock signal LockO_1221, the lock signal LockO_2231, the lock signal LockO_3241, and the lock signal LockO_4251 are detected (step S1113). ). If not detected in step S1113, the process proceeds to step S1117 described later.

  If detected in step S1113, the control unit 220 sets a delay time for each delay device using a delay control signal (step S1114). Specifically, the delay control units 244 and 254 set the delay times of the delay devices 242 and 252 on the input side corresponding to the input buffer amplifiers CB21, CB31, CB41, and CB51 to the delay times set in the setting process of FIG. To do. The delay time adjusted in FIG. 9 is stored in the delay time setting registers in the delay control units 244 and 254. The control unit 220 sets the delay times of the output-side delay devices 241 and 251 corresponding to the input buffer amplifiers CB12, CB22, CB32, and CB42 with the input-side delay devices 242 and 252 as a reference.

  Furthermore, the control unit 220 includes delay times of input delay devices 242 and 252 corresponding to the input buffer amplifiers CB12, CB22, CB32, and CB42, and output delay devices corresponding to the input buffer amplifiers CB21, CB31, CB41, and CB51. The delay times 241 and 251 are set as the reference Td.

  Subsequently, the control unit 220 performs processing similar to the processing in steps S1104 to S1113, and sets the delay times of the output-side delay devices 241 and 251 corresponding to the input buffer amplifiers CB12, CB22, CB32, and CB42 (step S1104). S1115).

  Subsequently, the control unit 220 determines whether a lock signal other than the lock signal LockE_1112, the lock signal LockO_1112, the lock signal LockE_5152, and the lock signal LockO_5152 has been detected (step S1116). If not detected in step S1116, the control unit 220 changes the sensitivity setting in all lock detection units of the CIJ compensation LSI 410 by the lock control signal (step S1117).

  If detected in step S1116, the control unit 220 ends the second delay time setting process.

  In the present embodiment, the second setting process sets the delay time of the output-side delay device in which the delay time is fixed to the reference value Td in the first setting process. In the second setting process, the delay time set for the input-side delay device in the first setting process is used to set the delay time for the output-side delay device. In the present embodiment, CIJ can be reduced even in single-ended transmission by the second setting process and the next third setting process. Note that the second setting process and the third setting process in the present embodiment correspond to single-ended transmission and are processes aimed at optimizing delay time in single-ended transmission.

  Next, a third procedure for setting the delay time according to the present embodiment will be described. FIG. 12 is a diagram for explaining a third setting procedure of the delay time.

  The third setting procedure of the delay time in this embodiment is a procedure for setting the delay time for canceling CIJ of the outer transmission line adjacent to the transmission line on only one side. Specifically, the delay times of the delay devices 241 and 251 corresponding to the input buffer amplifiers CB11 and CB52 are set based on the delay time of the adjacent signal. In the third setting procedure, the delay time is set by single-ended transmission.

  FIG. 13 is a flowchart illustrating a third delay time setting process. The control unit 220 of this embodiment performs initial setting (step S1301). Specifically, the control unit 220 validates the Even signal and Odd signal of all the mode detection units by the mode control signal. In addition, the control unit 220 performs setting so that different random pattern data signals are output from all the pattern generation units according to the pattern control signal.

  Subsequently, the control unit 220 causes a pattern data signal to be output at random from all the pattern generators in response to the pattern enable signal (step S1302). Subsequently, the control unit 220 validates only the Even signal for the mode detectors MD12 and MD52 by the mode control signal (step S1303). Subsequently, the control unit 220 determines whether or not the lock signal LockE_1112 and the lock signal LockE_5152 are detected (step S1304).

If not detected in step S1304, the process proceeds to step S1314 described later. When the lock signal LockE_1112 is detected in step S1304, the input buffer amplifier CB11 is set so that the phase difference between the signal TLO11 output from the transmission line 320 and the signal TLO12 output from the transmission line 321 is equal to or smaller than a predetermined value. In this state, the delay time of the corresponding delay device 241 is set.
The state in which the lock signal LockE_5152 is detected corresponds to the input buffer amplifier CB52 so that the phase difference between the signal TLO51 output from the transmission line 328 and the signal TLO52 output from the transmission line 329 is equal to or less than a predetermined value. This is a state in which the delay time of the delay device 241 is set.

  If detected in step S1304, the control unit 1304 uses the delay control signal to send delay control data corresponding to the delay time set in the delay device 241 corresponding to the input buffer amplifiers CB11 and CB52 to the buffer memory in the delay control unit 243. (Step S1305).

  Subsequently, the control unit 220 returns the delay time of the delay device 241 corresponding to the input buffer amplifiers CB11 and CB52 to the reference Td by the delay control signal (step S1306). Subsequently, the control unit 220 validates only the Odd signal for the mode detectors MD12 and MD52 by the mode control signal (step S1307). Subsequently, the control unit 220 determines whether or not the lock signal LockO_1112 and the lock signal LockO_5152 are detected (step S1308).

  If not detected in step S1308, the process proceeds to step S1314 described later. If detected in step S1308, the control unit 220 causes the delay device 251 corresponding to the input buffer amplifier CB11 to set the delay time at this time by the delay control signal. Also, the control unit 220 causes the delay device 251 corresponding to the input buffer amplifier CB52 to set the delay time at this time (step S1309).

  Subsequently, the control unit 220 sets the delay time temporarily stored in the delay control unit 243 in step S1305 to the delay device 241 corresponding to the input buffer amplifiers CB11 and CB52 (step S1310).

  Subsequently, the control unit 220 validates both the Even signal and the Odd signal of the mode detection units MD12 and MD52 by the mode control signal (step S1311). Subsequently, the control unit 220 determines whether or not the lock signal LockE_1112, the lock signal LockE_5152, the lock signal LockO_1112, and the lock signal LockO_5152 are detected (step S1312).

  If not detected in step S1312, the process proceeds to step S1314 described later. If detected in step S1312, the control unit 220 determines whether all lock signals have been detected (step S1313). If not detected in step S1313, the control unit 220 changes the sensitivity setting in all lock detection units of the CIJ compensation LSI 410 by the lock control signal (step S1314). If detected in step S1313, the control unit 220 ends the third setting process.

  The simulation result using the jitter tolerance test system 100 of the present embodiment is shown below. FIG. 14 is a diagram illustrating a simulation model. FIG. 14A shows a transmission line model used in the case of single-end transmission, and FIG. 14B shows a transmission line model used in the case of differential transmission.

  In FIG. 14A, single-ended transmission is performed using eight transmission lines, and in FIG. 14B, differential transmission is performed using eight transmission lines as four differential pairs.

  FIG. 15 is a first diagram illustrating a simulation result. FIG. 15A shows an eye pattern in which signals input to the input ends 1 to 8 of the transmission line shown in FIG. FIG. 15B shows an eye pattern of the far end 5 (fe5) when a signal is input only to the transmission line 5 shown in FIG. FIG. 15B shows the jitter amount when there is no CIJ. The signal source used for the simulation is a pseudo random pattern signal with a transmission rate of 6.25 Gbps and PRBS7.

  FIG. 16 is a second diagram for explaining the simulation result. FIG. 16 shows a change in jitter amount with and without CIJ compensation in the differential transmission model shown in FIG. FIG. 16A shows an eye pattern when CIJ compensation is not performed, and FIG. 16B shows an eye pattern when CIJ compensation is performed.

  Comparison of FIG. 16A and FIG. 16B shows that CIJ is reduced by CIJ compensation.

  FIG. 17 is a third diagram for explaining the simulation result. FIG. 17 shows a change in jitter amount with and without CIJ compensation in the single-ended transmission model shown in FIG. FIG. 17A shows an eye pattern when CIJ compensation is not performed, and FIG. 17B shows an eye pattern when CIJ compensation is performed. Also in FIG. 17, it can be seen that CIJ is reduced by CIJ compensation.

  In the present embodiment, the example in which the CIJ compensation function is applied to the jitter tolerance test system 100 has been described. However, the present invention is not limited to this. The CIJ compensation function described in this embodiment can be applied to a communication unit having a data transmission unit and a data reception unit that perform high-speed data communication via a microstrip transmission line, for example. In this case, it is preferable that a CIJ-compensated signal generation unit 210 is provided in the data transmission unit, and a CIJ compensation LSI 410 is provided in the data reception unit.

  The preferred embodiment and its modification have been described in detail above, but the present invention is not limited to the above-described embodiment and its modification, and the above-described implementation is performed without departing from the scope described in the claims. Various modifications and substitutions can be added to the embodiment and its modifications. For example, each embodiment and its modifications can be combined as appropriate.

DESCRIPTION OF SYMBOLS 100 Jitter tolerance test system 200 Jitter tolerance test apparatus 210 Signal generation unit with CIJ compensation 220 Control unit 230 Analysis unit 300 Probe card 320-329 Microstrip transmission line 400 Probe card adapter 410 CIJ compensation LSI

Claims (10)

A transmission system having a transmission device that transmits a high-speed data signal via a plurality of transmission lines, and a reception device that receives the high-speed data signal,
The receiving device is:
A mode detection unit for detecting whether a mode between the high-speed data signals adjacent to each other in the plurality of transmission lines is a differential mode or a common mode;
Depending on the detected mode, either the differential phase comparison unit or the in-phase phase comparison unit is enabled, and the level of the high-speed data signal output from the adjacent transmission line in the plurality of transmission lines is A phase comparison unit that detects that the phase difference is equal to or less than a predetermined value and outputs a detection signal to the transmission device, and
The transmission apparatus is
For each of the high-speed data signals corresponding to the plurality of transmission lines, an output-side delay device provided on the receiving device side, an input-side delay device provided on the input side,
Have a, a delay control unit that sets to the delay device to delay time of the delay device when receiving the detection signal from the receiving device,
The delay control unit
The delay time set in the delay device on the output side of the first high-speed data signal corresponding to the first transmission line is set on the output side of the second high-speed data signal adjacent to one of the first high-speed data signals. Set the delay device,
A transmission system for setting a delay time set in the delay device on the input side of the first high-speed data signal in the delay device on the input side of the third high-speed data signal adjacent to the other of the first high-speed data signal .   The delay control unit
  In setting the delay time of the delay device on the input side of the first high-speed data signal and the delay device on the input side of the second high-speed data signal,
  The transmission system according to claim 1, wherein the first high-speed data signal and the third high-speed data signal are set to a differential mode.   The delay control unit
  In setting the delay time of the delay device on the input side of the first high-speed data signal and the delay device on the output side of the second high-speed data signal,
  The transmission system according to claim 2, wherein the first high-speed data signal and the second high-speed data signal are set to a differential mode.   When only the third high-speed data signal is adjacent to the first high-speed data signal,
  The delay control unit
  4. The transmission system according to claim 2, wherein the first high-speed data signal and the third high-speed data signal are randomly set as pattern data signals. The transmission apparatus is
A mode detection unit for detecting a mode between the high-speed data signals adjacent to each other;
The input-side delay device and the output-side delay device each have a differential mode delay device and a common-mode delay device,
The delay control unit
When setting the delay time of the differential mode delay device when the first high-speed data signal and the third high-speed data signal are in a differential mode,
According to any one of claims 1 to 4 to set the delay time of the common-mode delay device when the first high-speed data signal and said third high-speed data signal becomes common mode Transmission system. Before Symbol delay control unit,
The delay time of the delay device on the output side is a predetermined reference value, and the delay time of the delay device on the input side is set,
6. The transmission system according to claim 1, wherein the delay time of the output-side delay device is set based on the set delay time of the input-side delay device. The transmission apparatus is
When setting the delay time of the delay device on the input side,
In the plurality of transmission lines, the delay time of the delay device for the high-speed data signal output from the outermost transmission line is set to a predetermined reference value,
The transmission system according to claim 6 , wherein a delay time of another delay device on the input side is set using the predetermined reference value. The transmission line is a microstrip transmission line,
The transmission system according to claim 1, wherein the high-speed data signal is a pseudo random pattern signal. A transmission device for transmitting a high-speed data signal via a plurality of transmission lines,
For each of the high-speed data signals corresponding to the plurality of transmission lines, an output-side delay device provided on the receiving device side, an input-side delay device provided on the input side,
Receiving the high-speed data signal , detecting whether a mode between the adjacent high-speed data signals in the plurality of transmission lines is a differential mode or a common-mode, and depending on the detected mode, a difference A phase difference between the high-speed data signals output from the transmission lines adjacent to each other in the plurality of transmission lines is less than or equal to a predetermined value from the receiving device that enables either the dynamic phase comparison unit or the in-phase phase comparison unit. the delay time of the delay device upon receiving a detection signal indicating that it is now, have a, a delay control unit for setting the delay device,
The delay control unit
The delay time set in the delay device on the output side of the first high-speed data signal corresponding to the first transmission line is set on the output side of the second high-speed data signal adjacent to one of the first high-speed data signals. Set the delay device,
A transmission apparatus for setting a delay time set in a delay device on the input side of the first high-speed data signal in a delay device on the input side of a third high-speed data signal adjacent to the other of the first high-speed data signal . A jitter compensation method by a transmission system having a transmission device for transmitting a high-speed data signal via a plurality of transmission lines and a receiving device for receiving the high-speed data signal,
The receiving device is:
Detecting whether a mode between the adjacent high-speed data signals in the plurality of transmission lines is a differential mode or an in-phase mode, and depending on the detected mode, a differential phase comparison unit or an in-phase mode Enable one of the phase comparators,
Detecting that the phase difference of the high-speed data signal output from the adjacent transmission line in a plurality of transmission lines is a predetermined value or less, and outputting a detection signal to the transmission device;
The transmission apparatus is
For each of the high-speed data signals corresponding to the plurality of transmission lines, an output-side delay device provided on the receiving device side, and an input-side delay device provided on the input side, the detection signal from the receiving device Set a delay time when receiving
When setting the delay time,
The delay time set in the delay device on the output side of the first high-speed data signal corresponding to the first transmission line is set on the output side of the second high-speed data signal adjacent to one of the first high-speed data signals. Set the delay device,
Jitter compensation for setting the delay time set in the delay device on the input side of the first high-speed data signal in the delay device on the input side of the third high-speed data signal adjacent to the other of the first high-speed data signal Method.