JP3791762B2 - Simultaneous bidirectional transmission / reception device and signal transmission / reception system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to signal transmission / reception between information processing apparatuses, and more particularly to a simultaneous bidirectional transmission / reception apparatus capable of transmitting and receiving signals simultaneously and bidirectionally using the same transmission line and a signal transmission / reception system using the same. is there.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, a technique that enables transmission and reception of signals simultaneously and bidirectionally using the same transmission line is known. For example, in Japanese Patent Application Laid-Open No. 56-98052, the output part of the transmission circuit in the transmission / reception circuit of the own station is connected to the transmission / reception circuit of the opposite station via the resistor and the transmission line, and further the resistor of the transmission circuit As a configuration in which the output signal of the previous stage is combined with a reference voltage via a voltage dividing resistor and input as a reference voltage of a differential input type receiving circuit, and a transmission / reception superimposed signal on a transmission line is input to a comparison input, This differential input type receiving circuit removes only the transmission signal of its own station and reproduces the signal transmitted from the other station. Also, for example, in Japanese Patent Laid-Open No. 3-186033, the transmission / reception number of the own station and the transmission signal from the other station are combined by the signal combining unit, and then the transmission signal of the own station and the transmission signal from the other station are combined from the combined signal. The signal is separated by the signal separation unit, only the transmission signal of the own station is removed from the separated signal, and the signal transmitted from the other station is received.
[0003]
[Problems to be solved by the invention]
2. Description of the Related Art In recent years, the speed of microprocessors and the like has been dramatically increased, and accordingly, signal transfer between information processing apparatuses, signal transfer between LSIs, and a large capacity have been demanded. In order to improve the throughput of signal transfer, there is a means of improving the frequency and extending the signal bit width. In particular, in the part where the throughput is important, it is common to provide a dedicated transmission line and a dedicated reception line for signal bits. Is. Against this background, the number of LSI signal pins is steadily increasing, but the price and external dimensions of LSIs are reduced as the number of signal pins decreases, so various devices for reducing the number of pins are available. It is going on.
[0004]
In this case, the number of LSI signal pins can be halved by using a simultaneous bidirectional transmission / reception circuit that enables simultaneous bidirectional transmission / reception using the same signal line as described above, resulting in signal transfer throughput. Improvement is possible. However, this type of conventional configuration has a peculiar problem due to simultaneous transmission of signals from both directions, which hinders speeding up. Specifically, an edge portion of a signal transmitted from another station and arriving at the own station (transient state in which the signal transitions from a “0” signal to a “1” signal or from a “1” signal to a “0” signal) And the edge portion of the signal transmitted from the own station to the other station collide at the receiving circuit input point of the own station, the signal becomes uncertain during that period, and the delay time of the receiving circuit itself fluctuates. The fluctuation of the delay time of the receiving circuit itself means that the signal decision time width of the received signal is narrowed, which not only hinders high-speed operation but also causes erroneous signal transfer and malfunction. It can also cause.
[0005]
An object of the present invention is a simultaneous bidirectional transmission / reception apparatus capable of high-speed and accurate signal transfer even when a delay time variation of a receiving circuit occurs due to collision between edges of signals transmitted from each terminal station And providing a signal transmission / reception system to which the same is applied.
[0006]
[Means for Solving the Problems]
In the simultaneous bidirectional transmission / reception apparatus of the present invention, a variable delay circuit (first variable delay means) that varies a delay time until the signal transmitted from the transmission circuit of the local station arrives at the reception circuit of the other station, A variable delay circuit (second variable delay means) for varying the delay time until the signal capturing clock signal transmitted from the transmitting circuit of the local station arrives at the receiving circuit of the other station in order to capture the signal at the other station The main feature is that
[0007]
Furthermore, in the present invention, a known signal sequence is transmitted from another station, and the signal sequence is transmitted from the own station with a variable delay time according to this, and the edges of the transmission signals from each terminal station collide with each other A detection unit that detects a signal determination time width of a signal sequence received by the own station by making a signal capturing clock signal transmitted from another station variable, and a memory for storing the detection result Part. Then, based on the detection result stored in the storage unit, the phase of the signal capturing clock signal is synchronized within the signal determination time width.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a block diagram showing an embodiment of a data transmission / reception system to which the simultaneous bidirectional transmission / reception apparatus of the present invention is applied. In FIG. 1, 10 and 20 are simultaneous bidirectional transmission / reception apparatuses, and 30 is a transmission line. A simultaneous bidirectional transmission / reception device (hereinafter, left station) 10 includes a simultaneous bidirectional transmission / reception circuit 100, a data transmission flip-flop circuit 110, a data variable delay circuit 120, a data reception flip-flop circuit 130, a detection storage circuit 140, and a clock transmission flip-flop circuit. 150 and a clock variable delay circuit 160. The configuration of the opposing simultaneous bidirectional transmission / reception apparatus (hereinafter, right station) 20 is the same. The transmission line 30 includes a data line 301 (parallel n bits) and clock signal lines 302 and 303, and here, the transmission lines 30 are of equal length.
[0009]
The simultaneous bidirectional transmission / reception circuits 100 and 200 transmit the transmission data Sdatala and Sdata2a of the local station 10 to the transmission line 30 (data line 301), and transmit data from other stations on the transmission line 30 and the local station. This circuit cancels only the transmission data of its own station from the combined wave with the transmission data, and receives and reproduces only the transmission data from other stations. The variable delay circuits 120 and 220 are circuits that variably adjust the delay time until transmission data from the simultaneous bidirectional transmission / reception circuit of the local station arrives at the simultaneous bidirectional transmission / reception circuit of the other station. Is a circuit that variably adjusts the delay time until the clock signals CLK1 and CLK2 for capturing signals from the own station arrive at other stations. The detection storage circuits 140 and 240 are circuits that detect signal determination time widths of the received data Rdatala and Rdata2a at their own stations and store the detection results.
[0010]
As will be described later, while the delay values of the variable delay circuits 120, 160, 220, and 260 are changed, the detection storage circuits 140 and 240 detect and store the signal determination time widths of the received data Rdatala and Rdata2a at the local station. To do. Based on the detection results stored in the detection storage circuits 140 and 240, the delay values of the variable delay circuits 160 and 260 are set so that the phases of the signal capturing clock signals CLK1 and CLK2 come (synchronize) within the signal determination time width. Set.
[0011]
The outline of the operation in the actual operation of FIG. 1 is as follows. Here, the data transfer from the left station 10 to the right station 20 is assumed, but the data transfer from the right station 20 to the left station 10 is the same, and both data transfers can be performed simultaneously.
[0012]
The transmission data Sdatala (parallel n bits) is transmitted from the transmission circuit of the simultaneous bidirectional transmission / reception circuit 100 to the transmission line 30 (data line 301) through the transmission flip-flop circuit 110 and the variable delay circuit 120. Similarly, a signal capturing clock signal CLK1 is transmitted from the transmission flip-flop circuit 150, the variable delay circuit 160, and the simultaneous bidirectional transmission / reception circuit 100 to the transmission line 30 (clock signal line 302).
[0013]
The data sent from the left station 10 to the transmission line 30 (data line 301) arrives at the receiving circuit in the simultaneous bidirectional transmission / reception circuit 200 of the right station 20 with a delay of the propagation delay time of the transmission line 30 and receives the received data. The circuit sends to the reception flip-flop circuit 230. In addition, the signal capturing clock signal also arrives at the reception flip-flop circuit 230 of the right station 20 along the same path as the data. The reception flip-flop circuit 230 captures data using this signal capture clock signal. During actual operation, the phase of the signal capturing clock signal is set to an optimum value, and the reception data Rdata 2a is determined as the output of the reception flip-flop circuit 230.
[0014]
Hereinafter, a circuit configuration example of the main part of FIG. 1 and its operation will be described. FIG. 2 is a circuit configuration example of the simultaneous bidirectional transmission / reception circuits 100 and 200. The simultaneous bidirectional transmission / reception circuits 100 and 200 cancel only the transmission data of the own station from the combined wave of the transmission data from the other station on the transmission line 30 (data line 301) and the transmission data from the own station. In addition, a signal sent from another station is reproduced. In FIG. 2, in the simultaneous bidirectional signal transmission / reception circuit 100 on the left station 10 side, the transmission circuit 2a transmits the transmission data Sdata1c via the resistor Rtt1, and in the simultaneous bidirectional transmission / reception circuit 200 on the right station 20 side, 2b sends the transmission data Sdata2c to the transmission line 30 through the resistor Rtt2 at an arbitrary timing. If the values of the resistors Rtt1 and Rtt2 are set equal to the characteristic impedance Z0 of the transmission line 30, 1 (both 1 is a composite wave of the transmission data Sdata1c and Sdata2c sent from both sides on the transmission line 30). ), 1/2 (only one of them is 1), and 0 (both 0) appear. The voltage Vbb is set to a potential that is ½ of the output signal amplitude level of the transmission circuits 2a and 2b. Therefore, for example, when paying attention to the simultaneous bidirectional transmission / reception circuit 100 on the left station 10 side, when the output signal of the transmission circuit 2a is a “0” signal, the reference voltage Vref1 of the differential input type reception circuit 2d is the output of the transmission circuit 2a. The value is 1/4 of the signal amplitude, and is 3/4 when the signal is “1”. The differential input type receiving circuit 2d compares the reference voltage Vref1 with the ternary voltage signal on the transmission line 30 (Lineel), cancels only the transmission data Sdatalc transmitted by the own station 10, and transmits it from the other station 20. The received transmission data Sdata2c is reproduced to obtain reception data Rdata1c. The same operation is performed in the simultaneous bidirectional transmission / reception circuit 200 on the right station 20 side.
[0015]
The timing chart of each part is as shown in FIG. However, in FIG. 3, the edge portion of the signal transmitted from the other station and arriving at the own station collides with the edge portion of the signal transmitted from the own station to the other station at the receiving circuit input point of the own station. It is a timing chart in the case of no ideal operation. Actually, depending on the process variation of the LSI and the transmission line length, as shown in the timing chart of FIG. 4, a collision between the edge portions (the circled portions of Line 1 and Line 2) occurs, and the delay of the receiving circuit fluctuates. End up. This means that the signal determination time width of the reception data Rdatac and Rdata2c is sandwiched, which hinders high-speed operation and causes malfunction.
[0016]
When the transmission data from the other station and the transmission data of the local station collide with each other, the reason why the delay of the receiving circuit fluctuates is that the reference voltage Vref which is an input signal of the differential input type receiving circuit and the transmission line This is because there is a difference in the rise and fall transition times with the above signal. The edge portion of the signal transmitted from another station and arriving at the own station is affected by the transmission line, parasitic capacitance, input capacitance of the receiving circuit, and the like, and the waveform becomes dull. On the other hand, since the signal transmitted by the local station is input to the receiving circuit of the local station, the waveform is hardly dulled. Even if these two signals having a difference in rising and falling transition times are input to the differential input type receiving circuit, correct comparison cannot be performed, and as a result, jitter occurs in that portion.
[0017]
A method of setting the phase of the clock signal for signal capture to an optimum value while avoiding the influence of delay fluctuation caused by the collision between the edges of the transmission data from other stations and the data of the local station A description will be given with reference to FIGS. Here, a case where data flows from the left station 10 to the right station 20 will be described.
[0018]
FIG. 5 is a detailed configuration example of a circuit portion that creates a state in which edge portions collide with each other and a state in which no collision occurs by using 3 bits of n-bit data in the configuration of FIG. FIG. 6 is a timing chart of each signal in FIG.
[0019]
First, the delay setting of the variable delay circuit 120 on the left office 10 side is set to zero. Next, a bit string (01000000 in FIG. 6) having a level different from the other one bit is applied to the 3 bits of the transmission data Sdata1a_0-2 of the left station 10 and the variable delay circuit 120 is simultaneously transmitted from the transmission flip-flop circuit 110. The data is transmitted to the opposite right station 20 via the bidirectional transmission / reception circuit 100. The transmitted data Sdata1a_0-2 arrives as reception data Rdata2in_0-2 at the differential input type receiving circuit input point of the simultaneous bidirectional transmission / reception circuit 200 of the right station 20 with a delay of the propagation delay time of the signal transmission system. .
[0020]
On the right station 20 side, transmission data Sdata2a_0-2 that collides with the reception data Rdata2in_0-2 is transmitted toward the opposite left station 10. In this case, the 0th bit data Sdata2a_0 transmits a bit string (00000000 or 11111111) in which the level does not change, a so-called level signal. Therefore, the signal transmission system of Sdata1a_0 and Sdata2a_0 is in an ideal state where no collision occurs between the data edge portions. The first bit of data Sdata2a_1 transmits a bit string (01111111 in FIG. 6) that changes only once from the “0” signal to the “1” signal. Therefore, in the signal transmission system of Sdata1a_1 and Sdata2a_1, the rising edge transmitted from the right station 20 collides with the edge portion of the data transmitted from the left station 10. In contrast to the first bit, the second bit data Sdata2a_2 transmits a bit string (10000000 in FIG. 6) that transitions only once from the “1” signal to the “0” signal. Therefore, in the signal transmission system of Sdata1a_2 and Sdata2a_2, the falling edge of the data transmitted from the right station 20 collides with the edge portion of the data transmitted from the left station 10.
[0021]
By the way, the edge portions of data cannot collide with each other at the input point of the differential input type receiving circuit of the simultaneous bidirectional transmission / reception circuit only by the combination of the bit string patterns as described above. It is necessary to adjust the timing due to the propagation delay of the signal transmission system. This is performed using the variable delay circuits 120 and 220.
[0022]
The propagation delay time until the data transmitted from the left station 10 arrives at the differential input type receiving circuit input point of the simultaneous bidirectional transmission / reception circuit 200 of the right station 20 can be estimated and predicted at the design stage. In FIG. 6, this propagation delay time is t. Here, the delay setting value of the variable delay circuit 210 of the right station 20 is changed in order to cause the data edge portions to collide with each other. The variable width is based on the propagation delay time estimated and predicted in the design stage, as in the relationship between the reception data Rdata2in_0-2 and the transmission data Sdata2a_0-2 in FIG. Can be fully included.
[0023]
FIG. 7 is a circuit configuration example of the variable delay circuit 220. The configuration of the variable delay circuit 120 is the same. In FIG. 7, four selector circuits 7b and a buffer circuit 7a are provided at the input of each selector circuit. By setting arbitrary values to the delay setting terminals a, b, c, and d, a delay value as shown in FIG. 8 can be obtained. For example, if a = 0, b = 1, c = 1, and d = 0, a delay value corresponding to four stages of selector circuits + two stages of buffer circuits + four stages of buffer circuits can be obtained.
[0024]
In this way, by performing simultaneous bidirectional transmission / reception of data, as shown in FIG. 6, in the right station 20, there is no collision between edge portions in Rdata2c_0, a collision between rising edge and rising edge, and falling edge in Rdata2c_1. The rising collision state, Rdata2c_2, can create a rising and falling collision state and a falling and falling collision state.
[0025]
FIG. 9 is a detailed configuration example of a circuit portion that adjusts the phase of the signal capturing clock signal and sets it to an optimum value. Here, the detection storage circuit 240 includes an AND circuit 9b that detects the signal determination time width of the received data, and a RAM circuit 9c that stores the detection result. The configuration of the variable delay circuit 160 for the clock signal for signal capture is basically the same as that shown in FIG.
[0026]
As described with reference to FIGS. 5 and 6, the data Rdata2c_0-2 receives the transmission data Sdata1a__2 from the left station 10, and the transmission data Sdata2a__2 from the right station 20 generated by the variable delay circuit 220 of the right station 20 And the received signal when there is no collision between the edge portions. These signals are input to the reception flip-flop circuit 230. At the CLK terminal of the reception flip-flop circuit 230, the transmission flip-flop circuit 150 of the left office 10 → the variable delay circuit 160 → the simultaneous bidirectional transmission / reception circuit 100 → the transmission line 30 (clock line 302) → right as well as the transmission data Sdata2a_2_2. A signal capturing clock signal CLK1 that has followed the normal path of the simultaneous bidirectional transmission / reception circuit 200 of the station 20 is applied. The phase of the fetch clock signal CLK1 can be adjusted by the variable delay circuit 160. As described in FIGS. 5 and 6, the variable width can capture data by sufficiently including the edge portion of the transmission data from the left station 10 based on the propagation delay time estimated and predicted in the design stage. Keep it. The 3-bit data fetched by the reception flip-flop circuit 230 is ANDed by the AND circuit 9b, and the result is written in the RAM circuit 9c.
[0027]
The signal determination time width of data received by the right station 20 is detected by the following procedure. The delay setting of the variable delay circuit 120 for the data bits of the left office 10 is always set to zero. First, the delay value of the variable delay circuit 220 for the data bits of the right station 20 is set to 0, and the simultaneous bidirectional transmission / reception described with reference to FIGS. 5 and 6 is performed. At this time, the delay value of the variable delay circuit 160 of the clock signal for data capture of the left office 10 is changed while sequentially incrementing from 0, and for each set value, the output signal of the AND circuit 9b is stored in the RAM on the right office 20 side. Write to the circuit 9c. Next, the delay value of the variable delay circuit 220 for the data bits of the right station 20 is incremented, and the same operation is performed. When this series of operations is repeated, data as shown in FIG. 10 is finally written in the RAM circuit 9c. In FIG. 10, the data in the shaded portion is the target data, and it is possible to confirm the fluctuation of the signal determination time width of the received data due to the collision between the edge portions of the transmission data.
[0028]
In the case of the example of FIG. 10, the target data is a “1” signal, but at the end of the data, 1 → 1 → 1 does not continue, and the data may not be correctly captured as 1 → 0 → 1. . Such a portion cannot be regarded as a signal determination time width. For example, when the target data continues three times or more like 1 → 1 → 1, the range is defined as the signal determination time width. When this definition is applied to FIG. 10, the inside of the bold line frame is the signal determination time width. In FIG. 9, the delay setting of the variable delay circuit 160 for the data capture clock signal CLK1 is set to a = 0, b on the left station 10 side. = 1, c = 1, d = 0 to a = 1, b = 0, c = 0, d = 0.
[0029]
If the optimum value of the CLK phase obtained in this way is used during actual operation, even if the delay time fluctuation of the receiving circuit due to the collision of the edge portions of the data transmitted from each terminal station occurs, it can be performed at high speed. A simultaneous bidirectional data transmission / reception system that enables accurate data transmission / reception can be constructed.
[0030]
The above description focuses on the received data at the right station 20 when the data flows from the left station 10 to the right station 20, but the same method can be used when the data flows from the right station to the left station 20 Since it can do, description is abbreviate | omitted.
[0031]
In this embodiment, 3 bits out of n bits of data are used to detect the optimum value of the CLK phase, but there are various other detection methods. For example, using 6 bits of data n bits, (1) a bit where no collision occurs (rising and level signal), (2) a bit where no collision occurs (falling and level signal), and (3) rising Bits that collide with rising edges, (4) Bits with falling and falling collisions, (5) Bits with rising and falling collisions, (6) Bits with falling and rising collisions individually There are ways to produce and detect. There is also a method of detecting using only one bit by using a bit string that can create the states (1) to (6) with only one bit. Although several detection methods can be considered in this way, the essence of the present invention is that a known signal sequence is used to detect the optimum value of the CLK phase.
[0032]
Next, in order to make the superiority of the present invention easier to understand, the conventional method and the present method are compared in FIG. In the conventional method, since the phase of the data capture clock signal is fixed, the balance between the setup-side timing margin and the hold-side timing margin is deteriorated, and as a result, high-speed operation is hindered. In the example of FIG. 11, the setup side timing margin is small. On the other hand, in the system according to the present invention, the phase of the data capturing clock signal is optimized, so that the setup side timing margin and the hold side timing margin are well balanced. In addition, even if the signal determination time width is very small, it can be operated as long as it is secured, so that high-speed operation can be realized.
[0033]
【The invention's effect】
As described above, according to the present invention, in the simultaneous bidirectional transmission / reception circuit, when the edge portions of the signal collide at the input point of the receiving circuit, the delay time of the receiving circuit itself fluctuates, preventing high-speed operation or malfunctioning. Can be avoided, and a system capable of high-speed and accurate data transmission can be constructed.
[Brief description of the drawings]
FIG. 1 is a block diagram of a data transmission / reception system according to an embodiment of the present invention.
FIG. 2 is a configuration example of a simultaneous bidirectional transmission / reception circuit.
FIG. 3 is an ideal timing chart of each signal in FIG. 2;
4 is a timing chart when the edge portions of the transmission signal in FIG. 2 collide with each other. FIG.
5 is a configuration example of a circuit portion that creates a state in which edge portions of transmission signals collide with each other in FIG. 1;
6 is a timing chart of each signal in FIG. 5;
FIG. 7 is a circuit configuration example of a variable delay circuit.
8 is a table showing the correspondence between delay settings and delay values in FIG.
FIG. 9 is a configuration example of a circuit portion for setting a signal capturing clock signal to an optimum value in FIG. 1;
FIG. 10 is an example of a signal determination time width detection result according to FIG. 9;
FIG. 11 is a timing chart comparing a conventional method and a method according to the present invention.
[Explanation of symbols]
10, 20 Simultaneous bidirectional transceiver (terminal station)
100, 200 Simultaneous bidirectional transmission / reception circuit 110, 210 Data transmission flip-flop circuit 120, 220 Transmission data variable delay circuit 130, 230 Data reception flip-flop circuit 140, 240 Detection storage circuit 150, 250 Clock transmission flip-flop circuit 160 for capturing signals 260 clock variable delay circuit

Claims (3)

A transmission circuit and a reception circuit connected to the same transmission line are provided. A signal is transmitted from the transmission circuit to the transmission line, and a signal from the local station on the transmission line and a signal from another station are combined by the reception circuit. In a simultaneous bidirectional transmission / reception device that receives signals from other stations from waves and enables simultaneous transmission / reception of signals between end stations,
Transmitted from the first variable delay means for varying the delay time until the signal transmitted from the transmitting circuit arrives at the receiving circuit of the other station, and the transmitting circuit for capturing the signal transmitted from the own station in the other station Second variable delay means for varying a delay time until the signal capturing clock signal arrives at the receiving circuit of another station;
A simultaneous bidirectional transmission / reception apparatus comprising: 2. The simultaneous bidirectional transmission / reception apparatus according to claim 1, wherein a signal train is received from another station with a variable delay time of a signal capturing clock signal, and a signal train is transmitted from the own station with a variable delay time. Thus, there is provided a simultaneous bidirectional transmission / reception apparatus comprising means for detecting a signal determination time width of a received signal sequence from another station and storing the detection result. 3. A signal transmission / reception system in which the simultaneous bidirectional transmission / reception devices according to claim 2 are connected to each other via the same transmission line, based on the detection result of the signal determination time width of the received signal trains from other stations stored in each other. Adjusting the delay time of the second variable delay means of the partner simultaneous bidirectional transmission / reception apparatus, and synchronizing the phase of the clock signal for signal capture within the signal determination time width of the received signal train from the other station, Signal transmission / reception system.

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