JP5987486B2 - Manufacturing method of semiconductor device - Google Patents

Description

  Embodiments described below relate to a method for manufacturing a semiconductor device.

  In a so-called high voltage MOS transistor, a large electric field concentration is likely to occur particularly in the vicinity of the drain end of the channel region. Therefore, the breakdown voltage at the drain end of the gate insulating film is important.

  As such a high voltage MOS transistor, a so-called LDMOS (Laterally Diffused MOS) structure is used in which the drain region is greatly separated from the gate electrode and a drift region is formed between them in order to improve the breakdown voltage in the vicinity of the drain end. Yes.

  It is desired that such an MOS transistor having an LDMOS structure (hereinafter referred to as an LDMOS transistor) be integrated on a semiconductor substrate in the form of an integrated circuit together with other logic elements and flash memories.

JP 2003-246277 A JP 2011-204938 A

  In a logic element or flash memory, a so-called STI (shallow trench isolation) structure is generally used as an element isolation region in order to reduce the element area. In the element isolation region of the STI structure, an element isolation groove is formed in the semiconductor substrate so as to surround the element region of the logic element or the flash memory, and an insulating film such as a silicon oxide film is formed as the element isolation insulating film in the element isolation groove. Thus, desired element isolation is realized.

  On the other hand, in a high voltage transistor such as an LDMOS transistor, in order to improve the breakdown voltage, a field similar to that in the element isolation region is formed between the drain side end of the channel region and the drain region by a silicon oxide film continuously with the gate insulating film. A structure is used in which the thickness of the gate insulating film is substantially increased at the drain side end of the gate electrode by forming an oxide film and extending the drain side end of the gate electrode on the field oxide film. . In an LDMOS transistor having such a field oxide film formed, carriers emitted from the source region and passed through the channel region immediately below the gate electrode further pass under the field oxide film and then reach the drain region. Conventionally, a silicon oxide film formed by a LOCOS (Local Oxidation of Silicon) process has been widely used as a field oxide film of an LDMOS transistor.

  When the LDMOS transistor is integrated on a common semiconductor substrate together with other logic elements and flash memory, it is conceivable that the field oxide film is formed in the STI structure simultaneously with the element isolation region of the logic element and flash memory. However, in this case, since carriers reach the drain region from the drain end of the LDMOS transistor through the deep STI structure, there arises a problem that the carrier path becomes long. Further, this causes a problem that the on-resistance of the element increases.

  On the other hand, when the STI structure is used as the field oxide film of the LDMOS transistor, the element isolation trench is formed to have a shallow depth corresponding to the insulating film of the LOCOS structure so as not to increase the on-resistance, thereby forming the field oxide film. It may be possible to reduce the depth of the structure. However, in such a configuration, it is necessary to execute a process of forming the field oxide film of the LDMOS transistor in a shallower STI structure separately from the process of forming the element isolation region of another semiconductor element in the STI structure. There arises a problem that the manufacturing process of the apparatus becomes complicated and the manufacturing cost increases. In addition, when the depth of the element isolation trench is reduced in this way, it is necessary to increase the width of the element isolation region in order to obtain a desired element isolation effect. As a result, the area of the element isolation region increases. It will cause problems.

  Further, when the STI structure is used for the element isolation region of the logic element or the flash memory and the LOCOS film is used only for the LDMOS transistor, the STI structure isolation region is formed, and further, the LOCOS structure insulating film is formed. Therefore, there is an unavoidable problem that the number of processes increases and the manufacturing cost of the semiconductor device increases.

According to one aspect, a method of manufacturing a semiconductor device includes forming a first element isolation region having an STI structure on a semiconductor substrate, and defining the first element region in the first substrate region by the first element isolation region. And a stacked pattern in which a first oxide film pattern, a first nitride film pattern, and a second oxide film pattern are sequentially stacked in the first element region. Forming a non-volatile semiconductor memory element as a first semiconductor element; and a second semiconductor including a third oxide film pattern in a second element region included in a second substrate region of the semiconductor substrate Forming the first semiconductor element, the first oxide film and the nitride film are sequentially formed so as to cover the first substrate region and the second substrate region. The first oxide film and the nitride film in the first step. Patterning in the second element region while covering the element region, and forming a mask pattern comprising a stack of the first oxide film and the nitride film in the second element region; Oxidizing the surface of the first element region to form a second oxide film on the nitride film in the first element region; and the first oxide film and the nitride film in the first element region; The first oxide film pattern, the first nitride film pattern, and the second oxide film pattern are sequentially laminated by patterning the laminated film sequentially laminated with the second oxide film. Forming the laminated pattern, wherein the step of forming the second semiconductor element thermally oxidizes the surface of the semiconductor substrate in the second substrate region using the mask pattern as a mask. Especially An oxidation process for forming the third oxide film pattern, and the thermal oxidation process for forming the second oxide film and the oxidation process for forming the third oxide film pattern are performed simultaneously. The

  According to this embodiment, it is possible to form the field oxide film on the second semiconductor element by the LOCOS process without increasing the number of steps while performing the element isolation of the first semiconductor element by the element isolation region having the STI structure. It becomes possible.

FIG. 6 is a process cross-sectional view (part 1) illustrating the manufacturing process of the semiconductor device according to the first embodiment; FIG. 9 is a process cross-sectional view (part 2) illustrating the manufacturing process of the semiconductor device according to the first embodiment; FIG. 6 is a process cross-sectional view (part 3) illustrating the manufacturing process of the semiconductor device according to the first embodiment; FIG. 7 is a process cross-sectional view (part 4) illustrating the manufacturing process of the semiconductor device according to the first embodiment; FIG. 10 is a process cross-sectional view (part 5) illustrating the manufacturing process of the semiconductor device according to the first embodiment; FIG. 9 is a process cross-sectional view (No. 6) for describing the manufacturing process of the semiconductor device according to the first embodiment; It is process sectional drawing (the 7) explaining the manufacturing process of the semiconductor device by 1st Embodiment. FIG. 11 is a process cross-sectional view (No. 8) for explaining the manufacturing step of the semiconductor device according to the first embodiment; It is process sectional drawing (the 9) explaining the manufacturing process of the semiconductor device by 1st Embodiment. It is process sectional drawing (the 10) explaining the manufacturing process of the semiconductor device by 1st Embodiment. It is process sectional drawing (the 11) explaining the manufacturing process of the semiconductor device by 1st Embodiment. It is process sectional drawing (the 12) explaining the manufacturing process of the semiconductor device by 1st Embodiment. It is process sectional drawing (the 13) explaining the manufacturing process of the semiconductor device by 1st Embodiment. It is process sectional drawing (the 14) explaining the manufacturing process of the semiconductor device by 1st Embodiment. It is process sectional drawing (the 15) explaining the manufacturing process of the semiconductor device by 1st Embodiment. It is process sectional drawing (the 16) explaining the manufacturing process of the semiconductor device by 1st Embodiment. It is process sectional drawing (the 17) explaining the manufacturing process of the semiconductor device by 1st Embodiment. It is process sectional drawing (the 18) explaining the manufacturing process of the semiconductor device by 1st Embodiment. It is process sectional drawing (the 19) explaining the manufacturing process of the semiconductor device by 1st Embodiment. It is process sectional drawing (the 20) explaining the manufacturing process of the semiconductor device by 1st Embodiment. It is process sectional drawing (the 21) explaining the manufacturing process of the semiconductor device by 1st Embodiment. FIG. 22 is a process cross-sectional view (No. 22) for describing the manufacturing process of the semiconductor device according to the first embodiment; It is process sectional drawing (the 23) explaining the manufacturing process of the semiconductor device by 1st Embodiment. It is process sectional drawing (the 24) explaining the manufacturing process of the semiconductor device by 1st Embodiment. It is sectional drawing explaining the operation | movement of the LDMOS transistor in 1st Embodiment. It is sectional drawing explaining the LDMOS transistor by the comparative example of 1st Embodiment. It is sectional drawing explaining the LDMOS transistor by the modification of 1st Embodiment. It is process sectional drawing (the 1) explaining the manufacturing process of the semiconductor device by 2nd Embodiment. It is process sectional drawing (the 2) explaining the manufacturing process of the semiconductor device by 2nd Embodiment. It is process sectional drawing (the 3) explaining the manufacturing process of the semiconductor device by 2nd Embodiment. It is process sectional drawing (the 4) explaining the manufacturing process of the semiconductor device by 2nd Embodiment. It is process sectional drawing (the 5) explaining the manufacturing process of the semiconductor device by 2nd Embodiment. It is process sectional drawing (the 6) explaining the manufacturing process of the semiconductor device by 2nd Embodiment. It is process sectional drawing (the 7) explaining the manufacturing process of the semiconductor device by 2nd Embodiment. It is process sectional drawing (the 8) explaining the manufacturing process of the semiconductor device by 2nd Embodiment. It is process sectional drawing (the 9) explaining the manufacturing process of the semiconductor device by 2nd Embodiment. It is process sectional drawing (the 10) explaining the manufacturing process of the semiconductor device by 2nd Embodiment. It is process sectional drawing (the 11) explaining the manufacturing process of the semiconductor device by 2nd Embodiment. It is process sectional drawing (the 12) explaining the manufacturing process of the semiconductor device by 2nd Embodiment.

[First Embodiment]
The semiconductor device manufacturing method according to the first embodiment will be described below with reference to the process cross-sectional views of FIGS.

Referring to FIG. 1, for example, substrate regions 21A, 21B, and 21C are defined on a p ^- type silicon substrate 21, and the substrate region 21A includes an n-channel MOS transistor and a p-channel as will be described later. An element region for a high-speed logic element composed of a MOS transistor, an element region for a flash memory that is a nonvolatile memory element in the substrate region 21B, and an LDMOS transistor that is a high voltage MOS transistor in the substrate region 21C. An element region is formed. In the process of FIG. 1, a pad oxide film 121Op having a thickness of 3 nm to 30 nm, for example, 15 nm, and a silicon nitride film is formed on the silicon substrate 21 over the substrate regions 21A to 21C. A mask film 121N having a thickness of 50 nm to 200 nm, for example, 150 nm is sequentially formed.

  In the following description of the embodiment, for the sake of convenience, the high-speed logic element operates with a power supply voltage of 1.8V, the flash memory operates with a power supply voltage of 5V, and the LDMOS transistor operates with a power supply voltage of 42V. Obviously, the present embodiment is not limited to elements operating at these specific power supply voltages.

  Next, in the step of FIG. 2, the mask film 121N and the pad oxide film 121Op are patterned by a photolithography process (not shown) to form an opening 121Ap corresponding to the element isolation region in the substrate regions 21A and 21B.

  Next, in the step of FIG. 3, the silicon oxide film 121O is patterned using the mask film 121N as an etching mask, and the silicon substrate 21 is dry-etched using the mask film 121N as a mask, whereby the silicon substrate 21 is filled with the silicon oxide film 121O. An element isolation trench 21T having a depth of 150 nm to 500 nm, for example, 330 nm is formed corresponding to the opening 121Ap.

  Next, in the step of FIG. 4, a silicon oxide film 121Ox is deposited on the silicon substrate 21 so as to cover the mask film 121N and fill the element isolation trench 21T by, for example, a CVD method or a high-density plasma CVD method. Further, in the step of FIG. 5, the silicon oxide film 121Ox is polished and removed by chemical mechanical polishing (CMP) using the mask film 121N as a polishing stopper. Further, by removing the mask film 121N, the pad oxide film 121Op, and the protruding portion of the silicon oxide film 121Ox from the surface of the substrate 21 by wet etching or the like, the substrate regions 21A and 21B are subjected to STI (shallow trench isolation). Thus, the silicon substrate 21 in which the element isolation region 21I having the structure is formed is obtained. The element isolation region 21I having the STI structure defines element regions 21N and 21P of n-channel MOS transistors and p-channel MOS transistors constituting high-speed logic elements in the substrate region 21A, and flashes in the substrate region 21B. A memory element region 21F is defined.

Next, in the step of FIG. 7, the surface of the silicon substrate 21 is thermally oxidized to form a sacrificial oxide film 21Os having a thickness of 3 nm to 30 nm, for example, 10 nm, and the substrate region 21A is not illustrated in the step of FIG. Then, a p-type impurity element and an n-type impurity element are ion-implanted into the silicon substrate 21 through the sacrificial oxide film 21Os by respective ion implantation processes. In the substrate region 21B, a deep n-type well 21DNW and a shallow one are formed. A p-type well 21PW is formed, and in the substrate region 21C, a deep n ⁻ -type well 21Dr serving as a drift region of an LDMOS transistor and a shallower p-type well 21Bdy serving as a p-type body region are formed.

The deep n-type well 21DNW has phosphorus ions (P ⁺ ) under an acceleration voltage of 1 MeV to 3 MeV, for example 2 MeV, 1 × 10 ¹² cm ⁻² to 4 × 10 ¹³ cm ⁻² , for example 2.0 × 10 ¹³ cm ^−2. For example, it can be formed by ion implantation with a dose amount of 0 ° and a twist angle of 0 °. On the other hand, the shallow p-type well 21PW is boron ion (B ⁺ ) under an acceleration voltage of 200 keV to 500 keV, for example 420 keV, 1 × 10 ¹³ cm ⁻² to 4 × 10 ¹³ cm ⁻² , for example 2 × 10 ¹³ cm ^{−. It} can be formed by ion implantation with a dose amount of ² and a twist angle of 0 °, for example.

Further, the drift region 21Dr has a P ⁺ dose of 1 × 10 ¹² cm ^{−2 to} 5 × 10 ¹² cm ⁻² , for example, 2.5 × 10 ¹² cm ⁻² at an acceleration voltage of 1 MeV to 3 MeV, for example 2 MeV. And then at an acceleration voltage of 150 keV to 800 keV, for example 500 keV, at a dose of 5 × 10 ¹¹ cm ^{−2 to} 5 × 10 ¹² cm ⁻² , for example 1.5 × 10 ¹² cm ⁻² and for example 7 ° It can be formed by ion implantation from four directions with a twist angle of.

Further, the body region 21Bdy has a B ⁺ of 300 × 600 to 600 × 10 keV, for example, under an acceleration voltage of 420 × 5V, for example, 5 × 10 ¹² cm ^{−2 to} 3 × 10 ¹³ cm ⁻² , for example 1.2 × 10 ¹³ cm ⁻² . With a dose, then under an acceleration voltage of 100 keV to 250 keV, for example 150 keV, with a dose of 1 × 10 ¹² cm ⁻² to 1 × 10 ¹³ cm ⁻² , for example 5.0 × 10 ¹² cm ⁻² , for example 7 It can be formed by ion implantation from four directions with a twist angle of °.

  In the above ion implantation, the order of implantation may be changed as appropriate.

  Next, the sacrificial oxide film 21Os is removed in the step of FIG. 9 to expose the surface of the fresh silicon substrate 21, and the upper surface of the silicon substrate 21 is thermally oxidized in the step of FIG. A silicon oxide film 22T to be a tunnel insulating film of the flash memory to be formed is formed to a thickness of 5 nm to 30 nm, for example, 10 nm. In the state of FIG. 10, the silicon oxide film 22T is formed so as to continuously cover the substrate regions 21A to 21C.

Next, in the step of FIG. 11, a polysilicon film 23Fl is continuously formed on the silicon oxide film 22T over the first to third substrate regions, and in the step of FIG. 12, the polysilicon film 23Fl and its lower layer are formed. The silicon oxide film 22T is patterned and removed from the substrate regions 21A and 21C. As a result, a structure in which the silicon oxide film 22T and the polysilicon film 23Fl are stacked is left only in the substrate region 21B. In the illustrated example, the surface of the silicon substrate 21 is exposed in the substrate regions 21A and 21C in the step of FIG. 12, but the silicon oxide film 22T may be left in these regions. In the present embodiment, a polysilicon film containing phosphorus (P) at a concentration of 6 × 10 ¹⁹ cm ⁻³ is formed as the polysilicon film 23Fl. However, the polysilicon film 23Fl may be doped with different impurity elements or with different concentrations, or may be an undoped polysilicon film. It is also possible to use an amorphous silicon film instead of the polysilicon film 23Fl.

  Next, in the step of FIG. 13, the silicon oxide film 24 and the silicon nitride film 25 are formed on the 12 structures, the silicon oxide film 24 and the silicon nitride film 25 are the substrate regions 21A to 21C, and the layers are 3 to 15 nm and 15 nm, respectively. The film is formed so as to be continuously covered with a film thickness of 5 nm to 20 nm, for example, a film thickness of 6 nm and 8 nm, respectively. In the substrate regions 21A and 21C, the silicon oxide film 24 and the silicon nitride film 25 cover the surface of the silicon substrate 21 directly or via the silicon oxide film 22T. In the substrate region 21B, Note that the polysilicon film 23F1 is covered. In the step of FIG. 13, the silicon oxide film 24 and the silicon nitride film 25 are typically formed by a thermal CVD method.

  Next, in the present embodiment, the silicon nitride film 25 is patterned in the substrate region 21C in the step of FIG. 14, and an opening corresponding to the field oxide film of the LDMOS transistor formed in the substrate region 21C is formed in the silicon nitride film 25. A portion 25A and an opening 25B corresponding to the element isolation region defining the element region of the LDMOS transistor are formed. 14, the silicon oxide film 24 may be patterned subsequent to the patterning of the silicon nitride film 25 so that the surface of the silicon substrate 21 is exposed.

Next, in the present embodiment, the structure of FIG. 14 is wet-thermally oxidized at a temperature of 950 ° C. in the step of FIG. Thus, an insulating film 25 _ONO having a so-called ONO structure in which the silicon oxide film 24, the silicon nitride film 25, and the silicon oxide film 26 are stacked on the silicon film 25Fl is formed in the substrate region 21B. At the same time, in the step of FIG. 15, a silicon oxide film 27A having a thickness of 150 nm to 400 nm, for example, 254 nm, is formed as a field oxide film of the LDMOS transistor by the so-called LOCOS process in the opening 25A in the substrate region 21C. The At the same time, corresponding to the opening 25B, a similar silicon oxide film 27B is formed as an element isolation film so as to define an element region of the LDMOS transistor. It should be noted that the silicon nitride film 25 functions as an oxidation-resistant mask pattern that prevents oxidation of the silicon substrate 21 in the substrate region 21A and the substrate region 21C.

  The silicon oxide film 27A formed in the substrate region 21C in this way has a so-called LOCOS structure, so that the lower half enters below the surface of the silicon substrate 21, but the upper half protrudes above the surface of the silicon substrate 21. Have a shape to As a result, when such a silicon oxide film 27A is used as a field oxide film of an LDMOS transistor, the depth of the lower end of the field oxide film can be reduced while ensuring a sufficient film thickness as the field oxide film. . For this reason, as will be described later, the path length of carriers passing under the field oxide film can be significantly reduced as compared to the case where an STI structure oxide film having the same film thickness is formed. It is.

  In this embodiment, next, in the step of FIG. 16, in the substrate region 21A for the logic element, the p-type and n-type wells are respectively formed in the element region 21N of the n-channel MOS transistor and the element region 21P of the p-channel MOS transistor. 21APW and 21ANW are formed, and the insulating film 25ONO having the ONO structure is removed from the substrate region 21A and the substrate region 21C in the step of FIG. 17, and the surface of the silicon substrate 21 is exposed.

  Further, in the step of FIG. 18, the structure of FIG. 17 is thermally oxidized, and a thermal oxide film 28A serving as a gate insulating film of the n-channel MOS transistor and the p-channel MOS transistor formed in the element regions 21N and 21P on the substrate region 21A. Form. In the step of FIG. 18, a similar thermal oxide film 28B is also formed as a gate insulating film of the LDMOS transistor in the element region 21DL in the substrate region 21C. In the illustrated example, the thermal oxide films 28A and 28B are formed with the same film thickness at the same time. However, the thermal oxide films 28B have different film thicknesses, for example, such that the thermal oxide film 28B has a larger film thickness than the thermal oxide film 28A. It is also possible to form it. In the example of FIG. 18, the thermal oxide film 28A is drawn so as to be formed also on the surface of the silicon oxide film constituting the element isolation region 21I having the STI structure in the substrate region 21A. The surface of the CVD oxide film formed in the trench 21T corresponds to a state modified by thermal oxidation, and the CVD oxide film is a high quality silicon oxide film formed by, for example, a high density plasma CVD method. If so, such a modified layer may not be formed. The same applies to the tunnel oxide film 22T in the substrate region 22B.

Next, in the step of FIG. 19, a polysilicon film 29 is formed on the structure of FIG. 18 so as to cover the substrate regions 21A to 21C to a film thickness of, for example, 180 nm, and in the step of FIG. the film 29, the ONO film _{25 ONO} and poly-silicon film 23FL thereunder, is patterned tunnel oxide film 22T in company, the tunnel oxide film 22T, the polysilicon film 23FL, laminated with ONO film _{25 ONO,} and a polysilicon film 29 is laminated A gate structure 29G is formed. Here, the polysilicon film 23Fl forms a floating gate electrode of the flash memory, the polysilicon film 29 constitutes a control electrode of the flash memory, and the ONO film 25 _ONO is an electrode between the floating gate electrode 23Fl and the control electrode 29. An inter-layer insulating film is formed.

  Further, in the step of FIG. 20, an n-type impurity element such as P or As is introduced into the silicon substrate 21 by using the stacked gate electrode 29FG as a mask in the substrate region 21B, and in the element region 21F of the flash memory. N-type LDD regions 21fa and 21fb are formed.

  Further, in the step of FIG. 21, a thin sidewall insulating film 29FS is formed on the stacked gate electrode 29FG, and the left and right sidewall surfaces of the floating gate electrode 23Fl are surrounded by the sidewall insulating film 29FS.

  Next, in the step of FIG. 22, the polysilicon film 29 and the silicon oxide film 28 thereunder are patterned in the substrate regions 21A and 21C. In the substrate region 21A, the polysilicon gate electrode 29N is formed in the element region 21N, and A polysilicon gate electrode 29P is formed in the element region 21P via the gate insulating film 28A.

At the same time, in the step of FIG. 22, by patterning the polysilicon film 29, the gate electrode 29LD of the LDMOS transistor in the substrate region 21C starts from the first end located on the p-type well 21Bdy in the substrate region 21C. Patterning is performed so as to continuously extend to the second end located on field oxide film 27A. At this time, in the p-type well 21Bdy, a first opening 28AP that exposes the p-type well 21Bdy is defined between the end of the element isolation region 21B and the first end of the gate electrode 29LD. . Further, the gate electrode 29LD covers the surface of the silicon substrate 21 through the thermal oxide film 28B from the first end to the field oxide film 27A, and the thermal oxide film 28B is covered with the LDMOS transistor. The gate oxide film is formed. In addition, a channel region of an LDMOS transistor is formed in a portion of the p-type well 21Bdy covered with the gate electrode 29LD. Further, in the step of FIG. 22, the thermal oxide film 28B is removed in the second opening 28BP corresponding to the drain region of the LDMOS transistor, and the n ⁻ type well constituting the drift region is exposed in the opening 28BP. ing.

  Further, in the step of FIG. 22, in the element region 21N in the substrate region 21A, n-type impurity elements are ion-implanted using the polysilicon gate electrode 20N mask on both sides of the polysilicon gate electrode 29N. A source extension region 21a and a drain extension 21b are formed. Similarly, a p-type source extension region 21c and a drain extension 21d are formed on both sides of the polysilicon gate electrode 29P in the element region 21P by ion implantation of a p-type impurity element using the polysilicon gate electrode 20P as a mask. Has been.

Next, in the step of FIG. 23, side wall oxide films 29Os are formed on the side wall surfaces of the gate electrodes 29N, 29P, and 29LD, and the gate electrode 29N and the side wall oxide films are formed in the element region 21N in the substrate region 21A. An n-type impurity element such as P or As is ion-implanted using 29 Os as a mask. Thus, in the element region 21N, the n ⁺ -type source region 21e and the n ⁺ -type region are partially overlapped with the n-type source extension region 29a and the drain extension region 29b on the outside of the sidewall oxide film 29O, respectively. A drain region 21f is formed. Accordingly, the polysilicon gate electrode 29N is doped n ⁺ type. The polysilicon gate electrode 29N is formed in the substrate region 21A together with the n ⁺ -type source region 21e and drain region 21f, and the n-type source extension region 21a and drain extension region 21b in the element region 21N. An n-channel MOS transistor constituting a part of the logic element is formed.

In the step of FIG. 23, a p-type impurity element such as B is ion-implanted into the element region 21P in the substrate region 21A using the gate electrode 29P and the sidewall oxide film 29Os as a mask. As a result, in the element region 21P, the p ⁺ type source region 21g and the p ⁺ type regions are partially overlapped with the p type source extension region 29c and the drain extension region 29d, respectively, outside the sidewall oxide film 29O. A drain region 21h is formed. As a result, the polysilicon gate electrode 29P is also doped p ⁺ type. The polysilicon gate electrode 29P is formed in the substrate region 21A together with the p ⁺ -type source region 21g and drain region 21h, and the p-type source extension region 21c and drain extension region 21d in the element region 21P. A p-channel MOS transistor constituting a part of the logic element is formed.

23, the sidewall oxide film 29Os is formed outside the thin sidewall insulating film 29Fs in the substrate region 21B, and the stacked gate electrode structure 29FG, the thin sidewall insulating film 29Fs and the sidewall oxide film 29Os are used as a mask. As a result of the ion implantation of the n-type impurity element, the n ⁺ -type source region is partially overlapped with the source extension region 29fa and the drain extension region 29fb, respectively, outside the sidewall oxide film 29Os in the element region 21F. 29fc and n ⁺ -type drain region 29fd are formed. At that time, the uppermost polysilicon film 29 of the laminated gate electrode structure 29FG is doped n ⁺ type. As a result, a flash memory having a stacked gate 29FG in the element region 21F is formed in the substrate region 21B.

Further, in the step of FIG. 23, in the substrate region 21C, n-type impurity elements such as P and As are ion-implanted using the gate electrode 29LF and the sidewall oxide film 29Os as a mask to correspond to the opening 28AP of the element region 21LD. during the p-type well 21Bdy, first the ^{n +} -type source region 21l adjacent the ends, also ^{n +} type in the n-type drift region 21Dr corresponding to the opening 28BP of the gate electrode 29LS Each drain region 21m is formed. As a result, in the substrate region 21C, an LDMOS transistor having a source region 21l, a drain region 21m, and a gate electrode 29LD is formed in the element region 21LD.

Further, in the step of FIG. 23, a p ⁺ -type contact region 21n is formed adjacent to the source region 21l in the p-type well 21Bdy corresponding to the opening 28AP for controlling the potential of the well 21Bdy. .

Further, in the step of FIG. 24, in the element region 21N, the n ⁺ -type source region 21e and drain region 21f and further on the surface of the gate electrode 29N, and in the element region 21P, the p ⁺ -type source region 21g and In the drain region 21h and the surface of the gate electrode 29P, in the element region 21F, the n ⁺ -type source region 21fc and the drain region 21fd, and further on the surface of the polysilicon film 29 in the stacked gate electrode 29FG In the element region 21LD, a silicide layer 30 is formed by the salicide method on the surfaces of the n ⁺ -type source region 21l and drain region 21m and the polysilicon gate electrode 29LD. In the element region 21LD, the silicide layer 30 is formed by connecting the n + type source region 21l and the p + type contact region 21n.

  Further, an interlayer insulating film 31 is formed on the silicon substrate 21 so as to cover the gate electrodes 29N and 29P, the stacked gate structure 29FG and the gate electrode 29LD, and in the interlayer insulating film 31, the source region 21e, the drain region 21f, Via plugs 31A to 31I are formed in contact with the silicide layers 30 corresponding to the source region 21g, the drain region 21h, the source region 21fc, the drain region 21fd, the source region 21l, and the gate electrodes 29LD and 21m, respectively.

  As a result, a semiconductor device is obtained in which n-channel MOS transistors and p-channel MOS transistors constituting high-speed logic elements are integrated on a silicon substrate 21 together with flash memory and LDMOS transistors.

  FIG. 25 is a sectional view for explaining the operation of the LDMOS transistor in FIG.

  Referring to FIG. 25, in the LDMOS transistor, a channel region CH is formed in the p-type well 21Bdy directly below the gate electrode 29LD with a gate insulating film 28B interposed therebetween, and carriers ( After passing through the channel region CH, the electrons) pass through the drift region 21Dr along the path L indicated by the dotted line in FIG. 25 and reach the drain region 21m. At this time, the second end portion, that is, the drain end of the gate electrode 29LD is located on the field oxide film 27A, so that the discharge at the drain end of the gate electrode is suppressed and the breakdown voltage of the transistor is improved. .

  In the LDMOS transistor of FIG. 25, carriers pass under the field oxide film 27A when moving in the drift region 21Dr. Of the field oxide film 27A having a total thickness of T, the surface of the silicon substrate 21 is transferred. The region penetrating below does not reach half of the total thickness T. For this reason, the depth t of the carrier path L immediately below the field oxide film 27A does not reach 1 / 2T as measured from the surface of the silicon substrate 21 (t <T / 2), and further, at both ends of the field oxide film 27A. Since the slope portions 27a and 27b are formed, an increase in the carrier path length in the drift region 21Dr caused by bypassing the field oxide film 27A is slight.

  On the other hand, FIG. 26 is a sectional view showing an LDMOS transistor according to a comparative example in which a field oxide film 127A having an STI structure having the same thickness as the thickness T of the field oxide film 27A is formed instead of the field oxide film 27A. It is. For comparison, in FIG. 26, parts corresponding to those in FIG.

  Referring to the comparative example of FIG. 26, in such a configuration, the carrier path L indicated by the dotted line is pushed down to the depth T by the distance from the surface of the substrate 21, and both ends of the field oxide film 127A. Are substantially right angles, and there are no inclined portions 27a, 27b as in the present embodiment. For this reason, in the configuration of the comparative example, the path length of the carrier path L is significantly increased as compared with the LDMOS transistor according to the present embodiment of FIG.

  Further, in the configuration of the comparative example of FIG. 26, the depth of the field oxide film 127A having the STI structure is set equal to the film thickness T of the field oxide film 27A, that is, 245 nm. It should be noted that the depth is shallower than the depth of the element isolation region 21I having the STI structure formed in the other substrate regions 21A and 21B, that is, 330 nm. This means that the field oxide film 127A needs to be formed separately from the step of forming the STI structure 21I previously shown in FIGS. However, repeating the same process once more after the processes of FIGS. 1 to 6 leads to a significant increase in the number of manufacturing processes.

  On the other hand, in the comparative example of FIG. 26, if the formation of the field oxide film 127A having the STI structure is performed simultaneously with the formation of the element isolation region 21I having the STI structure, the depth of the field oxide film 127A is set to the depth of the element isolation region 21I. However, in such a configuration, the path length of the carriers passing under the field oxide film 127A further increases.

  In the comparative example of FIG. 26, consider a case where the depth of the field oxide film 127A having the STI structure is formed to be equal to the depth t of the field oxide film 27A in the present embodiment of FIG. In such a case, as the thickness of the field oxide film 27A decreases, the drain region 21m is separated from the drain end of the gate electrode 29LD by a larger distance in order to ensure a sufficient breakdown voltage. Need to be made. As a result, there is a problem that the element area increases even when the STI structure is used. Further, as described above, after forming the element isolation region 21I in the steps of FIGS. 1 to 6, it is necessary to perform the same step again to form the field oxide film 127A, and the number of steps is remarkably increased. The problem that ends up also arises.

  In contrast, in the method of manufacturing the semiconductor device according to the present embodiment, the LDMOS transistor having the field oxide film 27A having the so-called LOCOS structure shown in FIG. 25 and having a low on-resistance is formed on the same silicon substrate simultaneously with the flash memory element. It is possible to obtain a special effect that it can be formed without increasing the thickness.

  FIG. 27 is a cross-sectional view showing a configuration of a semiconductor device according to a modification of the present embodiment. In FIG. 27, portions corresponding to the portions described above are denoted by the same reference numerals, and description thereof is omitted. In FIG. 27, illustration of the interlayer insulating film 31 and the via plugs 31A to 31H is omitted for simplicity.

  Referring to FIG. 27, in the present embodiment, when the STI type element isolation region 21I is formed in the substrate regions 21A and 21B by the steps of FIGS. 1 to 6, the STI type element isolation is simultaneously performed in the substrate region 21C. Region 21I is formed, thereby defining element region 21LD. According to such a configuration, the element area can be reduced by forming the STI type element isolation region in the LDMOS transistor.

27 can be obtained, for example, by forming only the opening 25A in the ONO film 25 _ONO covering the substrate region 21C in the oxidation treatment step for forming the field oxide film 27A in FIG.

[Second Embodiment]
Next, a method for fabricating a semiconductor device according to the second embodiment will be described with reference to process cross-sectional views in FIGS. In the figure, the same reference numerals are given to the parts described above, and the description thereof is omitted.

  In this embodiment, the process of FIG. 28 is executed following the process of FIG. 7 in the previous embodiment, and in the semiconductor region 21, the substrate region 21A has a p corresponding to the element region 21N of the n-channel MOS transistor. Ion implantation through a sacrificial oxide film 21Os having a thickness of 10 nm and a n-type well 21ANW formed on the surface of the silicon substrate 21 corresponding to the element region 21P of the p-channel MOS transistor. Is formed.

  In the step of FIG. 28, a deep n-type well 21DNW and a shallow p-type well 21PW are formed in the substrate region 21B by ion implantation through the sacrificial oxide film 21Os for the element region 21F of the flash memory, Further, a deep n-type well 21Dr serving as a drift region of the LDMOS transistor and a shallow p-type well 21Bdy serving as a channel region are similarly formed in the substrate region 21C by ion implantation through the sacrificial oxide film 21Os. Each ion implantation condition can be set in the same manner as in the previous embodiment.

  In the present embodiment, next, in the step of FIG. 29, the sacrificial oxide film 21Os is removed from the surface of the silicon substrate 21 by wet etching using, for example, HF, and a thermal oxide film 22T is newly formed on the surface of the silicon substrate 21. The tunnel oxide film is formed with a thickness of 7 nm, for example. Further, in the step of FIG. 29, a silicon nitride film 25 serving as a charge storage film of the flash memory is continuously formed on the tunnel oxide film 22T to a thickness of 5 nm to 30 nm to the substrate regions 21A to 21C by, eg, thermal CVD. For example, it is formed to a thickness of 10 nm.

  Further, in the step of FIG. 30, the silicon nitride film 25 is patterned in the substrate region 21C, and an opening 25A corresponding to the field oxide film formation region of the LDMOS transistor is formed in the silicon nitride film 25 and the LDMOS. An opening 25B is formed corresponding to the element isolation region of the transistor. In the illustrated example, the silicon oxide film 22T is exposed in the openings 25A and 25B. However, the openings 25A and 25B may be formed so as to expose the surface of the silicon substrate 21.

  Further, in the present embodiment, the surface of the silicon nitride film 25 is thermally oxidized in the step of FIG. 31 corresponding to the step of FIG. 15 of the previous embodiment, and the surface of the silicon nitride film 25 is thermally oxidized in the substrate regions 21A and 21B. The oxide film 26 is formed with a film thickness of 2 nm to 3 nm. At that time, in the substrate region 21C, a so-called LOCOS process occurs in which the surface of the silicon substrate 21 is oxidized directly or locally through the silicon oxide film 22T, corresponding to the openings 25A and 25B. The silicon oxide films 27A and 27B having a LOCOS structure and a film thickness of 150 nm to 350 nm, for example, 245 nm are formed as a field oxide film and an element isolation insulating film of the LDMOS transistor, respectively. The element isolation insulating film 27B defines an element region 21LD of the LDMOS transistor.

  Next, in the step of FIG. 32, the tunnel insulating film 22T, the silicon nitride film 25 and the thermal oxide film 26 are removed in the substrate regions 21A and 21C, and further, the silicon substrate 21 is thermally oxidized on the silicon substrate 21 in the step of FIG. A thermal oxide film 28A serving as a gate insulating film of the n-channel MOS transistor and p-channel MOS transistor is formed in the substrate region 21A, and a thermal oxide film 28B serving as a gate oxide film of the LDMOS transistor is formed in the substrate region 21C. . In the illustrated example, the thermal oxide films 28A and 28B are formed with the same film thickness at the same time. However, the thermal oxide films 28B have different film thicknesses, for example, such that the thermal oxide film 28B has a larger film thickness than the thermal oxide film 28A. It is also possible to form it.

  Next, in the step of FIG. 34, a polysilicon film 29 is formed on the surface of the silicon substrate 21 up to the substrate regions 21A to 21C, and the polysilicon film 29 is patterned in the step of FIG. Then, an n-channel MOS transistor gate electrode 29N is formed on the element region 21N, a p-channel MOS transistor gate electrode 29P is formed on the element region 21P, and a flash memory control electrode 29B is formed on the substrate region 21B. The substrate region 21C is formed with a gate electrode 29LD of an LDMOS transistor. At this time, the gate electrodes 29N and 29P are formed on the element regions 21N and 21P via a thermal oxide film 28A, and the gate electrode 29LD is formed on the element region 21LD via the field oxide film 27A. It is formed on the silicon substrate 21 through a thermal oxide film 28B except for the portion that is formed. The thermal oxide films 28A and 28B constitute gate insulating films of the respective gate electrodes.

  Further, in the step of FIG. 36, the thermal oxide film 26, the silicon nitride film 25 and the thermal oxide film 22T thereunder are sequentially patterned using the control electrode 29B as a mask in the substrate region 21B. In the element region 21F, a tunnel insulating film made of the thermal oxide film 22T, a charge storage film made of a silicon nitride film 25, and a control electrode made of a polysilicon pattern 29B are formed on the silicon substrate 21. A gate electrode structure 29F is formed with the thermal oxide film 26 interposed between the control electrode 29B and the control electrode 29B.

  Further, in the step of FIG. 37, in the substrate region 21A, an n-type impurity element is ion-implanted into the element region 21N using the gate electrode 29N as a mask, so that an n-type is formed on both sides of the gate electrode 29N in the element region 21N. Source extension region 21a and n-type drain extension region 21b are formed. Further, in the same substrate region 21A, a p-type impurity element is ion-implanted into the element region 21P using the gate electrode 29P as a mask, whereby a p-type source extension region 21c is formed on both sides of the gate electrode 29P in the element region 21P. Then, a p-type drain extension region 21d is formed.

  In the step of FIG. 37, n-type impurity elements are ion-implanted into the element region 21F using the gate electrode structure 29F as a mask in the substrate region 21B, thereby forming n-type source extension regions on both sides of the gate electrode structure 29F. 29fa and an n-type drain extension region 29fb are formed.

Next, in the step of FIG. 38 , sidewall oxide films 29Os are formed on the gate electrodes 29N and 29P and the gate electrode structure 29F, and further on the gate electrode 29LD, and the sidewall oxide film 29Os is used as a mask to form n-type or p-type in each element region. By ion-implanting a type impurity element, the n-type source extension region 21a and the n-type drain extension region 29b are partially formed outside the sidewall insulating film 29Os in the element region 21N as in the previous embodiment. Overly, n ⁺ -type source region 21e and n ⁺ -type drain region 21f are formed. Similarly, in the element region 21P, the p ⁺ -type source region 21g and the p ⁺ -type are partially overlapped with the p-type source extension region 21c and the p-type drain extension region 29d, respectively, outside the sidewall insulating film 29Os. A drain region 21h is formed. In the element region 21F, the n ⁺ -type source region 21fc and the n ⁺ -type drain are partially overlapped with the n-type source extension region 21fa and the n-type drain extension region 29fb, respectively, outside the sidewall insulating film 29Os. Region 21fd is formed. Further, in the element region 21LD, the n ⁺ -type source region 21l included in the p-type well 21Bdy and the n ⁺ -type drain region included in the drift region 21Dr are outside the sidewall insulating film 29Os, respectively. 21 m is formed.

In the step of FIG. 38, a p ⁺ -type contact region 21n is further formed in the p-type well 21Bdy adjacent to the n ⁺ -type source region 21l for the substrate bias of the p-type well 21Bdy.

  Further, in the step of FIG. 39, the silicide film 30 is formed by the salicide method on the surface of each gate electrode 29N, 29P, 29B, 29LD and the surface of each diffusion region 21e, 21f, 21g, 21h, 21fc, 21fd, 21l, 21m and 21m. Then, an interlayer insulating film 31 is formed on the silicon substrate 21 so as to cover the silicide film 30, and diffusion regions 21 e, 21 f, 21 g, 21 h, 21 fc, 21 fd, 21 l, 21 m are formed in the interlayer insulating film 31. And via plugs 31A to 31I that are in contact with each other through respective silicide layers 30, n channel MOS transistors, p channel MOS transistors, flash memories, and LDMOS transistors constituting high-speed logic elements on the silicon substrate 21 are formed. Is integrated The semiconductor device can be obtained.

  Also in the semiconductor device obtained in this way, as in the previous embodiment, the increase in the on-resistance of the LDMOS transistor is similar to that of the LDMOS transistor while using the STI structure for element isolation in the high-speed logic element and the flash memory. By forming the field oxide film 27A in the LOCOS structure, it can be avoided and an increase in the number of processes can be avoided.

  Further, as can be seen from the above description, in the present embodiment, the high voltage transistor is not limited to the specific LDMOS transistor described in the embodiment, but silicon whose surface is thermally oxidized in the substrate region 21A or the substrate region 21B. This is effective in manufacturing a semiconductor device including a first semiconductor element having a nitride film and including a second semiconductor element in which a silicon oxide film is formed in the substrate region 21C by a LOCOS process.

  As mentioned above, although this invention was described about preferable embodiment, this invention is not limited to this specific embodiment, A various deformation | transformation and change are possible within the summary described in the claim.

21 silicon substrate 21I STI element isolation region 21A logic element substrate region 21APW p-type well 21ANW n-type well 21B flash memory substrate region 21Bdy body region 21C LDMOS transistor substrate region 21DNW deep n-type well 21Dr drift region 21F flash memory device region 21LD LDMOS transistor Element region 21N n-channel MOS transistor element region 21Os sacrificial oxide film 21P p-channel MOS transistor element region 21PW shallow p-type well 21T element isolation trench 21a, 21fa n-type source extension region 21b, 21fb n-type drain extension region 21c p-type source extension Region 21d p-type drain extension region 21e n ⁺ -type source region 21f n ⁺ type drain region 21g p ⁺ type source region 21h p ⁺ type drain region 21l n ⁺ type source region 21m n ⁺ type drain region 21n p ⁺ type substrate contact region 22 silicon oxide film 22T tunnel oxide film 23 polysilicon film 23Fl poly Silicon film and floating gate electrode 24 Silicon oxide film 25 Silicon nitride film 25 _ONO ONO film 26 Thermal oxide film 27A LOCOS structure field oxide film 27B LOCOS element isolation region 28A, 28B Gate oxide film 28AP, 28BP Opening 29 Polysilicon film 29N, 29P, 29LD Gate electrode 29B Control electrode 29FG Laminated gate structure 29Fs Side wall insulating film 29Os Side wall oxide film 30 Silicide film 31 Interlayer insulating film 31A to 31I Via plug 121Ap Mask opening 121O Pad oxide film 121N silicon nitride mask 121Ox silicon oxide film

Claims (8)

Forming a first element isolation region having an STI structure on a semiconductor substrate, and defining the first element region in the first substrate region by the first element isolation region;
A non-volatile semiconductor memory device including a stacked pattern in which a first oxide film pattern, a first nitride film pattern, and a second oxide film pattern are sequentially stacked in the first element region Forming as a first semiconductor element;
Forming a second semiconductor element including a third oxide film pattern in a second element region included in the second substrate region of the semiconductor substrate;
Including
The step of forming the first semiconductor element includes:
Sequentially forming a first oxide film and a nitride film so as to cover the first substrate region and the second substrate region;
The first oxide film and the nitride film are patterned in the second element region while covering the first element region, and the first oxide film and the nitride film in the second element region. Forming a mask pattern comprising a stack of
Oxidizing the surface of the nitride film to form a second oxide film on the nitride film in the first element region; and
In the first element region, the first oxide film pattern and the first oxide film pattern are patterned by patterning a laminated film in which the first oxide film, the nitride film, and the second oxide film are sequentially laminated. Forming a laminated pattern in which a nitride film pattern and the second oxide film pattern are sequentially laminated;
Including
The step of forming the second semiconductor element includes an oxidation step for forming the third oxide film pattern by thermally oxidizing the surface of the semiconductor substrate using the mask pattern as a mask in the second substrate region. Including steps,
A method of manufacturing a semiconductor device, wherein a thermal oxidation step for forming the second oxide film and an oxidation step for forming the third oxide film pattern are performed simultaneously. The second semiconductor element has a drift region including a first conductivity type first well and a second conductivity type second well included in the first well, and the second well has a first conductivity type. A source region of a type, the first well including a drain region of a first conductivity type spaced apart from the second well, and a surface of the semiconductor substrate including the second well in the first well The third oxide film pattern is provided between the drain region, a gate electrode on the semiconductor substrate via a gate insulating film, and the gate electrode from a first end adjacent to the source region. The second well and the first well are gate-insulated between the source region and the third oxide film pattern up to a second end closer to the drain region than the first end. Covering through the membrane and further the gate The method of manufacturing a semiconductor device according to claim 1, characterized in that it comprises an LDMOS transistor having a so as to extend the emission above - the pole the third oxide film pattern to the second end.   The step of patterning the nitride film is performed so that the surface of the semiconductor substrate is exposed surrounding the second element region in the second substrate region, thereby forming the third oxide film pattern. In the step, the surface of the semiconductor substrate exposed surrounding the second element region is simultaneously oxidized, and the second element isolation region surrounding the second element region is formed of a fourth oxide film pattern. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is formed in a shape.   The method further includes the step of forming a second element isolation region having an STI structure surrounding the second element region in the second substrate region, wherein the step of forming the second element isolation region includes the first element isolation region. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the method is performed simultaneously with the step of forming the element isolation region.   The step of forming the first semiconductor element includes a step of forming a tunnel insulating film on the semiconductor substrate in the first element region prior to the step of forming the first oxide film and the nitride film. Forming a first film to be a floating gate electrode on the tunnel insulating film so that the first film covers the first and second substrate regions; and patterning the first film. 5. The method for manufacturing a semiconductor device according to claim 1, further comprising: removing from the second substrate region.   The step of forming the first semiconductor element includes a step of forming the first oxide film as a tunnel oxide film, and the nitride film is formed on the first oxide film as a charge storage film. The method for manufacturing a semiconductor device according to claim 1, wherein: A step of forming a second film over the first substrate region and the second substrate region so that the second film covers the laminated pattern in the first substrate region; 7. The step of patterning the second film in at least one substrate region including at least the laminated pattern to form a control electrode of the nonvolatile semiconductor memory element. Semiconductor device manufacturing method. 8. The second film is patterned also in the second substrate region simultaneously with the step of patterning the second film, and the gate electrode of the second semiconductor element is formed. The manufacturing method of the semiconductor device of description.

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