JP5987314B2 - Printed wiring board - Google Patents

Description

The present invention relates to a printed wiring board for mounting a chip on which a resin insulating layer and a conductor layer are alternately laminated on a core substrate.

A printed wiring board for a package on which a logic chip or the like is mounted is required to efficiently release heat generated in the logic chip. Patent Document 1 proposes a configuration in which a metal plate is used for a core substrate in order to improve heat dissipation of a multilayer wiring board on which a semiconductor element is mounted.

JP 2005-72064 A

However, Patent Document 1 can improve the heat dissipation in the horizontal direction by the core substrate made of a metal plate, but improves the heat dissipation in the vertical direction from the mounted chip side to the external connection substrate side to be mounted. The effect is considered to be weak. In addition, the core substrate made of a metal plate has a high copper occupancy ratio of the entire substrate, and it is assumed that the printed wiring board is likely to warp when the resin insulating layers and the conductor layers are alternately laminated.

The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a printed wiring board having high heat dissipation in the vertical direction.

A core substrate having a first surface and a second surface opposite to the first surface;
A through hole conductor formed by filling a through hole for a through hole conductor penetrating the core substrate from the first surface to the second surface direction with copper plating;
A through hole penetrating the core substrate from the first surface to the second surface direction;
A heat dissipating member accommodated in the through hole;
A printed wiring board comprising a wiring laminated portion in which resin insulating layers and conductor layers are alternately laminated on the core substrate:
The heat dissipating member is disposed in a region immediately below the chip on which the printed wiring board is mounted, and via conductors are connected to both the front and back surfaces of the heat dissipating member,
The through-hole conductor is disposed in a region immediately below a chip on which a printed wiring board is mounted, and via conductors are connected to the first surface side and the second surface side of the through-hole conductor ,
A technical feature is that an electronic component is accommodated in a through hole adjacent to the through hole in which the heat dissipation member is accommodated .

Since the printed wiring board of the present invention includes a heat dissipation member in the through hole of the core substrate, the heat dissipation in the vertical direction is high, and the heat of the mounted chip can be efficiently released to the mounted external connection substrate side. . Since the heat radiating member is accommodated only in the through hole, the copper occupation ratio of the entire printed wiring board is low, and the wiring laminated portion in which the resin insulating layers and the conductor layers are alternately laminated hardly warps.

FIG. 4 is a process diagram showing a method for manufacturing a printed wiring board having solder bumps according to the first embodiment of the present invention. Process drawing which shows the manufacturing method of the printed wiring board of 1st Embodiment. Process drawing which shows the manufacturing method of the printed wiring board of 1st Embodiment. Process drawing which shows the manufacturing method of the printed wiring board of 1st Embodiment. Process drawing which shows the manufacturing method of the printed wiring board of 1st Embodiment. Sectional drawing of the printed wiring board which has the solder bump of 1st Embodiment. The application example of the printed wiring board of 1st Embodiment. Sectional drawing of the printed wiring board of 2nd Embodiment. Sectional drawing of the printed wiring board which concerns on the 1st modification of 2nd Embodiment. The top view of the printed wiring board which concerns on the 2nd modification of 2nd Embodiment.

[First embodiment]
FIG. 6 shows a cross section of the printed wiring board 100 having solder bumps according to the first embodiment of the present invention. In the printed wiring board 100, a copper heat dissipation block 80 is built in the core substrate 30, and one buildup layer is formed on the first surface and the second surface of the core substrate 30.

The core substrate 30 includes an insulating base material 30M having a through hole (opening) 20 for accommodating the first heat dissipation block 80, and a first conductor layer 34A formed on the main surface (F) of the insulating base material. And a second conductor layer 34B formed on the sub-surface (S) of the insulating substrate. The main surface and the sub surface are opposing surfaces. The through hole (opening) 20 penetrates the insulating base material. Furthermore, the core substrate has a through-hole conductor 36 that connects the first conductor layer and the second conductor layer. The first surface (FF) of the core substrate is the upper surface of the first conductor layer, and the second surface (SS) of the core substrate is the upper surface of the second conductor layer. A heat dissipation block 80 is accommodated in the through hole 20 formed in the core substrate. The heat dissipation block has a main surface and a sub surface opposite to the main surface. A via conductor 60M is connected to the main surface of the heat dissipation block, and a via conductor 60D is connected to the sub surface.

The through hole 20 is filled with a filling resin 50α. The through-hole conductor 36 is formed by filling the through-hole 31 for the through-hole conductor formed in the insulating base material with copper plating. The through hole 31 for the through-hole conductor is formed by a first opening 31a formed on the main surface side of the insulating base material and a second opening 31b formed on the sub surface side of the insulating base material. Has been. The first opening 31a tapers from the main surface toward the sub surface. The second opening 28a tapers from the sub surface toward the main surface. The first opening 31a and the second opening 31b are connected inside the core substrate.

An upper buildup layer is formed on the main surface F of the insulating base material 30M, the first conductor layer, and the main surface of the heat dissipation block. The upper buildup layer is a single layer, and is formed of via conductors 60A and 60M that connect the insulating layer 50A and a conductor layer different from the conductor layer 58A on the insulating layer and penetrate the insulating layer 50A. In FIG. 6, the via conductor 60 </ b> A connects the conductor layer 34 </ b> A of the core substrate to the conductor layer 58 </ b> A on the insulating layer and the through-hole conductor and the conductor layer 58 </ b> A formed on the insulating layer. The via conductor (upper connection via conductor) 60M connects the main surface of the heat dissipation block (heat dissipation block) and the conductor layer 58A.

A lower buildup layer is formed on the sub surface S of the insulating base material 30M, the second conductor layer, and the sub surface of the heat dissipation block. The lower buildup layer is a single layer, and is formed of via conductors 60B and 60D that connect the insulating layer 50B and a conductive layer different from the conductive layer 58B on the insulating layer and penetrate the insulating layer 50B. In FIG. 6, the via conductor 60B connects the conductor layer 34B of the core substrate and the conductor layer 58B on the insulating layer, and the through-hole conductor and the conductor layer 58B formed on the insulating layer. A via conductor (lower connection via conductor) 60D connects the sub-surface of the heat dissipation block (heat dissipation block) and the conductor layer 58B.

Solder resist layers 70 having openings 71 exposing the conductor layers 58A and 58B, the via conductors, and the connection via conductors are formed on the upper and lower buildup layers. Solder bumps 76U and 76D are formed on the conductor (pad) exposed from the opening 71.
The solder resist layer on the upper buildup layer has a region for mounting an IC chip. As shown in FIG. 7, the IC chip 90 is mounted on a printed wiring board by being connected to pads 92 of the IC chip 90 via solder bumps 76U formed on the upper buildup layer. The printed wiring board 100 is mounted on the motherboard 98 by being connected to the pads 96 of the motherboard via solder bumps 76D formed on the lower buildup layer.

Since the printed wiring board of the first embodiment includes the heat dissipation block 80 in the through hole 20 of the core substrate 30, the heat dissipation in the vertical direction is high, and the heat of the mounted IC chip 90 is efficiently transferred to the mounted motherboard 98 side. Can be escaped. Since the copper heat dissipation block is accommodated only in the through hole 20, the copper occupation ratio of the entire printed wiring board is low, and the buildup layer in which the resin insulating layers and the conductor layers are alternately stacked hardly warps.

Here, the thickness of the core substrate is 70 to 250 μm. The thickness of the heat dissipation block is preferably equal to or less than the core substrate, and the volume is preferably 0.2 mm 3 or more and 0.4 mm 3 or less. If the volume is less than 0.2 mm 3, the heat dissipation is reduced. On the other hand, if it exceeds 0.4 mm 3, there is a possibility of causing warpage due to the difference in thermal expansion coefficient with the core substrate.

The via conductor 60M on the main surface side and the via conductor 60D on the sub surface side connected to the heat dissipation block constitute a ground line. This increases the capacity of the ground line as well as heat dissipation, and stabilizes the power supply to the IC chip.

The number of via conductors 60M on the main surface side is larger than the number of via conductors 60D on the sub surface side. Heat dissipation is enhanced by increasing the number of via conductors 60M on the IC chip side that are heat sources.

A method of manufacturing the printed wiring board 100 of the first embodiment is shown in FIGS.
(1) A copper-clad laminate 20M in which a 15 μm copper foil 32 is laminated on both surfaces of an insulating base material 30M made of a reinforcing material such as epoxy resin or BT (bismaleimide triazine) resin and glass cloth is a starting material. . The insulating base material 30M has a main surface and a sub surface opposite to the main surface, and the thickness thereof is 70 to 250 μm. If it is thinner than 70 μm, the strength of the insulating substrate is too low. When the thickness exceeds 250 μm, it becomes difficult to sandwich the heat dissipation block with via conductors. In addition, it is difficult to form a through hole for a tapered through-hole conductor by laser. First, a blackening process is performed on the surface of the copper foil 32 (FIG. 1A).

(2) The CO2 laser is irradiated from the main surface F side of the insulating base material 30M, and the first opening 31a that is narrowed from the main surface toward the sub surface S is formed on the main surface F side (FIG. 1). (B)). The first opening 31 a is tapered from the main surface F toward the sub surface S.

(3) The CO2 laser is irradiated from the sub surface S side of the insulating base material 30M, and the second opening 31b that is narrowed from the sub surface toward the main surface F is formed on the sub surface S side. A through hole 31 for a through hole conductor is formed by the first opening and the second opening (FIG. 1C). The second opening 31 b is tapered from the sub surface S toward the main surface F.

(4) The electroless plating film 33 is formed on the inner wall of the through hole and the copper foil 32 by the electroless plating process (FIG. 1D). Furthermore, an electrolytic plating film 37 is formed on the electroless plating film 33 by electrolytic plating treatment, and a through-hole conductor 36 is formed in the through hole. The through hole 31 is filled with an electrolytic plating film. A through-hole conductor 36 made of a plating film filling the through-hole is formed (FIG. 1E).

(5) An etching resist 35 having a predetermined pattern is formed on the electrolytic plating film 37 on the insulating substrate 30M (FIG. 1F).

(6) The electrolytic plating film 37, the electroless plating film 33, and the copper foil 32 exposed from the etching resist are removed. Thereafter, the etching resist is removed to form conductor layers 34A and 34B and a through-hole conductor 36 (FIG. 2A). The conductor layers 34A and 34B include conductor circuits and lands of through-hole conductors.

(7) A through-hole (opening) 20 for accommodating a heat dissipation block such as a capacitor is formed in the center of the insulating base material 30M by a laser. The core substrate 30 is completed (FIG. 2B).

(8) The tape 94 made of a PET film is attached to the first surface FF of the core substrate so that the through-hole 20 is closed (FIG. 2C).

(9) The heat dissipation block 80 is mounted by a mounter from the second surface side of the core substrate (FIG. 2D). Here, a resin film can be formed on the tape 94 exposed by the through-hole 20, and the heat dissipation block can be fixed on the resin film.

(10) A resin film 50b such as a B-stage prepreg and a copper foil 49 are laminated on the second surface SS of the core substrate 30 so as to close the through hole 20 (FIG. 2E). By the heat press, the resin and the inorganic particles ooze out from the resin film 50b into the through hole 20, and the through hole 20 is filled with the resin 50α. The resin film 50b includes a resin and inorganic particles such as silica. The resin film may or may not contain a reinforcing material such as glass cloth in addition to the inorganic particles. When the resin film includes a reinforcing material, the thermal expansion coefficient of the insulating layer and the thermal expansion coefficient of the heat dissipation block are close to each other. When the resin film does not include a reinforcing material, damage to the heat dissipation block due to the heating press can be reduced.

The first filling resin 50α is formed in the through hole 20 by curing the resin filling the through hole and the resin film, and the sub surface of the insulating substrate, the second conductor layer, and the heat dissipation block. An insulating layer 50B is formed thereon. The insulating layer 50B is an interlayer resin insulating layer of the lower buildup layer.

(11) After removing the tape (FIG. 3A), a resin film such as a B-stage prepreg and a copper foil 49 are laminated on the first surface FF of the core substrate 30. By curing the resin of the resin film, an insulating layer 50A is formed on the main surface of the insulating base, the first conductor layer, and the heat dissipation block from the resin film (FIG. 3B). The insulating layer 50A is an interlayer resin insulating layer of the upper buildup layer.

(12) An opening 51A reaching the main surface of the heat dissipation block is formed in the insulating layer 50A. In addition, an opening 51 reaching the conductor layer and the through-hole conductor is formed. An opening 51B reaching the heat radiation block sub-surface is formed in the insulating layer 50B. In addition, an opening 51 reaching the conductor layer and the through-hole conductor is formed (see FIG. 3C). The inside of the openings 51, 51A, 51B is cleaned with an oxidizing agent such as permanganate. In addition, rough surfaces are provided on the surfaces of the insulating layers 50A and 50B (not shown).

(13) Electroless plating film 52 is formed on the surfaces of insulating layers 50A and 50B and the inner walls of openings 51, 51A and 51B (FIG. 3D).

(14) A plating resist 54 is formed on the electroless plating film 52 (FIG. 4A).

(15) Next, an electrolytic plating film 56 is formed on the electroless plating film exposed from the plating resist 54 by electrolytic plating (see FIG. 4B).

(16) Thereafter, the plating resist 54 is removed with 5% NaOH. The electroless plating film between the electroplating films is removed, and the conductor layer 58 (58A, 58B) and the via conductors 60A and 60B, the upper via conductor 60M, and the lower via formed by the electroless plating film 52 and the electrolytic plating film 56 are removed. A conductor 60D is formed (FIG. 4C). The conductor layer 58 includes lands of conductor circuits and via conductors.
An upper buildup layer and a lower buildup layer formed by the insulating layer, the conductive layer 58 on the insulating layer, and via conductors that penetrate the insulating layer and connect different conductive layers are formed. The upper buildup layer is formed on the main surface of the insulating base material, and the lower buildup layer is formed on the sub surface of the insulating base material.

(17) A solder resist layer 70 having an opening 71 is formed on the upper and lower buildup layers. The printed wiring board 100 is completed (FIG. 5A). The conductor layer or via conductor exposed from the opening 71 functions as a pad. The solder resist on the upper buildup layer is the upper solder resist layer, and the solder resist on the lower buildup layer is the lower solder resist layer.

(18) A metal film is formed on the pad in the order of the nickel layer 72 and the gold layer 74 (FIG. 5B). Examples of other metal films include tin and Ni / Pd / Au.

(19) Thereafter, solder bumps 76U are formed on the pads exposed from the openings 71 of the upper solder resist layer. A solder bump 76D is formed on the pad exposed from the opening 71 of the lower solder resist layer. A printed wiring board 100 having solder bumps is completed (FIG. 6).

The IC chip 90 is mounted on the printed wiring board 100 via the solder bumps 76U on the upper buildup layer. Then, the printed wiring board 100 is mounted on the motherboard (FIG. 7).

[Second Embodiment]
FIG. 8 shows a cross section of the printed wiring board of the second embodiment.
The printed wiring board of the second embodiment includes a through hole 20A for housing the heat dissipation block 80A and a through hole 20B for housing an electronic component 80B such as a chip capacitor. In the second embodiment, heat dissipation can be improved while reducing the distance between the electronic component and the IC chip.

[First Modification of Second Embodiment]
FIG. 9 shows a cross section of a printed wiring board according to a first modification of the second embodiment.
The printed wiring board according to the first modification of the second embodiment includes a through hole 20A for housing the heat dissipation block 80A and a through hole 20B for housing the chip capacitor 80B. The negative terminal 80BT of the chip capacitor and the heat dissipation block 80A are simultaneously connected via the ground line 58AL on the insulating layer 50A and the ground line 58BL on the insulating layer 50B. In the first modification of the second embodiment, the ground line to the IC chip can be strengthened together with the chip capacitor.

[Second Modification of Second Embodiment]
FIG. 10 shows a plan view of a printed wiring board according to a second modification of the second embodiment.
In the printed wiring board according to the second modified example of the second embodiment, the through hole 20B for accommodating the electronic component 80B such as a chip capacitor is disposed in the center, and the through holes 20A for accommodating the heat dissipation block 80A are provided at the four corners. Be placed. In the second modification of the second embodiment, heat from the IC chip can be evenly conducted to the external connection substrate side.

In the above-described embodiment, an example in which one build-up layer of the core substrate is provided is illustrated. However, the configuration of the present invention is also applicable when a plurality of build-up layers are provided.

20 Through hole 30 Core substrate 34A, 34B Conductor layer 50A, 50B Insulating layer 58A Conductor layer 60A, 60B, 60M, 60D Via conductor 80, 80A Heat dissipation block

Claims (7)

A core substrate having a first surface and a second surface opposite to the first surface;
A through hole conductor formed by filling a through hole for a through hole conductor penetrating the core substrate from the first surface to the second surface direction with copper plating;
A through hole penetrating the core substrate from the first surface to the second surface direction;
A heat dissipating member accommodated in the through hole;
A printed wiring board comprising a wiring laminated portion in which resin insulating layers and conductor layers are alternately laminated on the core substrate:
The heat dissipating member is disposed in a region immediately below the chip on which the printed wiring board is mounted, and via conductors are connected to both the front and back surfaces of the heat dissipating member,
The through-hole conductor is disposed in a region immediately below a chip on which a printed wiring board is mounted, and via conductors are connected to the first surface side and the second surface side of the through-hole conductor ,
An electronic component is accommodated in a through hole adjacent to the through hole in which the heat dissipation member is accommodated. The printed wiring board of claim 1, wherein:
The heat dissipation member is a rectangular copper block. The printed wiring board of claim 1, wherein:
The volume of the heat radiating member is 0.2 mm 3 or more and 0.4 mm 3 or less. The printed wiring board of claim 1, wherein:
The via conductor connected to the heat radiating member constitutes a ground line. The printed wiring board of claim 1, wherein:
The number of via conductors connected to the heat dissipation member is greater on the chip side surface than on the external connection substrate side surface. A core substrate having a first surface and a second surface opposite to the first surface;
A through hole conductor formed by filling a through hole for a through hole conductor penetrating the core substrate from the first surface to the second surface direction with copper plating;
A through hole penetrating the core substrate from the first surface to the second surface direction;
A heat dissipating member accommodated in the through hole;
A printed wiring board comprising a wiring laminated portion in which resin insulating layers and conductor layers are alternately laminated on the core substrate:
The heat dissipating member is disposed in a region immediately below the chip on which the printed wiring board is mounted, and via conductors are connected to both the front and back surfaces of the heat dissipating member,
The through-hole conductor is disposed in a region immediately below a chip on which a printed wiring board is mounted, and via conductors are connected to the first surface side and the second surface side of the through-hole conductor,
A heat dissipation block is accommodated in a through hole adjacent to the through hole in which the heat dissipation member is accommodated. The printed wiring board according to claim 6,
The heat dissipating block adjacent to the heat dissipating member is externally connected to the conductor layer on the chip-side surface via a via conductor connected to the heat dissipating member and a via conductor connected to the heat dissipating block. The front and back are connected by the conductor layer on the surface on the substrate side.

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