JP5980661B2 - Semiconductor integrated circuit identification method and identification apparatus - Google Patents

Description

  The present invention relates to a method for identifying a semiconductor integrated circuit.

  Reducing the incidence of defective products in the manufacturing process of semiconductor integrated circuits, that is, improving the yield is one of the important issues for semiconductor manufacturers. In order to improve the yield, the cause of the defect is clarified based on the history information such as the manufacturing history of each semiconductor integrated circuit, the manufacturing history such as the manufacturing line and the manufacturing lot, and the inspection history such as the inspection type and the inspection result. It is desirable.

  As one of means for specifying such history information, each semiconductor integrated circuit is given an identifier for distinguishing the semiconductor integrated circuit from other semiconductor integrated circuits, and the history information of the semiconductor integrated circuit is obtained. It is possible to manage on the database in association with the identifier.

  Assigning an identifier to each semiconductor integrated circuit has the advantage of not only improving the yield, but also helping to quickly identify and analyze a defective part even when a defect is discovered after manufacturing.

  Conventionally, as a method for assigning an identifier to a semiconductor integrated circuit, a method of providing a nonvolatile memory in the semiconductor integrated circuit and writing the identifier in the nonvolatile memory has been known. However, since the process of creating a nonvolatile memory inside a semiconductor integrated circuit is generally complicated, there arises a problem that the number of processes and manufacturing cost increase.

  As another method, a method of directly marking a semiconductor integrated circuit with a laser, a method of cutting a fuse using a laser, and the like have been known. However, a separate process for marking and cutting the fuse is required. Therefore, there arises a problem that the number of steps and the manufacturing cost increase as in the above method.

  Patent Document 1 discloses a configuration for generating an identifier to be assigned to each of a plurality of semiconductor integrated circuits based on an analog signal output from the semiconductor integrated circuit under the same conditions in order to improve the above problem. Has been.

JP 2011-9691 A (published January 13, 2011)

  With recent progress in the manufacturing process of semiconductor integrated circuits, there is a demand for more efficiently specifying the cause of defective products in the manufacturing process of semiconductor integrated circuits.

  The present invention has been made on the basis of the inventor's knowledge in view of the above problems, and its main purpose is identification that contributes to more efficient identification of the cause of defective products in the manufacturing process of a semiconductor integrated circuit. Implementing a method and identification device.

In order to solve the above-described problem, an identification method according to an aspect of the present invention is a semiconductor integrated circuit identification method for identifying a plurality of semiconductor integrated circuits having the same configuration in a wafer state from each other. 1 is generated for each semiconductor integrated circuit in a wafer state, and a first generation step of generating one identifier based on each value of input / output signals for a plurality of predetermined internal states of each semiconductor integrated circuit A management step of managing the first identifier in association with position information indicating the position of the semiconductor integrated circuit on the wafer; and a single piece state in which the plurality of semiconductor integrated circuits are cut out from the wafer. A second identifier for identifying the semiconductor integrated circuit from other semiconductor integrated circuits in the individual piece state is the plurality of predetermined internal states of the certain semiconductor integrated circuit. A second generation step that is generated based on each value of the input / output signal and the second identifier generated for the semiconductor integrated circuit is identified and identified as one of the first identifiers And a specifying step of specifying the position information associated with the first identifier.

An identification apparatus according to an aspect of the present invention is an identification apparatus for identifying a semiconductor integrated circuit, and includes a first identifier for identifying a plurality of semiconductor integrated circuits having the same configuration in a wafer state, First generation means for generating based on each value of input / output signals for a plurality of predetermined internal states of each semiconductor integrated circuit, and a first identifier generated for each semiconductor integrated circuit in the wafer state Management means for managing the semiconductor integrated circuit in association with position information indicating the position of the semiconductor integrated circuit on the wafer ; and a semiconductor integrated circuit in a single piece state in which the plurality of semiconductor integrated circuits are cut out from the wafer . Input / output with respect to the plurality of predetermined internal states of the certain semiconductor integrated circuit as a second identifier for identifying from another semiconductor integrated circuit in the individual state Second generation means for generating based on each value of the signal, and the second identifier generated for the semiconductor integrated circuit identified as one of the first identifiers, And a specifying unit that specifies the position information associated with the identifier.

  The above identification method and identification apparatus contribute to more efficient identification of the cause of defective products in the manufacturing process of a semiconductor integrated circuit.

1 is a block diagram illustrating a configuration of an identification device according to an embodiment of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates an embodiment of the present invention and is an explanatory diagram relating to an identifier generation method using variations in power supply current. 1 is a block diagram showing a configuration of a liquid crystal driver, showing a semiconductor integrated circuit to which an identifier is to be assigned in an embodiment of the present invention. FIG. 1 is a circuit diagram of a reference power supply circuit having a gamma resistance in a liquid crystal driver, showing a semiconductor integrated circuit to which an identifier is to be assigned in an embodiment of the present invention. 4 is a graph for explaining an embodiment of the present invention and showing a value of an output voltage from a liquid crystal driver. 4 is a graph for explaining an embodiment of the present invention and showing a value of a gradation output voltage output from a liquid crystal driver. FIG. 4 is a graph for explaining the embodiment of the present invention and shows a power supply current value for each state of the same liquid crystal driver. 1 is a circuit diagram of a reference power supply circuit having a gamma resistance in a dot inversion type liquid crystal driver, showing a semiconductor integrated circuit to which an identifier is to be assigned in an embodiment of the present invention. FIG. 5 is a diagram illustrating an embodiment of the present invention, and is a diagram illustrating a state of a liquid crystal driver when measuring a power supply current value for generating an identifier using a variation in power supply current. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1, showing an embodiment of the present invention, is a block diagram showing a configuration of an identification system including an identification device and a database, together with information stored in the database. FIG. 11 illustrates an embodiment of the present invention, and is a conceptual diagram illustrating processing for creating a wafer map using a trace result by the identification system illustrated in FIG. 10.

(Identifier generation method)
A method for identifying a semiconductor integrated circuit according to an embodiment of the present invention will be described below with reference to the drawings.

  First, FIG. 3 shows a block diagram of a liquid crystal driver having an analog output function as an example of a semiconductor integrated circuit to which an identifier is given when generating an identifier according to the present embodiment. The liquid crystal driver shown in FIG. 3 is a semiconductor integrated circuit for outputting a drive signal (analog signal) for driving a liquid crystal panel (not shown) of the liquid crystal display.

  In the liquid crystal driver shown in FIG. 3, the digital video input signal input to the logic unit is converted to an analog signal by the DAC unit, voltage level conversion is performed by the level shifter unit, and the output amplifier unit passes through the output level as a liquid crystal drive signal. Output from a plurality of analog output terminals. Note that the liquid crystal driver shown in FIG. 3 can output an analog signal of 256 gradations for each analog output terminal.

  FIG. 4 schematically shows a reference voltage generation circuit used for gamma correction of an analog signal in the level shifter section. A voltage is input from V0H, V1H,..., V5H, VnH, and resistance division is performed to generate a gamma characteristic.

  FIG. 5 is a graph in which output voltages output from a specific analog output terminal of a liquid crystal driver, that is, an analog output terminal having a specific terminal number, are plotted for each gradation for a certain input signal. . The liquid crystal driver outputs an output voltage corresponding to each of 256 gradations for each analog output terminal. In addition, the unit of the vertical axis | shaft of FIG. 5 is a volt | bolt (V).

  Hereinafter, a method for generating the power supply current of the liquid crystal driver shown in FIG. 3 as an identifier will be described.

  FIG. 6 is a diagram showing an output voltage (unit: volts) as a liquid crystal drive signal output from the liquid crystal driver shown in FIG. 3, that is, a gradation voltage. Output voltage value at X1 gradation (minimum gradation) from each terminal, output voltage value at X2 gradation from each terminal, output voltage value at X3 gradation from each terminal,..., Xn from each terminal It is the figure which arranged and plotted the output voltage value in a gradation, equivalent to 256 gradations in this description (maximum gradation) in order of gradation.

  FIG. 7 is a plot of power supply current values supplied to a semiconductor integrated circuit in a total of 1024 states with respect to a specific power supply terminal, and the unit of the vertical axis is μA. Details of the 1024 state will be described later.

  In general, the power supply current supplied to the semiconductor integrated circuit is not constant and varies depending on the device state. Accordingly, by plotting the power supply current value for each internal state of various devices against a specific power supply terminal, it is possible to generate an identifier using the power supply current.

  Hereinafter, an example of a specific device state will be described using the liquid crystal driver of FIG. 3 as an example.

  The liquid crystal driver sequentially samples input data corresponding to each liquid crystal system output, fetches data corresponding to the number of outputs, latches it in a data latch (not shown), and inputs it to the DAC via a level shifter.

  The DAC selects a gradation level for each output, and outputs each gradation level generated by a reference voltage generation circuit (gamma resistor) via an operational amplifier provided for each output.

  The driving method of the liquid crystal driver at this time is a dot inversion driving method in which adjacent liquid crystal system outputs are inverted to a VH side level and a VL side level, and a line inversion driving method in which the same level is output when the same gradation level is selected. It is roughly divided into two. Although detailed description of dot inversion drive and line inversion drive is omitted, the following description assumes a dot inversion drive driver. FIG. 8 shows a gamma resistance circuit of a dot inversion drive driver.

  With respect to the above-described input data, it is possible to display 64 gradations in the case of 6-bit DAC, 256 gradations in the case of 8-bit DAC, and 1024 gradations in the case of 10-bit DAC. In the case of a liquid crystal driver with 256 gradations, there are states for outputting 256 kinds of gradation voltages.

Here, as the state of the LCD driver,
State 1) State before the liquid crystal driver captures data 2) State when the liquid crystal driver captures data 3) State when the liquid crystal driver is latching 4) According to the data captured by the liquid crystal driver The 1024 states are set by combining the four static states in which the output voltage is output and 256 ways of input data (gradation). Here, static means that the signal is stopped by setting the input signals CK, RGB input, LS to VDD level or GND level, and the current that always flows in the analog circuit is cut off so that the liquid crystal driver does not operate. is there. Hereinafter, the four static states will be described with reference to FIG.

  FIG. 9 is a diagram showing four states of the liquid crystal driver when measuring a power supply current value for generating an identifier using a variation in power supply current. As shown in FIG. 9, the liquid crystal driver has an operation clock that repeats ON / OFF at a constant cycle. As shown in FIG. 9, the liquid crystal driver receives from the tester a start signal indicating that the measurement of the power supply current value is started at the timing of the operation clock. The state at this point is a state before the liquid crystal driver takes in the input data, and is the state 1 described above. After receiving the start signal from the tester, the liquid crystal driver starts to take in input data having any gradation. The state at this point is a state in which the liquid crystal driver is taking in input data, which is state 2 described above. Subsequently, when the input of the input data is completed, the liquid crystal driver performs a latch operation indicating that data is latched in the data latch based on the latch signal. The state at this point is a state in which the liquid crystal driver is performing a latch operation, and is state 3 described above. Subsequently, the liquid crystal driver outputs an output voltage corresponding to the fetched data. The state at this point is a state in which the liquid crystal driver outputs an output voltage, which is state 4 described above. In the present embodiment, power supply current values for these four states are measured.

  Hereinafter, the 1024 states determined by the above four static states and 256 patterns of input data (gradation) are referred to as internal states of the liquid crystal driver.

  The internal state of the liquid crystal driver is set by an apparatus (tester) that measures a semiconductor device. Since the tester can accurately control the timing of the input signal, the current measurement timing, etc., the internal transistor of the liquid crystal driver to be measured can be set to the same internal state for each measurement.

  In each internal state, the power supply current value is measured, and each power supply current value is associated with 0011, 0012, 0013, 0014,... As internal state identification numbers (also called numbers) indicating the internal state. . The number associated here is a number composed of a three-digit number indicating any gradation of the input data and a one-digit number indicating one of the static states. For example, 0011 represents the first state of one gradation, 0012 represents the second state of one gradation, 0013 represents the third state of one gradation, and 0014 represents the fourth state of the first gradation. Yes. In the example shown in FIG. 9, input data indicating 134 gradations is used, and 1341, 1342, 1343, and 1344 are associated with the power supply current values measured in states 1 to 4, respectively.

  Hereinafter, a more specific description will be given with reference to FIG.

  FIG. 2 shows an embodiment of the present invention and is an explanatory diagram related to an identifier generation method. The upper part of FIG. 2A shows an example of a graph in which the power supply current value in the 1024 state of the liquid crystal driver in the wafer state is measured, and the unit of the vertical axis is μA. As shown in the lower part of FIG. 2A, for each of the measured power supply current values of 1024 states, as internal state identification numbers that are numbers for identifying the internal state of the liquid crystal driver at the time of measurement, 0011, 0012, Are associated with each other.

  The number associated here is a number composed of a three-digit number indicating any gradation of the input data and a one-digit number indicating one of the static states. For example, 0011 represents the first state of one gradation, 0012 represents the second state of one gradation, 0013 represents the third state of one gradation, and 0014 represents the fourth state of the first gradation. Similarly, the second and subsequent gradations are associated as 0021, 0022, 0023, 0024,. For example, in the example shown in the lower part of FIG. 2A, 0011 = 0.822 μA, 0012 = 0.721 μA, 0013 = 0.799 μA, and 0014 = 0.824 μA.

  By measuring the power supply current values in the four static states at all the gradations, power supply current data indicating the power supply current values for 1024 states of 256 gradations × 4 states can be collected. The collected power supply current data may be used as an identifier, but in the present embodiment, an identification number list (0011, 0012, 0013, 0014, 0021, 0022,...) Indicating an internal identification number corresponding to the measured power supply current value. .., 2561, 2562, 2563, 2564) are used as identifiers.

  The respective power supply current values in the measured 1024 states are compared, and in the order of increasing power supply current values (in the example shown in FIG. 2A, 1463 → 2273 → 2263 → 0862...) And the rearranged identification number list as the identifier of the semiconductor integrated circuit.

  This identifier hardly changes even if the temperature condition or measurement condition changes in the wafer state or the individual state. For example, when the power source current value of the wafer state device measured at room temperature is 1.2 μA and the power source current value of the individual device is measured at high temperature, the characteristics of the semiconductor integrated circuit The current value is shifted to 2.4 μA corresponding to the temperature shift. In this embodiment, the measurement value itself is not used as an identifier, and the identification number list rearranged in a state with a large current value and a state with a small current value is used as an identifier, so that the influence of the measurement environment can be reduced.

  The upper part of FIG. 2B shows an example of a graph obtained by measuring the power supply current value in the 1024 state of the liquid crystal driver in the individual state, and the unit of the vertical axis is μA. As shown in the lower part of FIG. 2B, as with the identifier generation in the wafer state, the internal state identification numbers 0011, 0012, 0013, 0014,. , Respectively.

  For example, the power supply current value of the number 0011 in the wafer state shown in FIG. 2A is 0.822 μA, while the number 0011 in the individual state is shown in the lower part of FIG. The power supply current value is 0.832 μA. In all of the numbers 0012, 0013, and 0014, the power supply current value is shifted. As described above, the power supply current value of the liquid crystal device fluctuates due to changes in temperature conditions and measurement conditions. Therefore, when the power supply current value itself is used as an identifier, the individual state device and the wafer state device are linked. It may happen that is not done correctly.

  Therefore, by using this identifier created based on the magnitude relationship of current values as described below, it becomes possible to link a device in the individual state and a device in the wafer state.

  Specifically, the lower part of FIG. 2B shows an example of an identification number list in which the power supply current values in the 1024 states in the individual state are compared and rearranged in order of the power supply current values. . The wafer number identification number list shown in the lower part of FIG. 2A is 1463, 2273, 2263, 0862,... In order from the top, whereas the list shown in FIG. The one-state identification number list is in the order of 1463, 2273, 2263, 1011,. Similarly, the wafer state identification number list shown in FIG. 2 (a) is 2422, 2412, 1984, 1763,... In order from the bottom, whereas the individual state shown in FIG. The identification number list is in the order of 2422, 2103, 1984, 1763,.

  Although it is desirable that all the magnitude relations of the power supply current values corresponding to the respective internal state identification numbers match, in the example shown in FIGS. 2A and 2B, the measurement of the power supply current value in each state is performed. Since the value difference is a minimum value of about 0.001 μA, the magnitude relationship may be switched depending on the current measurement accuracy. In consideration of this point, the identifier of the wafer state and the identifier in the individual piece state are compared, and if the matching rate is equal to or higher than a predetermined threshold (for example, 85% or more), the individual state device and the wafer It is preferably possible to distinguish the device from the state. Note that the threshold value of the coincidence rate can be determined statistically by collecting the identifiers of the identified wafer state devices and the individual state device identifiers.

  Furthermore, the power supply current values of the measured 1024 states are compared, and the identification number list is rearranged in order of the power supply current values. Further, in the rearranged identification number list, the power supply current values from 1 to Nth (N is a natural number of 1024 or less) are increased, and the power supply current values from 1 to Nth are also reduced. Create a list of identification numbers. An identifier of each semiconductor integrated circuit is generated based on the created identification number list.

  By using this identifier, it is possible to identify the semiconductor integrated circuit by comparing the identifier in the wafer state with the identifier in the individual piece state.

  The number N used as an identifier is determined based on the match rate. For example, the coincidence rate and the necessary value of N are calculated statistically by stacking data. If the match rate is high, N can be set small.

  The specific value of N is not limited to the present embodiment, but for example, N = 30, N = 50, and the like can be taken as typical values.

  In Patent Document 1, for example, a liquid crystal driver is characterized by an output voltage value for each output terminal having several hundred to 1000 pins or more and a current value variation for each internal state, which are used as identifiers. In the method of Patent Document 1, the amount of data is enormous for analyzing and identifying the output voltage value for each output terminal having several hundred to more than 1000 pins used as each identifier, and it is necessary to analyze the enormous data. This can increase the time required for identification.

  According to the identifier generation method of the present invention, since the power supply current value of the semiconductor integrated circuit is used as an identifier without increasing the chip area, the data collection time is suppressed along with the data amount, and the identification is performed with high efficiency. Can do.

  In the present embodiment, the variation of the power supply current value in the internal state of the 1024 states (256 gradations × 4 states) of the liquid crystal driver is used, but the power supply current values in various states of the internal circuit are used. It is also possible.

  For example, a 256 state in which 256 grayscale input data is input in the state 1 of the liquid crystal driver (the state before the liquid crystal driver takes in data) may be defined as an internal state, and the power supply current value in each state may be measured. For example, any one of four static states is selected, and power supply current data for 256 states of 256 gradations × 1 state is collected. The measured power supply current values in the 256 states are compared, the identification number list is rearranged in order of increasing or decreasing power supply current value, and the rearranged identification number list is used as the identifier of the semiconductor integrated circuit. In this case, since it is possible to save the trouble of setting each of the four states using a tester, the time required for measuring the power supply current value can be shortened.

  Further, identifiers may be generated based on an identification number list in which M (M is a natural number of 256 or less) in order of increasing power supply current value and M in order of decreasing power among the 256 states.

  The number M used as an identifier in this case can also be determined by the matching rate. The match rate and the required value of M are calculated statistically by stacking the data. If the match rate is high, M can be set small.

  In this case, the time required for performing identification using the identifier generated by the above procedure can be further shortened.

  Also, instead of associating an internal state identification number with each of the measured power supply current values of 1024 states, the difference between the power supply current values from the liquid crystal driver placed under two predetermined conditions in the non-operating state An identification number may be associated with. For example, the difference between the power supply current value when the input data of gradation 001 in state 1 is input and the power supply current value when the input data of gradation 001 in state 2 is input is obtained, and the identification number 0011 is associated. Similarly, the difference between the power supply current value in state 1 and the power supply current value in state 2 when the input data of each gradation is input is obtained, respectively, and identification numbers 0021, 0031,..., 2541, 2551, 2561 are sequentially assigned. Associate. The obtained 256 difference values may be compared to create an identification number list in which the identification numbers are rearranged in order of increasing or decreasing difference values, and this identification number list may be used as an identifier. Furthermore, among the rearranged identification number lists, L (L is a natural number of 256 or less) in the descending order of difference values and L identification number lists rearranged in the smaller order may be used as identifiers.

  The number L used as an identifier in this case can also be determined by the matching rate. The coincidence rate and the required L value are calculated statistically by stacking data. If the matching rate is high, L can be set small.

  In this case, since the identifier is generated based on the difference between the power supply current values in the two states, it is possible to generate a more reliable identifier.

  In the present embodiment, a four-digit number is used as the internal state identification number, but this does not limit the present invention. That is, it is only necessary to identify the internal state of the semiconductor integrated circuit in the non-operating state, and a character string and a combination of a number and a character string may be used. For example, by expressing a 3-digit number indicating input data of 256 gradations in hexadecimal and using 2 digits, the number of digits of the internal state identification number can be reduced, and the data amount of the identifier can be reduced. .

  In the present embodiment, the case where the power supply current values for a plurality of predetermined internal states in the non-operating state of the semiconductor integrated circuit are used as identifiers is described. However, this does not limit the present invention. Alternatively, the variation between the output terminals of the analog voltage for each gradation may be used as the identifier.

  In the above example, a liquid crystal driver has been described as an example of a semiconductor integrated circuit. However, the present invention is not limited to this and can be applied to a semiconductor integrated circuit other than a liquid crystal driver. It is.

(About the trace method)
Hereinafter, the semiconductor integrated circuit is identified using the identifier of the semiconductor integrated circuit generated by the method described above with reference to FIG. 10, and the position of the identified semiconductor integrated circuit on the wafer is determined. A method for specifying the indicated chip position information will be described. In this embodiment, specifying the chip position information indicating the position of the identified semiconductor integrated circuit on the wafer in the wafer state is expressed as “trace”, but will be described below. In addition, further specifying other data (for example, test data and wafer number) managed in association with the chip position information may be expressed as “trace”. Details of the “chip position information” will be described later.

  FIG. 10 is a block diagram showing the configuration of the identification system including the identification device 1 and the database 50 together with information stored in the database. As shown in FIG. 10, the above tracing method is realized by using, for example, the identification device 1 and the database 50. Details of the identification device 1 will be described later.

  In general, an electrical test (wafer test, final test) is performed by a tester in order to determine whether a semiconductor integrated circuit in a wafer state or an individual state satisfies a predetermined specification as a product. Note that various measurement data such as a power supply current value group and an analog voltage value group used for generating the identifier are included in the test data which is data acquired by this electrical test.

  First, an electrical test of the semiconductor integrated circuit in the wafer state is performed using a tester, and test data (test data W11 in FIG. 10) of the wafer state of the semiconductor integrated circuit is obtained. The identification device 1 generates an identifier (identifier W12 in FIG. 10) of the semiconductor integrated circuit using the power supply current value group included in the acquired test data (corresponding to the first generation step). Further, when performing the electrical test, the identification device 1 generates chip information (chip information W13 in FIG. 10) corresponding to the semiconductor integrated circuit to be tested. Here, the chip information refers to chip position information (history indicating a wafer lot acquisition route, etc., a wafer number assigned to the wafer from which the semiconductor integrated circuit is cut out, and a coordinate position of the semiconductor integrated circuit on the wafer. (Chip coordinates shown) and measurement data (electrical characteristic data, etc.) of the semiconductor integrated circuit. The wafer number is a unique number assigned to identify the wafer and other wafers in the wafer lot to which the wafer belongs. The identification device 1 associates the test data of the semiconductor integrated circuit acquired by the electrical test, the generated identifier of the semiconductor integrated circuit, and the generated chip information corresponding to the semiconductor integrated circuit with each other. Remember me.

  The database includes information on a plurality of wafer lots (lot number, wafer production manufacturer, date of purchase, etc.), and processing history for each of the plurality of wafers (production factory, equipment used, date of execution of each processing step, etc.). Stored in advance. The identification device 1 includes the test data, the identifier of the semiconductor integrated circuit, chip information corresponding to the semiconductor integrated circuit, and wafer lot information corresponding to the semiconductor integrated circuit (wafer lot information W14 in FIG. 10). And the wafer processing history (wafer processing history W15 in FIG. 10) are stored in the database in association with each other. The identification device 1 manages the associated information as wafer information (wafer information 1 in FIG. 10) of the semiconductor integrated circuit in the wafer state.

  As shown in FIG. 10, the identification apparatus 1 repeats the above procedure to thereby obtain a plurality of pieces of wafer information corresponding to each of a plurality of semiconductor integrated circuits in a wafer state (wafer information 1, wafer information 2, wafers in FIG. 10). The information 3,... Is accumulated in the database (corresponding to the management process).

  The wafer-state semiconductor integrated circuit in which the wafer information is stored in the database is cut out from the wafer and becomes a single-piece semiconductor integrated circuit.

  Next, the identification device 1 performs an electrical test on the semiconductor integrated circuit in the individual piece state, and acquires test data on the individual piece state of the semiconductor integrated circuit (test data P11 in FIG. 10). The identification device 1 generates an identifier (identifier P12 in FIG. 10) of the semiconductor integrated circuit using the power supply current value group included in the acquired test data (corresponding to the second generation step). Further, the identification device 1 associates the test data of the semiconductor integrated circuit acquired by the electrical test with the generated identifier of the semiconductor integrated circuit. Furthermore, the identification device 1 stores the associated information in the database as individual piece information (individual piece information 1 in FIG. 10) of the semiconductor integrated circuit in the individual piece state.

  Using the above-described identification method, the identification device 1 uses any one of the identifiers included in the plurality of wafer information stored in the database, and the individual piece information of the target semiconductor integrated circuit. By identifying the identifier included in the semiconductor integrated circuit, the semiconductor integrated circuit can be identified. Further, the identification device 1 identifies chip position information of the target semiconductor integrated circuit based on the chip information stored in the database in association with the identifier of the semiconductor integrated circuit in the wafer state (specifying step). ).

  As described above, the identification device 1 manages wafer lot information, wafer numbers, chip coordinates, and the like for each semiconductor integrated circuit in the database as wafer information, so that the target semiconductor integrated circuit can be selected. The chip position information indicating the position of the identified semiconductor integrated circuit on the wafer in the wafer state can be identified.

  According to the identification method of one embodiment of the present invention, an identifier can be generated using a function that has been provided in the past without using a new identifier circuit or process for a semiconductor integrated circuit. Further, as described above, the power supply current value group used when generating the identifier included in the piece information is included in the test data acquired when the electrical test is performed by the tester. Therefore, the identifier can be generated while performing an electrical test of the semiconductor integrated circuit in the individual state. Accordingly, the semiconductor integrated circuit can be identified, and the chip position information indicating the position of the identified semiconductor integrated circuit on the wafer in the wafer state can be specified more quickly, and the increase in wafer manufacturing cost can be suppressed. .

  Further, by comparing the test data of the semiconductor integrated circuit acquired in the wafer state with the test data of the semiconductor integrated circuit acquired in the individual piece state, the identification device 1 can determine whether the wafer state and the individual piece state are It is possible to detect the fluctuation amount of the measurement result of the electrical test. Therefore, the cause investigation and countermeasure when various problems such as troubles occur can be smoothly performed, and the yield can be improved.

(Wafer map creation method)
Next, referring to FIG. 11, a method for creating a wafer map that is a set of chip position information (or chip coordinates) related to one or more target semiconductor integrated circuits based on the trace result obtained by the trace method described above. explain. The wafer map indicates the position of the semiconductor integrated circuit in the individual piece state on the wafer. FIG. 11 is a conceptual diagram showing a process of creating a wafer map using the trace result by the identification system shown in FIG.

  As a specific method for creating a wafer map by the identification device 1, as shown in FIG. 11, based on chip position information traced by using the above-described tracing method, a plurality of semiconductor integrated circuits in an individual state, Then, a wafer map is created by associating one-to-one chip position information among the chip position information of a plurality of semiconductor integrated circuits in a wafer state (corresponding to a wafer map creating process).

  When various problems occur in the electrical test of the semiconductor integrated circuit in the individual state by using the wafer map, the wafer lot of the wafer to which the semiconductor integrated circuit belongs, and the wafer dependency (the problem in which wafer is manufactured from which ingot) And the presence / absence of the in-wafer tendency (where the problem is likely to occur on each wafer).

  Note that the data format of the wafer map created by the identification device 1 does not limit the present invention, and data indicating at which position on which wafer the individual semiconductor integrated circuit is produced. Any format is acceptable. For example, in order to distinguish the chip position information included in the wafer information traced based on the electrical test of the semiconductor integrated circuit in the individual piece state from other semiconductor integrated circuits given to the semiconductor integrated circuit A data format such as a data table indicating a list in which the individual identification numbers are associated with each other may be used. Further, the set of chip position information included in the wafer map may be only the chip position information related to one target semiconductor integrated circuit.

  Further, based on the chip position information traced by using the tracing method, the identification device 1 aggregates test data of a plurality of individual semiconductor integrated circuits manufactured from the same wafer, By associating test data of a plurality of semiconductor integrated circuits with chip position information, it is possible to create a wafer map to which individual piece information is further added. As a result, not only a wafer map for one-to-one association with all semiconductor integrated circuits but also, for example, a chip that fails in an individual state (a predetermined specification could not be satisfied in an electrical test) It is also possible to create a wafer map by summing up only those.

  Further, the identification device 1 aggregates test data of a plurality of individual semiconductor integrated circuits manufactured from the same wafer based on the chip position information traced using the tracing method, and The test data of the semiconductor integrated circuit in the wafer state corresponding to the plurality of semiconductor integrated circuits may be compared with the test data of the semiconductor integrated circuit in the individual piece state. By further associating the difference test data indicating the difference between the test data obtained by comparison and the chip position information, the amount of variation in the test data when the semiconductor multi-integrated circuit transitions from the wafer state to the individual state is further increased. An added wafer map can be created. For example, it is possible to create a wafer map indicating the difference between the current value in each individual state of a plurality of semiconductor integrated circuits and the current value in the wafer state.

  In the one-to-one association between the wafer state and the individual piece state of each semiconductor integrated circuit, the characteristic fluctuation amount due to the influence of the package in the individual piece state can be confirmed. In addition, if the temperature condition is different between the wafer state and the individual piece state, whether or not there is a dependency can be confirmed. Furthermore, by generating a wafer map, the presence or absence of the above-mentioned wafer lot, wafer, and wafer in-plane tendency can be confirmed in parallel. Therefore, it is possible to respond more quickly when various troubles occur, and to improve the yield.

(Examples of utilizing the wafer map)
In the following, some examples in which the created wafer map is actually used will be described.

  In the above-described tracing method, an identifier is generated using test data acquired by an electrical test (wafer test, final test) performed on a semiconductor integrated circuit in a wafer state and a piece state. Therefore, tracing can be performed while an electrical test (final test) is performed on a semiconductor integrated circuit in a single piece state, so that it can be used as follows in almost real time.

  The wafer information stored in the database includes the test data, the identifier of the semiconductor integrated circuit, the chip information corresponding to the semiconductor integrated circuit, and the wafer lot information corresponding to the semiconductor integrated circuit. Since the processing history of the wafer is associated with each other, various analyzes can be performed by referring to the created wafer map and the database.

  In the following embodiment, an example in which a liquid crystal driver is used as a semiconductor integrated circuit will be described. Most of the liquid crystal driver packages are provided in a form in which individual states are arranged on a tape. The identifier of the individual state liquid crystal driver in the state of tape (equal to several hundred to several thousand reels) and the liquid crystal in the wafer state Identifies the driver identifier. By tracing the chip position information of the identified liquid crystal driver, a wafer map can be generated. Therefore, when various troubles occur in the electrical test for the liquid crystal driver in the individual state, it is possible to check the wafer lot, wafer dependence, presence / absence of in-wafer tendency, etc., and quickly take measures to improve the yield. Can do.

(Utilization example 1)
In the individual state liquid crystal driver, there were many current failures, so when creating a wafer map, it was found that wafers with frequent current failures occurred. It was discovered that the current measurement temperature conditions are different between the electrical test in the wafer state and the electrical test in the individual state, and a wafer with frequent defects has a large current shift amount with respect to temperature. Based on the production history information, it was found that defects occurred due to variations in process conditions during production. Therefore, the management of process conditions was tightened and measures were taken to prevent defects.

(Utilization example 2)
In the individual state liquid crystal driver, there were many current failures, so when creating a wafer map, it was found that wafers with frequent current failures occurred. Since the current measurement temperature conditions are different between the electrical test in the wafer state and the electrical test in the individual state, different test specs were set. However, current defects are large from wafer lots with high current values in the wafer state. It was confirmed that a wafer was generated. Since it was found that the test spec limit product in the wafer state exceeded the spec in the electrical test in the individual state, it was possible to take measures by reviewing the test spec in the electrical test in the individual state.

(Utilization example 3)
In an electrical test for a liquid crystal driver in a single state, output delay time frequently occurs, so when a wafer map is created, variation in the wafer surface occurs, and it is biased to half of the wafer surface. I understood. A wafer in which a defect has occurred has a defect in which an exposure defect occurs and the line width of the transistor increases. Since the output load is small in the wafer state, it has been found that the failure occurs only in the individual state where the output load is large. It was possible to take measures by stopping the production equipment that caused the exposure failure.

  The above is the description of the identification method, the tracing method, and the wafer map creation method according to the present embodiment. Next, the identification device 1 according to the present invention used for actually using the identification method will be described.

[About identification device 1]
FIG. 1 shows a block diagram of an identification apparatus 1 according to this embodiment. The identification device 1 includes a DC measurement unit 11, a memory unit 12, a calculation unit 13, a comparison unit 14, and a power supply unit 15. The identification device 1 is connected to the database 50, for example. In FIG. 1, the double line indicates the path of the power supply current, and the solid line indicates the path of the signal. First, an identifier assigning process for assigning an identifier to a liquid crystal driver (semiconductor integrated circuit) to be identified will be described along a specific signal flow.

  The power supply unit 15 is means for supplying power to the semiconductor integrated circuit to be identified.

  A tester for measuring a semiconductor device is connected to the liquid crystal driver to be identified. The tester is a means for setting the state of the liquid crystal driver. Specifically, the four static states described above are set.

  The identification device 1 includes an input signal supply unit (not shown). The input signal supply unit is means for supplying 256-gradation input data to a liquid crystal driver to be identified. In the four static states set by the tester, the input signal supply unit is controlled by the tester so that the input signal of 256 gradations is input to the liquid crystal driver. In this embodiment, 1024 internal states are set by the tester and the input signal supply unit.

  In the present embodiment, the configuration in which the identification device 1 includes an input signal supply unit and input data is supplied from the input signal supply unit to the semiconductor integrated circuit will be described. However, this restricts the present invention. is not. The input signal supply unit that supplies the input data may be included in the identification device 1 or may be configured as included in another device.

  The DC measurement unit 11 is a means for measuring the power supply current supplied from the power supply unit 15 to the semiconductor integrated circuit. In particular, in the present embodiment, the DC measurement unit 11 measures a power supply current value for each of a plurality of internal states, and sequentially transmits the measured power supply current value to the memory unit 12. Further, the DC measurement unit 11 is controlled by the tester for the measurement timing of the power supply current value.

  The memory unit 12 is a means for accumulating the power supply current value for each of a plurality of internal states sent from the DC measurement unit 11 for each semiconductor integrated circuit.

  The arithmetic unit 13 is a means for generating an identifier based on power supply current values in a plurality of internal states for each semiconductor integrated circuit stored in the memory unit 12. Specifically, the arithmetic unit 13 has an internal state identification number 0011, 0012, 0013, 0014 which is a number for identifying the internal state of the liquid crystal driver for each of the 1024 state power supply current values measured by the DC measuring unit 11. , ... are associated with each other. Subsequently, the calculation unit 13 compares the power supply current values associated with the internal state identification numbers, rearranges the internal state identification numbers in order of increasing or decreasing power supply current values, and creates an identification number list. . Further, the calculation unit 13 selects the identification number list rearranged in a state where the power supply current values from 1 to Nth are large, similarly in a state where the power supply current value is small from 1 to Nth. create. The calculation unit 13 generates the created identification number list as an identifier of the semiconductor integrated circuit. The calculation unit 13 outputs the identifier generated for each semiconductor integrated circuit in this manner to the database 50.

  The database 50 is a means for associating identifiers input to each semiconductor integrated circuit with manufacturing histories, inspection histories and the like related to the semiconductor integrated circuits, and accumulating and managing the associated information.

  Specifically, the database 50 associates the input identifier with the manufacturing history and inspection history of the liquid crystal driver, and stores and manages the associated data for each liquid crystal driver.

  In the present embodiment, a configuration in which the identification device 1 is connected to the database 50 will be described, but the present invention is not limited to this. For example, the identification device 1 may be configured to include the database 50.

  As described above, by using the identification device 1 according to the present embodiment, a unique identifier can be generated for each liquid crystal driver, and by using it together with the database 50, manufacturing information and inspection regarding individual semiconductor integrated circuits can be generated. Information and the like can be stored and managed.

  Hereinafter, an identification method and an identification method using the identification device 1 will be described.

(About the identification method by the identification device 1)
First, it is assumed that the identifier of the liquid crystal driver in the wafer state is generated by the identification device 1 and stored in the database 50 in advance. The liquid crystal driver in the individual state is set to the internal state of 1024 by the tester and the input signal supply unit, and transmits the power supply current value in each state to the DC measurement unit 11. The DC measurement unit 11 measures the power supply current value of the signal and sequentially outputs the measured value to the memory unit 12.

  The memory unit 12 stores the power supply current measurement value input from the DC measurement unit 11 for each liquid crystal driver. Based on the power supply current measurement value stored in the memory unit 12, the calculation unit 13 performs the same processing as that for generating an identifier in the wafer state, and generates an identifier for each liquid crystal driver. The generated identifier is input to the comparison unit 14.

  The comparison unit 14 compares the input identifier with the identifier for the same type of semiconductor integrated circuit stored in the database 50, and compares the input identifier with the identifier for the same type of semiconductor integrated circuit stored in the database 50. Among them, it is a means for identifying one of them.

  Specifically, the comparison unit 14 compares the input identifier with all identifiers for the same type of liquid crystal driver stored in the database 50, and compares the input identifier with the same type of liquid crystal stored in the database 50. Identify one of the driver identifiers.

  In the identification operation, any one of the identifiers stored in the database 50 and the input identifier are sorted, for example, in a state where the power supply current values from 1 to Nth in the sorted identification number list are large. Can be easily performed by sequentially comparing.

  In an ideal situation, the identifiers stored in the comparison unit 14 and the database 50 are compared with the input identifiers, and if the order of the internal state identification numbers in the identification number list all match, both identifiers are the same. Judged as an identifier.

  Actually, since the measurement of the power supply current value in the DC measurement unit 11 involves a measurement error, the identifier stored in the database 50 and the input identifier may not completely match. Identification with sufficient accuracy is possible. Specifically, the comparison unit 14 does not change the identifiers stored in the database 50 and the input identifiers even if there are several internal state identification numbers whose orders are different due to measurement errors. If the order of the internal state identification numbers matches, both identifiers may be identified as the same identifier, and the identification operation has a very high accuracy to the extent that there is no practical problem.

  This completes the description of the method for discriminating between the semiconductor integrated circuit in the individual state and the semiconductor integrated circuit in the wafer state using the identification device 1 according to the present embodiment. Below, the trace procedure by the identification device 1 will be described.

(Trace procedure and wafer map creation procedure by the identification device 1)
First, the DC measurement unit 11 of the identification device 1 acquires test data on the wafer state of the semiconductor integrated circuit generated by an electrical test of the semiconductor integrated circuit in the wafer state. The DC measurement unit 11 stores the acquired wafer state test data in the memory unit 12. Further, the DC measurement unit 11 acquires chip information corresponding to the test target semiconductor integrated circuit generated when the electrical test is performed, and similarly stores the chip information in the memory unit 12.

  Subsequently, based on the wafer state test data stored in the memory unit 12, the arithmetic unit 13 generates an identifier of the semiconductor integrated circuit by the identifier generation method described above (corresponding to the first generation unit), and the memory Stored in the unit 12.

  The arithmetic unit 13 associates the test data of the semiconductor integrated circuit stored in the memory unit 12, the identifier of the semiconductor integrated circuit, and the chip information corresponding to the semiconductor integrated circuit, and stores them in the database 50.

  The database 50 stores in advance information on a plurality of wafer lots and processing histories for each of the plurality of wafers. The arithmetic unit 13 corresponds to the test data of the semiconductor integrated circuit stored in the database 50, the identifier of the semiconductor integrated circuit, chip information corresponding to the semiconductor integrated circuit, and the semiconductor integrated circuit. The wafer lot information and the processing history of the wafer are associated with each other. The calculation unit 13 manages the associated information as wafer information of the semiconductor integrated circuit in the wafer state.

  The identification apparatus 1 repeats the above procedure for each of a plurality of semiconductor integrated circuits in a wafer state, and accumulates a plurality of pieces of wafer information in the database 50 (corresponding to management means).

  Next, the DC measurement unit 11 performs an electrical test on the semiconductor integrated circuit in the individual piece state, acquires test data on the individual piece state of the semiconductor integrated circuit, and stores it in the memory unit 12. The calculation unit 13 generates an identifier of the semiconductor integrated circuit based on the individual piece state test data stored in the memory unit 12 by the above-described identifier generation method (corresponding to the second generation unit), and the memory unit 12.

  The arithmetic unit 13 associates the test data of the individual state of the semiconductor integrated circuit stored in the memory unit 12 and the identifier of the semiconductor integrated circuit, and stores them in the database 50. The calculation unit 13 manages the associated information as individual piece information of the semiconductor integrated circuit in the individual piece state.

  The comparison unit 14 identifies the semiconductor integrated circuit using the identification method described above with reference to the database 50. The comparison unit 14 specifies the chip position information of the target semiconductor integrated circuit based on the chip information stored in the database in association with the identified wafer state identifier of the semiconductor integrated circuit (specification). Corresponding to the means). The comparison unit 14 stores the chip position information specified by the above procedure in the memory unit 12.

  With the above procedure, tracing can be performed using the identification device 1.

  In the present embodiment, the generation of the identifier of the semiconductor integrated circuit, the identification of the semiconductor integrated circuit, and the trace are all performed using the same identification device 1, but this does not limit the present invention. Absent.

  For example, an identifier in the wafer state of the semiconductor integrated circuit (first identifier) is generated by a certain apparatus, and an identifier (second identifier) in the individual state of the semiconductor integrated circuit is generated by another apparatus, The generated identifier (second identifier) may be used to identify and trace the semiconductor identifier. In such a configuration, the certain device and the other device may be connected to the database 50.

  In the present embodiment, the case where the power supply current values for a plurality of predetermined internal states in the non-operating state of the semiconductor integrated circuit are used as identifiers is described. However, this does not limit the present invention. Alternatively, the variation between the output terminals of the analog voltage for each gradation may be used as the identifier.

  The above is the description of the method of tracing information related to the semiconductor integrated circuit in the individual piece state using the identifier generated by the above method. Next, a method for creating a wafer map based on the trace result by the above-described trace method using the identification apparatus 1 will be described.

  The chip position information traced by the tracing method using the identification device 1 is stored in the memory unit 12. Based on the chip position information stored in the memory unit 12, the arithmetic unit 13 selects any one of the chip position information of a plurality of individual semiconductor integrated circuits in a target state and a plurality of semiconductor integrated circuits in a wafer state. A wafer map is created by associating the chip position information with one-to-one. The arithmetic unit 13 stores the created wafer map in the memory unit 12. The wafer map created at this time may be stored in the database 50 as well.

  Hereinafter, several modified examples of wafer map creation using the identification device 1 according to the present embodiment will be described. As a first modification of the identification device 1 according to the present embodiment, the calculation unit 13 includes a plurality of pieces of semiconductor integrated devices that are manufactured from the same wafer based on chip position information stored in the memory unit 12. Aggregate circuit test data. Further, the calculation unit 13 associates the test data and the chip position information of the plurality of semiconductor integrated circuits in the individual state. Thereby, the identification device 1 creates a wafer map to which the piece information is further added. For example, by using the identification device 1, it is possible to create a wafer map by counting only chips that have failed (in which an electrical test could not satisfy a predetermined specification) in an individual state.

  Further, as a second modification of the identification device 1 according to the present embodiment, the calculation unit 13 includes a plurality of pieces in a single state produced from the same wafer based on chip position information stored in the memory unit 12. Summarize test data for semiconductor integrated circuits. Further, the arithmetic unit 13 compares the test data of the semiconductor integrated circuit in the wafer state corresponding to the plurality of individual semiconductor integrated circuits with the test data of the semiconductor integrated circuit in the individual state. The calculation unit 13 further associates the difference test data indicating the difference of the test data obtained by comparison with the chip position information. As a result, the identification device 1 creates a wafer map to which a variation amount of test data when the semiconductor multi-integrated circuit transitions from the wafer state to the individual state is further added. For example, by using the identification device 1, it is possible to create a wafer map indicating the difference between the current value in the individual state of each of the plurality of semiconductor integrated circuits and the current value in the wafer state.

  In the above example, the liquid crystal driver is described as an example of the semiconductor integrated circuit. However, the present invention is not limited to this, and can be applied to semiconductor integrated circuits other than the liquid crystal driver. It is.

[Summary]
An identification method according to an aspect of the present invention is an identification method of a semiconductor integrated circuit, wherein a first identifier for identifying a plurality of semiconductor integrated circuits having the same configuration in a wafer state is used as each semiconductor integrated circuit. A first generation step that is generated based on respective values of input / output signals for a plurality of predetermined internal states, and a first identifier generated for each semiconductor integrated circuit in the wafer state A management step of managing in association with position information indicating the position of the circuit on the wafer, and a second identifier for identifying a semiconductor integrated circuit in the individual piece state from other semiconductor integrated circuits in the individual piece state, A second generation step of generating based on each value of input / output signals for the plurality of predetermined internal states of the certain semiconductor integrated circuit, and for the certain semiconductor integrated circuit A step of identifying the formed second identifier as one of the first identifiers, and identifying the position information associated with the identified first identifier. .

  According to the method, the second identifier generated for the certain semiconductor integrated circuit is identified as one of the first identifiers, and the position information associated with the identified first identifier is obtained. Therefore, it is possible to efficiently specify from which position on the wafer the semiconductor integrated circuit in the individual piece state is cut out.

  Therefore, the above method contributes to more efficient identification of the cause of occurrence of defective products in the manufacturing process of the semiconductor integrated circuit.

  It should be noted that the values of the input / output signals referred to for generating the identifier may be those obtained when an electrical test of the semiconductor integrated circuit is performed. In this case, for example, while performing an electrical test of the semiconductor integrated circuit, the second identifier to be given to the semiconductor integrated circuit is generated substantially in real time, and the generated second identifier is used to generate the second identifier. Location information can be traced.

  Furthermore, the identification method according to an aspect of the present invention includes a wafer map creation step of creating a wafer map indicating the position of the semiconductor integrated circuit in the individual piece state on the wafer based on the position information. Is preferred.

  According to the above method, a wafer map that is a set of chip position information (or chip coordinates) related to one or a plurality of target semiconductor integrated circuits is created. According to the above method, by analyzing the created wafer map, for example, it is possible to efficiently identify how the occurrence frequency of defective products of a semiconductor integrated circuit depends on the wafer lot and the position on the wafer. can do.

  Furthermore, in the identification method according to one aspect of the present invention, the first identifier is generated based on power supply current values for a plurality of predetermined internal states in a non-operating state of the semiconductor integrated circuit. The second identifier is generated based on a power supply current value for a part of the plurality of predetermined internal states in the non-operating state of the semiconductor integrated circuit. preferable.

  In general, each semiconductor element constituting a semiconductor integrated circuit is the same type of semiconductor element due to microscopic factors such as slight non-uniformity in processing dimensions and slight non-uniformity of doped impurities. But their characteristics are different from each other. Therefore, even in a semiconductor integrated circuit having the same configuration constituted by the same kind of semiconductor elements, the power supply current value under the same condition differs for each semiconductor integrated circuit.

  Further, the characteristics of the semiconductor elements constituting the semiconductor integrated circuit hardly change even if time elapses or the wafer state is cut out from the wafer state. Therefore, the power supply current value of a certain semiconductor integrated circuit hardly changes under the same conditions. Therefore, the power supply current value of the semiconductor integrated circuit can be used as an identifier unique to each semiconductor integrated circuit under the same conditions.

  Therefore, according to the above identification method, the identifier to be assigned to each of the plurality of semiconductor integrated circuits can be generated based on the power supply current value of the semiconductor integrated circuit under the same conditions, thereby increasing the chip area. In addition, there is an effect that the data collection time can be suppressed and the trace can be performed with high efficiency together with the data amount.

  Furthermore, in the identification method according to one aspect of the present invention, the first identifier is generated based on analog signals for a plurality of predetermined internal states in a non-operating state of the semiconductor integrated circuit, The second identifier is preferably generated based on an analog signal for a part of the plurality of predetermined internal states in the non-operating state of the semiconductor integrated circuit.

  Furthermore, in the identification method according to one embodiment of the present invention, the semiconductor integrated circuit is preferably a liquid crystal driver.

  An identification apparatus (identification apparatus 1) according to one embodiment of the present invention is an identification apparatus for identifying a semiconductor integrated circuit, and is a first apparatus for identifying a plurality of semiconductor integrated circuits having the same configuration in a wafer state from each other. 1 is generated on the basis of each value of input / output signals for a plurality of predetermined internal states of each semiconductor integrated circuit, and each semiconductor integrated circuit in the wafer state Management means (arithmetic unit 13, database 50) for managing the first identifier generated for the semiconductor integrated circuit in association with position information indicating the position of the semiconductor integrated circuit on the wafer, and a semiconductor integrated circuit in a single piece state Is a second identifier for identifying a plurality of predetermined internal states of the certain semiconductor integrated circuit. A second generation unit (arithmetic unit 13) that generates based on each value of the first and second identifiers generated for the semiconductor integrated circuit are identified as one of the first identifiers And specifying means (comparison unit 14) for specifying the position information associated with the first identifier.

  According to said identification apparatus, there exists an effect similar to said identification method.

  In addition, a program for operating the identification device according to one aspect of the present invention, the program for causing a computer to function as each unit included in the identification device, and a computer readable recording of the program Such recording media are also included in the scope of the present invention.

(Additional notes)
The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention. Furthermore, a new technical feature can be formed by combining the technical means disclosed in each embodiment.

[Example of software implementation]
Finally, each block of the identification device 1 may be realized by hardware by a logic circuit formed on an integrated circuit (IC chip), or by software using a CPU (Central Processing Unit). May be.

  In the latter case, the identification device 1 includes a CPU that executes instructions of a program that realizes each function, a ROM (Read Only Memory) that stores the program, a RAM (Random Access Memory) that expands the program, the program, and various types A storage device (recording medium) such as a memory for storing data is provided. An object of the present invention is to provide a recording medium in which a program code (execution format program, intermediate code program, source program) of a control program of the identification device 1 which is software that realizes the above-described functions is recorded so as to be readable by a computer. This can also be achieved by supplying the identification device 1 and reading and executing the program code recorded on the recording medium by the computer (or CPU or MPU).

  Examples of the recording medium include non-transitory tangible medium, such as magnetic tape and cassette tape, magnetic disk such as floppy (registered trademark) disk / hard disk, and CD-ROM / MO. Discs including optical discs such as / MD / DVD / CD-R, cards such as IC cards (including memory cards) / optical cards, semiconductor memories such as mask ROM / EPROM / EEPROM (registered trademark) / flash ROM Alternatively, logic circuits such as PLD (Programmable Logic Device) and FPGA (Field Programmable Gate Array) can be used.

  The identification device 1 may be configured to be connectable to a communication network, and the program code may be supplied via the communication network. The communication network is not particularly limited as long as it can transmit the program code. For example, the Internet, intranet, extranet, LAN, ISDN, VAN, CATV communication network, virtual private network, telephone line network, mobile communication network, satellite communication network, and the like can be used. The transmission medium constituting the communication network may be any medium that can transmit the program code, and is not limited to a specific configuration or type. For example, even with wired lines such as IEEE 1394, USB, power line carrier, cable TV line, telephone line, and ADSL (Asymmetric Digital Subscriber Line) line, infrared rays such as IrDA and remote control, Bluetooth (registered trademark), IEEE 802.11 wireless, HDR ( It can also be used by radio such as High Data Rate (NFC), Near Field Communication (NFC), Digital Living Network Alliance (DLNA), mobile phone network, satellite line, and digital terrestrial network. The present invention can also be realized in the form of a computer data signal embedded in a carrier wave in which the program code is embodied by electronic transmission.

  The identification method according to the present invention can be suitably used for identification of a semiconductor integrated circuit.

DESCRIPTION OF SYMBOLS 1 Identification apparatus 11 DC measurement part 12 Memory part 13 Calculation part (1st production | generation means, 2nd production | generation means, management means)
14 Comparison part (specifying means)
15 Power supply unit

Claims (5)

A method for identifying a semiconductor integrated circuit, comprising:
A first identifier for identifying a plurality of semiconductor integrated circuits having the same configuration in a wafer state is generated based on each value of input / output signals for a plurality of predetermined internal states of each semiconductor integrated circuit. A first generation step;
A management step of managing the first identifier generated for each semiconductor integrated circuit in a wafer state in association with position information indicating the position of the semiconductor integrated circuit on the wafer;
A second identifier for identifying a semiconductor integrated circuit in a single piece state in which the plurality of semiconductor integrated circuits are cut from the wafer from other semiconductor integrated circuits in the single piece state; A second generation step of generating based on each value of the input / output signal for the plurality of predetermined internal states of
A specifying step of identifying the second identifier generated for the certain semiconductor integrated circuit as one of the first identifiers and specifying the position information associated with the identified first identifier;
The identification method characterized by including.   2. A wafer map creating step for accumulating the position information and creating a wafer map indicating a position on the wafer for each of one or a plurality of semiconductor integrated circuits in an individual state. Identification method described in 1. The identification method according to claim 1,
The first identifier is generated based on power supply current values for a plurality of predetermined internal states in a non-operating state of the semiconductor integrated circuit,
The second identifier is generated based on a power supply current value for a part of the plurality of predetermined internal states in the non-operating state of the semiconductor integrated circuit.
An identification method characterized by the above. The identification method according to claim 1,
The first identifier is generated based on analog signals for a plurality of predetermined internal states in a non-operating state of the semiconductor integrated circuit,
The second identifier is generated based on an analog signal for a part of the plurality of predetermined internal states in the non-operating state of the semiconductor integrated circuit.
An identification method characterized by the above. An identification device for identifying a semiconductor integrated circuit,
A first identifier for identifying a plurality of semiconductor integrated circuits having the same configuration in a wafer state is generated based on each value of input / output signals for a plurality of predetermined internal states of each semiconductor integrated circuit. First generation means;
Management means for managing the first identifier generated for each semiconductor integrated circuit in a wafer state in association with position information indicating the position of the semiconductor integrated circuit on the wafer;
A second identifier for identifying a semiconductor integrated circuit in a single piece state in which the plurality of semiconductor integrated circuits are cut out from the wafer from other semiconductor integrated circuits in the single piece state, Second generation means for generating based on each value of the input / output signal for the plurality of predetermined internal states of the circuit;
Identifying means for identifying the second identifier generated for the certain semiconductor integrated circuit as one of the first identifiers and identifying the position information associated with the identified first identifier;
An identification device comprising:

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