JP5973144B2 - Distributed power supply apparatus, control program thereof, and control method thereof - Google Patents

Description

The present invention relates to a distributed power supply apparatus that uses a frequency shift method for isolated operation detection of grid-connected operation using both private power generation and commercial power supply, a control program thereof, and a control method thereof.

  Distributed power sources such as cogeneration are widespread. Distributed power sources include those that convert DC power of solar cells into AC power, and those that use a small engine as a drive source to drive a generator to use its exhaust heat or power. Such a connection between a distributed power source and a commercial power source is a grid connection. Regarding this grid connection operation, detailed standards are defined in the grid connection regulations (JEAC 9701-2010) published by the Japan Electric Association and refer to ensuring the quality, security, reliability, and protection coordination of power supply. Yes.

  In a grid connection, when the system is shut down (system accident, maintenance work, emergency such as a fire), if the power generation facility continues to operate without being disconnected from the commercial power system, there is essentially no voltage This causes inconveniences such as charging the system that should be. For this reason, it is necessary to detect whether or not it is a single operation. One detection method for detecting this isolated operation is a frequency shift method. In this frequency shift method, a frequency bias is given to the distributed power source to detect a frequency change that appears at the time of shifting to an independent operation. With regard to this frequency shift method, in the grid connection regulations, the frequency fluctuation range is a frequency bias of several percent of the rated frequency, the detection element is a frequency abnormality, the disconnection time limit (the time limit until disconnection after the occurrence of independent operation) is 0. It is specified to be 5 seconds or more and 1 second or less. This numerical value is a time limit of disconnection of one unit, and it is considered desirable to disconnect and stop the power generation equipment within at least 5 seconds when connecting multiple units.

  Regarding the detection of isolated operation using this frequency shift method, Patent Document 1 describes a distributed power supply device that determines that it is isolated operation when a frequency deviating from a reference frequency is equal to or higher than a predetermined frequency. This distributed power supply unit recognizes the frequency of the connection point voltage from the frequency data stored in the storage means, and when the frequency deviates from the reference frequency, a shift value in the direction that promotes the deviation is added to the frequency. And determining the output frequency. In this distributed power supply device, Patent Document 2 describes that it is determined whether or not a single operating condition is satisfied from a state where the frequency deviates from a reference frequency by a predetermined frequency or more.

In Patent Document 3, the period information of the current target value is set to a value obtained by adding a minute bias B to the voltage period information, and the current phase of the current target value is reset in accordance with the voltage phase in the normal state. It is described that the reset process is stopped after the possibility of isolated operation is detected.

JP 2000-014018 A JP 2000-050504 A JP 2002-262464 A

  By the way, in the grid connection using the frequency shift method for detecting whether or not it is an independent operation, there is a problem that an instantaneous power failure on the commercial power supply side induces a malfunction. In addition, when shifting to a single operation, depending on the demand load, it may affect the frequency of the system voltage, and may cause a malfunction in detection.

In view of the above-described problems, an object of the present invention is to provide a highly reliable distributed power supply apparatus, a control program thereof, and a control method thereof that improve the accuracy of isolated operation detection using a frequency shift method.

In order to achieve the above object, a distributed power supply apparatus of the present invention includes an opening / closing means, a storage means, a determination means, and a control means. The switching means receives power supply from a power source, generates an AC output, closes in parallel and supplies the AC output to a commercial power system and a load, and opens when disconnected to supply the commercial power system and the load Shut off. The storage means stores a predetermined number of frequencies of the system voltage acquired for each cycle, and takes in an average sub-frequency calculated by averaging the frequencies for a predetermined cycle from the oldest stored frequency every predetermined time. The average frequency calculated by averaging the average sub-frequency for each predetermined time is stored. Determining means, when the polarity every predetermined time to impart a frequency change in the system voltage by applying an active signal that varies the difference of the average frequency and frequency of the system voltage is changed more than a predetermined value, a predetermined The increase or decrease in the frequency change is fixed for the time, and the increase or decrease in the frequency of the system voltage is monitored. When the detected frequency change exceeds a predetermined range, it is determined that the system is operating independently. The control means opens the opening / closing means in accordance with the determination result of the determination means that it is an independent operation, and controls the parallel to the disconnection.

In order to achieve the above object, a control program for a distributed power supply apparatus according to the present invention is a program to be executed by a computer installed in the above-described distributed power supply apparatus, and the system voltage acquired by the computer for each cycle. Is stored in the storage means, and the average sub-frequency calculated by averaging the frequencies of the predetermined cycle from the oldest stored frequency is taken every predetermined time, and the average sub-frequency for each predetermined time is taken. a function of storing average frequency calculated by averaging the frequency to the SL 憶手 stage, the function of imparting a frequency change in the system voltage by applying an active signal changes polarity at a predetermined time interval, the system voltage When the difference between the average frequency and the average frequency changes to a predetermined value or more, the increase or decrease in frequency change is fixed for a predetermined time until the frequency of the grid voltage increases. Is a function of monitoring the reduction, the detected frequency change is achieved by said and a determining function is in isolated operation in case of exceeding a predetermined range computer.

In order to achieve the above object, a control method for a distributed power supply apparatus according to the present invention generates an AC output by receiving power from a power source, and closes the AC output in parallel to supply the AC output to a commercial power system and a load. A step of opening at the time of disconnection and cutting off the supply to the commercial power system and the load, and storing a predetermined number of frequencies of the system voltage acquired for each cycle in the storage means, and starting from the oldest stored frequency uptake average sub frequency calculated by averaging the frequency of a predetermined cycle at a predetermined time interval, a step of storing the average frequency calculated by averaging the average sub-frequency in each predetermined time in the SL 憶手 stage, predetermined It is a predetermined time when an active signal whose polarity changes with time is applied to change the frequency of the system voltage, and the difference between the frequency of the system voltage and the average frequency changes to a predetermined value or more. Monitoring the increase or decrease in the system voltage frequency while fixing the increase or decrease in the frequency change, and determining that the operation is in isolation when the detected frequency change exceeds the specified range. And controlling from the parallel to the solution sequence in accordance with the determination result that is.

  (1) The detection accuracy of the frequency change superimposed on the system voltage can be improved, and it can be accurately known whether or not the system is operating independently, thereby realizing a highly reliable operation.

(2) The instantaneous power failure on the commercial power supply side and the malfunction of frequency detection due to the influence of the system voltage from the demand load side on the frequency can be prevented, and the operation reliability can be improved.

It is a figure which shows an example of the distributed power supply system of this invention. It is a figure which shows an example of an electric power source. It is a figure which shows an example of a control part. It is a figure which shows an example of an inverter part. It is a figure which shows an example of the frequency shift of an output current. It is a figure which shows an example of the zero cross detection for a frequency change detection. It is a figure which shows the structural example of a frequency detection counter and an average frequency calculation buffer. It is a figure which shows an example of a frequency change and its detection. It is a figure which shows an example of a frequency change and its detection. It is a figure which shows an example of a frequency change and its detection. It is a figure which shows an example of a frequency change and its detection. It is a figure which shows an example of a frequency change and its detection. It is a figure which shows an example of a frequency change and its detection. It is a figure which shows an example of a frequency change and its detection. It is a figure which shows an example of a frequency change and its detection. It is a flowchart which shows an example of the process sequence of a frequency change detection. It is a figure which shows the example of calculation of an average frequency. It is a flowchart which shows an example of the process sequence of frequency detection. It is a flowchart which shows an example of a detection and control of a driving | running state. It is a flowchart which shows an example of the process sequence of frequency detection. It is a flowchart which shows an example of the process sequence of frequency detection. It is a flowchart which shows an example of the process sequence of frequency detection. It is a flowchart which shows other embodiment of a period process. It is a flowchart which shows other embodiment of a period process.

  FIG. 1 shows a distributed power supply system according to an embodiment of the present invention. The configuration shown in FIG. 1 is an example, and the present invention is not limited to such a configuration.

  This distributed power supply system is an example of the distributed power supply apparatus of the present invention, and is configured to supply the output of the distributed power supply apparatus to a load or to a load and a commercial power supply.

  A power source 4 is connected to the input side of the distributed power supply device 2, a load 6 is connected to the output side, and a commercial power system 10 is connected via a circuit breaker 8.

  The power source 4 is a facility that generates electric power, such as a generator of a cogeneration system and a solar battery of a solar power generation system. In this embodiment, a DC power source is assumed, but either a DC power source or an AC power source may be used.

  The load 6 is, for example, an AC load in a house. That is, the load 6 can be supplied with power from the power source 4 and the power from the commercial power supply system 10 via the distributed power supply device 2, and can be fed by grid connection operation. The circuit breaker 8 disconnects the commercial power supply system 10 from the load 6 and is used to interrupt the power supply from the commercial power supply system 10 to the load 6.

  A rectifier 12 is installed at the input section of the distributed power supply device 2 to rectify the input voltage. The output of the rectifier 12 is applied to a booster circuit 14 in the input stage of the inverter unit, and boosted to a predetermined DC voltage. This voltage is referred to as a boosted voltage. This boosted voltage is applied to the FET bridge circuit 16 to adjust the voltage waveform. After the noise component is removed by the filter 18, the boosted voltage becomes an AC output of the distributed power supply device 2 via the switch 20. This AC output is supplied to the load 6.

  In the distributed power supply device 2, a control unit 22 is installed as a control unit that controls the booster circuit 14, the FET bridge circuit 16, and the switch 20. The control unit 22 takes in the boosted voltage described above as control information, the output current from the output side of the filter 18, and the system voltage from the output side of the switch 20.

  The control unit 22 is configured by a computer, and includes a processor 24, an IO port 26, an AD converter 28, a ROM (Read-Only Memory) 30, an EEPROM 32, a RAM (Random-Access Memory) 34, a clock oscillator 36, and an alarm device 37. I have.

  The processor 24 also configures a timer that executes a program stored in the ROM 30 and counts clock signals. This program includes programs such as an OS (Operating System), a firmware program, and an application program. By executing this program, a detection process for determining whether or not the vehicle is operating independently and a control based on the detection are included.

  The IO port 26 is an input / output unit for various types of information. In this embodiment, boost control information for the boost circuit 14, switching information for the FET in the FET bridge circuit 16, and open / close information for the switch 20 are output. The step-up control information of the step-up circuit 14 includes both control information in the step-up direction of the output voltage and control information in the step-down direction of the current value. The FET switching information of the FET bridge circuit 16 is a pulse for controlling the FET constituting the FET bridge circuit 16 to be in a conductive state or a cut-off state. The switching information of the switch 20 is information for controlling the switch 20 to be opened or closed. When the switch 20 is controlled to be opened, the distributed power supply device 2 is disconnected from the load 6 or the commercial power supply system 10, that is, It becomes a disconnection.

  The AD converter 28 performs analog / digital conversion and converts the boosted voltage, output current, or system voltage, which is analog information, into a digital value.

  The ROM 30, EEPROM 32, and RAM 34 are examples of storage means. The ROM 30 stores the above-described program, and the EEPROM 32 is an example of a nonvolatile storage unit, and is used for holding a setting value, a correction value, and the like. The RAM 34 constitutes a work area and is used for temporarily storing frequencies, control data, and the like.

  The clock oscillator 36 generates a clock signal for system control, and this clock signal is applied to the processor 24, and is used for measuring the operation timing of the system and a predetermined time. The alarm device 37 is an example of a notification means for notifying the time of independent operation.

  The processor 24 is connected to a hot water supply control unit 40 of a hot water supply system 38 installed outside the distributed power supply device 2. The hot water supply system 38 uses the exhaust heat generated by the power source 4 as a heat source, and heats the heat medium and clean water. The hot water supply control unit 40 serving as the control means is constituted by a computer system, and an interconnection relation with the operation of the processor 24 described above is established.

[Power source 4]

  FIG. 2 shows an example of the power source 4. The power source 4 includes an engine 42 as a drive source, and a generator 44 is driven by the engine 42. In the engine 42, for example, gas is used as fuel, and exhaust or exhaust heat is generated by the combustion. The exhaust path 46 of the engine 42 is provided with an exhaust heat exchanger 48 for exchanging heat of the exhaust to the heat medium, and the exhaust heat recovery path 50 is provided with an exhaust heat recovery heat exchanger 52 and a surplus power heater 54. The exhaust heat recovery heat exchanger 52 exchanges heat absorbed by the refrigerant of the engine 42 with a heat medium. The surplus power heater 54 is supplied with surplus power from the distributed power supply device 2 and heats the heat medium.

[Control unit 22]

  FIG. 3 shows an example of functions realized by the control unit 22. As described above, since the control unit 22 is configured by a computer, the frequency detection unit 56, the output frequency determination unit 58, the output current control unit 60, the cycle timer 62, and the islanding operation detection unit 64 are configured by executing this computer. Is done.

  The frequency detection means 56 includes the above-described AD converter 28 and the processor 24, and detects the frequency of the system voltage. The detected frequency is added to the output frequency determining means 58. The output frequency determining means 58 includes the processor 24 and the clock oscillator 36, receives an active signal from the isolated operation detection unit 64, determines a frequency to be applied to the output current, and sends the determined frequency to the output current control means 60. Add.

  The output current control means 60 includes an AD converter 28 and a processor 24, and applies a control signal on which the frequency is superimposed to the FET bridge circuit 16 according to the system voltage, output current and output frequency.

  The period timer 62 is composed of the processor 24 and the clock oscillator 36, and generates a period signal representing a fixed period. This periodic signal is applied to the isolated operation detection unit 64.

  The islanding operation detection unit 64 includes the processor 24 and the RAM 34, detects whether or not the islanding operation is performed based on the frequency detected from the system voltage, and generates control information corresponding to the detection. Therefore, the isolated operation detection unit 64 includes an isolated operation determination unit 66 and an active signal determination unit 68.

  The single operation determination unit 66 determines whether or not the single operation is performed based on the detection frequency, and outputs a control signal for opening the switch 20 to the switch 20 if the single operation is performed. The determination result of the isolated operation determining means 66 is added to the active signal determining means 68. If the isolated operation is not performed, the active signal determining means 68 outputs an active signal during parallel operation and outputs it to the output frequency determining means 58.

[FET bridge circuit 16, filter 18 and switch 20]

  FIG. 4 shows the above-described inverter unit. The configuration shown in FIG. 4 is an example, and the present invention is not limited to such a configuration.

  The FET bridge circuit 16 includes FETs 70, 72, 74, and 76. The FETs 70 and 74 form a series circuit, and the FETs 72 and 76 form a series circuit. With the common gates of the FETs 70 and 76 and the common gates of the FETs 74 and 72, a switching control signal is applied from the control unit 22, and a one-phase output is generated as an alternating current output from the direct current input and applied to the filter 18.

  The filter 18 includes choke coils 78 and 80 and a capacitor 82, and unnecessary components are removed. A current detection unit 84 is installed at the output unit of the filter 18, and the output current of the distributed power supply device 2 is detected from the current detection unit 84.

  The switch 20 is composed of an electromagnetic switch as an example of a switching means, and contacts 86 and 88 are provided for each phase. An electromagnetic solenoid 90 is provided as means for opening and closing the contacts 86 and 88. The excitation current for the electromagnetic solenoid 90 is supplied and controlled by the control unit 22.

  A voltage detector 92 for detecting the system voltage is installed on the commercial power system side of the switch 20. The voltage detector 92 detects the output voltage of the distributed power supply device 2 when the commercial power supply system 10 has a power failure.

  A load 6 and a commercial power supply system 10 are connected to the switch 20 via capacitors 94 and 96 constituting a filter. The capacitors 94 and 96 are connected at a midpoint, and the midpoint is connected to the commercial power supply system 10 side. In this case, the commercial power system 10 side is a single-phase three-wire AC. As a result, the output of the distributed power supply device 2 is supplied to the load 6.

[Frequency shift]

  FIG. 5 shows the frequency shift operation of the output current. 5A shows a case where the frequency of the system voltage is shifted in the positive direction, and FIG. 5B shows a case where the frequency of the system voltage is shifted in the negative direction.

  In FIGS. 5A and 5B, V indicates a waveform of the system voltage. When the active signal amount (frequency) fe = 0.1 [Hz] is added to the current frequency f (f + 0.1), the waveform of the output current I shown by the broken line is the amount corresponding to the active signal amount fe = 0.1 [Hz]. , The cycle becomes shorter. That is, when the frequency of the output current I shifts in the positive direction and f = 50 [Hz], f + 0.1 = 50.1 [Hz].

  When the active signal amount (frequency) fe = 0.1 [Hz] is subtracted (f−0.1) from the current frequency f, the waveform of the output current I indicated by the broken line is the active signal amount fe = 0.1 [Hz]. ], The period becomes longer. That is, when the frequency of the output current I is shifted in the negative direction and f = 50 [Hz], f−0.1 = 49.9 [Hz].

  Such a frequency shift can be detected from the level of the zero cross point of the system voltage or the output current.

[Detection of zero cross point]

  FIG. 6 shows the detection of the zero cross point. If the polarity of the sampled waveform and its level change are detected for the phase-shifted waveform M (V or I), the zero cross point P can be known. Further, the time T (waveform period) between the zero cross points P can be obtained by counting the clock signal based on the sampling frequency. From this time T, the current frequency f can be detected.

[Frequency detection counter and average frequency calculation]

  As shown in FIG. 7, the RAM 34 includes an array A, an array B, and an array C (FIG. 17). The array B is a means for counting the number of changes in the same direction as the active signal direction. A frequency negative direction divergence counter 100 is provided as means for counting the number of times of no change in the same direction.

[Frequency shift and its detection]

  In the frequency shift and its detection, for example, a frequency bias of frequency ± 0.1 [Hz] is added as an active signal frequency to the output current target value, and a frequency change that appears when the commercial power supply system 10 is interrupted is detected. Based on the frequency change, it is determined whether or not the sequence is disconnected. The frequency shift and detection thereof will be described with reference to FIGS. 8, 9, 10, 11, 12, 13, 14 and 15. FIG.

  FIG. 8 shows an example of a frequency shift when the reference frequency = 50 [Hz]. In this embodiment, for example, 0.1 [Hz] is set as the active signal frequency to be added. 8A shows the current frequency f and the target output frequency fout by setting the elapsed time t on the horizontal axis and the frequency on the vertical axis, and FIG. 8B shows the sampling timing.

  In this embodiment, the sampling timing is set to 100 [msec], and the frequency shift timing is set to 300 [msec], which is three times the sampling timing.

In this example, it is assumed that the current frequency f is constant, and the active signal frequency 0.1 [Hz] is added to or subtracted from the current frequency f to obtain the target output frequency fout. That is, for the target output frequency fout, an addition period t ₁ and a subtraction period t ₂ of 0.1 [Hz] alternately come every 300 [msec], and fout = fout = in the addition period t ₁ with respect to the current frequency f. f + 0.1 = 50.1 [Hz], and fout = f−0.1 = 49.9 [Hz] is obtained in the subtraction period t2.

FIG. 9A shows an example of frequency change of the current frequency and fixation of the active signal frequency, and FIG. 9B shows sampling timing. In this example, the current frequency tends to increase during the addition period t1 in which the frequency of the active signal is increasing. When the current frequency rises by 0.05 [Hz] or more as a constant frequency threshold, a fixed time t _fix of a fixed time is set from that point. In this embodiment, the fixed time t _fix = 1.2 [seconds], the rising direction of the active signal is fixed at the fixed time t _fix and the increasing tendency of the current frequency is monitored. In FIG. 9A, f _ave indicates an average frequency. After the fixed time t _fix elapses, the period shifts to an active signal frequency subtraction period t2.

FIG. 10A shows an example of frequency change of another current frequency and fixed active signal frequency, and FIG. 10B shows sampling timing. In this example, the current frequency tends to increase during the subtraction period t2 in which the frequency of the active signal is decreasing. When this current frequency rises by 0.05 [Hz] or more as the above-described frequency threshold, a fixed time t _fix is set for a fixed time from that point. In this embodiment, the fixed time t _fix = 1.2 [seconds], the increasing direction of the active signal is fixed at the fixed time t _fix and the increasing tendency of the current frequency is monitored. In FIG. 10A, f _ave indicates an average frequency. After the fixed time t _fix elapses, the period shifts to an active signal frequency subtraction period t2.

  FIG. 11A shows an example of frequency changes of the current frequency and the target output frequency, and FIG. 11B shows sampling timing. This example shows that the target output frequency changes according to the current frequency.

  12A shows the frequency change of the current frequency and the target output frequency, FIG. 12B shows the sampling timing, and FIG. 12C shows the increase in the count value of the frequency positive direction divergence counter 98.

  In this example, the target output frequency and the current frequency are increased from the frequency increase period, and the frequency increase is fixed from the time when the frequency has increased by 0.05 [Hz] or more.

  In this case, as shown in FIG. 12C, the frequency positive direction divergence counter 98 counts the clock signal with the sampling timing as the counting timing. For example, when the count value reaches 6 as a predetermined value, it is determined that the operation is an independent operation, and an alarm indicating that the operation is an independent operation is generated in the alarm device 37.

  13A is the frequency change of the current frequency and the target output frequency, FIG. 13B is the sampling timing, FIG. 13C is the increase of the count value of the frequency positive direction divergence counter 98, FIG. D) shows the count value of the frequency negative direction divergence counter 100.

  In this example, the target output frequency and the current frequency are increased from the frequency increase period, and the frequency increase is fixed from the time when the frequency has increased by 0.05 [Hz] or more.

  In the fixed period of frequency increase, there is a section where the increase of the current frequency and the target output frequency is stopped, and the frequency transition between the current frequency and the target output frequency is 0.2 [Hz] from the point when this section is exceeded. ing. In this case, the count value of the frequency negative direction divergence counter 100 becomes 0 in the interval between the count values 1 to 3 of the frequency positive direction divergence counter 98 and 1 in the interval of the count values 4 to 6 of the frequency positive direction divergence counter 98. .

  In this case, as shown in FIG. 13C, the frequency positive direction divergence counter 98 counts the clock signal with the sampling timing as the count timing, so when this count value reaches, for example, 6 as a predetermined value, It is determined that the operation is an independent operation, and an alarm indicating that the operation is an independent operation is generated in the alarm device 37.

  Similarly, FIG. 14A and FIG. 15A are frequency changes of the current frequency and the target output frequency, FIG. 14B and FIG. 15B are sampling timings, and FIG. 14C. 15C shows an increase in the count value of the frequency positive direction divergence counter 98, and FIG. 14D and FIG. 15D show the count value of the frequency negative direction divergence counter 100.

  In the example of FIG. 14, the frequency is constant or increased within the fixed increase period of the frequency, and then starts decreasing after the increase. In this case, even if the frequency lowering is fixed, the frequency positive direction divergence counter 98 counts the clock signal with the sampling timing as the counting timing, as shown in FIG. For example, when 6 is reached as the predetermined value, it is determined that the operation is an isolated operation, and the alarm 37 indicates that the operation is an independent operation.

  On the other hand, in the example of FIG. 15, when the frequency increase fixed period has elapsed, the frequency shifts to the fixed period. Since the difference is less than 0.05 [Hz] compared to the frequency before 300 [msec], the forward divergence counter is “−1” and becomes “4”. For this reason, it is not determined as an isolated operation, and an alarm indicating an isolated operation by the alarm device 37 is not generated. In this case, the count value of the frequency negative direction divergence counter 100 becomes 0 in the interval between the count values 1 to 3 of the frequency positive direction divergence counter 98 and 1 in the interval of the count values 4, 5, and 4 of the frequency positive direction divergence counter 98. 2 and 3 are incremented.

  FIG. 16 shows these processing procedures. In this processing procedure, a frequency change (active signal) of ± 0.1 [Hz] is given to the current frequency f, and the target output frequency fout is determined (S11: FIGS. 8 and 11). The direction of the active signal is switched every 300 [msec] (S12: FIG. 8). The current frequency and average frequency are sampled every 100 [msec] (S13: FIG. 8).

  The current frequency is compared with the average frequency, and if the frequency difference is 0.05 [Hz] or more, the active signal is fixed in the frequency increasing direction for 1.2 [seconds] so that the frequency diverges (S14: FIG. 9, FIG. 10). Similarly, the current frequency is compared with the average frequency, and if the frequency difference is 0.05 [Hz] or less, the active signal is fixed in the frequency decreasing direction for 1.2 [seconds] so that the frequency diverges ( S15)

  After 1.2 [seconds], the direction is switched every 300 [msec] (S16: FIGS. 9 and 10). If the current frequency is higher than the value of 100 [msec] before the upward direction is fixed, the count value of the frequency positive direction divergence counter 98 is incremented by 1 (S17: FIG. 12). While the rising direction is fixed, if the current frequency does not rise above the value of 100 [msec], the frequency negative direction divergence counter 98 is incremented by 1 (S17: FIG. 13). If the current frequency is higher than the previous value of 100 [msec] while the decrease direction is fixed, the count value of the frequency positive direction divergence counter 98 is incremented by 1 (S18: FIG. 12). While the decreasing direction is fixed, if the current frequency is not higher than the previous value 100 [msec], the frequency negative direction divergence counter 100 is incremented by 1 (S18: FIG. 13).

  When the count value of the frequency positive direction divergence counter 98 is counted as “6”, an independent operation active detection alarm is set (S19: FIG. 12).

  When the count value of the frequency negative direction divergence counter 100 is counted as “1”, the active signal is increased to ± 0.2 [Hz], and the frequency positive direction divergence counter 98 is incremented by 1 (S20: FIG. 13).

  When the count value of the frequency negative direction divergence counter 100 is counted to “2” or “4”, the fixed direction is reversed and the frequency positive direction divergence counter 98 is incremented by 1 (S21: FIG. 14). The positive frequency direction divergence counter 98 and the negative frequency direction divergence counter 100 are reset to 0 after a fixed time of 1.2 [seconds] (S22).

  If the count value of the frequency positive direction divergence counter 98 reaches “5” or more, the frequency positive direction divergence counter 98 is determined if the difference between the current frequency f and the frequency before 300 [msec] is less than 0.05 [Hz]. Is set to -1 (S23: FIG. 15).

[Calculation of average frequency]

FIG. 17 shows an example of calculating the average frequency using the array B and the array C described above. In FIG. 17, each symbol is
f _n : current frequency f
f _{n -1} : frequency f one cycle before
f _{n -2} : frequency f two cycles before
・
・
・
f _{n -79} : frequency f before 79 cycles

f _ave ' _m : average value of f _{n -79 to} f _{n -70} f _ave ' _m-1 : average value f _ave 'before 200 [msec]
f _ave ' _m-2 : Average value f _ave ' before 400 [msec]
It is.

The array B and the array C are set in the RAM 34 as described above, and the storage number No. 1-No. 80 storage fields of 80 are set. A storage value f _n is stored in each storage column.

Ten stored values f _{n-79 to} f _n-70 are extracted from the stored value f _n to calculate an average value f _ave ′. The average sub-frequency f _ave ′ is taken every 200 [msec]. The acquired average sub-frequency f _ave ′ is stored in the array C. The average sub frequency f _ave 'has an average value of f _{n -79} ~f _{n -70,} 200 [msec] previous average value f _ave', is three 400 [msec] previous average value f _ave ' .

Therefore, the storage number No. 1-No. 3, three storage fields are set, and three average sub-frequency f _ave ' _m-2 , f _ave ' _m-1 and f _ave ' _m are stored. The average frequency f _ave is calculated from these three stored values. As shown in the array B in the calculation of the average frequency f _ave , for example, 80 stored values are used as the predetermined number of stored values, so that the change in frequency can have a delay of a certain value or more, Variation errors in a short time and detection errors in isolated operation can be avoided.

The processing procedure for detecting the average frequency f _ave will be described with reference to FIG. FIG. 18 shows a processing procedure of frequency detection.

  This frequency detection processing procedure is an example of the control program and control method of the present invention. In this processing procedure, each data used for processing is as follows.

t: Elapsed time from up cross T: System voltage 1 cycle time A: Array for holding 1 cycle time (up to 12)
T _ave : 1 cycle time average value T _max : Maximum value stored in array A T _min : Minimum value stored in array A T _sum : Total value stored in array A f: Current frequency B: Current frequency holding array (up to 80)
f _ave ': average value of the first to tenth oldest values stored in array B f _ave : average frequency C: f _ave ' holding array (up to 3)

  In this processing procedure, a system voltage value is acquired for frequency detection (S31). In this system voltage value acquisition, the elapsed time is counted (t ← t + 1) (S32), and this count increments a count value representing the current time.

  It is determined whether or not an up cross has been detected (S33). If it is an up cross (YES in S33), one cycle time is determined (S34). In this step, T ← t The elapsed time is reset t ← 0.

  The system voltage 1 cycle time T is stored in the array A of the storage means (step S35). In this storage processing, data is updated, that is, processing for discarding the oldest data and holding up to the past 12 is performed.

An average value T _ave for one cycle time is obtained from 12 pieces of data stored in the array A (S36). This average value T _ave is an average of the remaining 10 time data excluding the maximum value and the minimum value. This average value T _ave is
T _ave = (T _Sum −T _max −T _min ) ÷ 10 (1)
Ask more.

The current system frequency is calculated using the average value _Tave (S37). The current system frequency f is the reciprocal of the average value T _ave ,
f = 1 / T _ave (2)
It is requested from.

  The current frequency f is stored in the array B (S38). Data is updated in this storage process, that is, the oldest data is discarded and the past 80 data are retained.

The average value f _ave ′ for the 10 oldest data among the 80 stored in the array B is obtained (S39). This average value f _ave ′ is an average from the oldest data to the 10th oldest data.

Further, it is determined whether or not the average value f _ave is the calculation cycle (S40). If the average value f _ave is the calculation cycle (YES in S40), the average value f _ave ′ is stored in the array C (S41). In this storage process, the oldest data is discarded and the past three are retained.

Then, the average value f _ave is determined from the three pieces of data stored in the array C (S42). In this case, one data remaining after removing the maximum value and the minimum value from the data in the array C is determined as f _ave , and the process returns to step S31.

In step S40, if the average value f _ave is not the calculation cycle (NO in S40), the process returns to step S31, the system voltage value is acquired, and the above processing procedure is executed.

〔basic action〕

  FIG. 19 shows a processing procedure for basic operations. This processing procedure is an example of the control program and the control method of the present invention. In this processing procedure, after power-on, initialization is performed (S101) and the presence / absence of an operation instruction is monitored (S102). If there is an operation instruction (YES in S102), it is determined whether or not the operation instruction is power generation (S103). If the operation instruction is power generation (YES in S103), it is determined whether the current state is power generation and parallel (S104).

  If power generation and parallel operation are not being performed (NO in S104), it is determined whether or not the reconnection standby time has elapsed (S105). If the reconnection standby time has elapsed (YES in S105), power generation is performed. Then, parallel processing is started (S106), and the process returns to step S102.

  If there is no operation instruction in step S102 (NO in S102), it is determined whether the current state is power generation and parallel (S107). If power generation and parallel are being performed (YES in S107), power generation and parallel are continued (S108), and the process returns to step S102.

  In step S107, if power generation and parallel operation are not being performed (NO in S107), since the disconnection is in progress, the disconnection is continued (S109) and the process returns to step S102.

  In step S103, if the operation instruction is not power generation (NO in S103), processing for the operation instruction is executed (S110), and the process returns to step S102.

[Frequency shift operation]

  20, FIG. 21 and FIG. 22 show the processing procedure of the frequency shift. This processing procedure is executed at the sampling timing (for example, every 100 [ms]) in FIGS. A, B in FIGS. 20, 21 and 22 show connectors between the flowcharts.

  In this processing procedure, it is determined whether or not the line is being disconnected (S111). If the line is being disconnected (YES in S111), the frequency positive direction divergence counter 98 and the frequency negative direction divergence counter 100 are reset ( a ← 0, b ← 0), the active signal direction fixing flag is turned OFF, the active signal amount fe is returned to 0.1 [Hz] (S112), and this process is terminated. The OFF of the active signal direction fixing flag means that the active signal direction is switched at a constant period.

  If the line is not being disconnected (NO in S111), the current frequency f is detected (S113), and it is determined whether the active signal direction fixing flag is ON (S114). In this case, ON of the active signal direction fixed flag means that the active signal direction is not switched at a constant period. If the active signal fixing flag is ON (YES in S114), it is determined whether or not the current frequency f has changed in the active signal direction (S115).

  If the current frequency f changes in the direction of the active signal (YES in S115), a ← a + 1 is incremented (S116), and it is determined whether a is a predetermined value, for example, 5 or more (S117).

  If a is a predetermined value, for example, 5 or more (YES in S117), it is determined whether or not the current frequency f has diverged more than a certain value (S118). If the current frequency f diverges more than a certain value (YES in S118), it is determined whether a = 6 (S119). If the current frequency f does not diverge more than a certain value (NO in S118), the count value a of the frequency positive direction divergence counter 98 is decremented to a ← a−1 (S120).

  Either the count value a of the frequency positive direction divergence counter 98 is not "5" or more (NO in S117), after decrementing to a ← a-1 (S120), or a ≠ 6 (NO in S119). If there is, + fe or -fe is stored as an active signal, and this process is terminated. If a = 6 (YES in S119), the process is terminated (S122), and this process ends.

If the active signal fixing flag is not ON (NO in S114), it is determined whether or not the value obtained by subtracting the average frequency f _ave from the current frequency f is equal to or greater than a predetermined frequency range ± 0.05 [Hz] (S123). If _ffave is ± 0.05 [Hz] or more (YES in S123), the following processing is performed (S124). In this case, if the frequency fluctuation is +0.05 [Hz] or more, the active signal direction is set to the rising direction, and if the frequency fluctuation is -0.05 [Hz] or less, the active signal direction is set to the decreasing direction. Further, the active signal direction fixing flag is turned ON, and measurement for a certain time is started.

  The count value a of the frequency positive direction divergence counter 98 is incremented to a ← (a + 1) (S125), + fe or −fe is stored as an active signal (S126), and this process is terminated.

If f-f _ave is not ± 0.05 [Hz] or more (NO in S123), it is determined whether or not it is the active signal direction switching period (S127). If it is the active signal direction switching cycle (YES in S127), it is determined whether or not the active signal direction is the upward direction (S128). If the active signal direction is the upward direction (YES in S128), the active signal direction is the downward direction (S129). If the active signal direction is not the upward direction (NO in S128), the active signal direction is the upward direction (S128). S130).

  If it is not the active signal direction switching cycle (NO in S127), + fe or -fe is stored as the active signal as described above (S131), and this process is terminated.

  If the system frequency f does not change in the active signal direction (NO in S115), the count value b of the frequency negative direction divergence counter 100 is incremented to b ← b + 1, and the active signal amount fe is set to 0.2 [Hz]. (S132).

  It is determined whether or not the count value b of the frequency negative direction divergence counter 100 is b = 1 (S133). If b = 1 is not set (NO in S133), b is either b = 2 or b = 4. It is determined whether or not (S134).

  If b is either b = 2 or b = 4 (YES in S134), it is determined whether or not the active signal direction is the upward direction (S135). If the active signal direction is the upward direction (YES in S135), the active signal direction is the downward direction (S136). If the active signal direction is not the upward direction (NO in S135), the active signal direction is the upward direction (S135). S137).

  A ← a + 1 is incremented (S138), and it is determined whether a is a predetermined value, for example, 5 or more (S139). The same applies to the case of b = 1 (YES in S133) in S133.

  If a is a predetermined value, for example, 5 or more (YES in S139), it is determined whether or not the current frequency f has diverged more than a certain value (S140). If the current frequency f diverges above a certain value (YES in S140), it is determined whether a = 6 (S141). If the current frequency f does not diverge more than a predetermined value (NO in S140), the count value a of the frequency positive direction divergence counter 98 is decremented to a ← a−1 (S142).

  If the count value a of the frequency positive direction divergence counter 98 is not 5 or more (NO in S139), or after a decrement to a ← a−1 (S142), or a ≠ 6 (NO in S141) Then, + fe or -fe is stored as an active signal (S143), and this process is terminated. If a = 6 (YES in S141), the process is terminated (S144), and the process ends.

  If b is neither b = 2 nor b = 4 (NO in S134), the elapse of a certain time is judged (S145), and if the certain time elapses (YES in S145), the active signal direction fixing flag is turned OFF. The active signal amount fe is returned to 0.1 [Hz] (S146). After this process or if a certain time has not elapsed (NO in S145), + fe or -fe is stored as an active signal as described above (S147), and this process is terminated.

[Other Embodiments]

  FIG. 23 shows another embodiment of the periodic process. In this processing procedure, periodic processing is performed in units of 1 [msec].

  In this processing procedure, it is determined whether or not the zero-cross detection flag is ON (S201). If the zero-cross detection flag is ON (YES in S201), the zero-cross detection flag is cleared (S202), and 100 [μsec]. The number of interruptions is stored in array A (S203). The system voltage 1 cycle time T can be obtained from the number of interruptions × 100 [μsec].

Among the past 12 frequency detections, the total value of the number of interruptions of 100 [μsec] for the remaining 10 times with the maximum value and the minimum value cut is calculated (S204). This total number of interrupts corresponds to the average value T _ave for one cycle time. The current frequency is calculated from the total number of interrupts (S205). Then, the amount of phase addition is calculated from the total number of interrupts (S206), and this process ends.

  In step S201, if the zero cross detection flag is not ON, this process is terminated.

  FIG. 24 shows another embodiment of the periodic process. In this processing procedure, periodic processing is performed in units of 100 [μsec].

  In this processing procedure, the number of interruptions of 100 [μsec] is incremented by 1 (S211). This corresponds to counting the elapsed time from the up cross. Current phase update processing is performed (S212). In this current phase update process, (1) a phase addition amount is added, and (2) an active signal determined by the frequency process of FIGS.

  Then, the system voltage value is acquired (S213), and it is determined whether or not the down cross has been detected (S214). If the down cross has been detected (YES in S214), it is determined whether or not the system voltage is a positive value for four consecutive times (S215).

  If the system voltage is a positive value for four consecutive times (YES in S215), down cross detection is not performed (S216), and the zero cross detection flag is turned ON (S217). The number of 100 [μsec] interrupts is stored in the buffer of the RAM 34 (S218), the number of 100 [μsec] interrupts is cleared to 0 (S219), the phase is reset (S220), and this process is terminated.

  In step S214, if a down cross has not been detected (NO in S214), it is determined whether or not the system voltage is a negative value for four consecutive times (S221). If the system voltage is a negative value for four consecutive times (YES in S221), the down cross is detected (S222), and this process is terminated.

  In step S215, if the system voltage is not a positive value for four consecutive times (NO in S215), or if the system voltage is not a negative value in four consecutive times in step S221 (NO in S221), the process is terminated. To do.

  Even using such a processing procedure, it is possible to perform processing of the distributed power supply apparatus, its control program, and its control method similar to those of the above-described embodiment.

[Other Embodiments]

  (1) In the above embodiment, an array is shown as an example of a data structure for obtaining frequency fluctuations. However, the data structure for obtaining frequency fluctuations may be other than the array.

  (2) Although the arrays A, B and C are stored in the RAM 34, the final data may be stored in the EEPROM 32 from the RAM 34 when the power is shut off, and the data in the EEPROM 32 may be used as the initial value at the start.

As described above, the most preferable embodiment and the like of the present invention have been described. However, the present invention is not limited to the above description, and is described in the claims or disclosed in the specification. It goes without saying that various modifications and changes can be made by those skilled in the art based on the above gist, and such modifications and changes are included in the scope of the present invention.

The present invention relates to a distributed power supply or a power supply system including a distributed power supply that determines whether or not isolated operation is performed by a frequency shift method. Realize driving.

DESCRIPTION OF SYMBOLS 2 Distributed type power supply device 4 Electric power source 6 Load 8 Circuit breaker 10 Commercial power supply system 12 Rectifier 14 Booster circuit 16 FET bridge circuit 18 Filter 20 Switch 22 Controller 24 Processor 26 IO port 28 AD converter 30 ROM
32 EEPROM
34 RAM
Reference Signs List 36 Clock oscillator 37 Alarm 42 Engine 44 Generator 46 Exhaust path 48 Exhaust heat exchanger 50 Exhaust heat recovery path 52 Exhaust heat recovery heat exchanger 54 Surplus power heater 56 Frequency detection means 58 Output frequency determination means 60 Output current control means 62 Period timer 64 Isolated operation detection unit 66 Isolated operation determination unit 68 Active signal determination unit 84 Current detection unit 86, 88 Contact 90 Electromagnetic solenoid 92 Voltage detection unit

Claims (3)

Opening and closing to generate AC output upon receiving power supply from a power source, close the parallel power supply to supply the AC output to the commercial power supply system and the load, and open when disconnected to cut off the supply to the commercial power supply system and the load Means,
A predetermined number of grid voltage frequencies acquired for each cycle are stored, and an average sub-frequency calculated by averaging the frequencies for a predetermined cycle from the oldest stored frequency is taken every predetermined time, and this predetermined time Storage means for storing an average frequency calculated by averaging the average sub-frequency for each;
Give an active signal whose polarity changes every predetermined time to give a frequency change to the system voltage,
When the difference between the frequency of the system voltage and the average frequency changes to a predetermined value or more, the increase or decrease of the frequency change is fixed for a predetermined time to monitor the increase or decrease of the system voltage frequency, and the detected frequency change is detected. A determination means for determining that the vehicle is operating independently when the state exceeding the predetermined range continues;
Control means for opening and closing the opening and closing means according to the determination result of the determination means that it is a single operation, and controlling from the parallel to the disconnection,
A distributed power supply device comprising: Opening and closing to generate AC output upon receiving power supply from a power source, close the parallel power supply to supply the AC output to the commercial power supply system and the load, and open when disconnected to cut off the supply to the commercial power supply system and the load A control program for a distributed power supply device comprising means for a computer mounted on the distributed power supply device,
Store a predetermined number of grid voltage frequencies acquired for each cycle in the storage means, and take in the average sub-frequency calculated by averaging the frequency for a predetermined cycle from the oldest stored frequency every predetermined time, a function of storing average frequency of calculation of the average sub-frequency in each predetermined time on average the Symbol 憶手 stage,
A function of giving an active signal whose polarity changes every predetermined time to give a frequency change to the system voltage;
A function of monitoring the increase or decrease in the frequency of the system voltage by fixing the increase or decrease in the frequency change for a predetermined time when the difference between the frequency of the system voltage and the average frequency is changed to a predetermined value or more;
A function that determines that the operation is being performed independently when the detected frequency change exceeds a predetermined range; and
Is realized by the computer. A control program for a distributed power supply apparatus. A process of generating an AC output by receiving power supply from a power source, closing in parallel and supplying the AC output to a commercial power supply system and a load, and opening in disconnection to cut off supply to the commercial power supply system and the load When,
Store a predetermined number of grid voltage frequencies acquired for each cycle in the storage means, and take in the average sub-frequency calculated by averaging the frequency for a predetermined cycle from the oldest stored frequency every predetermined time, a step of storing the average frequency of calculation of the average sub-frequency in each predetermined time on average the Symbol 憶手 stage,
A frequency change is applied to the system voltage by applying an active signal whose polarity changes every predetermined time, and when the difference between the frequency of the system voltage and the average frequency changes to a predetermined value or more, the frequency changes for a predetermined time. Monitoring the increase or decrease of the system voltage frequency while fixing the increase or decrease of the system voltage, and determining that the operation is isolated when the detected frequency change exceeds the predetermined range; and
A step of controlling from the parallel to the disengagement according to the determination result that it is an isolated operation;
A control method for a distributed power supply apparatus, comprising:

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