JP5958390B2 - Voltage conversion circuit and overvoltage protection method - Google Patents

Description

  The present invention relates to a voltage conversion circuit that steps down or boosts a voltage of a power supply by a voltage induced in an inductor, and an overvoltage protection method in the voltage conversion circuit.

  Conventionally, as a non-insulated power circuit for converting DC voltage, a step-down type (buck type) or a boost type (boost) that uses a voltage induced in an inductor when a DC voltage on the input side is turned on / off by a semiconductor switch. Type) DC-DC converters are widely used. For example, in the case of a synchronous rectification type DC-DC converter that steps down (or boosts) a voltage, a high-side (or low-side) semiconductor switch turns on / off current flowing in an inductor, and a low-side (or high-side) semiconductor switch Circulates the current flowing through the inductor.

  For example, in a step-down DC-DC converter, when the high-side semiconductor switch continues to be conductive due to a short circuit or the like, the DC voltage on the input side continues to be applied to one end of the inductor, and the voltage on the output side Rises excessively. In addition, for example, when the control for turning on / off the low-side and / or high-side semiconductor switch becomes temporarily abnormal, the voltage on the output side may become excessive.

  On the other hand, in Patent Document 1, when the output-side voltage becomes higher than a predetermined threshold level, the low-side semiconductor switch is kept on so that the high-side semiconductor switch is turned on. A step-up DC-DC converter is disclosed in which a fuse on the side is blown to prevent an overvoltage on the output side (see the left column on page 10 and FIG. 9).

  Further, in Patent Document 2, when the output voltage is in an overvoltage state, the high-side and low-side semiconductor switches are forcibly controlled to be turned on so that they are connected in series. A step-down DC-DC converter is disclosed in which an input side fuse is blown to prevent an output side overvoltage (see paragraph [0006] and FIG. 1).

Japanese Patent Publication No. 8-32162 Japanese Patent No. 3349897

  However, with the technology disclosed in Patent Documents 1 and 2, in the configuration in which the fuse on the input side is blown by continuously turning on the low-side semiconductor switch when an overvoltage is detected, a storage circuit including a secondary battery or the like is connected on the output side In such a case, there is a problem that current flows backward from the output side to the low-side semiconductor switch and the power supply voltage on the output side abnormally decreases.

  The present invention has been made in view of such circumstances, and its object is to detect an output-side (or input-side) overvoltage and shut off the input-side (or output-side) circuit. An object of the present invention is to provide a voltage conversion circuit and an overvoltage protection method capable of preventing a voltage drop on the side.

A voltage conversion circuit according to the present invention includes a first switching element that switches a current flowing from a power source to an inductor, and a second switching element that circulates a current flowing through the inductor during an off period of the first switching element, In a voltage conversion circuit that steps down (or boosts) the voltage of the power source by a voltage induced in an inductor and supplies the voltage to a power storage circuit, the current circuit is cut off by a current flowing through the circuit from the power source (or to the power storage circuit) Unit, a switch that opens and closes the electric circuit to (or from the power supply), a comparison unit that compares the reduced voltage (or the voltage of the power supply) and a predetermined first voltage, and the reduced voltage (or the A second comparison unit that compares a second voltage lower than the first voltage, a reduced voltage (or the voltage of the power supply), and And a third comparator for comparing the lower third voltage than the second voltage, the comparison result of the comparison unit, if the stepped-down voltage (or voltage of the power supply) is higher than the first voltage, the second 2 The switching element (or the first switching element) is turned on and the switch is opened, and the comparison result of the second comparison unit is that the stepped down voltage (or the voltage of the power supply) is equal to or higher than the second voltage. In some cases, the first switching element (or the second switching element) is turned off, and the comparison result of the third comparison unit indicates that the stepped down voltage (or the voltage of the power supply) is equal to or lower than the third voltage. , characterized in that you have to so that to release the off state.

  The voltage conversion circuit according to the present invention further includes a fourth comparison unit that compares the stepped down voltage (or the stepped up voltage) and a fourth voltage lower than a target voltage to be supplied to the power storage circuit. When the comparison result of the comparison unit indicates that the stepped down voltage (or the stepped up voltage) is lower than the fourth voltage, the ON state is released.

  The voltage conversion circuit according to the present invention further includes a current detector that detects a current flowing through the interrupting unit, and releases the on-state when the current detected by the current detector is less than a predetermined current. It is characterized by that.

  The voltage conversion circuit according to the present invention further includes a notification unit that performs predetermined notification when the switch is opened.

The overvoltage protection method according to the present invention includes a first switching element that switches a current flowing from a power source to an inductor, and a second switching element that circulates a current flowing through the inductor during an off period of the first switching element, In the overvoltage protection method in the voltage conversion circuit that steps down (or steps up) the voltage of the power source by the voltage induced in the inductor and supplies the voltage to the power storage circuit, the current path is generated by a current flowing through the circuit from the power source (or to the power storage circuit). And a switch that opens and closes the electric circuit to (or from the power source) the power storage circuit, compares the stepped down voltage (or the voltage of the power source) with a predetermined first voltage, and compares the results. However, when the stepped down voltage (or the voltage of the power source) is higher than the first voltage, the second switching element (or the first switching element). Switching element) is opened the switch while the ON state, the voltage of the stepped-down voltage (or the power), and comparing the first lower than the voltage second voltage comparison result, the step-down the voltage (or the When the voltage of the power supply is equal to or higher than the second voltage, the first switching element (or the second switching element) is turned off, and the stepped down voltage (or the voltage of the power supply) and the second voltage lower than the second voltage are set. 3 compares the voltage comparison result, if the stepped-down voltage (or voltage of the power supply) is equal to or less than the third voltage, it characterized that you release the off state.

  In the present invention, the first switching element connected between the external power supply and one end of the inductor is turned on / off to switch the current flowing from the power supply to the inductor, and the inductor is switched off during the off period of the first switching element. By turning on the second switching element connected to one end of the inductor and causing the current flowing through the inductor to flow back from the second switching element, the voltage obtained by subtracting the voltage induced in the inductor from the voltage of the power source is reduced to the other end of the inductor From the power source to the inductor by switching on and off the first switching element connected to the other end of the inductor to which the voltage of the external power source is once applied. The second switching element connected between the other end of the inductor and the storage circuit during the OFF period of the switching element The turned on by refluxing the current flowing through the inductor to the storage circuit and supplies the voltage boosted by adding a voltage induced in the inductor to the voltage of the power supply to the storage circuit from the second switching element).

Meanwhile, when the stepped-down voltage (or power supply voltage) exceeds the control target voltage (or original power supply voltage) and becomes higher than the first voltage, the second switching element (or first switching element) is forcibly forced. In addition to turning on the switch, the switch that opens and closes the electric circuit to the storage circuit (or from the power supply) is opened.
That is, when the output side (or input side) voltage becomes an overvoltage, the first switching element (or the second switching element) may be short-circuited, so the second switching element (or the first switching element). Is forcibly turned on. Furthermore, in order to block the current flowing from the power storage circuit (or power supply) into the second switching element (or first switching element) via the inductor, the switch is opened to disconnect the power storage circuit (or power supply).

In the present invention, when the stepped down voltage (or power supply voltage) is equal to or higher than the second voltage lower than the first voltage, the first switching element (or second switching element) is forcibly turned off, and then When the stepped down voltage (or the voltage of the power supply) drops below a third voltage lower than the second voltage, the off state of the first switching element (or the second switching element) is released.
That is, when the voltage on the output side (or input side) becomes an overvoltage, the step-down operation is temporarily stopped by forcibly turning off the first switching element (or the second switching element) first (or The voltage boosting operation is temporarily stopped and the storage circuit is disconnected). After that, when the voltage on the output side (or input side) decreases and the overvoltage is eliminated, the forced switching off state of the first switching element (or the second switching element) is canceled and the step-down operation (or step-up operation) is performed. To resume.

In the present invention, when the stepped down voltage (or stepped up voltage) becomes lower than the fourth voltage that is lower than the target voltage to be supplied to the power storage circuit, the second switching element (or the first switching element) is forced. To cancel the on-state.
That is, when the voltage on the output side further falls below, for example, the fourth voltage that cannot be lower than that unless the shut-off unit is activated, the control for operating the shut-off unit is terminated.

In the present invention, when the current flowing through the interrupting portion becomes smaller than a predetermined current, the forced on state of the second switching element (or the first switching element) is canceled.
That is, for example, when the current flowing through the interrupting unit becomes smaller than a predetermined current that does not become lower unless the interrupting unit is activated, the control for operating the interrupting unit is terminated.

  In the present invention, when the switch for opening and closing the electric circuit to (or from the power supply) is opened, the user is informed that irreversible overvoltage protection has been started by performing a predetermined notification. .

According to the present invention, when the voltage on the output side (or input side) becomes an overvoltage, the first switching element (or the second switching element) may be short-circuited, so the second switching element (or the second switching element) 1 switching element) is forcibly turned on. In this case, in order to prevent the current flowing from the power storage circuit (or power supply) to the first switching element (or second switching element) via the inductor, the switch is opened to disconnect the power storage circuit (or power supply).
Therefore, when an overvoltage on the output side (or input side) is detected and the input side (or output side) circuit is shut off, it is possible to prevent a voltage drop on the output side.

It is a circuit diagram which shows the structure of the voltage converter circuit which concerns on Embodiment 1 of this invention. It is a wave form diagram which shows a simulation result in case the output voltage of a voltage converter circuit fluctuates temporarily. It is explanatory drawing which shows typically the time change of the output voltage in the case of performing control which prevents an overvoltage. It is a flowchart which shows the process sequence of the control circuit which performs the control which concerns on overvoltage protection in the voltage converter circuit which concerns on Embodiment 1 of this invention. It is a flowchart which shows the process sequence of the control circuit which performs control which concerns on the overvoltage protection in the voltage converter circuit which concerns on the modification 1 of Embodiment 1 of this invention. It is a circuit diagram which shows the structure of the voltage converter circuit which concerns on Embodiment 2 of this invention. It is a flowchart which shows the process sequence of the control circuit which performs control which concerns on overvoltage protection in the voltage converter circuit which concerns on Embodiment 2 of this invention. It is a flowchart which shows the process sequence of the control circuit which performs control which concerns on the overvoltage protection in the voltage converter circuit which concerns on the modification 2 of Embodiment 2 of this invention.

Hereinafter, the present invention will be described in detail with reference to the drawings illustrating embodiments thereof.
(Embodiment 1)
FIG. 1 is a circuit diagram showing a configuration of a voltage conversion circuit according to Embodiment 1 of the present invention. In the figure, reference numeral 1 denotes a voltage conversion circuit. The voltage conversion circuit 1 steps down the voltage of the power supply 3 applied from the input terminals 10a and 10b and supplies the voltage from the output terminals 19a and 19b to the power storage circuit 5 including the secondary battery. .

  The voltage conversion circuit 1 includes a first switching element (hereinafter referred to as a first FET) composed of an N-channel MOSFET whose drain is connected to an input terminal 10a through a fuse (breaking unit) 11 that is blown by a current flowing through an electric path from a power source 3. 12), an inductor 13 having one end connected to the source of the first FET 12, and a second switching element (hereinafter referred to as a second FET) 14 made of a MOSFET having a drain connected to the source of the first FET 12. The first FET 12 and the second FET 14 may be P-channel MOSFETs or other switching elements such as bipolar transistors. The fuse 11 may be a current breaker such as a no-fuse breaker (the same applies hereinafter). The other end of the inductor 13 is connected to an output terminal 19a via a switch 15 formed of a MOSFET that opens and closes an electric path to the power storage circuit 5. The switch 15 may be a relay switch having a mechanical contact. A smoothing capacitor 16 is connected between the other end of the inductor 13 and a ground potential (common potential). The source of the second FET 14 is connected to the ground potential.

  The electric path from the power source 3 is a circuit portion in which substantially the same current flows between the power source 3 and specifically, from the input terminal 10a, one end of the inductor 13, the source of the first FET 12, and the first It refers to the circuit part up to the connection node of the drain of 2FET14. Therefore, the fuse 11 may be interposed, for example, between the source of the first FET 12 and the connection node. On the other hand, the electric circuit to the electric storage circuit 5 is a circuit portion through which an electric current having substantially the same magnitude as the electric storage circuit 5 (excluding the electric current flowing into and out of the smoothing capacitor 16 and the electric current flowing into the resistor 22) flows. Specifically, it refers to the electric circuit from the connection node to the output terminal 19a. Therefore, the switch 15 may be interposed, for example, between the connection node and one end of the inductor 13.

  The voltage conversion circuit 1 also includes a control unit 2 having a control circuit 21. As a method for configuring the control circuit 21, there are a method including a CPU and a method including a logic circuit. Hereinafter, a method including a CPU will be described. The signal input terminal of the control unit 2 is detected by the current detector 24 that detects the divided voltage of the resistors 22 and 23 connected in series between the other end of the inductor 13 and the ground potential and the current flowing through the fuse 11. A detection signal is provided. The signal output terminal of the control unit 2 is connected to the gates of the first FET 12 and the second FET 14 and the control terminal (gate) of the switch 15. The divided voltage of the resistors 22 and 23 is a voltage proportional to the voltage obtained by stepping down the voltage of the power supply 3.

  The control unit 2 generates a PWM control signal based on the result of comparing the error voltage indicating the difference between the divided voltage of the resistors 22 and 23 and the reference voltage and the internally generated triangular wave, and generates the generated PWM control signal. Each of the inverted signals of the PWM control signal is applied to the gates of the first FET 12 and the second FET 14. As a result, the current flowing from the power source 3 to the inductor 13 is switched by the first FET 12 according to the duty of the PWM control signal, and the current flowing to the inductor 13 is returned from the second FET 14 during the OFF period of the first FET 12. In this way, the voltage obtained by subtracting the voltage induced in the inductor 13 from the voltage of the power supply 3 is supplied to the power storage circuit 5 from the other end of the inductor 13 via the switch 15 and the output terminals 19a and 19b. .

  In addition to the PWM control described above, the control unit 2 controls the first FET 12 to be always in an off state and the control to cancel the off state, the control to always keep the second FET 14 in an on state, and cancels the on state. It is configured to be controllable.

  In the voltage conversion circuit 1 configured as described above, the voltage output from the output terminals 19a and 19b is controlled by the PWM control in the control unit 2 so as to be a constant voltage obtained by stepping down the voltage of the power supply 3. . However, the output voltage (output-side voltage) output from the output terminals 19a and 19b temporarily rises due to the influence of fluctuations in the storage circuit 5 and noise flowing in from the load side (not shown) connected to the storage circuit 5. There is a case.

  FIG. 2 is a waveform diagram showing a simulation result when the output voltage of the voltage conversion circuit 1 temporarily varies. In the figure, the horizontal axis represents time, and the vertical axis represents output voltage. In FIG. 2, the time variation of the output voltage is shown as an example in which an abnormal state in which the first FET 12 is temporarily turned on with a large duty occurs and then the abnormal state is resolved.

  Even when the duty at which the first FET 12 is turned on becomes high, the inductor 13 acts to suppress a rapid increase in the output voltage. Further, as long as the second FET 14 is turned on with an appropriate duty, the second FET 14 acts to periodically lower the output voltage. For this reason, as shown in FIG. 2, the output voltage gradually rises while fluctuating up and down in the PWM control cycle. Thereafter, when the abnormal state related to the duty of the first FET 12 is resolved, the output voltage gradually decreases in accordance with the characteristics of the power storage circuit 5, the current consumed by the load 4, and the like.

Next, the overvoltage protection executed in the first embodiment will be described.
FIG. 3 is an explanatory diagram schematically showing a change over time in the output voltage when control for preventing overvoltage is performed. In the figure, the horizontal axis represents time, and the vertical axis represents output voltage. The solid line in FIG. 3 indicates the output voltage when the fuse 11 is blown to prevent overvoltage, and the alternate long and short dash line indicates the output voltage when the overvoltage is prevented without blowing the fuse 11.

  As shown in FIG. 3, the output voltage according to the target value of PWM control by the control unit 2 fluctuates up and down at a PWM control cycle around a predetermined voltage (target voltage to be supplied to the storage circuit 5) V0. doing. Here, when the output voltage temporarily rises and becomes higher than the voltage V1 (V1> V0) at time t1 due to some factor, there is a possibility that the first FET 12 has a short circuit failure. Therefore, in order to blow the fuse 11, the second FET 14 is forcibly turned on by the control of the control unit 2, and the switch 15 is controlled by the control of the control unit 2 in order to prevent a backflow of current from the power storage circuit 5. Turn off.

  Here, when the first FET 12 is actually short-circuited, overcurrent flows into the second FET 14 from the power supply 3 through the fuse 11 and the first FET 12, but is detected because the on-resistance of the second FET 14 is low. The output voltage is much lower than the voltage V0. Thereafter, when the fuse 11 is blown, the voltage drop in the second FET 14 is reduced, so that the detected output voltage further decreases, and for example, at time t4, the output voltage becomes lower than the voltage V4 that is much lower than the voltage V0. This voltage V4 is a voltage at which the output voltage cannot be lower than that unless the fuse 11 is blown. That is, when the output voltage becomes lower than the voltage V4, it is certain that the fuse 11 has blown, so that the forced ON state of the second FET 14 is canceled under the control of the control unit 2.

  One possible cause for the temporary increase in the output voltage is that the first FET 12 may be short-circuited, while there is a possibility that the on / off control of the first FET 12 can be performed normally. For example, when the output voltage becomes higher than the voltage V2 at time t2 before rising to the voltage V1, the control of the control unit 2 attempts to forcibly turn off the first FET 12 and lower the output voltage. As a result, when the first FET 12 is turned off as controlled and the output voltage drops below the voltage V3 at time t3, the forced off state of the first FET 12 is released under the control of the control unit 2. Thereafter, the first FET 12 and the second FET 14 are repeatedly turned on / off according to the PWM control signal, so that the output voltage is assumed to return to a voltage centered on the voltage V0.

  Note that when the first FET 12 is forcibly turned off, the second FET 14 need not be specially controlled. For example, even when the second FET 14 is forcibly turned off together with the first FET 12, the reflux current of the inductor 13 cannot be prevented from conducting the body diode of the second FET 14. The case where the second FET 14 is forcibly turned on is as described above.

  By the way, when the first FET 12 is short-circuited, the output voltage rises as in the waveform diagram shown in FIG. In this case, it is conceivable that the duty of the PWM control signal for the second FET 14 increases due to the PWM control of the control unit 2 that reduces the output voltage. That is, even if it is left as it is, the first FET 12 and the second FET 14 may be substantially turned on and the fuse 11 may be blown. However, since such PWM control is accompanied by a time delay of several milliseconds, it is not sufficient as overvoltage protection. In the first embodiment, overvoltage protection is performed with a time delay of several μs to several tens μs, for example.

  Below, operation | movement of the control part 2 of the voltage conversion circuit 1 mentioned above is demonstrated using the flowchart which shows it. The processing shown below is executed by the control circuit 21 in accordance with a control program stored in advance in a ROM (not shown) of the control unit 2. Information temporarily generated during execution is stored in a RAM (not shown) of the control unit 2. Also, the voltages V1, V2, V3, and V4 shown in FIG. 3 are referred to as a first voltage, a second voltage, a third voltage, and a fourth voltage, respectively.

  FIG. 4 is a flowchart showing a processing procedure of the control circuit 21 that executes control related to overvoltage protection in the voltage conversion circuit 1 according to the first embodiment of the present invention. The process of FIG. 4 is started, for example, at a period of 50 μs after the control circuit 21 finishes executing the predetermined initialization process, but is not limited to this period. Further, once activated, the control circuit 21 may repeatedly execute the processing of FIG.

  When the process of FIG. 4 is started, the control circuit 21 takes in the divided voltage of the resistors 22 and 23, detects the voltage (that is, the output voltage) obtained by stepping down the voltage of the power supply 3 (S10), and detects it. It is determined whether or not the voltage, that is, the stepped down voltage is equal to or higher than the second voltage lower than the first voltage (S11: second comparison unit). The second voltage here is a voltage higher than a predetermined voltage V0 corresponding to the target value of PWM control (see FIG. 3).

  When the stepped down voltage is equal to or higher than the second voltage (S11: YES), the control circuit 21 forcibly turns off the first FET 12 (S12). In this case, the fact that the first FET 12 is turned off may be stored in the RAM. By doing so, it is possible to skip the process of turning off the first FET 12 when the process of FIG. However, even if the same process is executed a plurality of times in step S12, no particular problem occurs.

  Next, the control circuit 21 compares and determines whether or not the stepped down voltage is higher than the first voltage higher than the second voltage (S13: comparison unit), and if higher than the first voltage (S13: YES), The 2FET 14 is forcibly turned on (S14) and the switch 15 is opened (S15). As a result, on the assumption that the first FET 12 is short-circuited, the fuse 11 is blown and the storage circuit 5 is disconnected. Also in this case, the fact that the second FET 14 is turned on may be stored in the RAM in order to skip the same process at the next activation.

  Thereafter, the control circuit 21 performs a predetermined notification using an external interface (not shown) included in the control unit 2 (S16: notification unit) and notifies the outside that the overvoltage protection for blowing the fuse 11 has been executed. The process of 4 is finished. When the process of step S14 is skipped based on the contents stored in the RAM, the processes of steps S15 and S16 may be skipped.

  In step S11, when the stepped down voltage is not equal to or higher than the second voltage (S11: NO), the control circuit 21 compares and determines whether or not the stepped down voltage is equal to or lower than a third voltage lower than the second voltage ( S17: Third comparison unit) When the voltage is equal to or lower than the third voltage (S17: YES), the forced off state of the first FET 12 is canceled (S18). When the stepped down voltage is not equal to or lower than the third voltage (S17: NO), the control circuit 21 ends the process of FIG. 4 as it is.

  If it is determined in step S12 that the first FET 12 is turned off in the RAM, the first FET 12 is forcibly turned off based on the stored contents of the RAM. What is necessary is just to perform a process. However, even if the same process is executed a plurality of times in step S18, no particular problem occurs.

  When the process of step S18 is completed, the control circuit 21 compares and determines whether or not the reduced voltage is further lower than the fourth voltage that is much lower than the voltage V0 (S19: fourth comparison unit). When the voltage is lower than the fourth voltage (S19: YES), the forced ON state of the second FET 14 is canceled (S20), and the process of FIG. When the stepped down voltage is not lower than the fourth voltage (S19: NO), the control circuit 21 ends the process of FIG. 4 as it is.

  In step S14, if the fact that the second FET 14 is turned on is stored in the RAM, it is determined that the second FET 14 is in a forced on state based on the stored contents of the RAM, and then step S20. It is sufficient to execute the process. However, even if the same process is executed a plurality of times in step S20, no particular problem occurs.

  In the first embodiment, the CPU included in the control circuit 21 executes the comparison determination between the stepped down voltage and each of the first voltage, the second voltage, the third voltage, and the fourth voltage. It is not limited. For example, the stepped-down voltage and the first, second, third, and fourth voltages are compared by a plurality of voltage comparators (comparators), and the forced OFF state of the second FET 14 and You may make it perform setting or cancellation | release about each forced ON state of 1st FET12.

  More specifically, two hysteresis comparators are prepared, and two trip points (threshold values) of one comparator are set as the first voltage and the second voltage, and two trip points of the other comparator are set as the third voltage and the second voltage. Four voltages may be used.

As described above, according to the first embodiment, when the stepped-down voltage exceeds the control target voltage V0 and becomes higher than the first voltage, the second FET 14 is forcibly turned on and the power storage circuit 5 is supplied. The switch 15 for opening and closing the electric circuit is opened.
That is, when the output voltage becomes an overvoltage, the first FET 12 may be short-circuited, so the second FET 14 is forcibly turned on. Furthermore, in order to block the current flowing from the power storage circuit 5 to the second switching element via the inductor 13, the switch 15 is opened to disconnect the power storage circuit 5.
As a result, when the first FET 12 is actually short-circuited, the storage circuit 5 is also disconnected when the fuse 11 is blown by the overcurrent flowing from the power source 3 to the first FET 12 and the second FET 14 and the external power source 3 is disconnected. It is.
Therefore, when the output side overvoltage is detected and the input side circuit is shut off, the output side voltage drop can be prevented.

Further, when the stepped down voltage is equal to or higher than the second voltage lower than the first voltage, the first FET 12 is forcibly turned off, and then the stepped down voltage drops below the third voltage lower than the second voltage. The off state of 1FET12 is cancelled.
That is, when the output voltage becomes an overvoltage, the step-down operation is temporarily stopped by forcibly turning off the first FET 12 first. Thereafter, when the output voltage decreases and the overvoltage is eliminated, the forced off state of the first FET 12 is canceled and the step-down operation is resumed.
Therefore, when the voltage on the output side temporarily becomes excessive, it is possible to automatically recover after trying to suppress the overvoltage.

Furthermore, when the stepped down voltage becomes lower than the fourth voltage, the forced ON state set for the second FET 14 is canceled.
Therefore, when the voltage on the output side further falls below, for example, the fourth voltage that cannot be lowered unless the fuse 11 is blown, the control for blowing the fuse 11 can be terminated.

  Furthermore, when the switch 15 is opened, it is possible to notify the user that the irreversible overvoltage protection that the fuse 11 is blown is started by performing a predetermined notification.

(Modification 1)
In the first embodiment, when the stepped-down voltage becomes lower than the fourth voltage, the forced on state of the second FET 14 is canceled. In the first modification, the current flowing through the fuse 11 is a predetermined current. In this configuration, the second FET 14 is released from the forced on state when the number of the second FETs 14 is decreased.
In the present modification 1, since the same circuit as the voltage conversion circuit 1 in the first embodiment is used except that the current detector 24 not used in the first embodiment is used, the description of the circuit diagram is omitted.

Below, operation | movement of the control part 2 of the voltage conversion circuit 1 which concerns on the modification 1 is demonstrated using the flowchart which shows it. The processing shown below is executed by the control circuit 21 in accordance with a control program stored in advance in a ROM (not shown) of the control unit 2.
FIG. 5 is a flowchart showing a processing procedure of the control circuit 21 that executes control related to overvoltage protection in the voltage conversion circuit 1 according to the first modification of the first embodiment of the present invention. The processing in FIG. 5 is started at a cycle of, for example, 250 μs after the control circuit 21 finishes executing the predetermined initialization processing, but is not limited to this cycle. Of the processing in FIG. 4 in the first embodiment, the processing in steps S19 and S20 for releasing the ON state of the second FET 14 may be executed in parallel with the processing in FIG. 5 or may be skipped. .

  When the processing of FIG. 5 is activated, the control circuit 21 receives the detection signal from the current detector 24 to detect the current flowing through the fuse 11 (S22), and determines whether or not the detected current is less than a predetermined current. Determine (S23). The predetermined current here is a current that cannot be less than that unless the fuse 11 is blown. When the detected current is smaller than the predetermined current (S23: YES), the control circuit 21 cancels the forced ON state of the second FET 14 (S24), and ends the process of FIG. If the detected current is not less than the predetermined current (S23: NO), the control circuit 21 ends the process of FIG. 5 as it is.

  If it is determined in step S14 in the process of FIG. 4 that the second FET 14 is turned on and stored in the RAM, it is determined that the second FET 14 is in a forced on state based on the stored contents of the RAM. Above, the process of step S24 should just be performed. However, even if the same process is executed a plurality of times in step S24, no particular problem occurs.

  In the first modification of the first embodiment, the CPU included in the control circuit 21 executes the comparison determination between the current detected by the current detector 24 and the predetermined current. However, the present invention is not limited to this. . For example, when a signal indicating that the second FET 14 is forcibly turned on is significant, a voltage comparison is made between the voltage corresponding to the detection signal from the current detector 24 and the predetermined voltage corresponding to the predetermined current. And the compulsory ON state of the second FET 14 may be canceled according to the comparison result.

As described above, according to the first modification of the first embodiment, when the current flowing through the fuse 11 becomes smaller than the predetermined current, the forced ON state set for the second FET 14 is canceled.
Therefore, when the current flowing through the fuse 11 becomes smaller than a predetermined current that does not become lower unless the fuse 11 is blown, for example, the control for blowing the fuse 11 can be finished.

(Embodiment 2)
While the first embodiment is a mode in which the voltage conversion circuit 1 steps down the voltage of the power supply 3 and supplies it to the power storage circuit 5, the power storage circuit 5 is protected from overvoltage, whereas the second embodiment is a voltage conversion In this configuration, the power supply 3 is protected from overvoltage while the circuit boosts the voltage of the power supply 3 and supplies it to the power storage circuit 5.
FIG. 6 is a circuit diagram showing a configuration of a voltage conversion circuit according to Embodiment 2 of the present invention. In the figure, reference numeral 1b denotes a voltage conversion circuit. The voltage conversion circuit 1b boosts the voltage of the power supply 3 supplied from the input terminals 10a and 10b, and supplies it from the output terminals 19a and 19b to the power storage circuit 5 including the secondary battery. .

  The voltage conversion circuit 1b includes an inductor 13 having one end connected to the input terminal 10a via a switch 15 that opens and closes an electric path from the power source 3, and a first FET 12 and a second FET 14 each having a drain connected to the other end of the inductor 13. Is provided. The source of the second FET 14 is connected to the output terminal 19 a via a fuse (breaking unit) 11 that is blown by a current flowing through the electric path to the power storage circuit 5. A smoothing capacitor 16 is connected between the source of the second FET 14 and the ground potential. The source of the first FET 12 is connected to the ground potential.

  The electric circuit from the power source 3 is a circuit part through which substantially the same current (excluding the current shunted to the resistor 22) flows between the power source 3 and specifically, from the input terminal 10a, The electric path to the connection node of the other end of the inductor 13, the drain of the first FET 12 and the drain of the second FET 14 is indicated. Therefore, the switch 15 may be interposed, for example, between the other end of the inductor 13 and the connection node. On the other hand, the electric path to the electric storage circuit 5 is a circuit portion through which an electric current of substantially the same magnitude as the electric storage circuit 5 (excluding the electric current flowing into and out of the smoothing capacitor 16 and the electric current dividing into the resistor 25) flows. Specifically, it refers to the electric circuit from the connection node to the output terminal 19a. Therefore, the fuse 11 may be interposed, for example, between the connection node and the drain of the second FET 14.

  The voltage conversion circuit 1 b also includes a control unit 2 having a control circuit 21. The signal input terminal of the control unit 2 has a detection detected by the current detector 24 that detects the divided voltage of the resistors 25 and 26 connected in series between the source of the second FET 14 and the ground potential and the current flowing through the fuse 11. A signal and a divided voltage of resistors 22 and 23 connected in series between one end of the inductor 13 and the ground potential are applied. The signal output terminal of the control unit 2 is connected to the gates of the first FET 12 and the second FET 14 and the control terminal (gate) of the switch 15. The divided voltage of the resistors 25 and 26 is a voltage proportional to the voltage obtained by boosting the voltage of the power supply 3.

  The control unit 2 generates a PWM control signal based on the result of comparing the error voltage indicating the difference between the divided voltage of the resistors 25 and 26 and the reference voltage and the internally generated triangular wave, and generates the generated PWM control signal. Each of the inverted signals of the PWM control signal is applied to the gates of the first FET 12 and the second FET 14. Thereby, the current flowing from the power source 3 to the inductor 13 is switched by the first FET 12 according to the duty of the PWM control signal, and the current flowing to the inductor 13 is returned to the power storage circuit 5 during the OFF period of the first FET 12. In this way, the voltage boosted by adding the voltage induced in the inductor 13 to the voltage of the power supply 3 is supplied from the source of the second FET 14 to the power storage circuit 5 via the fuse 11 and the output terminals 19a and 19b.

  In the control unit 2, regardless of the PWM control described above, the control to always turn on the first FET 12 and the control to release the on state, the control to always turn off the second FET 14 and the off state are released. It is configured to be controllable.

  In the voltage conversion circuit 1b configured as described above, the voltage output from the output terminals 19a and 19b is controlled by the PWM control in the control unit 2 so as to become a constant voltage obtained by boosting the voltage of the power supply 3. . However, the voltage of the power source 3 (input side voltage) at the input terminals 10a and 10b temporarily rises due to the influence of fluctuations in the storage circuit 5 and noise flowing in from the load side (not shown) connected to the storage circuit 5. There is a case.

  For example, when the second FET 14 is short-circuited and current flows backward from the power storage circuit 5 to the power supply 3, the inductor 13 acts to suppress a rapid increase in the voltage of the power supply 3. Further, as long as the first FET 12 is turned on with an appropriate duty, the first FET 12 acts to periodically lower the voltage of the power supply 3. For this reason, it is assumed that the voltage of the power source 3 gradually increases while fluctuating up and down in the PWM control cycle as in the waveform diagram shown in FIG.

Next, overvoltage protection executed in the second embodiment will be described. An explanatory diagram schematically showing the time change of the voltage of the power supply 3 is the same as that in FIG. 3 in the first embodiment, and will be described with reference to FIG. However, the output voltage on the vertical axis in FIG. In addition, since the current supplied from the power source 3 fluctuates in the PWM control cycle in the control unit 2, the voltage of the power source 3 is read as fluctuating in the PWM control cycle. Further, the voltage V0 is read as a predetermined voltage corresponding to the rated voltage of the power source 3.
Note that the voltage V4 at time t4 after time t3 is used herein to mean output voltage.

  As shown in FIG. 3 which has been replaced, when the voltage of the power supply 3 temporarily rises for some reason and becomes higher than the voltage V1 (V1> V0) at time t1, there is a possibility that the second FET 14 has a short circuit failure. is there. Therefore, in order to blow the fuse 11, the first FET 12 is forcibly turned on by the control of the control unit 2, and the switch 15 is controlled by the control of the control unit 2 to prevent inflow of current from the power source 3. Turn off.

  Here, when the second FET 14 is actually short-circuited, an overcurrent flows into the first FET 12 from the power storage circuit 5 via the fuse 11 and the second FET 14, but is detected because the on-resistance of the first FET 12 is low. The output voltage is much lower than the voltage V0. Thereafter, when the fuse 11 is blown, the voltage drop in the first FET 12 is reduced, so that the detected output voltage is further reduced. For example, the output voltage is much lower than the target voltage to be supplied to the storage circuit 5 at time t4. It becomes lower than the voltage V4 (fourth voltage). This voltage V4 is a voltage at which the output voltage cannot be lower than that unless the fuse 11 is blown. That is, when the output voltage becomes lower than the voltage V4, it is certain that the fuse 11 has blown, so that the forced ON state of the first FET 12 is canceled under the control of the control unit 2.

  One possible cause of the temporary increase in the output voltage is that the second FET 14 may have a short circuit failure, and there is a possibility that the on / off control of the second FET 14 can be performed normally. For example, when the output voltage becomes higher than the voltage V2 at time t2 before rising to the voltage V1, the second FET 14 is forcibly turned off and the voltage of the power supply 3 is lowered by the control of the control unit 2. Try. As a result, when the second FET 14 is turned off as controlled and the voltage of the power supply 3 is reduced to the voltage V2 or less at time t2, the forced off state of the second FET 14 is canceled by the control of the control unit 2. Thereafter, the first FET 12 and the second FET 14 are repeatedly turned on / off according to the PWM control signal, so that the voltage of the power supply 3 is assumed to return to a voltage centered on the voltage V0.

  Note that when the second FET 14 is forcibly turned off, another control may be performed on the first FET 12. For example, when the first FET 12 is forcibly turned off together with the second FET 14, switching of the current flowing through the inductor 13 can be completely stopped. The case where the first FET 12 is forcibly turned on is as described above.

  By the way, when the second FET 14 is short-circuited, the current flows backward from the power storage circuit 5 to the power source 3, so that the output voltage supplied to the power storage circuit 5 decreases. In this case, it is conceivable that the duty of the PWM control signal for the first FET 12 increases due to the PWM control of the control unit 2 that increases the output voltage. That is, even if it is left as it is, the first FET 12 and the second FET 14 may be substantially turned on and the fuse 11 may be blown. However, since such PWM control is accompanied by a time delay of several milliseconds, it is not sufficient as overvoltage protection. In the first embodiment, overvoltage protection is performed with a time delay of several μs to several tens μs, for example.

  Below, operation | movement of the control part 2 of the voltage conversion circuit 1b mentioned above is demonstrated using the flowchart which shows it. The processing shown below is executed by the control circuit 21 in accordance with a control program stored in advance in a ROM (not shown) of the control unit 2. Information temporarily generated during execution is stored in a RAM (not shown) of the control unit 2. Information temporarily generated during execution is stored in a RAM (not shown) of the control unit 2. Further, the read voltages V1, V2, and V3 shown in FIG. 3 are referred to as a first voltage, a second voltage, and a third voltage, respectively.

  FIG. 7 is a flowchart showing a processing procedure of the control circuit 21 that executes control related to overvoltage protection in the voltage conversion circuit 1b according to the second embodiment of the present invention. The process of FIG. 7 is started, for example, at a cycle of 50 μs after the control circuit 21 finishes executing the predetermined initialization process, but is not limited to this cycle. Further, once activated, the control circuit 21 may repeatedly execute the processing of FIG.

  When the processing of FIG. 7 is started, the control circuit 21 takes in the divided voltages of the resistors 22 and 23, detects the voltage of the power supply 3 supplied from the input terminals 10a and 10b (S30), and detects the detected voltage. That is, it is determined whether or not the voltage of the power source 3 is equal to or higher than the second voltage lower than the first voltage (S31: second comparison unit). The second voltage here is a voltage higher than a predetermined voltage V0 corresponding to the rated voltage of the power supply 3 (see FIG. 3).

  When the voltage of the power source 3 is equal to or higher than the second voltage (S31: YES), the control circuit 21 forcibly turns off the second FET 14 (S32). In this case, the fact that the second FET 14 is turned off may be stored in the RAM. By doing so, it is possible to skip the process of turning off the second FET 14 when the process of FIG. However, even if the same process is executed a plurality of times in step S32, no particular problem occurs.

  Next, the control circuit 21 compares and determines whether or not the voltage of the power source 3 is higher than the first voltage higher than the second voltage (S33: comparison unit). If the voltage is higher than the first voltage (S33: YES), The first FET 12 is forcibly turned on (S34) and the switch 15 is opened (S35). Thereby, on the assumption that the second FET 14 is short-circuited, the fuse 11 is blown and the power source 3 is disconnected. Also in this case, the fact that the first FET 12 is turned on may be stored in the RAM in order to skip the same process at the next startup.

  Thereafter, the control circuit 21 performs a predetermined notification using an external interface (not shown) included in the control unit 2 (S36: notification unit), and notifies the outside that the overvoltage protection for fusing the fuse 11 has been executed. The process of 7 is finished. When the process of step S34 is skipped based on the contents stored in the RAM, the processes of steps S35 and S36 may be skipped.

  When the voltage of the power source 3 is not equal to or higher than the second voltage in step S31 (S31: NO), the control circuit 21 compares and determines whether or not the voltage of the power source 3 is equal to or lower than the third voltage lower than the second voltage. If it is equal to or lower than the third voltage (S37: YES), the forced off state of the second FET 14 is canceled (S38). When the voltage of the power supply 3 is not less than or equal to the third voltage (S37: NO), the control circuit 21 ends the process of FIG. 7 as it is.

  If it is determined in step S32 that the second FET 14 is turned off in the RAM, the second FET 14 is forcibly turned off based on the stored contents of the RAM. What is necessary is just to perform a process. However, even if the same processing is executed a plurality of times in step S38, no particular problem occurs.

  When the process of step S38 is completed, the control circuit 21 takes in the divided voltage of the resistors 25 and 26 and detects the voltage obtained by boosting the voltage of the power source 3 (that is, the output side voltage) (S39). Whether or not the boosted voltage, that is, the boosted voltage is further lower than the fourth voltage that is much lower than the target voltage to be supplied to the storage circuit 5 (S40: fourth comparison unit), If it is lower (S40: YES), the forcible ON state of the first FET 12 is released (S41), and the process of FIG. 7 is terminated. When the boosted voltage is not lower than the fourth voltage (S40: NO), the control circuit 21 ends the process of FIG. 7 as it is.

  In step S34, if the fact that the first FET 12 is turned on is to be stored in the RAM, it is determined that the first FET 12 is in the forced on state based on the stored contents of the RAM, and then step S40. It is sufficient to execute the process. However, even if the same process is executed a plurality of times in step S40, no particular problem occurs.

  In the second embodiment, the control circuit 21 includes the comparison determination of the voltage of the power supply 3 and the first voltage, the second voltage, and the third voltage, and the comparison determination of the boosted voltage and the fourth voltage. Although it is executed by the CPU, the present invention is not limited to this, and voltage determination may be performed using a plurality of voltage comparators.

  In addition, the same code | symbol is attached | subjected to the location corresponding to Embodiment 1, and the detailed description is abbreviate | omitted.

As described above, according to the second embodiment, when the voltage of the power supply 3 exceeds the predetermined voltage V0 corresponding to the rated voltage and becomes higher than the first voltage, the first FET 12 is forcibly turned on. At the same time, the switch 15 for opening and closing the electric path from the power source 3 is opened.
That is, when the voltage of the power supply 3 becomes an overvoltage, the second FET 14 may be short-circuited, so the first FET 12 is forcibly turned on. Further, in order to prevent a current flowing from the power source 3 to the first switching element via the inductor 13, the switch 15 is opened to disconnect the power source 3.
Thereby, when the second FET 14 is actually short-circuited, the power source 3 is also disconnected when the fuse 11 is blown by the overcurrent flowing from the power storage circuit 5 to the second FET 14 and the first FET 12 and the power storage circuit 5 is disconnected. .
Therefore, when the output side overvoltage is detected and the input side circuit is shut off, the output side voltage drop can be prevented.

Further, when the voltage of the power supply 3 is equal to or higher than the second voltage lower than the first voltage, the second FET 14 is forcibly turned off, and then the stepped-down voltage drops below the third voltage lower than the second voltage. The off state of the second FET 14 is released.
That is, when the power supply 3 becomes overvoltage, first, the second FET 14 is forcibly turned off to temporarily stop the boosting operation and disconnect the power storage circuit 5. After that, when the voltage of the power supply 3 decreases and the overvoltage is eliminated, the forced off state of the second FET 14 is canceled and the boosting operation is resumed.
Therefore, when the voltage on the input side temporarily becomes excessive, it is possible to automatically recover after trying to suppress the overvoltage.

Further, when the boosted voltage becomes lower than the fourth voltage, the forced ON state set for the first FET 12 is canceled.
Therefore, when the voltage on the output side further falls below, for example, the fourth voltage that cannot be lowered unless the fuse 11 is blown, the control for blowing the fuse 11 can be terminated.

  Furthermore, when the switch 15 is opened, it is possible to notify the user that the irreversible overvoltage protection that the fuse 11 is blown is started by performing a predetermined notification.

(Modification 2)
In the second embodiment, the forced on state of the first FET 12 is canceled when the boosted voltage is lower than the fourth voltage. In the second modification, the current flowing through the fuse 11 is a predetermined current. This is a mode in which the forcible ON state of the first FET 12 is canceled when the number is smaller.
In the second modification, the same circuit as the voltage conversion circuit 1b in the first embodiment is used except that the current detector 24 that is not used in the second embodiment is used, and thus the description of the circuit diagram is omitted.

Below, operation | movement of the control part 2 of the voltage conversion circuit 1b which concerns on the modification 2 is demonstrated using the flowchart which shows it. The processing shown below is executed by the control circuit 21 in accordance with a control program stored in advance in a ROM (not shown) of the control unit 2.
FIG. 8 is a flowchart showing a processing procedure of the control circuit 21 that executes control related to overvoltage protection in the voltage conversion circuit 1b according to the second modification of the second embodiment of the present invention. The process of FIG. 8 is started after the control circuit 21 finishes executing the predetermined initialization process, for example, at a cycle of 250 μs, but is not limited to this cycle. Of the processing of FIG. 7 in the second embodiment, the processing of steps S39 to S41 for releasing the ON state of the first FET 12 may be executed in parallel with the processing of FIG. 8 or may be skipped. .

  When the process of FIG. 8 is started, the control circuit 21 receives the detection signal from the current detector 24 to detect the current flowing through the fuse 11 (S42), and determines whether or not the detected current is smaller than a predetermined current. Determine (S43). The predetermined current here is a current that cannot be less than that unless the fuse 11 is blown. When the detected current is smaller than the predetermined current (S43: YES), the control circuit 21 cancels the forced ON state of the first FET 12 (S44) and ends the process of FIG. If the detected current is not less than the predetermined current (S43: NO), the control circuit 21 ends the process of FIG. 8 as it is.

  If it is determined in step S34 in the process of FIG. 7 that the first FET 12 is turned on and stored in the RAM, it is determined that the first FET 12 is in the forced on state based on the stored contents of the RAM. Above, the process of step S44 should just be performed. However, even if the same processing is executed a plurality of times in step S44, no particular problem occurs.

  In the second modification of the second embodiment, the control circuit 21 performs the comparison determination between the current detected by the current detector 24 and the predetermined current. However, the present invention is not limited to this. For example, when a signal indicating that the first FET 12 is forcibly turned on is significant, the voltage corresponding to the detection signal from the current detector 24 is compared with the predetermined voltage corresponding to the predetermined current. And the forced on-state of the first FET 12 may be canceled according to the comparison result.

As described above, according to the second modification of the second embodiment, when the current flowing through the fuse 11 becomes smaller than the predetermined current, the forced ON state set for the first FET 12 is canceled.
Therefore, when the current flowing through the fuse 11 becomes smaller than a predetermined current that does not become lower unless the fuse 11 is blown, for example, the control for blowing the fuse 11 can be finished.

  The embodiment disclosed this time is to be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the meanings described above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims. In addition, the technical features described in each embodiment can be combined with each other.

1, 1b Voltage conversion circuit 11 Fuse (breaking part)
12 First switching element 13 Inductor 14 Second switching element 15 Switch 2 Control unit 21 Control circuit 3 Power supply 4 Load 5 Power storage circuit

Claims (5)

A first switching element that switches a current flowing from the power source to the inductor; and a second switching element that circulates the current flowing to the inductor during an off period of the first switching element. In the voltage conversion circuit that steps down (or steps up) the voltage and supplies it to the storage circuit,
A blocking unit that blocks the electric circuit by a current flowing through the electric circuit from the power source (or to the power storage circuit);
A switch for opening and closing an electric path to the storage circuit (or from the power source);
A comparison unit that compares the stepped down voltage (or the voltage of the power supply) and a predetermined first voltage ;
A second comparison unit that compares the stepped down voltage (or the voltage of the power supply) and a second voltage lower than the first voltage;
A third comparison unit that compares the reduced voltage (or the voltage of the power supply) and a third voltage lower than the second voltage ;
When the comparison result of the comparison unit indicates that the stepped down voltage (or the voltage of the power supply) is higher than the first voltage, the second switching element (or the first switching element) is turned on and the switch is opened. ,
When the comparison result of the second comparison unit indicates that the reduced voltage (or the voltage of the power supply) is equal to or higher than the second voltage, the first switching element (or the second switching element) is turned off,
Said third comparing section comparing a result of, when the step-down the voltage (or voltage of the power supply) is equal to or less than the third voltage, the voltage converter circuit, wherein you have to so that to release the OFF state . A fourth comparison unit that compares the stepped down voltage (or stepped up voltage) and a fourth voltage lower than a target voltage to be supplied to the power storage circuit;
Comparison result of the comparison of said 4, when the step-down the voltage (or boosted voltage) is lower than the fourth voltage, according to claim 1, characterized in that are to be released the on-state Voltage conversion circuit. A current detector for detecting a current flowing through the interrupting unit;
If the current said current detector detects less than a predetermined current, voltage conversion circuit according to claim 1, characterized in that are to be released the on-state. If allowed to open the switch, the voltage conversion circuit according to any one of claims 1 to 3, further comprising a notification unit that performs a predetermined notification. A first switching element that switches a current flowing from the power source to the inductor; and a second switching element that circulates the current flowing to the inductor during an off period of the first switching element. In the overvoltage protection method in the voltage conversion circuit that steps down (or boosts) the voltage and supplies the voltage to the storage circuit,
Preparing a cut-off unit that cuts off the electric circuit by a current flowing through the electric circuit from the power source (or to the power storage circuit), and a switch that opens and closes the electric circuit to the power storage circuit (or from the power source);
Compare the stepped down voltage (or the voltage of the power supply) and a predetermined first voltage,
When the comparison result is that the stepped down voltage (or the voltage of the power supply) is higher than the first voltage, the second switching element (or the first switching element) is turned on and the switch is opened ,
Compare the reduced voltage (or the voltage of the power supply) and the second voltage lower than the first voltage,
When the comparison result is that the stepped down voltage (or the voltage of the power supply) is equal to or higher than the second voltage, the first switching element (or the second switching element) is turned off,
Compare the reduced voltage (or the voltage of the power supply) and the third voltage lower than the second voltage,
Comparison result, if the stepped-down voltage (or voltage of the power supply) is equal to or less than the third voltage, an overvoltage protection method characterized that you release the off state.

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