JP5958019B2 - Image processing device - Google Patents

Description

  The present invention relates to an image processing apparatus having a serial communication control function for controlling serial communication of image data using a high-speed bus such as a PCI (Peripheral Component Interconnect) bus.

  2. Description of the Related Art Conventionally, in an image processing apparatus, in order to avoid concentration of access to a bus at the time of image data transfer, image data from an image input unit is transferred to a storage unit (memory) and image data from the storage unit (memory) is transferred. When the transfer to the image output unit occurs simultaneously on the same bus, a function for adjusting the bus so as not to fail is provided.

  In the known adjustment method, the access interval is adjusted in units of lines, or the access interval obtained in advance for each data transfer start is set depending on the connected controller (system CPU) and transfer conditions. Since the same access interval is used until the next setting change, there is a problem that the bus usage rate does not increase.

  In order to solve these problems, a technique has been proposed in which a transfer rate is constantly measured using a PCI bus, and a transfer interval is automatically adjusted so that the result falls within a preset setting range. As the well-known technique, “image information processing apparatus and image data transfer method” (patent) that can improve the processing efficiency of the entire apparatus by making the best use of the double-sided parallel reading function and the parallel transfer function of the image reading means. "Image forming system" that enables high-speed image data output and simultaneous transfer even when there are timing restrictions on line-synchronized transfer by effectively utilizing the PCI-Express standard high-speed serial bus (See Patent Document 2).

  The technique according to Patent Document 1 described above is to improve the processing efficiency of the entire apparatus by using the double-sided parallel reading function and the parallel transfer function to the maximum when the double-sided parallel reading function is connected as an image input unit. Change the transfer speed for transferring image data from the primary recording means to the secondary recording means using the primary storage means that temporarily stores the image data read by the image reading means according to the device configuration. This is a technique that can be changed or changed according to the transferable speed range.

  However, even if such a technique changes the transfer rate of image data, there is a problem in that the bus usage rate cannot be sufficiently improved because the method of adjusting line units does not change.

  The technique according to Patent Document 2 aims to output image data at a high speed even when there is a timing restriction on line synchronous transfer, so that the image input unit and the image output unit become initiators of image data transfer. In addition, the image input unit uses a memory write transaction and the image output unit uses an image data transfer method that uses a memory read transaction. When assigning these transactions to different traffic classes, a virtual channel is set and the image output unit The memory read transaction traffic class priority is set higher than the memory write transaction traffic class priority of the image input unit, and the memory write transaction is issued after all memory read transactions are issued. Which is a transfer technique to set the door priority.

  However, such technology can output image data at high speed even if there is a timing constraint for line synchronous transfer, and even when the same bus is used, image data can be transferred to the image output unit. This has the advantage that the image data can be output at high speed even when there is a timing constraint for line synchronous transfer. However, if there is a timing constraint on the image input side, the image data There is a problem that it is not possible to accurately adjust the transfer of.

  The present invention has been made to solve such problems, and its technical problem is that the transfer of image data can be accurately adjusted even when there is a timing constraint on the image input side, and the bus usage rate. An object of the present invention is to provide an image processing apparatus capable of sufficiently improving the image quality.

In order to solve the above technical problem, the basic configuration of the present invention includes an image input unit that inputs image data, a main storage unit that accumulates and stores the input image data, and an image output that outputs the stored image data A serial communication control unit that controls serial communication on the high-speed bus for image data transfer from the image input unit to the main storage unit and image data transfer from the main storage unit to the image output unit, and serial communication The serial communication control unit transfers the amount of image data transferred from the image input unit to the main storage unit and transfers the image from the main storage unit to the image output unit. It monitors the transfer of image data, is transferred after the transfer of the n-th line data in accordance with the transfer amount of the n-th line data in the image data to the image output unit That extending the transfer time of the line data of the (n + 1) -th in the image data, characterized by comprising a data transfer amount adjusting unit for adjusting the in-band limit the transfer amount of the image data from the image input unit.

According to the image processing apparatus of the present invention, with the above configuration, the transfer amount in the nth line in the image data is monitored, and transmission and reception are performed in the optimum band by delaying the command generation timing in the (n + 1) th line. It is possible to adjust the transfer of image data accurately even when there are timing restrictions on the image input side, the bus usage rate can be improved, the device configuration can be flexibly handled, and the bus can be used according to the image transfer conditions This saves time and effort to calculate the rate in advance.

1 is a block diagram illustrating a basic configuration of an image processing apparatus according to Embodiment 1 of the present invention and a flow of image processing functions. FIG. 2 is a block diagram showing a detailed configuration of a data transfer amount adjustment unit and its peripheral part as a detailed configuration in a serial communication control unit provided in the image processing apparatus shown in FIG. 1. 2 is a timing chart showing measurement timings of various signal waveforms required for calculating a transfer amount of image data by a data transfer amount adjustment unit in a serial communication control unit provided in the image processing apparatus shown in FIG. 3 is a timing chart showing adjustment timings of various signal waveforms required for adjusting the transfer amount of image data by a data transfer amount adjustment unit in a serial communication control unit provided in the image processing apparatus shown in FIG.

  Hereinafter, an image processing apparatus according to the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a block diagram illustrating a basic configuration of an image processing apparatus and a flow of image processing functions according to the first embodiment of the present invention.

  The image processing apparatus includes a serial communication control unit 4 capable of controlling serial communication via a high-speed serial bus using PCI-Express or the like as disclosed in Patent Document 2, and the serial communication control unit 4 An image input unit 2 connected to the reading unit 1 and the local memory 3 is connected to the input side of the data transfer amount adjusting unit 5, and an output side of the data transfer amount adjusting unit 5 is connected to the writing unit 7. Further, the system CPU 9 (controller connected by serial communication) connected to the external I / F 12, the memory 11, and the HDD (hard disk drive) are connected to the end point side of the serial communication control unit 4. ) The memory control unit 8 connected to 10 is connected.

  Among these, the reading unit 1 has a CCD scanner and a CIS scanner, and simultaneously reads from both sides of the document to acquire color image data. The image input unit 2 performs image processing such as MTF correction and smoothing processing on the image data transmitted from the reading unit 1, and temporarily stores the data in the local memory 3 in synchronization with the line synchronization signal, or stores The processed image data is sent to the data transfer amount adjustment unit 5 of the serial communication control unit 4.

  The image output unit 6 performs image processing for a written image such as gradation processing, edge correction, and total amount regulation on the data transmitted from the data transfer amount adjustment unit 5 of the serial communication control unit 4. Image data is output in accordance with a line synchronization signal synchronized with the rotation of the polygon. The writing unit 7 receives image data from the image output unit 6 and controls writing by a semiconductor laser (LD).

  The serial communication control by the high-speed serial bus of the serial communication control unit 4 is performed by using the memory for the image data sent from the image input unit 2 (stored in the memory 11 after being temporarily stored in the local memory 3). Transfer control to the memory control unit 8 using a write transaction and image data (stored and stored in the memory 11) sent to the image output unit 6 are transferred from the memory 11 through the memory control unit 8 using a memory read transaction. Control.

  The memory control unit 8 has a root function such as PCI-Express, transfers data to and from the serial communication control unit 4 through a high-speed bus, accesses data to the memory 11, and external I / O from the system CPU 9. Mediation between data transfer via / F12 and data transfer between the serial communication control unit 9 is performed. Incidentally, the memory 11 is for storing image data, code data, and programs, and the system CPU 9 controls each part of the image processing apparatus. The external I / F 12 is used for I / F control for transferring image data to the outside and inputting print data from the outside, and the HDD 10 is for storing code data and log data.

  The data transfer amount adjustment unit 5 in the serial communication control unit 4 measures the data transfer amount transferred from the image input unit 2 to the serial communication control unit 4 and transfers data transferred from the serial communication control unit 4 to the image output unit 6. In addition to measuring the transfer amount, the memory write transaction interval is adjusted according to the data transfer amount to the image output unit 6, and further, the interval of line-by-line data of image data read from the local memory 3 is adjusted.

  That is, in this image processing apparatus, the memory 11 is a main storage unit that accumulates and stores the image data input by the image input unit 2, and the local memory 3 is a storage that temporarily stores the image data on the image input side. It functions as a part. The serial communication control unit 4 performs serial communication for transfer of image data from the image input unit 2 to the memory 11 and transfer of image data from the memory 11 to the image output unit 6, such as a high-speed bus such as a PCI-Express bus. Control above. Further, the data transfer amount adjusting unit 5 provided in the serial communication control unit 4 monitors the transfer amount of the image data transferred from the image input unit 2 and the transfer amount of the image data transferred to the image output unit 6. The function of adjusting the transfer amount of the image data from the image input unit 2 within the bandwidth limit according to the transfer amount of the image data to the image output unit 6 is provided.

  Hereinafter, an image processing operation in the image processing apparatus according to the first embodiment will be specifically described. In this image processing apparatus, the image data read by the reading unit 1 is temporarily stored in the local memory 3 after being subjected to scanner image processing (shading correction, filter processing, color correction) by the image input unit 2. The reading unit 1 here is a unit that can read both sides of the document simultaneously, and therefore, the front image and the back image are simultaneously stored in the local memory 3. Incidentally, the image data transferred from the reading unit 1 to the local memory 3 follows a line cycle of a constant interval so as to keep the speed at which the original is conveyed in order to eliminate the disturbance of the read image in the reading unit 1.

  The image input unit 2 transfers image data from the local memory 3 to the serial communication control unit 4 in line order, and the serial communication control unit 4 transfers the image data to the memory control unit 8 using a memory write transaction. The memory control unit 8 arbitrates memory access and stores the received image data in the memory 11. Incidentally, for image data, the image is compressed and stored in the HDD 10 for image storage (storing) in the memory 11 and jam backup.

  When printing the image data stored in the memory 11, a memory read transaction is issued from the serial communication control unit 4 in synchronization with the line synchronization signal from the writing unit 9, and the memory control unit 8 that receives the memory read request. Reads out the image data from the memory 11 and returns the image data to the serial communication control unit 4. At this time, for the image data to be printed, the code data stored in the HDD 10 in advance is expanded and prepared as image data in the memory 11 or sent to the serial communication control unit 4 while expanding. The image output unit 6 performs gradation processing for printing the received image data and image processing for γ correction, and then passes the data to the writing unit 7. The writing unit 7 forms an image with a semiconductor laser (LD) and performs printing. Run. When the printing direction is changed, the image data is changed in direction by the rotation function (rotator) of the memory control unit 8 and printed.

  When the read image is transmitted to the outside, the read image data stored in the local memory 3 or the image data stored in the memory 11 obtained by reading and decompressing the code data from the HDD 10 is read out under the control of the system CPU 9 and, for example, JPEG or Tiff The image is converted to and transmitted to the outside via the external I / F.

  During printer operation, the system CPU 9 receives print data from the outside via the external I / F, translates the print data, draws and stores it in the memory 11, and sends the drawn image data to the writing unit 9 for printing. Make it.

  By the way, when printing image data, it is necessary to carry a document (paper) at a constant speed so as not to cause distortion and disturbance of the image, and it is necessary to keep the polygon cycle constant. As a result, a timing constraint on line synchronous transfer occurs when image data is transferred to the writing unit 9. If one line of image data cannot be read via the serial communication control unit 4 in one line, an abnormal image is generated.

  Similarly, the image data from the reading unit 1 also needs to be transferred at a fixed line cycle. When there is no local memory 3, when data transfer to the image output unit 6 is performed at the same time, priority is given to the data transfer to the image output unit 6. As a result, the serial communication control unit 4 to the memory control unit 8 is prioritized. There is a possibility that the data transfer is delayed and the data transfer from the image input unit 2 to the serial communication control unit 4 is overtaken. In such a case, an abnormal image is also generated in the read image.

  Therefore, in the image processing apparatus according to the first embodiment, the image data from the reading unit 1 is temporarily stored in the local memory 3 and the data transfer to the serial communication control unit 4 is adjusted. Further, since all image data passes through the memory 11, transfer of the image data is controlled by the performance of the system CPU 9 and the memory bandwidth of the memory control unit 8, and the high-speed serial communication itself is performed in full duplex. It will be limited to the corresponding serial communication band. As a result, it is necessary to limit the bandwidth also for data transfer from the image input side to the memory 11. The data transfer amount adjustment unit 5 of the serial communication control unit 4 has a function of adjusting data transfer in such a case.

  FIG. 2 is a block diagram showing a detailed configuration of the data transfer amount adjusting unit 5 and its peripheral part as a detailed configuration in the serial communication control unit 4.

  Referring to FIG. 2, the data transfer amount adjusting unit 5 includes an input data transfer amount monitoring unit 5a, a data transfer amount calculation adjusting unit 5b, and an output data transfer amount monitoring unit 5c, and the input data transfer amount monitoring unit 5a. Is connected to the peripheral input buffer 13 and the end point 15, and the output data transfer amount monitoring unit 5c is connected to the peripheral output buffer 14 and the end point 15.

  Among these, the input buffer 13 has a function of transferring image data from the transfer clock of the image input unit 2 to the transfer clock in the serial communication control unit 4. The output buffer 14 has a function of transferring image data from the transfer clock in the serial communication control unit 4 to the transfer clock of the image output unit 6.

  The endpoint 15 has a function on the PCI-Express side, transfers image data from the input buffer 13 to the memory control unit 8 for each payload size using memory write transactions mmw_ready and mmw_valid, and performs memory read transactions mmr_varid and mmr_ready. The image data for printing stored in the memory 11 is received from the memory control unit 8 and transferred to the output buffer 14 for each page size.

  The input data transfer amount monitoring unit 5a in the data transfer amount adjusting unit 5 monitors the image data transferred from the image input unit 2 in units of one line and measures the transfer amount. Here, the memory write transactions mmw_ready, mmw_valid are used. , And the time when the accumulated data amount for the main scanning size is reached is measured. The measurement time is initialized by the read line synchronization signal slsync, and the data transfer band is calculated for each line.

  The output data transfer amount monitoring unit 5c monitors and measures the transfer amount of image data transferred to the image output unit 6 in units of one line. Here, the memory read transactions mmr_varid and mmr_ready are monitored to read line A data transfer band is calculated by measuring the data integration amount during the period when the read signal reaches the main scanning size from the synchronization signal slsync.

  The data transfer amount calculation adjustment unit 5b sends the image transfer unit 6 to the image output unit 6 each time the bandwidth limitation for bandwidth limitation is confirmed in units of one line based on the monitoring results of the input data transfer amount monitor 5a and the output data transfer amount monitor 5c. For the transfer amount of the image data from the image input unit 2 according to the transfer amount of the image data, the line interval and the transaction interval are changed and set, and the bandwidth limit is switched according to the number of connection lanes of the PCI-Express standard. Calculate and adjust. Here, the calculated total amount of data transfer bandwidth (transfer bus bandwidth for image data, total amount of memory access bandwidth) is obtained so as to be within the memory bandwidth limit based on the read line synchronization signal slsync and the read main scan size scant_size. Is issued by adjusting the read line synchronization signal slsync interval and the memory write transaction interval wt_wid for the transfer amount of image data on the reading side (image input side).

  FIG. 3 is a timing chart showing measurement timings of various signal waveforms required for calculating the transfer amount of image data by the data transfer amount adjusting unit 5 in the serial communication control unit 4.

  Referring to FIG. 3, here, when calculating the transfer amount of image data, the data transfer amount calculation adjusting unit 5b initializes the measurement timing of various signal waveforms using the read line synchronization signal slsync input to the input buffer 13. To do.

  Therefore, the input data transfer amount monitoring unit 5a integrates these data amounts as the memory write data mmw_data during a period in which both of the memory write transactions mmw_ready and mmw_valid from the end point 15 are valid. _Integrated amount) wm is calculated. The memory write data transfer time (mmw_transfer time) wt is from the start of the read line synchronization signal slsync until the memory write data integrated amount (mmw_integrated amount) wm coincides with the read main scan size scant_size.

  Further, the output data transfer amount monitoring unit 5c integrates these data amounts as the memory read data mmr_data during a period in which both of the memory read transactions mmr_varid and mmr_ready from the endpoint 15 are valid, and adds up the memory read data integration amount (mmr _Integrated amount) rm is calculated.

  The read line synchronization signal slsync instructs transfer of the next line when the grant command becomes high level H.

  The bandwidth when image data is transferred from the image input unit 2 to the memory 11 is the relational expression wm obtained by dividing the memory write data integrated amount (mmw_integrated amount) wm by the memory write data transfer time (mmw_transfer time) wt. / Wt (byte / s). The bandwidth when image data is transferred from the memory 11 to the image output unit 6 is a relationship obtained by dividing the memory read data integrated amount (mmr_integrated amount) rm by the memory write data transfer time (mmw_transfer time) wt. It is obtained by the formula rm / wt (byte / s).

  FIG. 4 is a timing chart showing adjustment timings of various signal waveforms required for adjusting the transfer amount of image data by the data transfer amount adjusting unit 5 in the serial communication control unit 4.

  Referring to FIG. 4, here, when adjusting the transfer amount of the image data, the data transfer amount calculation adjusting unit 5 b receives the memory from the image input unit 2 in the n + 1th line of the read line synchronization signal slsync input to the input buffer 13. A case in which the transfer of the image data to 11 and the transfer of the image data from the memory 11 to the image output unit 6 occur simultaneously will be described.

  In this case, the transfer bandwidth of the image data at the time when the entire data amount for one line of the memory write transactions mmw_ready and mmw_valid has been transferred is wm0 / wt0 + rm0 / wt0. Here, if the upper limit band of the high-speed serial is limit_a (byte / s) due to the band limitation of the memory control unit 8, the transfer band wm0 / wt0 + rm0 / wt0 is larger than the upper limit band limit_a (wm0 / wt0 + rm0 / wt0). > If limit_a), the read bandwidth on the image input unit 2 side is calculated using the result of calculating the difference y (= wm0 / wt0 + rm0 / wt0−limit_a) obtained by subtracting the upper limit bandwidth limit_a from the transfer bandwidth wm0 / wt0 + rm0 / wt0. The generation of the grant command is delayed by the number of internal clocks add_lsw of the serial communication control unit 4 so that the difference y becomes zero (y = 0).

  When the reading band including the time x is wm0 / (wt0 + x) and calculation is performed so that wm0 / (wt0 + x) + rm0 / wt0 = limit_a, the difference y is obtained as y = wm0 / wt0−wm0 / (wt0 + x). Therefore, the time x can be rewritten as x = y * wt0 * wt0 / (wm0−y * wt0).

  The time x is converted into the internal clock number add_lsw of the serial communication control unit 4, and the generation of the grant command is delayed for that number of clocks add_lsw. This makes it possible to determine whether or not the upper limit band has been exceeded in one line (n + 1 line), and to suppress the reading-side band in that line.

  In the n + 2 line, the time x added in the n + 1 line is distributed over the memory write transaction interval wt_wid. The memory write transaction interval wt_wid is obtained by dividing the internal clock number add_lsw of the serial communication control unit 4 by the number of transactions.

  By increasing the memory write transaction interval wt_wid, the memory read request for generating the memory read transactions mmr_varid and mmr_ready is prevented from being obstructed by the memory write transactions mmw_ready and mmw_valid while reducing the bandwidth on the reading side. As a result, as in the case of the priority control of the traffic class disclosed in Patent Document 2, the timing constraint of the line-synchronous transfer on the writing side is observed.

  When the image data transfer bandwidth wm / wt + rm / wt is equal to or less than the upper limit bandwidth limit_a (when wm / wt + rm / wt ≦ limit_a), the serial communication control unit 4 internal clock number add_lsw and the memory write transaction interval wt_wid are set to 0 Return.

  Bandwidth confirmation is performed on a line-by-line basis, and each time the line interval and transaction interval are dynamically changed, so that transmission / reception can be performed with the optimum bandwidth, and the upper limit bandwidth limit_a is determined by the connection lane and switched. Thus, it is possible to correspond to a band according to the performance of the connected system CPU 9 or the memory control unit 8.

  In short, the image processing apparatus according to the first embodiment generates an abnormal image if the data transfer is not in time during the transfer of the image data to the image output unit 6. From the image input unit 2 that the bus band for transfer must be ensured, and when the transfer of the image data to the image output unit 6 has not occurred or when the transfer condition is small. Note that more bandwidth can be used for data transfer.

  Therefore, in the image processing apparatus according to the first embodiment, the local memory 3 is provided on the image input side so that the transfer interval of image data can be adjusted, and the data transfer amount adjusting unit 5 provided in the serial communication control unit 4 is adjusted. The input data transfer amount monitoring unit 5a that measures the transfer amount of image data from the image input unit 2 to the memory 11 and the input data transfer amount monitor that measures the transfer amount of image data from the memory 11 to the image output unit 6 In addition to providing the unit 5c, the transfer amount of the image data from the image input unit 2 is changed by changing the line interval or the transaction interval according to the transfer amount of the image data to the image output unit 6 based on these measured values. A data transfer amount calculation adjusting unit 5b that adjusts automatically is provided.

  With this configuration, it is possible to dynamically adjust the line interval and transaction interval so that the transfer amount of the image data is within the bandwidth limit (within the total bus bandwidth), and the adjustment of the transfer amount of the image data is automatically performed. Therefore, the labor of calculating and setting the line interval in advance can be saved, and the transfer efficiency of the image data is improved as compared with the case of setting the access interval for each line. As a result, the transfer amount of image data on the image input side can be adjusted appropriately according to the transfer amount of image data on the image output side, so the bus usage rate can be improved and the device configuration can be flexibly handled. This eliminates the need to calculate the bus usage rate in advance.

DESCRIPTION OF SYMBOLS 1 Reading part 2 Image input part 3 Local memory 4 Serial communication control part 5 Data transfer amount adjustment part 5a Input data transfer amount monitoring part 5b Data transfer amount calculation adjustment part 5c Output data transfer amount monitoring part 6 Image output part 7 Writing part 8 Memory control unit 9 System CPU
10 HDD (Hard Disk Drive)
11 Memory 12 External I / F
13 Input buffer 14 Output buffer 15 Endpoint

JP 2005-260846 A JP 2010-033602 A

Claims (8)

An image input unit that inputs image data, a main storage unit that stores and stores the input image data, an image output unit that outputs the stored image data, and the image input unit to the main storage unit A serial communication control unit for controlling serial communication on transfer of the image data and transfer of the image data from the main storage unit to the image output unit on a high-speed bus; and a controller connected by the serial communication; An image processing apparatus comprising:
The serial communication control unit monitors the transfer amount of the image data transferred from the image input unit to the main storage unit and the transfer amount of the image data transferred from the main storage unit to the image output unit, and According to the transfer amount of the nth line data in the image data to the image output unit, the transfer time of the (n + 1) th and subsequent line data in the image data transferred after the transfer of the nth line data is extended, An image processing apparatus comprising: a data transfer amount adjustment unit that adjusts the transfer amount of the image data from the image input unit within a band limit. 2. The image processing apparatus according to claim 1 , wherein when the transfer amount of the nth line data exceeds an upper limit transfer amount, the serial communication control unit transfers the nth line data from the upper limit transfer amount. An image processing apparatus characterized by extending a transfer time of the (n + 1) th and subsequent line data in accordance with a difference obtained by subtracting the amount . 3. The image processing apparatus according to claim 1, wherein the serial communication control unit extends a transaction interval of n + 2 and subsequent line data according to the extended transfer time . 4. The image processing apparatus according to claim 1, wherein the data transfer amount adjustment unit adjusts a line interval in units of one line . 5. 4. The image processing apparatus according to claim 1, wherein the data transfer amount adjustment unit adjusts a transaction interval in units of one line . 5. 4. The image processing apparatus according to claim 1, wherein the data transfer amount adjustment unit switches the band limitation according to the number of PCI-Express connection lanes . 5. 4. The image processing apparatus according to claim 1, wherein the data transfer amount adjustment unit monitors the image data transferred from the image input unit in units of one line and measures a transfer amount. A data transfer amount monitoring unit, an output data transfer amount monitoring unit that monitors and measures the transfer amount of the image data transferred to the image output unit in units of one line, the input data transfer amount monitoring unit, and the output data Each time the bandwidth limitation band confirmation is performed in units of one line based on the monitoring result in the transfer amount monitoring unit, the image data from the image input unit according to the transfer amount of the image data to the image output unit For the transfer amount, the line interval and the transaction interval are changed and set, and the bandwidth limit is switched according to the number of PCI-Express connection lanes and dynamically calculated and adjusted. The image processing apparatus characterized by comprising: the data transfer amount calculation adjusting section. 8. The image processing apparatus according to claim 1, further comprising a storage unit that temporarily stores the image data from the image input unit in addition to the main storage unit.

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