JP5956383B2 - PLL synthesizer, signal analysis apparatus and signal generation apparatus using the same, and calibration method - Google Patents

Description

  The present invention relates to a PLL synthesizer, a signal analysis apparatus and a signal generation apparatus using the same, and a calibration method.

  A synthesizer having high-performance phase noise performance is suitably used as an oscillation circuit such as a spectrum analyzer or a signal generator. Such a synthesizer generally takes a multi-loop method, for example, from a Fine loop (fine adjustment loop), a coarse loop (coarse adjustment loop), or a Sum loop (synthesis loop of a coarse adjustment loop and a fine adjustment loop). Composed.

  In general, YTO (YIG Tuned Oscillator) is used for the oscillator of the synthetic loop, and a voltage controlled oscillator (VCO) is used for the oscillator of the coarse adjustment loop from the aspect of cost. is there.

  As shown in FIG. 9, a PLL synthesizer that can be used as a coarse adjustment loop has a frequency divider 71, a phase comparator 72, a loop filter 73, a VCO 74, and a frequency Flo that divide and output a signal having a reference frequency Fref. The basic configuration includes a local oscillator 75 that outputs a local signal, a mixer 76 as a frequency mixer, a low-pass filter 77, and a frequency divider 78 that divides the input frequency by N (for example, see Patent Document 1).

  Furthermore, the PLL synthesizer disclosed in Patent Document 1 forms a feedback loop by the switches 79 and 80, the voltage target value recording unit 81, the D / A converter (DAC) 82, and the subtractor 83, and By controlling the output to be equal to the voltage of the analog signal output from the DAC 82, the oscillation frequency of the VCO 74 is locked to the target frequency.

  When configuring a multi-loop synthesizer, it is important to reduce the frequency division ratio of the frequency divider as much as possible in order to suppress the deterioration of phase noise. For this reason, in the PLL synthesizer as described above, frequency conversion is performed using the mixer 76 in addition to the frequency divider 78 as means for generating the comparison frequency input to the phase comparator 72. .

JP 2006-203558 A

  When frequency conversion is performed using a mixer, if the VCO pretune is not performed correctly, the level relationship between the output signal of the VCO and the frequency of the local signal input to the mixer may be reversed. In such a case, the control direction of the loop is opposite to the direction in which the phases are synchronized, and unlocking from the target frequency and mislocking occur.

  YTO, which is widely used as an oscillator of a synthetic loop, has excellent linearity, and it is not difficult to accurately perform pretune. On the other hand, a wideband VCO widely used as a coarse adjustment loop oscillator generally has high sensitivity and poor linearity, and therefore it is difficult to perform pretune with high accuracy.

  Further, the fact that the linearity is bad means that the loop band of the coarse adjustment loop is easily changed. If the loop band changes greatly, the phase noise within the band and the spurious performance generated outside the band will deteriorate.

  However, the conventional PLL synthesizer disclosed in Patent Document 1 forms a feedback loop that does not include the VCO 74, and makes the output of the loop filter 73 equal to the voltage of the analog signal output by the DAC 82, and the sensitivity. In other words, the pretune voltage is not accurately measured for VCOs having different linearities. For this reason, it is difficult to improve the linearity of a wideband VCO, and there is a problem that phase noise and spurious characteristics cannot be improved.

  The present invention has been made to solve such a conventional problem, and is a PLL synthesizer capable of achieving high-precision pretune and constant loop bandwidth, and a signal analyzer and signal using the PLL synthesizer. An object is to provide a generator and a calibration method.

  In order to solve the above-described problems, a PLL synthesizer according to claim 1 of the present invention includes a voltage-controlled oscillator that controls the frequency of an output signal in accordance with the voltage of the input signal, and a signal based on the output signal that is divided into 1 / N. Outputs a signal corresponding to the phase difference between the in-loop frequency dividing unit, the reference frequency dividing unit that divides the reference signal by 1 / R, and the output of the in-loop frequency dividing unit and the output of the reference frequency dividing unit. In the PLL synthesizer comprising: a phase comparator that performs the above operation; and a loop filter that passes the low-frequency component of the input signal and applies the low-frequency component to the voltage-controlled oscillator, the reference signal and the output signal of the voltage-controlled oscillator are input A PLL-IC that outputs a signal corresponding to a phase difference between the reference signal and the output signal, a switching unit that supplies the output of the phase comparison unit or the output of the PLL-IC to the loop filter, and the switching unit In An adjustment voltage measurement unit that measures an adjustment voltage to be applied to the voltage controlled oscillation unit so that the frequency of the output signal becomes a target frequency in a state where the output side of the PLL-IC and the input side of the loop filter are connected A sensitivity calculation unit that calculates a rate of change of the frequency with respect to a change in the adjustment voltage, and at least one of a gain of the loop filter and a charge pump current of the phase comparison unit according to the rate of change at the target frequency A loop gain adjustment unit that adjusts the output voltage, and an adjustment voltage output unit that outputs the adjustment voltage to the voltage controlled oscillation unit in a state where the output side of the phase comparison unit and the input side of the loop filter are connected by the switching unit. It has the composition provided with.

  With this configuration, the adjustment voltage and the sensitivity of the voltage-controlled oscillation unit are configured so that the sub-PLL circuit having the PLL-IC and the adjustment voltage measurement unit is configured independently of the main PLL circuit when measuring the adjustment voltage of the voltage-controlled oscillation unit. Can be measured with high accuracy, and high-precision pretune and constant loop bandwidth can be achieved.

  In addition, since the gain of the loop filter and the charge pump current of the phase comparison unit can be adjusted so that the loop band of the main PLL circuit is constant, it is possible to reduce spurious and stabilize the phase noise within the loop band.

  The PLL synthesizer according to claim 2 of the present invention further includes a frequency conversion unit that converts the frequency of the output signal and outputs the converted signal to the in-loop frequency division unit. ing.

  With this configuration, it is possible to reduce the frequency division ratio of the in-loop frequency dividing portion as much as possible and suppress the deterioration of the phase noise.

  According to a third aspect of the present invention, there is provided a PLL synthesizer comprising: a voltage-controlled oscillation unit that controls a frequency of an output signal according to a voltage of an input signal; and an in-loop frequency division that divides a signal based on the output signal by 1 / N. A reference frequency dividing unit that divides the reference signal by 1 / R, a phase comparison unit that outputs a signal corresponding to a phase difference between the output of the in-loop frequency dividing unit and the output of the reference frequency dividing unit, A loop filter that passes the low-frequency component of the output from the phase comparison unit and applies it to the voltage-controlled oscillation unit, converts the frequency of the output signal, and converts the frequency-converted signal into the in-loop frequency dividing unit In a PLL synthesizer comprising a frequency converter for outputting to the switching circuit, the output signal from the voltage controlled oscillator is supplied to the in-loop frequency divider through the frequency converter or without the frequency converter. Part and said In the state where the output side of the voltage controlled oscillation unit and the input side of the in-loop frequency dividing unit are connected without the frequency conversion unit by the conversion unit, the voltage control is performed so that the frequency of the output signal becomes the target frequency. An adjustment voltage measurement unit that measures an adjustment voltage to be applied to the oscillation unit, a sensitivity calculation unit that calculates a rate of change of the frequency with respect to a change in the adjustment voltage, A loop gain adjusting unit that adjusts at least one of a gain and a charge pump current of the phase comparison unit; and an output side of the voltage controlled oscillation unit and an input side of the in-loop frequency dividing unit by the switching unit And an adjustment voltage output unit that outputs the adjustment voltage to the voltage-controlled oscillation unit in a connected state.

  With this configuration, the sub-PLL circuit in which the frequency converter is separated from the main PLL circuit at the time of measuring the adjustment voltage of the voltage-controlled oscillator can be configured to accurately measure the sensitivity of the adjustment voltage and the voltage-controlled oscillator. It is possible to achieve a precise pretune and constant loop bandwidth.

  In addition, since the gain of the loop filter and the charge pump current of the phase comparison unit can be adjusted so that the loop band of the main PLL circuit is constant, it is possible to reduce spurious and stabilize the phase noise within the loop band.

  The signal analyzing apparatus according to claim 4 of the present invention generates a local signal capable of frequency sweep by a local signal generator and supplies it to the mixer together with the input signal, and outputs a signal in a predetermined intermediate frequency band from the output of the mixer. A frequency conversion unit to be extracted by a filter, and a local signal of the local signal generator so that a signal component of a designated observation band of the input signal is output in time series from the filter of the frequency conversion unit. A sweep control unit that performs frequency sweep control, an A / D converter that samples the output signal of the frequency conversion unit and converts it into a digital signal sequence, and an output from the A / D converter during the sweep of the local signal A signal analysis unit for storing a signal sequence to be obtained and obtaining a spectrum characteristic of frequency vs. signal intensity, and a table for displaying a waveform of the spectrum characteristic obtained by the signal analysis unit And a section, wherein the local signal generator has a structure containing any of the PLL synthesizer described above.

  With this configuration, since the PLL synthesizer with a highly accurate pretune and a constant loop band is provided, the spectrum characteristics of the input signal can be obtained with high accuracy.

  According to a fifth aspect of the present invention, there is provided a signal generator comprising a baseband signal output means for outputting a baseband signal, a local oscillation signal generating means for generating a local oscillation signal having a predetermined local oscillation frequency, and the base A radio frequency signal generating means for generating a radio frequency signal by performing quadrature modulation and frequency conversion by multiplying a band signal and the local oscillation signal, and setting the signal level of the radio frequency signal to a predetermined signal level and outputting it And a step attenuator for attenuating and outputting the radio frequency signal set to the predetermined signal level with a predetermined attenuation value, wherein the local oscillation signal generating means is one of the PLL synthesizers described above It has the composition containing.

  With this configuration, since the PLL synthesizer with high precision pretune and constant loop band is provided, it is possible to output an RF test signal with good signal purity.

  According to a sixth aspect of the present invention, there is provided a calibration method comprising: a voltage-controlled oscillation unit that controls a frequency of an output signal according to a voltage of an input signal; and an in-loop frequency division that divides the signal based on the output signal by 1 / N. A reference frequency dividing unit that divides the reference signal by 1 / R, a phase comparison unit that outputs a signal corresponding to a phase difference between the output of the in-loop frequency dividing unit and the output of the reference frequency dividing unit, A PLL synthesizer calibration method comprising a loop filter that passes a low-frequency component of an input signal and supplies the low-frequency component to the voltage-controlled oscillator, wherein the reference signal and the output signal of the voltage-controlled oscillator are input, A PLL-IC that outputs a signal corresponding to a phase difference between the reference signal and the output signal, and a switching unit that supplies the output of the phase comparison unit or the output of the PLL-IC to the loop filter, and Front by the switching part An adjustment voltage measuring step for measuring an adjustment voltage to be applied to the voltage controlled oscillation unit so that the frequency of the output signal becomes a target frequency in a state where the output side of the PLL-IC and the input side of the loop filter are connected; A sensitivity calculating step for calculating the rate of change of the frequency with respect to the change of the adjustment voltage, and adjusting at least one of the gain of the loop filter and the charge pump current of the phase comparison unit according to the rate of change at the target frequency A loop gain adjustment step, and an adjustment voltage output step of outputting the adjustment voltage to the voltage controlled oscillation unit in a state where the output side of the phase comparison unit and the input side of the loop filter are connected by the switching unit. .

  With this configuration, in the adjustment voltage measurement step, the sub-PLL circuit having the PLL-IC is configured independently of the main PLL circuit, thereby accurately measuring the sensitivity of the adjustment voltage and the voltage-controlled oscillation unit. It becomes possible to make the pretune and the loop band constant.

  In addition, since the gain of the loop filter and the charge pump current of the phase comparison unit can be adjusted so that the loop band of the main PLL circuit is constant, it is possible to reduce spurious and stabilize the phase noise within the loop band.

  According to a seventh aspect of the present invention, there is provided a calibration method comprising: a voltage-controlled oscillation unit that controls a frequency of an output signal according to a voltage of an input signal; and an in-loop frequency division that divides the signal based on the output signal by 1 / N. A reference frequency dividing unit that divides the reference signal by 1 / R, a phase comparison unit that outputs a signal corresponding to a phase difference between the output of the in-loop frequency dividing unit and the output of the reference frequency dividing unit, A loop filter that passes the low-frequency component of the output from the phase comparison unit and applies it to the voltage-controlled oscillation unit, converts the frequency of the output signal, and converts the frequency-converted signal into the in-loop frequency dividing unit A frequency synthesizer calibration method comprising: a frequency converter that outputs to the loop, wherein the output signal of the voltage controlled oscillator is passed through the frequency converter or without being passed through the frequency converter. With a switching section to give to the circumference Furthermore, in order for the frequency of the output signal to be the target frequency in a state where the output side of the voltage controlled oscillation unit and the input side of the in-loop frequency dividing unit are connected via the switching unit without passing through the frequency converting unit. According to the adjustment voltage measurement step for measuring the adjustment voltage to be applied to the voltage controlled oscillator, the sensitivity calculation step for calculating the rate of change of the frequency with respect to the change of the adjustment voltage, and the change rate at the target frequency, A loop gain adjustment step for adjusting at least one of a gain of a loop filter and a charge pump current of the phase comparison unit; and the switching unit causes the output side of the voltage controlled oscillation unit and the input side of the in-loop frequency division unit to have the frequency An adjustment voltage output step of outputting the adjustment voltage to the voltage controlled oscillation unit in a state of being connected via the conversion unit.

  With this configuration, in the adjustment voltage measurement step, a sub-PLL circuit in which the frequency conversion unit is separated from the main PLL circuit is configured, so that the sensitivity of the adjustment voltage and the voltage-controlled oscillation unit can be measured with high accuracy, and a high-precision pretune can be performed. It is possible to make the loop bandwidth constant.

  In addition, since the gain of the loop filter and the charge pump current of the phase comparison unit can be adjusted so that the loop band of the main PLL circuit is constant, it is possible to reduce spurious and stabilize the phase noise within the loop band.

  According to the present invention, the adjustment voltage and the sensitivity of the voltage controlled oscillation unit can be obtained by configuring the sub-PLL circuit having the PLL-IC and the adjustment voltage measuring unit independently of the main PLL circuit when measuring the adjusted voltage of the voltage controlled oscillation unit. Is provided with a PLL synthesizer that can accurately measure the frequency of the signal, and can achieve high-precision pretune and constant loop bandwidth, a signal analyzer and signal generator using the PLL synthesizer, and a calibration method.

It is a block diagram which shows the structure of the PLL synthesizer as the 1st Embodiment of this invention. It is a figure which shows the structure of the loop filter of the PLL synthesizer as the 1st Embodiment of this invention. It is a flowchart (the 1) for demonstrating the process which the control part of the PLL synthesizer as a 1st Embodiment of this invention performs. It is a flowchart (the 2) for demonstrating the process which the control part of the PLL synthesizer as a 1st Embodiment of this invention performs. It is a flowchart (the 3) for demonstrating the process which the control part of the PLL synthesizer as a 1st Embodiment of this invention performs. It is a block diagram which shows the structure of the PLL synthesizer as the 2nd Embodiment of this invention. It is a block diagram which shows the structure of the signal analyzer as the 3rd Embodiment of this invention. It is a block diagram which shows the structure of the signal generator as the 4th Embodiment of this invention. It is a block diagram which shows the structure of the conventional PLL synthesizer.

  Hereinafter, embodiments of a PLL synthesizer according to the present invention, a signal analysis device and a signal generation device using the same, and a calibration method will be described with reference to the drawings.

(First embodiment)
First, the configuration of the PLL synthesizer 1 as the first embodiment of the present invention will be described.

As shown in FIG. 1, the PLL synthesizer 1 of the present embodiment employs a multi-loop method, and receives a coarse adjustment loop 10 to which a reference signal of frequency f ₁ is input and a reference signal of frequency f _2. A fine adjustment loop 11, a coarse adjustment loop 10, and a synthesis loop 12 that combines the outputs of the fine adjustment loop 11.

  The coarse adjustment loop 10 includes a VCO 13, a local oscillator 14, a mixer 15, a low-pass filter 16, an in-loop divider 17, a reference divider 18, a phase comparator 19, a loop filter 20, a PLL-IC 21, and a switch as a switching unit. 22, 23, an A / D converter (ADC) 24, a D / A converter (DAC) 25, and a control unit 26.

  The VCO 13, the local oscillator 14, the mixer 15, the low-pass filter 16, the in-loop frequency divider 17, the reference frequency divider 18, the phase comparator 19, the loop filter 20, and the switches 22 and 23 constitute a main PLL circuit. Further, the VCO 13, the loop filter 20, the PLL-IC 21, the switches 22, 23, the ADC 24, and the DAC 25 constitute a sub PLL circuit.

  The VCO 13 controls the frequency of the output signal in accordance with the voltage of the input signal. Specifically, the VCO 13 outputs a signal having an oscillation frequency fv proportional to the voltage of the input signal as an output signal.

Local oscillator 14, and outputs a local signal of a local frequency f _0. The mixer 15 mixes the output signal output from the VCO 13 and the local signal output from the local oscillator 14 by multiplication. The low-pass filter 16 passes a low-frequency component of the output of the mixer 15.

  The local oscillator 14, the mixer 15, and the low-pass filter 16 constitute a frequency conversion unit that converts the frequency of the output signal of the VCO 13 and outputs the converted signal to the in-loop frequency divider 17.

The in-loop frequency divider 17 divides the output of the low-pass filter 16 by 1 / N and outputs the result. The reference frequency divider 18 divides the input reference signal of the frequency f ₁ by 1 / R and outputs it. Here, N and R are one or more real numbers.

  The phase comparator 19 detects the phase difference between the output of the in-loop divider 17 and the output of the reference divider 18 and outputs a voltage signal having a pulse width proportional to the phase difference. The phase comparator 19 has a charge pump for outputting a voltage signal having a pulse width proportional to the phase difference.

  The loop filter 20 passes the low frequency component of the output of the switch 22 and applies it to the VCO 13. That is, the output of the phase comparator 19 is smoothed by the loop filter 20 and becomes the control voltage of the VCO 13.

  More specifically, as shown in FIG. 2, the loop filter 20 includes four types of integration circuits A1 to A4 including an amplifier 31, four types of lag / lead filters P1 to P4, a common filter C1, and an integration. It comprises a switch 32 for selecting one of the circuits A1 to A4 and a switch 33 for selecting any one of the lag / lead filters P1 to P4.

  Among these, the integration circuit A4 is used only for the loop including the PLL-IC 21 in the VCO sensitivity measurement mode described later. Accordingly, the loop gain adjustment of the coarse adjustment loop 10 corresponds to 12 × 3 × 4 loop filter designs.

Table 1 summarizes the combinations of the 4 × 4 integration circuits A1 to A4 and the lag / lead filters P1 to P4. That is, a1 to a3, b1 to b3, c1 to c3, and d1 to d3 are loop filters for the phase comparator 19, and c4 and d4 are loop filters for the PLL-IC21.

The PLL-IC 21 has a circuit configuration such as a frequency divider, a phase comparator, a charge pump, etc. housed in one chip. The reference signal of the frequency f ₁ and the output signal of the VCO 13 are input, the reference signal and the output A signal corresponding to the phase difference from the signal is output. In the present embodiment, as the PLL-IC 21, for example, “ADF4106” of Analog Devices, Inc. is preferably used.

  The switch 22 connects the output side of the PLL-IC 21 and the input side of the loop filter 20 in the VCO sensitivity measurement mode described later, and the output side of the phase comparator 19 in the coarse adjustment loop mode and the pretune execution mode described later. The input side of the loop filter 20 is connected.

  The switch 23 connects the output side of the loop filter 20 to the ADC 24 in the VCO sensitivity measurement mode, connects the output side of the loop filter 20 to the DAC 25 at the start of the pretune execution mode, and ends the pretune execution mode. , The output side of the loop filter 20 is disconnected from the ADC 24 and the DAC 25.

  The ADC 24 is connected to the output side of the PLL-IC 21 and the input side of the loop filter 20 by the switch 22, and the analog output from the loop filter 20 in a state where the output side of the loop filter 20 and the ADC 24 are connected by the switch 23. The voltage signal is converted into a digital signal, and the value of the converted digital signal is recorded in a memory (not shown). The ADC 24 constitutes an adjustment voltage measurement unit.

  Here, the value of the digital signal recorded in the ADC 24 is a VCO tune voltage V as an adjustment voltage to be applied to the VCO 13 so that the frequency fv of the output signal of the VCO 13 becomes the target frequency ft. That is, the ADC 24 measures the VCO tune voltage V.

  The DAC 25 is recorded in the memory of the ADC 24 with the switch 22 connecting the output side of the phase comparator 19 and the input side of the loop filter 20, and the switch 23 connecting the output side of the loop filter 20 and the DAC 25. The VCO tune voltage V is converted into an analog voltage signal, and the converted analog voltage signal is supplied to the VCO 13 via the switch 23. The DAC 25 constitutes an adjustment voltage output unit.

  The control unit 26 includes, for example, a CPU, a ROM, a RAM, and the like. The control unit 26 controls operations of the above-described units constituting the coarse adjustment loop 10 and executes a predetermined program to thereby execute a sensitivity calculation unit 27 and a loop gain adjustment unit. 28 is configured by software.

  The sensitivity calculator 27 calculates the rate of change of the oscillation frequency fv of the VCO 13 with respect to the change of the VCO tune voltage V, that is, the VCO sensitivity. For example, the VCO sensitivity is obtained by converting the oscillation frequency fv of the VCO 13 to the VCO tune voltage. It is obtained by differentiating with V.

  The loop gain adjustment unit 28 adjusts at least one of the gain of the loop filter 20 and the charge pump current of the phase comparator 19 according to the VCO sensitivity at the target frequency ft.

  Furthermore, the PLL synthesizer 1 may be configured to be able to output a signal having a frequency corresponding to data supplied to the control unit 26 from the outside via an operation unit (not shown).

  Hereinafter, a calibration method of the coarse adjustment loop 10 in the PLL synthesizer 1 of the present embodiment will be described. Here, the sub-PLL circuit having a simple configuration with little risk of mislocking is used, and the VCO tune voltage V is set by the ADC 24 for each oscillation frequency fv of the VCO 13 selected while changing the settings of the PLL-IC 21 and the loop filter 20. Processing to measure is performed.

  Hereinafter, the calibration program executed by the control unit 26 of the coarse adjustment loop 10 in the first embodiment will be described with reference to the flowcharts of FIGS.

<VCO sensitivity measurement mode>
FIG. 3 is a flowchart showing processing in the VCO sensitivity measurement mode. 3 corresponds to the adjustment voltage measurement step (steps S1 to S8) and the sensitivity calculation step (step S9).

  First, in step S1, the control unit 26 turns on the switch 22 in a direction connecting the output side of the PLL-IC 21 and the input side of the loop filter 20, and switches the control mode to the VCO sensitivity measurement mode.

  Next, in step S2, the control unit 26 performs various initial settings. Here, the initial value of the frequency division ratio in the N counter and R counter inside the PLL-IC 21 and the initial value of the charge pump current are set in the PLL-IC 21. At this time, in order to reduce the occurrence of mislock in the PLL-IC 21, a value in a frequency region where the VCO sensitivity is flat (for example, 4800 MHz) is used as the oscillation frequency fv of the VCO 13.

  Next, in step S3, the control unit 26 waits for a predetermined time (for example, 500 μsec) until the oscillation frequency fv of the VCO 13 is locked.

  Next, in step S4, the control unit 26 sets a desired oscillation frequency fv by switching between the frequency division ratio and charge pump current setting of the PLL-IC 21 and the filter selection setting of the loop filter 20.

  Next, in step S5, the control unit 26 waits for a predetermined time (for example, 100 μsec) until the oscillation frequency fv of the VCO 13 is locked.

  Next, in step S <b> 6, the control unit 26 turns on the switch 23 in a direction to connect the output side of the loop filter 20 and the ADC 24, controls the ADC 24, and measures the output voltage of the loop filter 20.

  Next, in step S7, the control unit 26 stores a value obtained by multiplying the measured output voltage of the loop filter 20 by a predetermined correction value as the VCO tune voltage V in the VCO tune voltage table in the memory of the ADC 24. Here, the predetermined correction value is attributed to the resistance of the feedback circuit including the ADC 24.

Table 2 shows an example of the VCO tune voltage V recorded in the VCO tune voltage table. This is an example in the case where the oscillation frequency fv is set in steps of 100 MHz in step S4, and a value obtained by linear interpolation is used for the VCO tune voltage having a frequency other than the oscillation frequency fv to be measured.

  Next, in step S8, it is determined whether or not the acquisition of the VCO tune voltage V for all the oscillation frequencies fv to be measured has been completed. If the acquisition of the VCO tune voltage V has not been completed, the control unit 26 executes the processes after step S4 again. On the other hand, when the acquisition of the VCO tune voltage V is completed, the control unit 26 executes the process of step S9.

  In the processing of steps S4 to S8, when the comparison frequency of the PLL-IC 21 is 12.5 MHz, for example, the control unit 26 sets the value of the R counter of the PLL-IC 21 to 2 and sets the value of the N counter from 160 to 320. It is changed in increments of 4 (N = 160, 164, 168,..., 320).

  As a result, the oscillation frequency fv of the VCO 13 can be changed in increments of 100 MHz. In addition, the interval of the oscillation frequency fv actually measured is not limited to the above-described 100 MHz, and is particularly preferably 10 MHz or less from the viewpoint of improving the linearity of the VCO 13.

  Next, in step S9, the control unit 26 calculates the VCO sensitivity from the frequency characteristic of the VCO tune voltage V acquired in the processing up to step S8. Specifically, the control unit 26 stores the value obtained from the calculation formula shown in Table 3 below as the VCO sensitivity in the VCO sensitivity table in the memory of the ADC 24.

  Here, the VCO sensitivity when the oscillation frequency fv is 4000 MHz is calculated as being on the extension line of the VCO sensitivity of 4050 MHz and 4150 MHz. Similarly, the VCO sensitivity when the oscillation frequency fv is 8000 MHz is calculated as being on the extension line of the VCO sensitivity of 7850 MHz and 7950 MHz.

Further, the VCO sensitivity at the oscillation frequency fv not listed in Table 3 may be obtained by linear interpolation, and the frequency increment of the VCO sensitivity recorded in the VCO sensitivity table is preferably 10 MHz or less.

  Note that the processing in steps S1 to S9 in the VCO sensitivity measurement mode may be performed before shipment, may be performed every time before processing in a coarse adjustment loop mode described later, or at any timing by the user. It may be done in. Moreover, the process of step S2, S3 may be abbreviate | omitted.

<Coarse adjustment loop mode>
When operating the coarse adjustment loop 10 in the present embodiment, the control unit 26 sets the oscillation frequency fv of the VCO 13. Depending on the setting of the oscillation frequency fv, the frequency division ratio of the in-loop frequency divider 17 in the feedback path of the main PLL circuit is determined.

In general, the loop bandwidth of the PLL circuit is determined by the sensitivity Kv of the VCO, the sensitivity KΦ of the phase comparator, the gain G of the loop filter, and the frequency division ratio N of the loop. This is shown in Equation 1.

  The sensitivity of the VCO 13 changes according to the oscillation frequency fv, and the range of the change is, for example, 100 [MHz / V] to 450 [MHz / V]. As is clear from Equation 1, when the sensitivity of the VCO 13 varies, the loop bandwidth of the main PLL circuit varies accordingly.

  In the present embodiment, in order to keep the loop band of the main PLL circuit in the coarse adjustment loop 10 constant, by setting the filter selection of the loop filter 20 and the charge pump current of the phase comparator 19 appropriately, Absorbs fluctuations in the sensitivity of the VCO 13.

  Hereinafter, processing in the coarse adjustment loop mode will be described with reference to the flowchart of FIG. Here, the process of the flowchart of FIG. 4 corresponds to the process of the loop gain adjustment step.

  First, in step S11, the control unit 26 turns on the switch 22 in a direction connecting the output side of the phase comparator 19 and the input side of the loop filter 20, and switches the control mode to the coarse adjustment loop mode.

Next, in step S <b> 12, the control unit 26 calculates “VCO sensitivity / feedback path division ratio” [MHz / V] according to Equation 2. Here, the VCO sensitivity is obtained from the VCO sensitivity table (see Table 3) acquired in the VCO sensitivity measurement mode. The feedback path division ratio is a set value R of the R counter of the phase comparator 19, and specifically, R takes a value of 1, 2, 4, or 8.

Next, in step S13, the control unit 26 sets the parameters used in the subsequent processing steps as shown in the following Equation 3 and Table 4.

Next, in step S14, the control unit 26 determines a range of S _Coarse values satisfying the following inequality (4) for each n that can take values of n = 1, 2,... Furthermore, the control unit 26 determines an appropriate filter selection of the loop filter 20 for each n according to Table 5 below. For example, when S _Coast is 300, a combination of filters “b1” corresponding to n = 2 (see Table 1) is selected, and when S _Coast is 200, a filter combination “c1” corresponding to n = 3 is selected. A combination is selected.

Further, the control unit 26 determines parameters _{G A} and _{G P} corresponding to the filter selection of the loop filter 20 in accordance with Table 4. For example, when n = 2, since the selected filters are A1 and P2, the values of the parameters are G _A = 1, G _P = b, and G _PS = z.

Next, in step S15, the control unit 26 obtains the gain G _LP of the loop filter 20 using Equation 5 according to the filter selected in step S14.

Next, in step S <b> 16, the control unit 26 calculates the set value CP of the charge pump current to be set in the phase comparator 19 in accordance with Equation 6. Further, the control unit 26 rounds the obtained set value CP to a value CP _set in increments of 20 μA that can be actually set in the phase comparator 19 by Equation 7.

That is, in the processing of steps S11 to S16, the control unit 26 compares the setting of the filter selection of the loop filter 20, that is, the gain of the loop filter 20 and the phase comparison, from the value of S _Coarse obtained based on the VCO sensitivity table of Table 3. The setting of the charge pump current of the device 19 is determined.

  Further, the control unit 26 sets the determined gain and set value of the charge pump current in the loop filter 20 and the phase comparator 19 respectively (step S17). As a result, the loop band of the main PLL circuit in the coarse adjustment loop 10 can be made constant.

In the above description, both the gain of the loop filter 20 and the charge pump current of the phase comparator 19 are set. However, the present embodiment is not limited to this. For example, when the charge pump current CP obtained by Equation 6 is very small, it is possible to make the loop band of the main PLL circuit in the coarse adjustment loop 10 constant only by adjusting the gain G _LP of the loop filter 20. .

Further, for example, when it is not necessary to change the gain G _LP of the loop filter 20 from the already set value, the loop band of the main PLL circuit in the coarse adjustment loop 10 is fixed only by adjusting the charge pump current CP _set. It is also possible.

<Pretune execution mode>
FIG. 5 is a flowchart showing processing in the pretune execution mode in the coarse adjustment loop mode. The process of the flowchart in FIG. 5 corresponds to the process of the adjustment voltage output step. Here, the pretune is a VCO tune voltage V for operating the VCO 13 at the target frequency ft is output from the DAC 25, and a voltage obtained by adding the output voltage of the DAC 25 and the output voltage of the loop filter 20 to the VCO 13 is output. It is an operation to apply.

  First, in step S21, the control unit 26 turns on the switch 23 in a direction in which the output side of the loop filter 20 and the DAC 25 are connected, and switches the control mode to the pretune execution mode. As a result, in addition to the output of the loop filter 20, the output of the DAC 25 is input to the VCO 13.

  Next, in step S22, the control unit 26 refers to the VCO tune voltage table in Table 2 and obtains the VCO tune voltage V of the desired oscillation frequency fv.

  Next, in step S23, the control unit 26 inputs a set value obtained by multiplying the VCO tune voltage V acquired in step S22 by a predetermined correction value to the DAC 25. Here, the predetermined correction value is attributed to the resistance of the feedback circuit including the DAC 25.

  Next, in step S24, the control unit 26 waits for a predetermined time (for example, 100 μsec) until the oscillation frequency fv of the VCO 13 is locked.

  Next, in step S25, the control unit 26 turns off the switch 23, disconnects the output side of the loop filter 20 from the DAC 25, and ends the pretune execution mode.

  By the processing of these steps S21 to S25, the oscillation frequency fv of the output signal of the VCO 13 is stabilized in the vicinity of the target frequency ft.

  As described above, according to the present embodiment, in the VCO sensitivity measurement mode, the sub PLL circuit having the PLL-IC 21 and the ADC 24 is configured independently of the main PLL circuit, so that the VCO tune as the pretune voltage is obtained. The sensitivity of the voltages V and VCO 13 can be measured with high accuracy, and high-precision pretune and constant loop bandwidth can be achieved.

  In addition, the loop filter 20 that determines the loop gain is divided into two stages, and it is possible to suppress fluctuations in the loop band by selecting an appropriate filter in accordance with the sensitivity of the VCO 13.

  In addition, by configuring the sub PLL circuit, it becomes possible to accurately measure the VCO tune voltage V for VCOs having different sensitivities and linearities. As a result, the main PLL circuit can be pretuned with high accuracy.

  Further, by measuring the sensitivity of the VCO 13, it becomes possible to obtain the VCO tune voltage V for making the loop band of the main PLL circuit constant, thereby reducing spurious and stabilizing the phase noise within the loop band. It becomes possible. In addition, by measuring the VCO tune voltage V in real time, it is possible to correct changes in the oscillation frequency of the VCO 13 due to temperature fluctuations and secular changes.

(Second Embodiment)
Next, a PLL synthesizer 2 as a second embodiment of the present invention will be described with reference to the drawings. Note that the description of the same configuration and operation as in the first embodiment will be omitted as appropriate.

  As shown in FIG. 6, the coarse adjustment loop 40 provided in the PLL synthesizer 2 of this embodiment includes a VCO 13, a local oscillator 14, a mixer 15, a low-pass filter 16, an in-loop divider 17, a reference divider 18, and a phase comparison. A device 19, a loop filter 20, switches 23, 29, and 30 as switching units, an ADC 24, a DAC 25, and a control unit 26.

  The VCO 13, the local oscillator 14, the mixer 15, the low pass filter 16, the in-loop frequency divider 17, the reference frequency divider 18, the phase comparator 19, the loop filter 20, and the switches 29 and 30 constitute a main PLL circuit.

  Further, the VCO 13, the in-loop frequency divider 17, the reference frequency divider 18, the phase comparator 19, the loop filter 20, the ADC 24, the DAC 25, and the switches 29 and 30 constitute a sub PLL circuit.

  The loop filter 20 passes the low frequency component of the output of the phase comparator 19 and supplies it to the VCO 13.

  The switches 29 and 30 are configured to connect the output side of the VCO 13 and the input side of the in-loop frequency divider 17 without the mixer 15 in the VCO sensitivity measurement mode. The switches 29 and 30 connect the output side of the VCO 13 and the input side of the mixer 15 in the coarse adjustment loop mode and the pretune execution mode, and the output side of the low-pass filter 16 and the input side of the in-loop frequency divider 17. Is supposed to be connected.

  In the ADC 24, the output side of the VCO 13 and the input side of the in-loop frequency divider 17 are connected by the switches 29 and 30 without going through the mixer 15, and the output side of the loop filter 20 and the ADC 24 are connected by the switch 23. The analog voltage signal output from the loop filter 20 is converted into a digital signal, and the value of the converted digital signal is recorded in a memory (not shown).

  In the DAC 25, the output side of the VCO 13 and the input side of the in-loop frequency divider 17 are connected via the mixer 15 by the switches 29 and 30, and the DAC 25 is connected to the output side of the loop filter 20 by the switch 23. The VCO tune voltage V recorded in the memory of the ADC 24 is converted into an analog voltage signal, and the converted analog voltage signal is supplied to the VCO 13 via the switch 23.

  Hereinafter, the calibration program executed by the control unit 26 of the coarse adjustment loop 40 according to the second embodiment will be described with reference to the flowcharts of FIGS.

<VCO sensitivity measurement mode>
First, in step S1 of the flowchart of FIG. 3, the control unit 26 turns on the switches 29 and 30 in a direction in which the output side of the VCO 13 and the input side of the in-loop frequency divider 17 are connected without going through the mixer 15. Switch the mode to VCO sensitivity measurement mode.

  Next, in step S2, the control unit 26 performs various initial settings. Here, the initial value of the frequency division ratio is set for the in-loop frequency divider 17 and the reference frequency divider 18, and the initial value of the charge pump current is set for the phase comparator 19. At this time, in order to reduce the occurrence of mislock in the sub PLL circuit, a value in a frequency region (for example, 4800 MHz) where the VCO sensitivity becomes flat is used as the oscillation frequency fv of the VCO 13.

  Next, in step S3, the control unit 26 waits for a predetermined time (for example, 500 μsec) until the oscillation frequency fv of the VCO 13 is locked.

  Next, in step S4, the control unit 26 sets the frequency division ratio of the in-loop frequency divider 17 and the reference frequency divider 18, the charge pump current of the phase comparator 19, and the filter selection setting of the loop filter 20. By switching, a desired oscillation frequency fv is set.

  Next, in step S5, the control unit 26 waits for a predetermined time (for example, 100 μsec) until the oscillation frequency fv of the VCO 13 is locked.

  Next, in step S <b> 6, the control unit 26 turns on the switch 23 in a direction to connect the output side of the loop filter 20 and the ADC 24, controls the ADC 24, and measures the output voltage of the loop filter 20.

  Next, in step S7, the control unit 26 stores a value obtained by multiplying the measured output voltage of the loop filter 20 by a predetermined correction value as the VCO tune voltage V in the VCO tune voltage table in the memory of the ADC 24.

  Next, in step S8, it is determined whether or not the acquisition of the VCO tune voltage V for all the oscillation frequencies fv to be measured has been completed. If the acquisition of the VCO tune voltage V has not been completed, the control unit 26 executes the processes after step S4 again. On the other hand, when the acquisition of the VCO tune voltage V is completed, the control unit 26 executes the process of step S9.

  In the processing of steps S4 to S8 described above, when the comparison frequency of the phase comparator 19 is 12.5 MHz, the control unit 26 sets the frequency division ratio R of the reference frequency divider 18 to 2 and sets the frequency divider 17 in the loop. The frequency division ratio N is changed from 160 to 320 in increments of 4 (N = 160, 164, 168,..., 320).

  Next, in step S9, the control unit 26 calculates the VCO sensitivity from the frequency characteristic of the VCO tune voltage V acquired in the processing up to step S8. Specifically, the control unit 26 stores the value obtained from the calculation formula shown in Table 3 as the VCO sensitivity in the VCO sensitivity table in the memory of the ADC 24.

<Coarse adjustment loop mode>
In step S11 of the flowchart of FIG. 4, the control unit 26 connects the output side of the VCO 13 and the input side of the mixer 15, and connects the output side of the low-pass filter 16 and the input side of the in-loop frequency divider 17. The switches 29 and 30 are turned on to switch the control mode to the coarse adjustment loop mode.

  The description of the subsequent steps S12 to S16 is the same as in the first embodiment, and will be omitted.

<Pretune execution mode>
FIG. 5 is a flowchart showing processing in the pretune execution mode in the coarse adjustment loop mode. The description of the processing in steps S21 to S25 is the same as that in the first embodiment, and will be omitted.

  As described above, according to the present embodiment, in the VCO sensitivity measurement mode, the sub PLL circuit in which the frequency conversion unit is separated from the main PLL circuit is configured, so that the sensitivity of the VCO tune voltage V and VCO 13 can be improved with high accuracy. Measurements can be made with high precision pretune and constant loop bandwidth.

(Third embodiment)
Next, a signal analysis device 50 as a third embodiment of the present invention will be described with reference to the drawings. Note that description of the configuration and operation similar to those of the first and second embodiments will be omitted as appropriate.

As shown in FIG. 7, the signal analyzing apparatus 50 of the present embodiment generates a local signal L that can be swept in frequency by the PLL synthesizer 1 or 2 of the first or second embodiment constituting the local signal generator. to provided to the mixer 52 along with the input signal S _iN, the frequency converter 51 to extract a signal M of a predetermined intermediate frequency band from the output of the mixer 52 in the filter 53, out of the input signal S _iN, and the designated observation zone The sweep control unit 54 that performs frequency sweep control of the local signal L of the PLL synthesizer 1 or 2 and the output signal of the frequency conversion unit 51 are sampled so that the signal components are output in time series from the filter 53 of the frequency conversion unit 51. A / D converter 55 that converts the signal into a digital signal string, and a signal string output from the A / D converter 55 during the frequency sweep of the local signal L Storing m, it comprises a signal analysis unit 56 for obtaining the spectrum characteristic of frequency versus signal strength, and a display unit 57 which displays the waveform spectrum characteristic obtained by the signal analyzer 56.

That is, the input signal _SIN is input to the mixer 52 of the frequency converter 51, mixed with the local signal L from the PLL synthesizer 1 or 2, and the frequency component of the difference or sum (hereinafter referred to as difference). Among them, a signal component M in a predetermined intermediate frequency band is extracted by the filter 53.

Here, when the center frequency of the filter 53 is F _IF , the frequency of the local signal L is F _L, and mixing is performed with an upper heterodyne having a local frequency F _L higher than the frequency F _IN of the analysis target signal to be converted to the intermediate frequency band. Assuming
_{F L} -F _IF = F _IN
The relationship holds.

Here, for _example, the F IF = 8 GHz, if swept local frequency _{F L} from 8.1GHz to 9 GHz, a frequency _{F IN} of the analyzed signal will vary from 100MHz to 1 GHz. That is, the filter 53, signal components from 100MHz to 1GHz of the input signal _{S IN} is to be extracted in chronological order of frequency of its original.

  Here, an example of a circuit that performs frequency conversion once is shown, but actually, frequency conversion processing (generally by a local signal of a fixed frequency) is performed a plurality of times in the frequency conversion unit 51, and Converting to a lower frequency band.

  As described in the first embodiment, the PLL synthesizer 1 or 2 is configured to output a local signal L having a frequency corresponding to data given from the outside, and the frequency sweep of the local signal L is performed. This is performed by sequentially updating the frequency data input from the sweep control unit 54.

  The sweep control unit 54 sweeps the frequency of the local signal L in a predetermined step according to the reference frequency (start frequency or center frequency) designated by the operation unit 58, the sweep width (span), the number of acquired samples, and the like. Information f of each frequency is given to the signal analysis unit 56.

  On the other hand, the signal M output from the frequency converter 51 is sampled by the A / D converter 55 at a predetermined sampling period (a frequency more than twice the upper limit of the pass band of the filter 53), and obtained by the sampling. A digital signal sequence Dm is input to the signal analysis unit 56.

  The signal analysis unit 56 receives the digital signal sequence Dm obtained by the frequency sweep and the frequency information f in association with each other, stores them in a memory (not shown), performs a designated band limiting process, etc. A characteristic of frequency versus signal intensity S (f), that is, a spectrum characteristic is obtained. The display unit 57 displays the spectrum characteristic waveform obtained by the signal analysis unit 56 on the screen.

  Since the signal analyzing apparatus 50 of the present embodiment configured as described above includes the PLL synthesizer 1 or 2 of the first or second embodiment that achieves high-precision pretune and constant loop bandwidth. The spectrum characteristics of the input signal can be obtained with high accuracy.

(Fourth embodiment)
Next, a signal generator 60 as a fourth embodiment of the present invention will be described with reference to the drawings. Note that description of the configuration and operation similar to those of the first and second embodiments will be omitted as appropriate.

  As shown in FIG. 8, the signal generator 60 of this embodiment includes a waveform data storage unit 61, DACs 62 and 63, a quadrature modulator 64, and a PLL synthesizer 1 of the first or second embodiment that constitutes a local oscillator. Alternatively, an automatic level control circuit (ALC) 65, an operation unit 66, a setting unit 67, and a step attenuator (step ATT) 68 are provided.

  The waveform data storage unit 61 stores digital baseband waveform data as a plurality of test signal data for testing the device under test. The tester can operate the operation unit 66 to select and output test signal data stored in the waveform data storage unit 61 via the setting unit 67. The test signal data includes baseband waveform data of an I-phase component (in-phase component) and a Q-phase component (orthogonal component). The waveform data is generated by, for example, a DSP (Digital Signal Processor) not shown. The waveform data storage unit 61 constitutes a baseband signal output unit.

  Each of the DACs 62 and 63 converts the digital baseband signal waveform data of the I-phase component and Q-phase component output from the waveform data storage unit 61 into an analog value and outputs the analog value to the quadrature modulator 64. .

  The PLL synthesizer 1 or 2 is configured to generate a local oscillation signal having a local oscillation frequency based on the setting signal from the setting unit 67 and output the local oscillation signal to the quadrature modulator 64. The PLL synthesizer 1 or 2 constitutes a local oscillation signal generation unit.

  The quadrature modulator 64 multiplies the I-phase component from the DAC 62 and the Q-phase component from the DAC 63 by the local oscillation signal input from the PLL synthesizer 1 or 2 to perform quadrature modulation and frequency conversion, thereby performing a radio frequency signal. (RF signal) is generated and output to the ALC 65. This quadrature modulator 64 constitutes a radio frequency signal generating means.

  The ALC 65 adjusts the power level of the output signal of the quadrature modulator 64 to a predetermined power level and outputs it to the step ATT 68. The power level set by the ALC 65 is set by a setting signal from the setting unit 67. The ALC 65 can adjust the output signal level in units of 0.1 dB, for example. The ALC 65 constitutes signal level setting means.

  The operation unit 66 is operated by a tester in order to make settings related to test conditions and test procedures, and includes, for example, an input device such as a keyboard, dial, or mouse, and a control circuit that controls these devices. . Test conditions set by the examiner include, for example, waveform data stored in the waveform data storage unit 61, the output level of the RF test signal output by the step ATT 68, the radio frequency, and the like.

  The setting unit 67 is constituted by a microcomputer, for example, and controls the entire apparatus. In addition, the setting unit 67 generates a setting signal for setting each test condition based on each test condition set by the tester by operating the operation unit 66, the waveform data storage unit 61, the PLL synthesizer 1 or 2, the ALC 65, and the step ATT 68. Each test condition is set.

  Here, as a setting for the ALC 65, for example, when the user sets the output level of the signal generator 60 to −40.2 dBm, the setting unit 67 sets the attenuation of the step ATT 68 to 30 dB, A control signal for setting the output signal level to -10.2 dBm is output.

  The step ATT 68 includes a plurality of attenuator sections each having a predetermined amount of attenuation, and an ATT capable of attenuating the level of the input RF signal in steps of a predetermined amount of attenuation by a combination of attenuations of each attenuator section. It is. The step ATT 68 attenuates the input signal by the attenuation amount set by the setting signal from the setting unit 67, and outputs an RF test signal having a power level desired by the tester.

  The signal generator 60 of the present embodiment configured as described above includes the PLL synthesizer 1 or 2 of the first or second embodiment that achieves highly accurate pretune and constant loop bandwidth. , RF test signals with good signal purity can be output.

1, 2 PLL synthesizer (local signal generator, local oscillation signal generating means)
10, 40 Coarse adjustment loop 11 Fine adjustment loop 12 Synthesis loop 13 VCO (voltage controlled oscillator)
14 Local oscillator (frequency converter)
15 Mixer (frequency converter)
16 Low-pass filter (frequency converter)
17 In-loop divider (in-loop divider)
18 Reference divider (reference divider)
19 Phase comparator (phase comparator)
20 loop filter 21 PLL-IC
22, 23, 29, 30 Switch (switching part)
24 ADC (adjusted voltage measurement unit)
25 DAC (Adjustment voltage output unit)
DESCRIPTION OF SYMBOLS 26 Control part 27 Sensitivity calculation part 28 Loop gain adjustment part 50 Signal analysis apparatus 51 Frequency conversion part 52 Mixer 53 Filter 54 Sweep control part 55 A / D converter 56 Signal analysis part 57 Display part 60 Signal generator 61 Waveform data storage part (Baseband signal output means)
64 quadrature modulator (radio frequency signal generating means)
65 ALC (signal level setting means)
68 Step attenuator (Step ATT)

Claims (7)

A voltage-controlled oscillator (13) that controls the frequency of the output signal according to the voltage of the input signal, an in-loop frequency divider (17) that divides the signal based on the output signal by 1 / N, and a reference signal that is 1 A reference frequency dividing unit (18) that divides / R, a phase comparison unit (19) that outputs a signal corresponding to the phase difference between the output of the in-loop frequency dividing unit and the output of the reference frequency dividing unit, and an input In a PLL synthesizer (1) comprising a loop filter (20) that passes a low-frequency component of a signal to be transmitted and applies it to the voltage-controlled oscillation unit,
A PLL-IC (21) that receives the reference signal and the output signal of the voltage controlled oscillator, and outputs a signal corresponding to the phase difference between the reference signal and the output signal;
A switching unit (22) for supplying the output of the phase comparison unit or the output of the PLL-IC to the loop filter;
Adjustment for measuring an adjustment voltage to be applied to the voltage controlled oscillation unit so that the frequency of the output signal becomes a target frequency in a state where the output side of the PLL-IC and the input side of the loop filter are connected by the switching unit A voltage measuring unit (24);
A sensitivity calculator (27) for calculating a rate of change of the frequency with respect to a change of the adjustment voltage;
A loop gain adjustment unit (28) that adjusts at least one of a gain of the loop filter and a charge pump current of the phase comparison unit according to the rate of change in the target frequency;
An adjustment voltage output unit (25) for outputting the adjustment voltage to the voltage controlled oscillation unit in a state where the output side of the phase comparison unit and the input side of the loop filter are connected by the switching unit; PLL synthesizer to do.   2. The PLL according to claim 1, further comprising a frequency converter (14 to 16) that converts a frequency of the output signal and outputs a signal obtained by converting the frequency to the frequency divider in the loop. Synthesizer. A voltage-controlled oscillator (13) that controls the frequency of the output signal according to the voltage of the input signal, an in-loop frequency divider (17) that divides the signal based on the output signal by 1 / N, and a reference signal that is 1 A reference frequency dividing unit (18) that divides / R, a phase comparison unit (19) that outputs a signal corresponding to the phase difference between the output of the in-loop frequency dividing unit and the output of the reference frequency dividing unit, A loop filter (20) that passes the low-frequency component of the output from the phase comparison unit and applies it to the voltage-controlled oscillation unit; converts the frequency of the output signal; In a PLL synthesizer (2) including a frequency converter (14 to 16) that outputs to the periphery,
A switching unit (29, 30) for supplying the output signal of the voltage controlled oscillation unit to the in-loop frequency dividing unit via the frequency converting unit or without using the frequency converting unit;
In order that the frequency of the output signal becomes the target frequency in a state where the output side of the voltage controlled oscillation unit and the input side of the in-loop frequency dividing unit are connected without the frequency converting unit by the switching unit, the voltage An adjustment voltage measurement unit (24) for measuring an adjustment voltage to be applied to the control oscillation unit;
A sensitivity calculator (27) for calculating a rate of change of the frequency with respect to a change of the adjustment voltage;
A loop gain adjustment unit (28) that adjusts at least one of a gain of the loop filter and a charge pump current of the phase comparison unit according to the rate of change in the target frequency;
Adjusted voltage output for outputting the adjusted voltage to the voltage-controlled oscillating unit in a state where the output side of the voltage-controlled oscillating unit and the input side of the in-loop frequency dividing unit are connected by the switching unit via the frequency converting unit And a PLL synthesizer. A local signal that can be swept in frequency is generated by a local signal generator (1, 2) and applied to a mixer (52) together with an input signal, and a signal in a predetermined intermediate frequency band is extracted from the output of the mixer by a filter (53). A frequency converter (51) to perform,
Among the input signals, a sweep control unit that performs frequency sweep control of the local signal of the local signal generator so that a signal component in a designated observation band is output in time series from the filter of the frequency conversion unit ( 54)
An A / D converter (55) that samples the output signal of the frequency converter and converts it into a digital signal sequence;
A signal analysis unit (56) for storing a signal sequence output from the A / D converter during sweeping of the local signal and obtaining a spectrum characteristic of frequency versus signal intensity;
A display unit (57) for displaying a waveform of the spectrum characteristic obtained by the signal analysis unit,
4. A signal analyzing apparatus, wherein the local signal generator includes the PLL synthesizer (1, 2) according to any one of claims 1 to 3. Baseband signal output means (61) for outputting a baseband signal;
Local oscillation signal generating means (1, 2) for generating a local oscillation signal having a predetermined local oscillation frequency;
Radio frequency signal generating means (64) for generating a radio frequency signal by multiplying the baseband signal and the local oscillation signal to perform quadrature modulation and frequency conversion;
Signal level setting means (65) for setting the signal level of the radio frequency signal to a predetermined signal level and outputting the signal level;
A step attenuator (68) for attenuating and outputting the radio frequency signal set to the predetermined signal level with a predetermined attenuation value;
4. The signal generator according to claim 1, wherein the local oscillation signal generator includes the PLL synthesizer (1, 2) according to any one of claims 1 to 3. A voltage-controlled oscillator (13) that controls the frequency of the output signal according to the voltage of the input signal, an in-loop frequency divider (17) that divides the signal based on the output signal by 1 / N, and a reference signal that is 1 A reference frequency dividing unit (18) that divides / R, a phase comparison unit (19) that outputs a signal corresponding to the phase difference between the output of the in-loop frequency dividing unit and the output of the reference frequency dividing unit, and an input A method for calibrating a PLL synthesizer (1) comprising a loop filter (20) for passing a low-frequency component of a signal to be transmitted to the voltage-controlled oscillation unit,
A PLL-IC (21) that receives the reference signal and the output signal of the voltage controlled oscillator, and outputs a signal corresponding to the phase difference between the reference signal and the output signal;
A switching unit (22) for supplying the output of the phase comparison unit or the output of the PLL-IC to the loop filter;
Adjustment for measuring an adjustment voltage to be applied to the voltage controlled oscillation unit so that the frequency of the output signal becomes a target frequency in a state where the output side of the PLL-IC and the input side of the loop filter are connected by the switching unit Voltage measurement step;
A sensitivity calculating step of calculating a rate of change of the frequency with respect to a change of the adjustment voltage;
A loop gain adjustment step of adjusting at least one of a gain of the loop filter and a charge pump current of the phase comparison unit according to the rate of change in the target frequency;
A calibration voltage output step of outputting the regulation voltage to the voltage controlled oscillation unit in a state in which the output side of the phase comparison unit and the input side of the loop filter are connected by the switching unit. . A voltage-controlled oscillator (13) that controls the frequency of the output signal according to the voltage of the input signal, an in-loop frequency divider (17) that divides the signal based on the output signal by 1 / N, and a reference signal that is 1 A reference frequency dividing unit (18) that divides / R, a phase comparison unit (19) that outputs a signal corresponding to the phase difference between the output of the in-loop frequency dividing unit and the output of the reference frequency dividing unit, A loop filter (20) that passes the low-frequency component of the output from the phase comparison unit and applies it to the voltage-controlled oscillation unit; converts the frequency of the output signal; A method for calibrating a PLL synthesizer (2) comprising a frequency converter (14 to 16) that outputs to the periphery,
A switching unit (29, 30) for supplying the output signal of the voltage controlled oscillation unit to the in-loop frequency dividing unit via the frequency converting unit or without using the frequency converting unit;
In order that the frequency of the output signal becomes the target frequency in a state where the output side of the voltage controlled oscillation unit and the input side of the in-loop frequency dividing unit are connected without the frequency converting unit by the switching unit, the voltage An adjustment voltage measurement step for measuring an adjustment voltage to be applied to the control oscillation unit;
A sensitivity calculating step of calculating a rate of change of the frequency with respect to a change of the adjustment voltage;
A loop gain adjustment step of adjusting at least one of a gain of the loop filter and a charge pump current of the phase comparison unit according to the rate of change in the target frequency;
Adjusted voltage output for outputting the adjusted voltage to the voltage-controlled oscillating unit in a state where the output side of the voltage-controlled oscillating unit and the input side of the in-loop frequency dividing unit are connected by the switching unit via the frequency converting unit Including a step.

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