JP2019047424A - Pll circuit, measuring apparatus with the same, and control method of pll circuit - Google Patents

Abstract

To provide a PLL circuit capable of reducing a pre-tuning voltage error than before.SOLUTION: A PLL circuit 10 comprises: a reference signal generation part 11 that generates a reference signal of a predetermined frequency; a VCO 13 that outputs the signal of an oscillation frequency in accordance with an input voltage; a PFD 12 that outputs a phase difference signal by comparing the reference signal generation part 11 and each output signal of the VCO 13; a first integration circuit 20 that outputs a first integration signal by integrating the phase difference signal; a second integration circuit 30 that includes a resistor 31 serially connected between the first integration circuit 20 and the VCO 13, integers the first integration signal, and outputs a second integration signal to the VCO 13; a pre-tuning voltage generation part 15 that generates a pre-tuning voltage that previously adjusts an oscillation frequency of the VCO 13; and an accumulator 41 that adds an electric potential difference between both ends of the resistance 31 and the pre-tuning voltage, generates a correction pre-tuning voltage obtained by correcting the pre-tuning voltage, and outputs it to the VCO 13.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a PLL circuit, a measurement apparatus including the same, and a control method of the PLL circuit.

  Conventionally, for example, in a measuring apparatus such as a spectrum analyzer or a signal generator, there is one using a phase locked loop (PLL) circuit as an oscillation circuit. In general, a PLL circuit includes a voltage controlled oscillator, and adjusts (pretunes) the oscillation frequency in advance using, for example, a DAC (digital analog converter) in order to quickly lock the oscillation frequency of the voltage controlled oscillator to a desired frequency. It has composition (for example, refer to patent documents 1).

  The pretune device described in Patent Document 1 selects a DAC for generating a pretune voltage, a switch for turning on or off the supply of the pretune voltage to a voltage controlled oscillator, and any one of a plurality of integrating circuits. And an integration circuit selection switch. With this configuration, it is possible to achieve operation stabilization and shortening of the lock time by performing pre-tuning more accurately in the one described in Patent Document 1.

JP, 2016-111650, A

  However, in the device described in Patent Document 1, a voltage error (pretune voltage error) occurs between the pretune voltage and the input voltage of the voltage controlled oscillator at the desired frequency oscillation due to aging or the like. There is a need for a circuit that reduces the pretune voltage error to zero the current of the integration circuit due to the tune voltage error. Also, in order to shorten the frequency lead-in time for zeroing the current of the integration circuit due to the pretune voltage error, a circuit that reduces the pretune voltage error has been desired.

  The present invention has been made in view of the above-described circumstances, and provides a PLL circuit capable of reducing pretune voltage error more than that of the prior art, a measuring apparatus including the same, and a control method of the PLL circuit. With the goal.

  A PLL circuit according to claim 1 of the present invention comprises signal generation means (11) for generating a signal of a predetermined frequency, and a voltage control oscillator (13) for outputting a signal of an oscillation frequency corresponding to an input voltage. A phase frequency comparator (12) for comparing the output signals of the signal generating means and the voltage control oscillator and outputting a phase error signal; integrating means (20) for integrating the phase error signal; and the integrating means A resistor (31) connected in series with the voltage controlled oscillator; a pretune voltage generation means (15) for generating a pretune voltage for adjusting the oscillation frequency of the voltage controlled oscillator in advance; A pretune voltage correction means for adding a potential difference between both ends and the pretune voltage to generate a corrected pretune voltage with the pretune voltage corrected and outputting the corrected pretune voltage to the voltage controlled oscillator. And has a configuration in which the (41 and 50), the.

  With this configuration, the PLL circuit according to claim 1 of the present invention corrects the pretune voltage by adding the potential difference between both ends of the resistor connected in series between the integration means and the voltage controlled oscillator and the pretune voltage. Since the corrected pretune voltage is generated and output to the voltage controlled oscillator, the pretune voltage error can be made smaller than in the prior art.

  The PLL circuit according to claim 2 of the present invention is a correction pretune voltage output that stops the output of the correction pretune voltage on condition that the potential difference between both ends of the resistor is within a predetermined voltage range including 0 V. It has the composition further provided with the stop means (70).

  With this configuration, the PLL circuit according to claim 2 of the present invention can automatically stop the output of the correction pretune voltage when the potential difference between both ends of the resistor becomes around 0V.

  A PLL circuit according to a third aspect of the present invention includes the integrating means according to the first aspect as a first integrating means for outputting a first integrated signal, and includes the resistor and integrates the first integrated signal. And second integrating means (30) for outputting a second integrated signal to the voltage controlled oscillator.

  With this configuration, the PLL circuit according to claim 3 of the present invention can make the pre-tune voltage error smaller than that of the prior art based on the potential difference between both ends of the resistance of the second integrating means.

  The PLL circuit according to claim 4 of the present invention further comprises a correction pretune voltage limiting means (47) for limiting the correction pretune voltage to a predetermined value.

  With this configuration, the PLL circuit according to claim 4 of the present invention can reliably converge the tuning voltage in a shorter time.

  In the PLL circuit according to claim 5 of the present invention, the pretune voltage correction means includes a differential amplifier circuit (50) for differentially amplifying the potential difference between both ends of the resistor, and the correction pretune voltage limiting means The correction pre-tune voltage is limited to a predetermined value by adjusting a power supply voltage supplied to the differential amplifier circuit.

  According to this configuration, the PLL circuit according to claim 5 of the present invention can reliably converge the tuning voltage in a short time by adjusting the power supply voltage supplied to the differential amplifier circuit.

  The measuring apparatus according to claim 6 of the present invention preferably has a configuration provided with the PLL circuit according to any one of claims 1 to 5.

  A measuring apparatus according to claim 7 of the present invention is configured such that the PLL circuit generates a local oscillation signal of a predetermined local oscillation frequency.

  With this configuration, the measurement apparatus according to claim 7 of the present invention can generate the local oscillation signal by the PLL circuit that can make the pretune voltage error smaller than in the conventional case, so switching of the frequency can be performed in a shorter time than in the conventional case. It becomes possible.

  A PLL circuit control method according to an eighth aspect of the present invention is the PLL circuit control method according to any one of the first to fifth aspects, wherein a signal of a predetermined frequency is generated. A signal generation step (S11), a frequency signal output step (S18) for outputting a signal of a frequency according to the input voltage, and an output signal of the signal generation means and the voltage control oscillator are compared to output a phase error signal. Phase error signal output step (S13), integration step (S14) for integrating the phase error signal, and pretune voltage generation step (S12) for generating a pretune voltage for adjusting the oscillation frequency of the voltage control oscillator in advance , Adding the potential difference between both ends of the resistor and the pretune voltage to generate a corrected pretune voltage obtained by correcting the pretune voltage; And outputs to the controlled oscillator has a configuration comprising a pretune voltage correction step (S17), the.

  With this configuration, the control method of the PLL circuit according to claim 8 of the present invention adds the potential difference between both ends of the resistor and the pretune voltage to generate a corrected pretune voltage in which the pretune voltage is corrected to generate a voltage controlled oscillator. Since the output is performed, the pretune voltage error can be made smaller than in the prior art.

  According to a ninth aspect of the present invention, there is provided a control method of a PLL circuit according to the ninth aspect of the present invention, wherein the correction pre-tuning voltage is stopped on condition that the potential difference between both ends of the resistor is within a predetermined voltage range including 0V. It has a configuration further including a tune voltage output stopping step (S19).

  With this configuration, the control method of the PLL circuit according to claim 9 of the present invention can automatically stop the output of the correction pretune voltage when the potential difference between both ends of the resistor becomes around 0V.

  The present invention can provide a PLL circuit having an effect that pre-tune voltage error can be made smaller than that of the prior art, a measuring apparatus including the same, and a control method of the PLL circuit.

It is a block diagram of the PLL circuit as a 1st embodiment of the present invention. It is a block diagram of the conventional PLL circuit. FIG. 7 is a comparative explanatory view of a pretune operation in the PLL circuit as the first embodiment of the present invention and the conventional PLL circuit. It is a flowchart for demonstrating the control method of the PLL circuit in 1st Embodiment of this invention. It is a figure which shows an example of the integrating circuit in the modification of 1st Embodiment of this invention. It is a block diagram of the PLL circuit as a 2nd embodiment of the present invention. It is function explanatory drawing of the correction | amendment pretune voltage limitation part in 2nd Embodiment of this invention. It is a block block diagram of the signal-analysis apparatus as 3rd Embodiment of this invention. It is a block block diagram of the signal generator as 4th Embodiment of this invention.

  Hereinafter, an embodiment of a PLL circuit according to the present invention, a measuring apparatus provided with the same, and a control method of the PLL circuit will be described with reference to the drawings.

First Embodiment
First, the configuration of the PLL circuit according to the first embodiment of the present invention will be described.

  As shown in FIG. 1, the PLL circuit 10 in this embodiment includes a reference signal generation unit 11, a phase frequency detector (PFD) 12, a voltage controlled oscillator (VCO) 13, and a feedback circuit 14. A pretune voltage generation unit 15, a first integration circuit 20, a second integration circuit 30, and a pretune voltage control unit 40 are provided.

  The reference signal generation unit 11 generates a reference signal of a predetermined frequency and outputs the reference signal to the PFD 12. The reference signal generation unit 11 is an example of a signal generation unit.

  The PFD 12 compares the output signal of the reference signal generator 11 with the output signal of the feedback circuit 14 and outputs a phase error signal to the first integration circuit 20. The PFD 12 is an example of a phase frequency comparator.

  The first integrating circuit 20 integrates the phase error signal output from the PFD 12 and outputs the integrated signal as a first integrated signal to the second integrating circuit 30. The first integration circuit 20 is configured by, for example, a loop filter, and includes an operational amplifier (operational amplifier) 21, a capacitor 22, and a resistor 23. The first integration circuit 20 is an example of an integration means and a first integration means.

  The second integrating circuit 30 integrates the first integrated signal output from the first integrating circuit 20 and outputs the integrated signal to the VCO 13 as a second integrated signal. The second integration circuit 30 includes a resistor 31, a capacitor 32 and a resistor 33. The resistor 31 is connected in series between the first integrating circuit 20 and the VCO 13. The terminal on the VCO 13 side of the resistor 31 is grounded via the capacitor 32 and the resistor 33. The second integration circuit 30 is an example of a second integration means.

  The VCO 13 outputs a signal of an oscillation frequency corresponding to the input voltage from the second integration circuit 30 to the feedback circuit 14 and outputs the signal as the output signal L of the PLL circuit 10. The VCO 13 is an example of a voltage control oscillator.

  The feedback circuit 14 includes, for example, a divider that divides the input frequency by N, a mixer that performs frequency conversion, or the like as means for generating the comparison frequency input to the PFD 12. The feedback circuit 14 may directly feed back the output signal of the VCO 13 to the PFD 12.

  The pretune voltage generation unit 15 is formed of, for example, a DAC, and generates a pretune voltage for adjusting the oscillation frequency of the VCO 13 in advance. The pretune voltage generation unit 15 is an example of a pretune voltage generation unit. In the present embodiment, the pretune voltage generated by the pretune voltage generation unit 15 is corrected by the pretune voltage control unit 40 and then input to the VCO 13.

  The pre-tune voltage control unit 40 includes a differential amplification circuit 50, an adder 41, an amplification circuit 60, and an output stop unit 70.

  The differential amplifier circuit 50 differentially amplifies the potential difference between both ends of the resistor 31 of the second integration circuit 30, and outputs the differentially amplified potential difference to the adder 41 as a feedback voltage. The potential difference between both ends of the resistor 31 is the difference between the output voltage V1 of the first integrating circuit 20 and the output voltage V2 of the second integrating circuit 30. This potential difference is generated by charge current or discharge current to the VCO 13. A period of V1 <V2 and a period of V1> V2 appear alternately until the tuning voltage (input voltage) of the VCO 13 converges after changing the setting of the frequency of the output signal L. When the tuning voltage of the VCO 13 converges, V1 = V2, and the potential difference between both ends of the resistor 31 becomes 0V.

  Specifically, the differential amplifier circuit 50 includes an operational amplifier 51, resistors 52 to 55, and capacitors 56 and 57. The non-inverted input terminal (+ input terminal) of the operational amplifier 51 is connected to one terminal of the resistor 31 via the resistor 52 and is grounded via the capacitor 56 and the resistor 54. The inverting input terminal (-input terminal) of the operational amplifier 51 is connected to the other terminal of the resistor 31 via the resistor 53 and to the output terminal of the operational amplifier 51 via the capacitor 57 and the resistor 55. The output terminal of the operational amplifier 51 is connected to the adder 41.

  The adder 41 adds the potential difference Vd at both ends of the resistor 31 differentially amplified by the differential amplifier circuit 50 and the pretune voltage Vp generated by the pretune voltage generation unit 15 and outputs the result to the amplifier circuit 60. It has become.

  The above-described differential amplifier circuit 50 and the adder 41 add the potential difference between both ends of the resistor 31 and the pretune voltage to generate a corrected pretune voltage in which the pretune voltage is corrected. It is an example of the means.

  The amplifier circuit 60 is configured to amplify and output the output signal of the adder 41. The amplifier circuit 60 includes an operational amplifier 61 and resistors 62 and 63. The non-inverted input terminal (+ input terminal) of the operational amplifier 61 is connected to the adder 41. The inverting input terminal (-input terminal) of the operational amplifier 61 is connected to the output terminal of the operational amplifier 61 via the resistor 62 and is grounded via the resistor 63. The output terminal of the operational amplifier 61 is connected to a switch 74 (described later) of the output stop unit 70 via a resistor 42.

  The output stop unit 70 includes a potential difference detection circuit 71, a resistor 72, a capacitor 73, and a switch 74. The output stop unit 70 is an example of a correction pretune voltage output stop unit.

  The potential difference detection circuit 71 is configured to detect the potential difference between both ends of the resistor 31 that the second integration circuit 30 has. The potential difference detection circuit 71 outputs a high level signal when the potential difference between both ends of the resistor 31 is 0 V, and can be realized, for example, with a simple configuration using a comparator circuit.

  One end of a resistor 72 is connected to the output side of the potential difference detection circuit 71, and the other end of the resistor 72 is connected to the control terminal of the switch 74 and is grounded via a capacitor 73.

  The switch 74 operates in accordance with the switching control signal C from the potential difference detection circuit 71. Specifically, the switch 74 is set to the on state during a period in which the correction pretune voltage is output to the VCO 13 in accordance with the switching control signal C from the potential difference detection circuit 71, and to the off state after the tuning voltage of the VCO 13 converges. It is a thing.

  With the above configuration, when the potential difference between both ends of the resistor 31 becomes 0 V, the output stop unit 70 can output the switching control signal C for switching the switch 74 from the on state to the off state to the switch 74. It is possible to automatically stop the output of the correction pretune voltage to the VCO 13.

  In the present embodiment, the case where the potential difference between both ends of the resistor 31 becomes 0 V does not mean only the case where the potential difference completely matches 0 V, and it can be practically used even if it is considered that the tuning voltage of the VCO 13 converges. It is sufficient if there is no problem in the potential difference. That is, the output stop unit 70 stops the output of the correction pretune voltage to the VCO 13 on the condition that the potential difference between both ends of the resistor 31 is within a predetermined voltage range including 0 V.

  A high level signal output by the potential difference detection circuit 71 when the potential difference between both ends of the resistor 31 is 0 V is output to the switch 74 after the charging time of the capacitor 43. Therefore, when the potential difference between both ends of the resistor 31 instantaneously becomes 0 V, the capacitor 73 is not fully charged, and the output stop unit 70 does not output the switching control signal C to the switch 74.

  Next, the pretune operation will be described by comparing the conventional PLL circuit with the PLL circuit 10 of the present embodiment.

  First, FIG. 2 shows the configuration of a conventional PLL circuit. As shown in FIG. 2, the conventional PLL circuit 1 includes a switch 74 and a control circuit 2 for controlling the switch 74, instead of the pretune voltage control unit 40 (see FIG. 1) in the present embodiment. ing.

  The control circuit 2 turns on the switch 74 at the start of pre-tuning and turns off the switch 74 at the end of pre-tuning. The other configuration of the conventional PLL circuit 1 is the same as that of the present embodiment.

  Next, the pre-tuning operation will be compared and described using FIG. FIG. 3 shows the conventional PLL circuit 1 (FIG. 3A) and the PLL circuit 10 of the present embodiment (FIG. 3) with respect to the output voltages of the first integrating circuit 20 and the second integrating circuit 30 during the pretuning operation. It is what represented the experimental data of (b) typically. In FIGS. 3A and 3B, the frequency setting change and application of the pretune voltage are started at time t = 0, and the output voltages of the first integration circuit 20 and the second integration circuit 30 are V1 and V2 respectively. V2, a target voltage is Vt, a pretune voltage is Vp, and initial values of V1 and V2 are V0, where Vt <V0.

  As shown in FIG. 3A, in the conventional PLL circuit 1, the output voltage V1 of the first integrating circuit 20 converges while fluctuating up and down with respect to the target voltage Vt as time passes. On the other hand, the output voltage V2 of the second integration circuit 30 gradually decreases toward the target voltage Vt more slowly than the output voltage V1 of the first integration circuit 20 with the passage of time, and fluctuates in the vicinity of the target voltage Vt. It converges.

  In the conventional PLL circuit 1, since there is an error (pretune voltage error) between the target voltage Vt and the pretune voltage Vp, the output voltage V2 of the second integration circuit 30 is substantially equal to the target voltage Vt at time t1. The application of the tune voltage Vp is turned off by the control circuit 2. This time t1 is a time obtained in advance by experiment.

  As illustrated, the output voltage V2 of the second integration circuit 30 (tuning voltage of the VCO 13) also fluctuates after time t1 when the application of the pretune voltage Vp is turned off, and it takes time to converge. Therefore, in the conventional PLL circuit 1, the tuning voltage of the VCO 13 is set to sufficiently converge even when the largest possible pretune voltage error occurs, so that a waiting time is provided as illustrated. As a result, conventionally, in most cases, the waiting time is excessive.

  On the other hand, as shown in FIG. 3B, since the PLL circuit 10 of this embodiment has a configuration for correcting the pretune voltage Vp, convergence is made while fluctuating up and down with respect to the target voltage Vt. .

  Specifically, the corrected pre-tune voltage Vpc in which the pre-tune voltage Vp has been corrected varies with the potential difference between the both ends of the resistor 31 (difference between V1 and V2) as time passes. As illustrated, the correction pretune voltage Vpc falls in the time domain of V1 <V2, rises in the time domain of V1> V2, and approaches the value of V2 with the passage of time, like V2 converges. And finally match the target voltage Vt at time t3. As a result, in the PLL circuit 10 of this embodiment, the application of the correction pretune voltage can be turned off in a state where the pretune voltage error is 0 V in a shorter time than in the related art, and the state is immediately locked to the desired frequency. be able to.

  Furthermore, since the PLL circuit 10 of the present embodiment includes the output stop unit 70, the application of the correction pretune voltage Vpc can be automatically turned off after the pretune voltage Vp is automatically corrected. A state where the tuning voltage has converged can be obtained.

  Next, the operation of the PLL circuit 10 in the present embodiment will be described using FIG. FIG. 4 is a flowchart for explaining a control method of the PLL circuit 10 in the present embodiment. In the initial state, the switch 74 is on.

  The reference signal generation unit 11 generates a reference signal of a predetermined frequency (step S11), and outputs the reference signal to the PFD 12.

  The pretune voltage generation unit 15 generates a predetermined pretune voltage Vp (step S12), and outputs the pretune voltage Vp to the adder 41.

  The PFD 12 compares the phases of the output signals of the reference signal generation unit 11 and the feedback circuit 14 to obtain a phase difference, and outputs a signal having a signal level corresponding to the phase difference to the first integration circuit 20 (step S13). .

  The first integrating circuit 20 integrates the phase error signal output from the PFD 12 and outputs the integrated signal as a first integrated signal (V1) to the second integrating circuit 30 (step S14).

  The second integrating circuit 30 integrates the first integrated signal output from the first integrating circuit 20, and outputs the integrated signal as a second integrated signal (V2) to the VCO 13 (step S15). Here, the differential amplifier circuit 50 of the pretune voltage control unit 40 differentially amplifies the potential difference between both ends of the resistor 31 of the second integration circuit 30, and uses the potential difference Vd differentially amplified as a feedback voltage. Output to The adder 41 adds the pretune voltage Vp and the potential difference Vd and outputs the result to the amplifier circuit 60. The amplifier circuit 60 amplifies the input voltage and outputs a corrected pretune voltage Vpc.

  The potential difference detection circuit 71 detects the potential difference between both ends of the resistor 31 of the second integration circuit 30 (step S16). If the potential difference is not 0 V, the pretune voltage control unit 40 corrects the corrected pretune voltage. Vpc is output to the VCO 13 (step S17).

  The VCO 13 outputs a signal of an oscillation frequency corresponding to the input voltage to the feedback circuit 14 and also outputs it as the output signal L of the PLL circuit 10 (step S18), and returns to the process of step S13.

  On the other hand, when the potential difference between both ends of the resistor 31 is 0 V in step S16, the potential difference detection circuit 71 switches the switch 74 to the off state, and stops the application of the correction pretune voltage (step S19).

  As described above, the PLL circuit 10 in the present embodiment adds the potential difference between both ends of the resistor 31 connected in series between the first integration circuit 20 and the VCO 13 and the pretune voltage to obtain the pretune voltage. Since the corrected corrected pretune voltage is generated and output to the VCO 13, the pretune voltage error can be made smaller than that in the prior art.

(Modification)
FIG. 5 shows an integration circuit 30a which replaces the second integration circuit 30 (see FIG. 1). The integration circuit 30a has two resistors 31a and 31b obtained by dividing the resistance 31 of the second integration circuit 30 into a plurality of, for example, arbitrary two resistance values. Also in this configuration, if the potential difference between both ends of the resistor 31a or 31b is detected by the potential difference detection circuit 71, the same effect as described above can be obtained.

Second Embodiment
As shown in FIG. 6, the PLL circuit 10A in the present embodiment is different from the PLL circuit 10 in the first embodiment shown in FIG. 1 in that a correction pretune voltage limiting unit 47 is provided. In addition, the same code | symbol is attached | subjected to the structure similar to the structure demonstrated in FIG. 1, and the description is abbreviate | omitted.

  The correction pretune voltage limiting unit 47 limits the correction pretune voltage Vpc to a predetermined value, for example, by setting the power supply voltage supplied to the differential amplifier circuit 50 to a predetermined voltage. The correction pretune voltage limiting unit 47 is an example of a correction pretune voltage limiting unit.

  Specifically, as shown in FIG. 7, the correction pretune voltage limiting unit 47 sets the power supply voltage supplied to the differential amplifier circuit 50 to a predetermined voltage, thereby setting the correction pretune voltage Vpc to the limit voltage Vpr. Restrict. With this configuration, since the PLL circuit 10A narrows and narrows the difference between the target voltage Vt and the correction pretune voltage Vpc, the pretune voltage error can be further reduced compared to the first embodiment.

  Note that by providing the correction pre-tuning voltage limiting unit 47, a trade-off that the error correction range is narrowed occurs simultaneously with shortening of the convergence time of the tuning voltage, so optimization of the limiting voltage Vpr is performed by experiment, for example. Is desirable.

Third Embodiment
Next, a signal analysis device 80 according to a third embodiment of the present invention will be described with reference to FIG. The signal analysis device 80 is an example of a measurement device.

As shown in FIG. 8, the signal analysis apparatus 80 of this embodiment generates an input signal by generating the local oscillation signal L capable of frequency sweeping by the PLL circuit 10 of the first embodiment constituting the local oscillation signal generator. The frequency converter 81 is provided to the mixer 82 together with S _IN , and the filter 83 extracts a signal M of a predetermined intermediate frequency band from the output of the mixer 82.

Further, the signal analysis device 80 outputs the local oscillation signal L of the PLL circuit 10 so that the signal component of the designated observation band in the input signal S _IN is output in time series from the filter 83 of the frequency conversion unit 81. A sweep control unit 84 that performs frequency sweep control, an ADC 85 that samples the output signal of the frequency conversion unit 81 and converts it into a digital signal sequence, and a signal sequence Dm output from the ADC 85 during frequency sweep of the local oscillation signal L The signal analysis unit 86 stores the frequency characteristic of the signal strength and the display unit 87 displays a waveform of the spectrum characteristic obtained by the signal analysis unit 86.

That is, the input signal S _IN is input to the mixer 82 of the frequency conversion unit 81, mixed with the local oscillation signal L from the PLL circuit 10, and among the frequency components of the difference or the sum (hereinafter referred to as difference). A signal component M of a predetermined intermediate frequency band is extracted by the filter 83.

Here, the center frequency of passage of the filter 83 is F _IF , the frequency of the local oscillation signal L is F _L, and mixing is performed in the upper heterodyne where the local frequency F _L is higher than the frequency F _IN of the analysis target signal to be converted to the intermediate frequency band. Assuming that, the relationship of F _L −F _IF = F _IN holds.

For example, if F _IF = 8 GHz and the local frequency F _L is swept from 8.1 GHz to 9 GHz, the frequency F _IN of the signal to be analyzed changes from 100 MHz to 1 GHz. That is, from the filter 83, the signal components from 100 MHz to 1 GHz in the input signal S _IN are extracted in time series in the order of the original frequency.

  Here, although a circuit example in which frequency conversion is performed once is shown, in actuality, frequency conversion processing (generally by a local oscillation signal of fixed frequency) is performed a plurality of times in the frequency conversion unit 81, Converted to a lower frequency band.

  The PLL circuit 10 can output a local oscillation signal L having a predetermined frequency. The frequency sweep of the local oscillation signal L is performed by sequentially updating the frequency data input from the sweep control unit 84.

  The sweep control unit 84 sweeps the frequency of the local oscillation signal L at a predetermined step according to the reference frequency (start frequency or center frequency), sweep width (span) specified by the operation unit 88, the number of acquired samples, etc. , And supplies information f of each frequency to the signal analysis unit 86.

  On the other hand, the signal M output from the frequency conversion unit 81 is sampled by the ADC 85 at a predetermined sampling period (a frequency of twice or more the upper limit of the pass band of the filter 83), and the digital signal string Dm obtained by the sampling Are input to the signal analysis unit 86.

  The signal analysis unit 86 correlates the digital signal sequence Dm obtained by frequency sweeping and the frequency information f, receives it, stores it in a memory (not shown), performs specified band limiting processing, etc. The characteristic of frequency versus signal strength S (f), that is, the spectrum characteristic is determined. The display unit 87 displays the waveform of the spectrum characteristic determined by the signal analysis unit 86 on the screen.

  As described above, the signal analysis apparatus 80 according to the present embodiment configures the local oscillation signal generator with the PLL circuit 10 that can make the pretune voltage error smaller than that in the conventional case, so the signal analysis device 80 can be performed in a shorter time than in the conventional It is possible to switch the frequency. As a result, the signal analysis device 80 of this embodiment can shorten the signal analysis time.

  In the above embodiment, the signal analysis apparatus 80 has been described by way of example of the configuration including the PLL circuit 10 of the first embodiment, but instead of this, a configuration including the PLL circuit 10A of the second embodiment and If so, the signal analysis time can be further shortened.

Fourth Embodiment
Next, a signal generator 90 according to a fourth embodiment of the present invention will be described with reference to FIG. The signal generator 90 is an example of a measuring device.

  As shown in FIG. 9, the signal generator 90 of this embodiment includes a waveform data storage unit 91, DACs 92 and 93, an orthogonal modulator 94, and a PLL circuit 10 of the first embodiment that constitutes a local oscillation signal generator. A level control circuit (ALC) 95, an operation unit 96, a setting unit 97, and a step attenuator (step ATT) 98 are provided.

  The waveform data storage unit 91 stores baseband waveform data of digital values as a plurality of test signal data for testing the device under test. The tester operates the operation unit 96 to select and output the test signal data stored in the waveform data storage unit 91 through the setting unit 97. The test signal data includes waveform data of baseband of I-phase component (in-phase component) and Q-phase component (quadrature component). The waveform data is generated by, for example, a DSP (Digital Signal Processor) not shown.

  The DACs 92 and 93 convert baseband signal waveform data of digital values of the I-phase component and the Q-phase component output from the waveform data storage unit 91 into analog values and output the analog signal values to the quadrature modulator 94. .

  The PLL circuit 10 generates a local oscillation signal L of a local oscillation frequency based on the setting signal from the setting unit 97, and outputs the local oscillation signal L to the quadrature modulator 94.

  The quadrature modulator 94 performs quadrature modulation and frequency conversion by multiplying the I-phase component from the DAC 92 and the Q-phase component from the DAC 93 by the local oscillation signal L input from the PLL circuit 10 to obtain a radio frequency signal ( (RF signal) is generated and output to ALC 95.

  The ALC 95 adjusts the power level of the output signal of the quadrature modulator 94 to a predetermined power level and outputs it to the step ATT 98. The power level set by the ALC 95 is set by the setting signal from the setting unit 97. The ALC 95 can adjust the output signal level, for example, in 0.1 dB steps.

  The operation unit 96 is operated by the tester for setting the test conditions and the test procedure, and includes, for example, an input device such as a keyboard, a dial or a mouse, and a control circuit for controlling these. . The test conditions set by the tester include, for example, waveform data stored in the waveform data storage unit 91, an output level of an RF test signal output from the step ATT 98, a radio frequency, and the like.

  The setting unit 97 is configured of, for example, a microcomputer, and controls the entire apparatus. In addition, setting section 97 sets a setting signal for setting each test condition to waveform data storage section 91, PLL circuit 10, ALC 95, and step ATT 98 based on each test condition set by the tester operating operation section 96. It outputs and sets each test condition.

  Here, as a setting for the ALC 95, for example, when the user sets the output level of the signal generator 90 to -40.2 dBm, the setting unit 97 sets the attenuation amount of step ATT 98 to 30 dB. It outputs a control signal for setting the output signal level to -10.2 dBm.

  The step ATT 98 includes a plurality of attenuator sections in which the respective attenuations are predetermined, and the combination of the attenuations of the respective attenuator sections can attenuate the level of the input RF signal in steps of a predetermined attenuation. It is. This step ATT 98 attenuates the input signal by the attenuation amount set by the setting signal from the setting unit 97, and outputs the RF test signal of the power level desired by the tester.

  The signal generator 90 of the present embodiment configured as described above constitutes a local oscillation signal generator with the PLL circuit 10 capable of making the pretune voltage error smaller than that of the prior art, so it is shorter than the prior art. It is possible to switch the frequency by time. As a result, the signal generator 90 of this embodiment can shorten the frequency switching time.

  In the above-described embodiment, the signal generator 90 has been described by way of example of the configuration including the PLL circuit 10 of the first embodiment. However, instead of this, a configuration including the PLL circuit 10A of the second embodiment If so, the frequency switching time can be further shortened.

  As described above, the PLL circuit according to the present invention, the measuring apparatus provided with the same, and the control method of the PLL circuit have an effect that pretune voltage error can be made smaller than before, and a spectrum analyzer or signal generation is generated. It is useful as a PLL circuit of a measuring device such as an instrument and a control method thereof.

10, 10A PLL circuit 11 Reference signal generator (signal generator)
12 PFD (phase frequency comparator)
13 VCO (voltage controlled oscillator)
14 feedback circuit 15 pretune voltage generation unit (pretune voltage generation means)
20 First integrating circuit (integrating means, first integrating means)
30 Second integration circuit (second integration means)
30a integration circuit 31 resistance 40 pretune voltage control unit 41 adder (pretune voltage correction means)
47 Correction pretune voltage limiter (correction pretune voltage limiter)
50 Differential amplifier circuit (pretune voltage correction means)
70 Output stop part (corrected pretune voltage output stop means)
71 Potential difference detection circuit 72 Resistance 73 Capacitor 74 Switch 80 Signal analyzer (measuring device)
90 Signal Generator (Measurement Device)

Claims (9)

Signal generation means (11) for generating a signal of a predetermined frequency;
A voltage control oscillator (13) that outputs a signal of an oscillation frequency corresponding to the input voltage;
A phase frequency comparator (12) which compares the output signals of the signal generation means and the voltage control oscillator and outputs a phase error signal;
Integrating means (20) for integrating the phase error signal;
A resistor (31) connected in series between the integrating means and the voltage controlled oscillator;
Pretune voltage generation means (15) for generating a pretune voltage for adjusting in advance the oscillation frequency of the voltage controlled oscillator;
Pretune voltage correction means (41, 50) for generating a corrected pretune voltage obtained by correcting the pretune voltage by adding the potential difference between both ends of the resistor and the pretune voltage, and outputting the corrected pretune voltage to the voltage controlled oscillator;
PLL circuit (10, 10A) characterized by having.   It further comprises a correction pretune voltage output stopping means (70) for stopping the output of the correction pretune voltage on condition that the potential difference between both ends of the resistor is within a predetermined voltage range including 0 V. The PLL circuit (10A) according to claim 1, wherein. The integrating means according to claim 1 is provided as a first integrating means for outputting a first integrated signal,
A second integration means (30) comprising the resistor and integrating the first integration signal to output a second integration signal to the voltage controlled oscillator, further comprising: The PLL circuit according to Item 2.   The PLL circuit according to any one of claims 1 to 3, further comprising correction pre-tune voltage limiting means (47) for limiting the correction pre-tune voltage to a predetermined value. The pretune voltage correction means comprises a differential amplifier circuit (50) for differentially amplifying the potential difference between both ends of the resistor,
The correction pre-tune voltage limiting means limits the correction pre-tune voltage to a predetermined value by adjusting a power supply voltage supplied to the differential amplifier circuit. PLL circuit.   A measuring apparatus (80, 90) comprising the PLL circuit according to any one of claims 1 to 5.   7. The measurement apparatus according to claim 6, wherein the PLL circuit generates a local oscillation signal of a predetermined local oscillation frequency. A control method of a PLL circuit according to any one of claims 1 to 5,
A signal generation step (S11) of generating a signal of a predetermined frequency;
A frequency signal output step (S18) for outputting a signal of a frequency according to the input voltage;
A phase error signal output step (S13) of comparing each output signal of the signal generation means and the voltage control oscillator and outputting a phase error signal;
Integrating the phase error signal (S14);
A pretune voltage generation step (S12) of generating a pretune voltage for adjusting the oscillation frequency of the voltage control oscillator in advance;
A pretune voltage correction step (S17) of adding a potential difference between both ends of the resistor and the pretune voltage to generate a corrected pretune voltage obtained by correcting the pretune voltage and outputting the corrected pretune voltage to the voltage controlled oscillator;
And controlling the PLL circuit.   The method further includes a correction pretune voltage output stopping step (S19) of stopping the output of the correction pretune voltage on condition that the potential difference between both ends of the resistor is within a predetermined voltage range including 0 V. The control method of the PLL circuit according to claim 8.

Images