JP5936937B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a semiconductor device provided with a thin film transistor and a technique effective when applied to manufacturing.

  A thin film transistor (TFT) is widely used as a pixel switch for driving a pixel of an FPD (Flat Panel Display) such as a liquid crystal display because it can be manufactured on a substrate having a large area. Applied.

  As for these FPDs, the use of flexible substrates is being studied from the viewpoint of physical distribution systems such as material procurement or the impact resistance of small and medium-sized displays as the area of the substrates increases. Further, from the viewpoint of cost reduction, adoption of a so-called roll-to-roll manufacturing technique for continuously manufacturing thin film transistors on a flexible substrate while moving a flexible substrate made of a long resin film has been studied.

  In addition, a flexible device in which various devices including thin film transistors are formed on a flexible substrate is applied not only to FPD but also to electronic devices including various analog circuits or digital circuits such as RFID (Radio Frequency Identification). There is expected. Therefore, there is an urgent need to put into practical use a roll-to-roll manufacturing technique for continuously forming thin film transistors on a flexible substrate.

  However, in such roll-to-roll manufacturing technology, the resin film used as a flexible substrate is likely to be uneven and stretchable, so that the desired pattern can be precisely aligned and aligned by processing using lithography technology. It is difficult to form with high accuracy. Also, using a drawing process such as an electron beam as the exposure process is disadvantageous from the viewpoint of cost reduction, although the shape accuracy can be improved.

  As a technique for such a roll-to-roll manufacturing technique, there is a method of forming a thin film transistor by a printing technique (see, for example, Non-Patent Document 1). Japanese Patent Laid-Open No. 2010-267719 (Patent Document 1) discloses that in a thin film transistor manufacturing process, a thin film electronic material layer is formed on a transfer mold on which a release layer has been formed in advance, and the formed thin film electronic material layer is separated. A transfer technique for transferring onto a substrate is described.

JP 2010-267719 A

M. Jung et al., IEEE Trans. Electron Devices, 57, p. 571 (2010)

  According to the study of the present inventor, the following has been found.

  The shape accuracy and alignment accuracy of the pattern processed by the printing technique or the transfer technique as described above are about 10 μm. On the other hand, the gate length (channel length) of a thin film transistor used for FPD is about several μm. Therefore, when the printing technique or the transfer technique is used, it is difficult to ensure the shape accuracy and alignment accuracy necessary for forming a thin film transistor having a gate length (channel length) of about several μm.

  In addition, when the shape accuracy or alignment accuracy necessary for forming such a thin film transistor cannot be ensured, the thin film transistor formed in each pixel of the FPD has, for example, an on-state current (on-state current) or an off-state state. The transistor characteristics such as current (off-state current) may vary.

  As described above, since the adoption of the roll-to-roll manufacturing technology and the securing of the shape accuracy and the alignment accuracy cannot be achieved at the same time, the performance of the semiconductor device including the thin film transistor manufactured by the roll-to-roll manufacturing technology is deteriorated.

  An object of the present invention is to provide a technique capable of improving the performance of a semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A semiconductor device according to a typical embodiment includes a TFT line member on which a thin film transistor is formed. The TFT line member has a conductor wire functioning as a gate line as a core wire, and the surface of the conductor wire is sequentially covered with a gate insulating film and a channel layer.

  In addition, a method for manufacturing a semiconductor device according to a typical embodiment is to form a thin film transistor as a TFT line member. A TFT line member is formed by sequentially covering the surface of the conductor line with a gate insulating film and a channel layer. Then, two source / drain electrodes are formed on the substrate, the TFT line member is arranged so as to be sandwiched between the two source / drain electrodes, and at positions separated from each other along the circumferential direction of the cross section of the TFT line member. Each of the two source / drain electrodes is electrically connected to the channel layer.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  According to the representative embodiment, the performance of the semiconductor device can be improved.

3 is a cross-sectional view of the thin film transistor of Embodiment 1. FIG. 2 is a perspective view of a thin film transistor of Embodiment 1. FIG. It is a perspective view of a TFT line member. It is sectional drawing which shows the modification of a TFT line member. It is sectional drawing which shows the other modification of a TFT line member. It is sectional drawing which shows the further another modification of a TFT line member. It is sectional drawing which shows the further another modification of a TFT line member. It is a side view including the partial cross section for demonstrating the process of forming a gate insulating film. It is a perspective view including the partial cross section for demonstrating the process of forming a gate insulating film. It is sectional drawing of the conductor line in which the gate insulating film was formed. It is a side view including the partial cross section for demonstrating the process of forming a channel layer. It is a perspective view including the partial cross section for demonstrating the process of forming a channel layer. It is sectional drawing of the conductor wire in which the channel layer was formed. It is a top view including the partial cross section for demonstrating the process of forming an electrode member. It is sectional drawing for demonstrating the process of forming an electrode member. 4 is a graph illustrating an example of measurement results of current-voltage characteristics of a thin film transistor which is the semiconductor device of the first embodiment. 6 is a cross-sectional view of a thin film transistor of a first modification of the first embodiment. FIG. It is sectional drawing for demonstrating the process of forming a channel layer. FIG. 6 is a cross-sectional view of a thin film transistor of a second modification example of the first embodiment. It is a figure for demonstrating Embodiment 2 of this invention, Comprising: It is a figure which shows the drive circuit of the active matrix TFT array for active matrix type liquid crystal displays. It is a top view of the active matrix TFT array for active matrix type liquid crystal displays. It is sectional drawing of the active matrix TFT array for active matrix type liquid crystal displays. It is a figure which shows the drive circuit of an organic electroluminescent display. It is a side view including the partial cross section for demonstrating the manufacturing process of an active matrix TFT array. It is a perspective view for demonstrating the process of arrange | positioning a TFT line member. It is a side view for demonstrating the process of arrange | positioning a TFT line member. It is a top view for demonstrating the state by which the TFT line member is arrange | positioned. It is a figure for demonstrating Embodiment 3 of this invention, Comprising: It is a circuit diagram which shows an example which applied the thin-film transistor to the bridge type rectifier circuit. It is a top view which shows the example of arrangement | positioning of the thin-film transistor in a bridge type rectifier circuit. It is sectional drawing of the bridge type rectifier circuit shown in FIG.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  Further, in the drawings used in the embodiments, hatching may be omitted even in a cross-sectional view for easy viewing of the drawings. Further, even a plan view may be hatched to make the drawing easy to see.

(Embodiment 1)
<Thin film transistor>
A semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. The semiconductor device of this embodiment includes a thin film transistor.

  FIG. 1 is a cross-sectional view of the thin film transistor of the first embodiment. FIG. 2 is a perspective view of the thin film transistor of the first embodiment. FIG. 3 is a perspective view of the TFT line member.

  As shown in FIG. 1, the thin film transistor 10 according to the first embodiment includes a support substrate 11, a TFT line member (line member) 12, and source / drain electrodes 13 and 14.

  The TFT wire member (wire member) 12 has a conductor wire 20 as a core wire, and the surface of the conductor wire 20 is sequentially covered with a gate insulating film (insulating film) 21 and a channel layer (semiconductor layer) 22. It is what. That is, in the first embodiment, the thin film transistor 10 is formed on the TFT line member (line member) 12.

  FIG. 1 shows a cross section perpendicular to the direction in which the TFT line member (line member) 12 extends, that is, the direction in which the conductor line 20 extends.

  The conductor wire 20 is a thin wire having a circular cross-sectional shape. The conductor line 20 is made of a conductive material such as a metal material, and the conductor line 20 itself also serves as a gate line. When the conductor wire 20 is a metal wire made of a metal material, for example, aluminum (Al) can be used as the metal material. Thereby, the internal resistance of the gate line can be reduced. Moreover, the diameter of the conductor wire 20 can be about 1-5 micrometers, for example. With such a configuration, the gate length (channel length) can be reduced to, for example, about several μm, and the thin film transistor can be miniaturized.

  As the conductive material of the conductor wire 20, in addition to a metal material, for example, a carbon-based conductive material, an inorganic conductive material such as ITO (Indium Tin Oxide), or an organic conductive material such as polythiophene can be used. In addition, a plurality of types of these conductive materials can be used in combination by mixing or laminating in the radial direction. Further, as the conductor wire 20, a core wire made of a semiconductor or an insulator can be used which is covered with a conductor film made of one or more kinds of materials among the above-described conductive materials.

  Hereinafter, an example in which the cross-sectional shape of the conductor wire 20 is circular as illustrated in FIG. 1 will be described. However, as will be described in a later-described modification, the cross-sectional shape of the conductor wire is elliptical, polygonal, or flat rectangular. It can also be.

The surface of the conductor wire 20, that is, the outer peripheral surface of the conductor wire 20, is covered with the gate insulating film 21 over the entire surface, that is, the entire periphery. The gate insulating film 21 functions as a gate insulating film of the thin film transistor 10 and also functions as an insulating film that secures insulation between the conductor line 20 and other wirings. The gate insulating film 21 is made of, for example, silicon oxide (SiO ₂ ) or silicon nitride (Si ₃ N ₄ ), and is formed by, for example, a CVD (Chemical Vapor Deposition) method. The thickness of the gate insulating film 21 depends on the dielectric constant of the gate insulating film 21 and the like, but can be about 10 to 200 nm, for example.

  The surface of the gate insulating film 21, that is, the outer peripheral surface of the gate insulating film 21, is covered with the channel layer 22 over the entire surface, that is, the entire periphery. The channel layer 22 is a semiconductor layer made of various semiconductor materials. The channel layer 22 is formed by various film forming methods such as CVD, sputtering, or vacuum deposition. The thickness of the channel layer 22 depends on the conductivity of the channel layer 22 or the dielectric constant and thickness of the gate insulating film 21, but can be about 5 to 80 nm, for example.

  The channel layer 22 is preferably made of amorphous silicon (a-Si), polysilicon (Poly-Si), or indium gallium zinc oxide (IGZO) or zinc tin composite oxide (Zinc Tin). It is made of an oxide semiconductor material containing Oxide (ZTO). When the channel layer 22 is made of such a material, good characteristics equivalent to those of a thin film transistor formed on a glass substrate by a normal manufacturing process can be obtained.

  Further, as shown in FIG. 3, the surface of the gate insulating film 21, that is, the outer peripheral surface of the gate insulating film 21, in a plurality of regions AR <b> 1 separated from each other along the direction in which the conductor line 20 (TFT line member 12) extends. Is covered with a channel layer 22. The region AR1 is a region where one thin film transistor 10 is formed. With such a configuration, since a plurality of thin film transistors 10 can be formed on one TFT line member 12, a semiconductor device in which a plurality of thin film transistors 10 are arranged, for example, an active matrix TFT array as described later Can be easily manufactured.

  The support substrate 11 is for supporting the TFT line member 12 and the source / drain electrodes 13 and 14. The support substrate 11 is made of, for example, glass, quartz, resin, or the like. The support substrate 11 is preferably a resin film made of, for example, PEN (Polyethylene Naphtalate) resin, PET (Polyethylene Terephthalate) resin, or the like. As a result, as will be described later, while feeding a long resin film from a roll on the feed side wound in a roll shape, the active matrix TFT array is placed on the resin film while winding the resin film on the roll on the take-up side. A so-called roll-to-roll manufacturing technique that is continuously formed can be applied. Therefore, the active matrix TFT array can be manufactured at high speed and at low cost.

  The source / drain electrodes 13 and 14 are formed on the support substrate 11 at positions separated from each other along a direction intersecting (orthogonal) with the conductor wire 20 (TFT line member 12) in plan view. The source / drain electrode 13 and the source / drain electrode 14 support the TFT line member 12 sandwiched from both sides. One of the source / drain electrodes 13 and 14 functions as a source electrode, and the other functions as a drain electrode. The source / drain electrodes 13, 14 have a bump shape, and the TFT line member 12 is sandwiched between the source / drain electrode 13 and the source / drain electrode 14, so that the TFT line member 12 is supported on the support substrate. 11 is a fastener (support member) that is fastened (supported).

  Further, as will be described later with reference to FIG. 21 in the second embodiment, in the region corresponding to the plurality of regions AR1 separated from each other along the direction in which the conductor line 20 (TFT line member 12) extends, the source / drain electrodes 13 and 14 can be formed. The source / drain electrodes 13 and the source / drain electrodes 14 formed in the regions corresponding to the respective regions AR1 are in a plurality of regions AR1 separated from each other along the direction in which the conductor line 20 (TFT line member 12) extends. The TFT line member 12 is sandwiched and supported from both sides.

  As shown in FIGS. 1 and 2, the side surface 13 a which is the side surface of the source / drain electrode 13 and faces the source / drain electrode 14 is in contact with the channel layer 22 of the TFT line member 12. The electrode 13 and the channel layer 22 are electrically connected. Further, the side surface 14 a which is the side surface of the source / drain electrode 14 and faces the source / drain electrode 13 is in contact with the channel layer 22 of the TFT line member 12, so that the source / drain electrode 14 and the channel layer 22 are connected. Electrically connected.

  In the cross section perpendicular to the direction in which the conductor line 20 (TFT line member 12) extends, the source / drain electrodes 13 and 14 are separated from each other along the circumferential direction of the cross section of the conductor line 20 (TFT line member 12). In contact with the channel layer 22 at the positions P1 and P2. That is, in the cross section perpendicular to the direction in which the conductor wire 20 (TFT line member 12) extends, each of the source / drain electrodes 13 and 14 extends along the circumferential direction of the conductor wire 20 (TFT line member 12). The channel layer 22 is electrically connected at positions P1 and P2 that are separated from each other.

  Note that the circumferential direction of the cross section of the conductor wire 20 (TFT line member 12) in the cross section perpendicular to the direction in which the conductor wire 20 (TFT line member 12) extends is the direction indicated by the arrow CD in FIG.

  At this time, the distance L1 between the position P1 and the position P2 along the circumferential direction of the conductor wire 20 (TFT line member 12) corresponds to the gate length (channel length) of the thin film transistor 10. As will be described later in the thin film transistor manufacturing process, the distance between the source / drain electrodes 13 and 14 can be easily controlled. When the distance between the source / drain electrodes 13 and 14 is constant, the gate length (channel length), that is, the distance L1 between the position P1 and the position P2 depends on the diameter D1 of the conductor wire 20. Therefore, in the thin film transistor 10 of the first embodiment, the gate length (channel length) can be easily controlled by controlling the diameter D1 of the conductor wire 20.

  In FIG. 1, for easy understanding, in the cross section perpendicular to the direction in which the conductor line 20 (TFT line member 12) extends, each of the source / drain electrodes 13, 14 contacts with the channel layer 22 at a position P 1 and The position P2 is displayed as a point. That is, in the cross section perpendicular to the direction in which the conductor wire 20 (TFT line member 12) extends, the source / drain electrodes 13 and 14 are in contact with the channel layer 22 at points.

  However, when the source / drain electrodes 13 and 14 or the TFT line member 12 is deformed by a minute amount, the source / drain electrodes 13 and 14 in the cross section perpendicular to the extending direction of the conductor line 20 (TFT line member 12) , Each may contact the channel layer 22 in a region having a certain length. In such a case, the position P1 is the conductor line 20 (of the region where the source / drain electrode 13 is in contact with the channel layer 22 in the cross section perpendicular to the direction in which the conductor line 20 (TFT line member 12) extends. This is the point closest to the region where the source / drain electrode 14 is in contact with the channel layer 22 along the circumferential direction of the cross section of the TFT line member 12). Further, the position P2 is a conductor line 20 (TFT line member 12) in a region where the source / drain electrodes 14 are in contact with the channel layer 22 in a cross section perpendicular to the direction in which the conductor line 20 (TFT line member 12) extends. This is the point closest to the region where the source / drain electrode 13 is in contact with the channel layer 22 along the circumferential direction.

  Alternatively, as will be described later with reference to FIG. 19, the shape of the side surfaces 13 a and 14 a of the source / drain electrodes 13 and 14 can correspond to the shape of the conductor wire 20. Thus, the source / drain electrodes 13 and 14 and the channel layer 22 can be brought into contact with each other in a region having a certain length in a cross section perpendicular to the extending direction of the conductor wire 20 (TFT line member 12).

  The source / drain electrodes 13 and 14 are made of a metal such as copper (Cu) or tungsten (W), for example, and are formed by, for example, a screen printing method, an ink jet method, a plating method, or the like. Thereby, the internal resistance of the source / drain electrodes 13 and 14 can be reduced.

  The source / drain electrode 13 and the channel layer 22 can be connected through, for example, a conductive adhesive, and the source / drain electrode 14 and the channel layer 22 can be connected through, for example, a conductive adhesive. Can be connected. With such a configuration, the channel layer 22 and the source / drain electrodes 13 and 14 can be electrically connected with low resistance.

  Preferably, the side surface 13a of the source / drain electrode 13 and the side surface 14a of the source / drain electrode 14 are inclined so that the height from the support substrate 11 increases. That is, in FIG. 1, the cross-sectional shape of the recess CC <b> 1 having the side surface 13 a of the source / drain electrode 13 and the side surface 14 a of the source / drain electrode 14 as both side walls has an upper base length larger than a lower base length. It has an inverted trapezoidal shape. By having such a shape, the TFT line member 12 is dropped into the concave portion CC1, so that the position of the TFT line member 12 along the direction intersecting (orthogonal) with the conductor line 20 (TFT line member 12) in plan view. Can be adjusted accurately. Therefore, in a plan view, the position of the TFT line member 12 along the direction intersecting (orthogonal) with the conductor line 20 (TFT line member 12) can be easily adjusted with high accuracy.

  The height H1 of the upper surfaces of the source / drain electrodes 13 and the source / drain electrodes 14 from the upper surface of the support substrate 11, that is, the height dimension H1 of the source / drain electrodes 13 and the source / drain electrodes 14 is preferably a conductor. It is larger than the diameter D1 of the wire 20, that is, the height dimension D1 from the lowest point to the highest point of the conductor wire 20. When the height dimension H1 of the source / drain electrode 13 and the source / drain electrode 14 is larger than the height dimension D1 from the lowest point to the highest point of the conductor line 20, the TFT line member 12 is further formed in the recess CC1. Can be easily dropped. Therefore, in the plan view, the position of the TFT line member 12 along the direction intersecting (orthogonal) with the conductor line 20 (TFT line member 12) can be more accurately aligned. Therefore, the position of the TFT line member 12 along the direction intersecting (orthogonal) with the TFT line member 12 in a plan view can be adjusted more easily and with high accuracy.

  Preferably, the height dimension H1 of the source / drain electrode 13 and the source / drain electrode 14 is set to the diameter of the TFT line member 12, that is, the diameter D1 of the conductor line 20, and the thickness of the gate insulating film 21 and the channel layer 22 is. It is larger than the dimension obtained by adding a dimension twice as long as the length. When satisfying such a size relationship, the TFT line member 12 can be more easily dropped into the concave portion CC1, so that the TFT line member along the direction intersecting (orthogonal) with the TFT line member 12 in a plan view. The positions of 12 can be adjusted more easily and with high accuracy.

  Further, as described above, the TFT line member 12 whose gate length (channel length) is controlled by controlling the diameter D1 of the conductor line 20 is sandwiched between the source / drain electrode 13 and the source / drain electrode 14. Thus, it is supported on the support substrate 11. Therefore, for example, when forming an active matrix TFT array, each thin film transistor can be manufactured by a simple method while ensuring the accuracy of the gate length (channel length). That is, a fine pattern of a thin film transistor can be processed without using a large-scale manufacturing apparatus for processing a pattern on the support substrate 11 by photolithography.

  Preferably, along the direction in which the conductor line 20 (TFT line member 12) extends, the length dimension of the region AR1 (the length dimension W1 in FIG. 21 described later) is the source / drain electrode 13 and the source / drain electrode. 14 is greater than the length dimension (length dimension W2 in FIG. 21 described later). In this case, the gate width (channel width) of the thin film transistor 10 is equal to the length of the source / drain electrode 13 and the source / drain electrode 14 along the direction in which the conductor line 20 (TFT line member 12) extends. Therefore, the gate width (channel width) can be controlled by controlling the length dimensions of the source / drain electrodes 13 and the source / drain electrodes 14 along the direction in which the conductor line 20 (TFT line member 12) extends. it can.

  On the other hand, when the length dimension of the region AR1 is larger than the length dimension of the source / drain electrode 13 and the source / drain electrode 14 along the direction in which the conductor line 20 (TFT line member 12) extends, the channel layer When forming 22, it is not necessary to control the length dimension of the area AR1 with high accuracy.

  Further, when the length dimension of the region AR1 is larger than the length dimension of the source / drain electrode 13 and the source / drain electrode 14 along the direction in which the conductor line 20 (TFT line member 12) extends, the TFT line When arranging the member 12, it is not necessary to align the position of the TFT line member 12 along the direction in which the conductor wire 20 (TFT line member 12) extends with high accuracy. Therefore, for example, effective alignment accuracy is improved as compared with a case where the thin film transistor is transferred onto the substrate by a transfer technique.

<Modification of TFT wire member>
4 to 7 are cross-sectional views showing modifications of the TFT line member. 4 shows that the cross-sectional shape of the conductor wire is elliptical, FIG. 5 shows that the cross-sectional shape of the conductor wire is polygonal, FIG. 6 shows that the cross-sectional shape of the conductor wire is a flat rectangle, and FIG. An example in which a member is provided will be described. 4 to 7, members having the same functions as those of the thin film transistor of FIG. 1 are denoted by the same reference numerals, and repetitive description thereof is omitted. 4 to 7 show a cross section perpendicular to the direction in which the TFT line member (line member), that is, the conductor line extends.

  In the modification shown in FIG. 4, the cross-sectional shape of the conductor wire 20a is an ellipse. The TFT line member (line member) 12a of the thin film transistor 10a also has an overall cross-sectional shape of an ellipse, and the surface of the conductor wire 20a as a core wire is covered by a gate insulating film (insulating film) 21 and a channel layer (semiconductor layer) 22. Sequentially coated. In the cross section perpendicular to the direction in which the conductor line 20a (TFT line member 12a) extends, the source / drain electrodes 13 and 14 are located at positions P1 and P2 that are separated from each other along the circumferential direction of the cross section of the conductor line 20a. The channel layer 22 is electrically connected. The distance between the positions P1 and P2 along the circumferential direction of the conductor line 20a, that is, the distance L2 between the position P1 and the position P2 corresponds to the gate length (channel length) of the thin film transistor 10a.

  Preferably, the height dimension H2 of the source / drain electrodes 13, 14 is larger than the height dimension D2 from the lowest point to the highest point of the conductor wire 20a. With such a configuration, even when the cross-sectional shape of the conductor wire 20a is elliptical, the TFT line member 12a can be easily dropped into the recess CC1 formed by the side surfaces 13a and 14a of the source / drain electrodes 13 and 14. it can. Therefore, in a plan view, the position of the TFT line member 12a along the direction intersecting (orthogonal) with the conductor line 20a (TFT line member 12a) can be more easily and accurately adjusted.

  In the modification shown in FIG. 5, the cross-sectional shape of the conductor wire 20 b is a polygon, and can be, for example, a hexagon as shown in FIG. 5. The TFT line member (line member) 12b of the thin film transistor 10b is also polygonal (hexagonal) in overall cross-sectional shape, and the surface of the conductor wire 20b as a core wire is formed with a gate insulating film (insulating film) 21 and a channel layer (semiconductor). Layer) 22 sequentially. In the cross section perpendicular to the direction in which the conductor line 20b (TFT line member 12b) extends, the source / drain electrodes 13 and 14 are regions (positions) PA1 that are separated from each other along the circumferential direction of the cross section of the conductor line 20b. , PA2, and is electrically connected to the channel layer 22. The distance between the regions (positions) PA1 and PA2, ie, the distance L3 between the region (position) PA1 and the region (position) PA2 along the circumferential direction of the conductor wire 20b is the gate length (channel length) of the thin film transistor 10b. Equivalent to.

  Preferably, the height dimension H3 of the source / drain electrodes 13, 14 is larger than the height dimension D3 from the lowest point to the highest point of the conductor wire 20b. With such a configuration, even when the cross-sectional shape of the conductor wire 20b is a polygon, the TFT line member 12b can be easily dropped into the recess CC1 formed by the side surfaces 13a and 14a of the source / drain electrodes 13 and 14. it can. Therefore, in a plan view, the position of the TFT line member 12b along the direction intersecting (orthogonal) with the conductor line 20b (TFT line member 12b) can be more easily and accurately adjusted.

  In the modification shown in FIG. 6, the cross-sectional shape of the conductor wire 20c is a flat rectangle. The TFT line member (line member) 12c of the thin film transistor 10c also has a flat cross-sectional shape as a whole, and the surface of the conductor line 20c as a core wire is covered by a gate insulating film (insulating film) 21 and a channel layer (semiconductor layer) 22. Sequentially coated. In the cross section perpendicular to the direction in which the conductor line 20c (TFT line member 12c) extends, the source / drain electrodes 13, 14 are regions (positions) PA1 that are separated from each other along the circumferential direction of the cross section of the conductor line 20c. , PA2, and is electrically connected to the channel layer 22. The distance between the regions (positions) PA1 and PA2, ie, the distance L4 between the region (position) PA1 and the region (position) PA2, along the circumferential direction of the conductor wire 20c is the gate length (channel length) of the thin film transistor 10c. Equivalent to.

  Preferably, the height dimension H4 of the source / drain electrodes 13, 14 is larger than the height dimension D4 from the lowest point to the highest point of the conductor wire 20c. In the example shown in FIG. 6, the source / drain electrodes 13, 14 have an L-shaped cross section composed of a bottom surface portion and a side wall portion, and the height H 4 of the source / drain electrodes 13, 14 is set to the bottom surface portion. It is assumed that the height is from the upper surface to the upper surface of the side wall portion. With such a configuration, the TFT line member 12c can be easily dropped into the recess CC1 formed by the side surfaces 13a and 14a of the source / drain electrodes 13 and 14 even when the cross-sectional shape of the conductor line 20c is a flat rectangle. it can. Therefore, in a plan view, the position of the TFT line member 12c along the direction intersecting (orthogonal) with the conductor line 20c (TFT line member 12c) can be more easily and accurately adjusted.

  In the specification of the present application, that the cross-sectional shape is a flat quadrangle means that the cross-sectional shape is a flat plate or block shape, and that the height dimension of the cross-sectional shape is smaller than the width dimension. To do.

  In the modification shown in FIG. 7, the conductor wire 20 has a circular cross-sectional shape. The TFT line member (line member) 12d of the thin film transistor 10d also has a circular overall cross-sectional shape, and the surface of the conductor line 20 as a core wire is sequentially formed by a gate insulating film (insulating film) 21 and a channel layer (semiconductor layer) 22. It is coated. In the cross section perpendicular to the direction in which the conductor wire 20 (TFT line member 12d) extends, the electrode member is formed on the surface of the channel layer 22, that is, the outer peripheral surface, at positions separated from each other along the circumferential direction of the cross section of the conductor wire 20. 23 and 24 are formed. The electrode members 23 and 24 are formed along the direction in which the conductor wire 20 (TFT line member 12d) extends.

  The source / drain electrode 13 is in contact with the electrode member 23, and the source / drain electrode 14 is in contact with the electrode member 24. Accordingly, the electrode member 23 is electrically connected to the source / drain electrode 13 and functions as one source / drain electrode integrally with the source / drain electrode 13. The electrode member 24 is electrically connected to the source / drain electrode 14, and is integrated with the source / drain electrode 14 and functions as the other source / drain electrode. That is, even in the modification shown in FIG. 7, the source / drain electrodes are separated from each other along the circumferential direction of the cross section of the conductor line 20 in the cross section perpendicular to the direction in which the conductor line 20 (TFT line member 12 d) extends. Thus, it is electrically connected to the channel layer 22.

  The electrode members 23 and 24 are conductor layers made of a metal such as tungsten (W), molybdenum (Mo), copper (Cu), or a conductive metal nitride such as titanium nitride (TiN). Moreover, the electrode members 23 and 24 are formed by various film-forming methods, such as CVD method, a sputtering method, or a vacuum evaporation method, for example.

  In the modification shown in FIG. 7, in the cross section perpendicular to the direction in which the conductor wire 20 (TFT line member 12d) extends, the electrode members 23 and 24 along the circumferential direction of the cross section of the conductor wire 20 (TFT line member 12d). The distance, that is, the distance L5 between the electrode member 23 and the electrode member 24 corresponds to the gate length (channel length) of the thin film transistor 10d. As will be described later in the thin film transistor manufacturing process, in the process of forming the electrode members 23 and 24, the distance between the electrode members 23 and 24 along the circumferential direction of the conductor wire 20 (TFT line member 12d) can be easily controlled. It is. When the distance between the electrode members 23 and 24 is constant, the gate length (channel length) depends on the diameter D1 of the conductor wire 20. Therefore, the gate length (channel length) can be easily controlled by controlling the diameter D1 of the conductor wire 20.

<Manufacturing process of thin film transistor>
Subsequently, a manufacturing process of the thin film transistor which is the semiconductor device of the first embodiment will be described.

  First, a support substrate 11 having source / drain electrodes 13 and 14 formed thereon is prepared.

  For example, a source / drain electrode 13 and a source / drain electrode 14 are formed on a support substrate 11 made of glass, quartz, resin, or the like, and made of a metal such as Cu or W, for example, by a screen printing method, an inkjet method, a plating method, or the like. Prepare what was done.

  Moreover, the conductor wire 20 is prepared.

  As the conductor wire 20, a metal wire made of a metal material such as Al and having a diameter of about 1 to 5 μm is prepared. Alternatively, as described above, as the conductive material of the conductor wire 20, in addition to a metal material, for example, a carbon-based conductive material, for example, an inorganic conductive material such as ITO, or an organic conductive material such as polythiophene can be used.

  Next, the gate insulating film 21 is formed.

  FIG. 8 is a side view including a partial cross section for explaining the step of forming the gate insulating film. FIG. 9 is a perspective view including a partial cross-section for explaining the step of forming the gate insulating film. FIG. 10 is a cross-sectional view of a conductor line on which a gate insulating film is formed.

  In the step of forming the gate insulating film 21, the surface of the conductor wire 20 is covered with the gate insulating film 21 by using a film forming apparatus 30 including, for example, a vacuum film forming apparatus or an atmospheric pressure film forming apparatus.

  As shown in FIGS. 8 and 9, the film forming apparatus 30 includes a chamber 31. At both ends of the chamber 31, an introduction port 32 into which the conductor line 20 is introduced and a lead-out port 33 from which the conductor line 20 with the gate insulating film 21 formed are formed. A feed-side roll (bobbin) 34 in which the conductor wire 20 is wound in a roll shape is provided outside the introduction port 32 side of the chamber 31. A winding-side roll (bobbin) 35 in which the conductor wire 20 on which the gate insulating film 21 is formed is wound in a roll shape is provided outside the chamber 31 on the outlet 33 side.

  The feed-side roll (bobbin) 34 and the take-up-side roll (bobbin) 35 are rotatably provided in synchronization with a rotation drive mechanism (not shown). Then, the conductor wire 20 is sent from the feed-side roll (bobbin) 34 by being rotated synchronously by this rotation drive mechanism, and the sent conductor wire 20 is taken up by the take-up-side roll (bobbin) 35. .

  The chamber 31 is provided with a heater (heating unit) 36 for heating the conductor wire 20 in the chamber 31. Further, the chamber 31 is provided with a gas supply unit 37 that supplies an inert gas or a raw material gas to the chamber 31 and a gas discharge unit 38 that discharges the gas from the chamber 31. Further, the chamber 31 is provided with a raw material supply unit 39 for supplying the raw material SRC to the conductor wire 20. When the film forming apparatus 30 is based on, for example, a CVD method, the raw material supply unit 39 supplies a raw material SRC made of, for example, a raw material gas to the conductor wire 20. Further, when the film forming apparatus 30 is based on, for example, a sputtering method, the raw material supply unit 39 supplies the raw material SRC to the conductor wire 20 by sputtering a raw material target using, for example, plasma.

In such a film forming apparatus 30, the conductor wire 20 is sent from the feed-side roll (bobbin) 34 by a rotational drive mechanism (not shown) and introduced into the chamber 31 through the introduction port 32. While the conductor wire 20 introduced into the chamber 31 moves at a constant speed toward the outlet port 33, the raw material SRC is supplied to the surface of the conductor wire 20, that is, the outer peripheral surface, from the raw material supply unit 39, for example. The gate insulating film 21 made of, for example, SiO ₂ or Si ₃ N ₄ is formed by, eg, CVD.

  At this time, by winding the conductor wire 20 fed from the feed-side roll (bobbin) 34 around the take-up roll (bobbin) 35 at a constant speed, the gate insulating film 21 is continuously formed along the conductor wire 20. Can be formed. The thickness of the gate insulating film 21 depends on the dielectric constant of the gate insulating film 21 and the like, but can be about 10 to 200 nm, for example. Further, by controlling the moving speed of the conductor wire 20 in the chamber 31, the thickness of the gate insulating film 21 formed on the conductor wire 20 can be made uniform along the conductor wire 20.

  The conductor wire 20 on which the gate insulating film 21 is formed on the surface, that is, the outer peripheral surface, moves to the lead-out port 33, then is led out from the chamber 31 through the lead-out port 33, and is wound on the winding-side roll (bobbin) 35. FIG. 10 shows a cross section of the conductor wire 20 having the gate insulating film 21 formed on the surface, that is, the outer peripheral surface.

  For example, when a gate insulating film is directly formed on a support substrate made of a resin film, the temperature at the time of forming the gate insulating film cannot be increased to, for example, about 300 to 400 ° C. There was a risk that the quality of the product would deteriorate.

  However, in the first embodiment, the gate insulating film 21 is formed not on the support substrate 11 but on the surface of the conductor line 20 made of, for example, Al. Therefore, the temperature at which the gate insulating film 21 is formed can be increased to, for example, about 300 to 400 ° C., and the deterioration of the quality of the gate insulating film 21 can be prevented or suppressed.

  Next, a channel layer (semiconductor layer) 22 is formed.

  FIG. 11 is a side view including a partial cross-section for explaining the step of forming the channel layer. FIG. 12 is a perspective view including a partial cross-section for explaining the step of forming the channel layer. FIG. 13 is a cross-sectional view of a conductor line in which a channel layer is formed.

  In the step of forming the channel layer 22, the surface of the gate insulating film 21 is covered with the channel layer 22 by using a film forming apparatus 40 such as a vacuum film forming apparatus or an atmospheric pressure film forming apparatus.

  As shown in FIGS. 11 and 12, the film forming apparatus 40 includes a chamber 41. At both ends of the chamber 41, an introduction port 42 into which the conductor wire 20 with the gate insulating film 21 formed is introduced, and an outlet port 43 through which the conductor line 20 with the channel layer 22 formed are formed. Has been. A feed-side roll (bobbin) 44 in which the conductor wire 20 on which the gate insulating film 21 is formed is wound in a roll shape is provided outside the introduction port 42 side of the chamber 41. A winding side roll (bobbin) 45 in which the conductor wire 20 on which the channel layer 22 is formed is wound in a roll shape is provided outside the chamber 41 on the outlet 43 side.

  The feed side roll (bobbin) 44 and the take-up side roll (bobbin) 45 are rotatably provided in synchronization by a rotation drive mechanism (not shown). Then, the conductor wire 20 is sent from the feed-side roll (bobbin) 44 by being rotated synchronously by this rotation drive mechanism, and the sent conductor wire 20 is taken up by the take-up-side roll (bobbin) 45. .

  The chamber 41 is provided with a heater (heating unit) 46 for heating the conductor wire 20 in the chamber 41. Further, the chamber 41 is provided with a gas supply unit 47 that supplies an inert gas or source gas to the chamber 41 and a gas discharge unit 48 that discharges the gas from the chamber 41. Further, the chamber 41 is provided with a raw material supply unit 49 for supplying the raw material SRC to the conductor wire 20. When the film forming apparatus 40 is based on, for example, a CVD method, the raw material supply unit 49 supplies a raw material SRC made of, for example, a raw material gas to the conductor wire 20. Further, when the film forming apparatus 40 is based on, for example, a sputtering method, the raw material supply unit 49 supplies the raw material SRC to the conductor wire 20 by sputtering a raw material target using, for example, plasma.

  In the film forming apparatus 40, a slit SLT 1 that functions as a shadow mask is provided in a chamber 41. The slit SLT1 is provided along the conductor line 20 so as to cover the region AR2 other than the region AR1 where the channel layer 22 is formed. In addition, in order to form the channel layer 22 in the plurality of regions AR1 that are spaced apart at regular intervals along the conductor line 20, a plurality of slits SLT1 are provided so as to cover the plurality of regions AR2 that are spaced apart at regular intervals. It has been.

  In such a film forming apparatus 40, the conductor wire 20 is fed from the feed-side roll (bobbin) 44 by a rotational drive mechanism (not shown) and introduced into the chamber 41 through the inlet 42. While the conductor wire 20 introduced into the chamber 41 moves toward the outlet port 43 at a constant speed, the raw material SRC is supplied from, for example, the raw material supply unit 49 to the surface of the gate insulating film 21, that is, the outer peripheral surface. Thus, the channel layer 22 made of, for example, a-Si, Poly-Si, IGZO, or ZTO is formed by, for example, CVD, sputtering, or vacuum deposition. The thickness of the channel layer 22 depends on the conductivity of the channel layer 22 or the dielectric constant and thickness of the gate insulating film 21, but can be about 5 to 80 nm, for example.

  At this time, a plurality of slits SLT1 are provided so as to cover a plurality of regions AR2 that are separated at a constant interval. Therefore, for example, the movement and stop of the conductor wire 20 are periodically repeated, the raw material is supplied when the movement of the conductor wire 20 is stopped, and the supply of the raw material is stopped when the conductor wire 20 is moving. As a result, the channel layer 22 can be formed in the plurality of regions AR1 on the surface of the conductor wire 20 and spaced apart at a constant interval. Alternatively, the channel layer 22 can be formed in a plurality of regions AR1 that are separated by a constant interval by moving the slit SLT1 in synchronization with the conductor line 20 along the moving direction of the conductor line 20. In the region AR1, the gate insulating film 21 and the channel layer 22 are sequentially formed on the surface of the conductor line 20, that is, the outer peripheral surface.

  In the first embodiment, as described above, when the length dimension of the region AR1 is larger than the length dimension of the source / drain electrodes 13 and 14 along the direction in which the conductor wire 20 extends. Since it is not necessary to control the length dimension of the region AR1 with high accuracy, the channel layer 22 can be easily formed.

  The conductor wire 20 on which the channel layer 22 is formed moves to the outlet port 43, is then led out from the chamber 41 through the outlet port 43, and is wound around a winding-side roll (bobbin) 45. FIG. 13 shows a cross section of the conductor wire 20 in which the gate insulating film 21 and the channel layer 22 are sequentially formed on the surface, that is, the outer peripheral surface.

  For example, when a channel layer is directly formed on a support substrate made of a resin film, the temperature at the time of forming the channel layer cannot be sufficiently increased, so that the quality of the formed channel layer may be deteriorated. .

  However, in the first embodiment, the channel layer 22 is formed not on the support substrate 11 but on the surface of the gate insulating film 21 formed on the conductor line 20 made of, for example, Al. Therefore, the temperature at the time of forming the channel layer 22 can be raised to, for example, about 300 to 400 ° C., and deterioration of the quality of the channel layer 22 can be prevented or suppressed.

  By performing the above-described steps, the TFT line member 12 shown in FIG. 3 is formed. Then, the thin film transistor 10 shown in FIG. 1 is formed by sandwiching and supporting the TFT line member 12 between the source / drain electrodes 13 and the source / drain electrodes 14 formed on the prepared support substrate 11.

  On the other hand, when the TFT line member 12d shown in FIG. 7 is formed as the TFT line member, electrode members 23 and 24 are further formed.

  FIG. 14 is a plan view including a partial cross-section for explaining the step of forming the electrode member. FIG. 15 is a cross-sectional view for explaining a step of forming an electrode member.

  In the step of forming the electrode members 23, 24, the electrode members 23, 24 are formed on the surface of the channel layer 22 using a film forming apparatus 50, for example, a vacuum film forming apparatus or an atmospheric pressure film forming apparatus.

  As shown in FIGS. 14 and 15, the film forming apparatus 50 includes a chamber 51. At both ends of the chamber 51, an introduction port 52 into which the conductor wire 20 in which the channel layer 22 is formed and a lead-out port 53 into which the conductor wire 20 in which the electrode members 23 and 24 are formed are led, Is formed. Although not shown in FIG. 14, each of a feed side roll (bobbin) and a take-up side roll (bobbin) is provided outside the chamber 51 on the introduction port 52 side and the outside on the lead-out port 53 side, The electrode members 23 and 24 can be formed continuously with the long conductor wire 20.

  The chamber 51 is provided with a heater (heating unit) 56 for heating the conductor wire 20 in the chamber 51. Further, the chamber 51 is provided with a gas supply unit 57 that supplies an inert gas or a raw material gas to the chamber 51 and a gas discharge unit 58 that discharges the gas from the chamber 51. Further, the chamber 51 is provided with a raw material supply unit 59 for supplying the raw material SRC (see FIG. 15) to the conductor wire 20. When the film forming apparatus 50 is based on, for example, a CVD method, the raw material supply unit 59 supplies a raw material SRC made of, for example, a raw material gas to the conductor wire 20. Further, when the film forming apparatus 50 is based on, for example, a sputtering method, the raw material supply unit 59 supplies the raw material SRC to the conductor wire 20 by sputtering a raw material target using, for example, plasma.

  In the film forming apparatus 50, a slit SLT 2 that functions as a shadow mask is provided in a chamber 51. The slit SLT2 is provided along the conductor line 20 so as to cover the region AR2 other than the region AR1 where the electrode members 23 and 24 are formed. Further, in order to form the electrode members 23 and 24 in the plurality of regions AR1 spaced apart at a constant interval along the conductor line 20, a plurality of slits SLT2 are provided so as to cover the plurality of regions AR2 separated by a certain interval. Is provided.

  In the film forming apparatus 50, the material supply unit 59 supplies the material SRC (see FIG. 15) to the conductor wire 20 from one side, for example, from above. Further, in the area AR1 sandwiched between the slits SLT2, as shown in FIG. 15, a mask line member MW made of, for example, a thin line is provided on the side of the raw material supply unit 59 of the conductor wire 20. The mask wire member MW has a diameter DM smaller than the diameter D1 of the conductor wire 20, and the center line of the mask wire member MW is the conductor wire 20 when viewed from the direction in which the raw material SRC is supplied to the conductor wire 20. It is provided so as to overlap the center line. In a state where the mask wire member MW is overlapped as a shadow mask, the raw material supply unit 59 supplies the raw material SRC from one side, so that in the cross section perpendicular to the direction in which the conductor wire 20 extends, in the circumferential direction of the conductor wire 20 Accordingly, the electrode members 23 and 24 can be formed at positions separated from each other.

  In such a film forming apparatus 50, the conductor wire 20 having the gate insulating film 21 and the channel layer 22 sequentially formed on the surface is introduced into the chamber 51 through the introduction port 52. While the conductor wire 20 introduced into the chamber 51 moves toward the outlet 53 at a constant speed, the raw material SRC is supplied from the raw material supply unit 59 to the surface of the channel layer 22, that is, the outer peripheral surface. As a result, electrode members 23 and 24 made of a metal such as W, Mo, Cu, or a conductive metal nitride such as TiN are formed by, for example, sputtering or vacuum deposition.

  At this time, a plurality of slits SLT2 are provided so as to cover a plurality of regions AR2 that are separated at a constant interval. Therefore, for example, the movement and stop of the conductor wire 20 are periodically repeated, the raw material is supplied when the movement of the conductor wire 20 is stopped, and the supply of the raw material is stopped when the conductor wire 20 is moving. Thus, the electrode members 23 and 24 can be formed on the surface of the conductor wire 20 in a plurality of regions AR1 that are separated by a certain interval. Alternatively, the electrode members 23 and 24 can be formed in a plurality of regions AR1 that are separated by a certain interval by moving the slit SLT2 in synchronization with the conductor wire 20 along the moving direction of the conductor wire 20. it can.

  Further, as described above, by using the mask wire member MW as a shadow mask, the electrode members are located at positions separated from each other along the circumferential direction of the conductor wire 20 in the cross section perpendicular to the direction in which the conductor wire 20 extends. 23, 24 can be formed. Then, by controlling the diameter DM of the mask wire member MW, the distance between the electrode members 23 and 24 along the circumferential direction of the conductor wire 20 can be easily controlled.

  As described above, when the length dimension of the area AR1 is larger than the length dimension of the source / drain electrodes 13 and 14 along the direction in which the conductor wire 20 extends, the length dimension of the area AR1. Therefore, the electrode members 23 and 24 can be easily formed.

  The conductor wire 20 on which the electrode members 23 and 24 are formed moves to the outlet 53 and then is led out from the chamber 51 through the outlet 53.

  By performing the above-described steps, the TFT line member 12d shown in FIG. 7 is formed. The TFT line member 12d is sandwiched and supported by the source / drain electrodes 13 and the source / drain electrodes 14 formed on the prepared support substrate 11, whereby the thin film transistor 10d shown in FIG. 7 is formed.

  When the length dimension of the region AR1 is larger than the length dimension of the source / drain electrodes 13 and 14 along the direction in which the conductor line 20 extends, the TFT line member 12 (or 12d) is disposed. It is not necessary to align the position of the TFT line member 12 (or 12d) with high accuracy along the direction in which the conductor line 20 extends. Therefore, for example, effective alignment accuracy is improved as compared with a case where the thin film transistor is transferred onto the substrate by a transfer technique.

  As will be described later in Embodiment 2, after the data lines and source / drain electrodes 13 and 14 are formed on the support substrate 11 made of a long resin film, the TFT line member 12 in which a plurality of thin film transistors 10 are formed is formed. As a gate line, an active matrix TFT array can be manufactured by a roll-to-roll manufacturing technique.

<Current-voltage characteristics>
Next, the current-voltage characteristics of the thin film transistor 10 which is the semiconductor device of the first embodiment will be described with reference to FIG.

FIG. 16 is a graph illustrating an example of measurement results of current-voltage characteristics of the thin film transistor which is the semiconductor device of the first embodiment. In FIG. 16, the measurement results are shown with the value on the horizontal axis being the gate voltage V _g (V) and the value on the vertical axis being the measured value of the current I (A) between the source and drain electrodes.

In the example shown in FIG. 16, a semiconductor layer made of any of a-Si, poly-Si, IGZO, and ZTO is used as the channel layer 22. Examples in which the channel layer 22 is made of a-Si, poly-Si, IGZO, and ZTO are referred to as Example 1, Example 2, Example 3, and Example 4, respectively. As the gate insulating film 21, a SiO ₂ film having a thickness of 100 nm was used. A metal wire made of Al having a diameter of 1 μm was used as the conductor wire 20. The gate length (channel length) was about 2 μm, the gate width (channel width) was 100 μm, and the drain voltage was 1V.

  As shown in FIG. 16, in any of Examples 1 to 4, the threshold voltage, the current when the thin film transistor is in an off state (off current), and the current when the thin film transistor is in an on state (on current) Good characteristics equivalent to those of a thin film transistor formed on a glass substrate by a normal manufacturing process were obtained. Therefore, the thin film transistor 10 of the first embodiment has sufficient characteristics to be applied to various electronic devices such as a liquid crystal display and RFID described later.

<Main features and effects of the present embodiment>
Unlike the thin film transistor formed by a normal manufacturing process on a glass substrate, the thin film transistor 10 that is the semiconductor device of the first embodiment is formed on the TFT line member 12.

  When the shape accuracy and alignment accuracy required for the gate length (channel length) of the thin film transistor cannot be ensured, for example, for each of the plurality of thin film transistors, for example, current in the on state (on current) or current in the off state There may be variations in transistor characteristics such as (off current).

  However, in the thin film transistor 10 of the first embodiment, the TFT line member 12 has a conductor line 20 as a core line. Further, the surface of the conductor wire 20 is sequentially covered with a gate insulating film 21 and a channel layer 22. Therefore, the accuracy of the gate length (channel length) can be easily ensured regardless of the alignment accuracy with which the TFT line member 12 is arranged on the support substrate 11. As a result, variation in transistor characteristics such as on-current and off-current can be reduced among a plurality of thin film transistors, and the performance of the semiconductor device can be improved even when manufactured by roll-to-roll manufacturing technology. .

  In the thin film transistor 10 of the first embodiment, the TFT line member 12 is supported while being sandwiched between the source / drain electrodes 13 and the source / drain electrodes 14 formed on the support substrate 11. By using the source / drain electrodes 13 and the source / drain electrodes 14 as bump-shaped fasteners (supporting members), the TFT line member 12 extends in a direction intersecting (orthogonal) with the TFT line member 12 in plan view. It is possible to easily and accurately match the position where the is disposed.

  Further, in the thin film transistor 10 according to the first embodiment, the length of the source / drain electrode 13 and the source / drain electrode 14 along the direction in which the conductor line 20 (TFT line member 12) extends is controlled, so that the gate The width (channel width) can be controlled. Therefore, since it is not necessary to control the length dimension of the channel layer 22 along the direction in which the conductor wire 20 (TFT line member 12) extends with high accuracy, the TFT line member 12 can be easily manufactured. Further, when the TFT line member 12 is disposed, it is not necessary to control the position of the TFT line member 12 along the direction in which the conductor line 20 (TFT line member 12) extends with high accuracy. Can be easily arranged.

<First Modification of First Embodiment>
FIG. 17 is a cross-sectional view of a thin film transistor of a first modification of the first embodiment. FIG. 18 is a cross-sectional view for explaining the step of forming the channel layer. Note that members having the same functions as those of the thin film transistor shown in FIG. 1 are denoted by the same reference numerals among the thin film transistors shown in FIGS. 17 and 18, and repeated description thereof is omitted. 17 and 18 show a cross section perpendicular to the direction in which the TFT line member (line member), that is, the conductor line extends.

  As shown in FIG. 17, the TFT line member 12e of the thin film transistor 10e has a conductor wire 20 as a core wire, and the surface of the conductor wire 20 is connected to a gate insulating film (insulating film) 21 and a channel layer (semiconductor layer). ) Sequentially coated with 22e. Similarly to the first embodiment, the surface of the gate insulating film 21, that is, the outer peripheral surface, is covered with the channel layer 22e in the region AR1 (see FIG. 3).

  However, in the first modification, unlike the first embodiment, the surface of the gate insulating film 21, that is, the outer peripheral surface of the gate insulating film 21, is not covered with the channel layer over the entire surface, that is, the entire periphery. As shown in FIG. 17, a channel layer 22e is formed in one half circumference (lower half circumference) of the outer periphery of the gate insulating film 21 in a cross section perpendicular to the direction in which the conductor line 20 extends. Further, the channel layer is not formed in the other half of the outer periphery of the gate insulating film 21 (upper half). Even in such a case, the path of the current flowing through the channel layer 22e is the same as that in the case where the outer peripheral surface of the gate insulating film 21 is covered with the channel layer over the entire periphery. The effect is obtained.

  In the manufacturing process of the thin film transistor 10e, in the process of forming the channel layer 22e, the raw material SRC is supplied to the conductor wire 20 from one direction, for example, by sputtering. As a result, as shown in FIG. 18, the channel layer 22 e is formed on one half of the outer periphery of the gate insulating film 21 in the cross section perpendicular to the direction in which the conductor line 20 extends, and the outer periphery of the gate insulating film 21 is formed. It is possible to prevent the channel layer from being formed in the other half-circle portion.

<Second Modification of First Embodiment>
FIG. 19 is a cross-sectional view of a thin film transistor of a second modification of the first embodiment. Note that members having the same functions as those of the thin film transistor of FIG. 1 are denoted by the same reference numerals among the thin film transistors of FIG. 19, and repeated description thereof is omitted. FIG. 19 shows a cross section perpendicular to the direction in which the TFT line member (line member), that is, the conductor line extends.

  As shown in FIG. 19, the TFT line member 12 f of the thin film transistor 10 f corresponds to the shape of the conductor wire 20 in the shape of the side surfaces 13 a and 14 a of the source / drain electrodes 13 and 14. Thereby, in the cross section perpendicular to the direction in which the conductor wire 20 (TFT line member 12) extends, the source / drain electrodes 13 and 14 and the channel layer 22 can be brought into contact with each other in a region having a certain length.

  In the second modification, the source / drain electrodes 13 and 14 are spaced from each other along the circumferential direction of the conductor wire 20 (TFT line member 12), that is, the source and drain electrodes. The distance L6 between the two corresponds to the gate length (channel length) of the thin film transistor 10f. In the second modification, the gate length (channel length) is easily controlled by controlling the diameter D1 of the conductor wire 20 and the shape and interval of the source / drain electrodes 13 and 14 in correspondence with each other. can do.

  The source / drain electrode 13 and the channel layer 22 may be in contact with each other through, for example, a conductive adhesive, and the source / drain electrode 14 and the channel layer 22 are in, for example, through a conductive adhesive. May be in contact with each other. With such a configuration, the channel layer 22 and the source / drain electrodes 13 and 14 can be electrically connected with low resistance.

  Preferably, the length dimension of the region AR1 (see FIG. 3) is longer than the length dimension of the source / drain electrode 13 and the source / drain electrode 14 along the direction in which the conductor line 20 (TFT line member 12f) extends. Is also big. In this case, the gate width (channel width) of the thin film transistor 10f is equal to the length of the source / drain electrode 13 and the source / drain electrode 14 along the direction in which the conductor line 20 (TFT line member 12f) extends. Therefore, the gate width (channel width) can be controlled by controlling the lengths of the source / drain electrodes 13 and the source / drain electrodes 14 along the direction in which the conductor line 20 (TFT line member 12f) extends. it can.

  On the other hand, when the length dimension of the region AR1 is larger than the length dimension of the source / drain electrode 13 and the source / drain electrode 14 along the direction in which the conductor line 20 (TFT line member 12f) extends, the channel layer In the step of forming 22, the length of the region AR1 does not need to be controlled with high accuracy, and the channel layer 22 can be easily formed.

(Embodiment 2)
<Active matrix TFT array>
Next, a semiconductor device according to the second embodiment of the present invention will be described. In the first embodiment described above, the basic structure and manufacturing method of a single thin film transistor have been described. In contrast, in Embodiment 2, an active matrix TFT array in which thin film transistors are arranged in a matrix array and a manufacturing process thereof will be described.

  Hereinafter, an example in which the thin film transistor 10 of Embodiment 1 is used will be described. However, instead of the thin film transistor 10, the thin film transistor 10a (see FIG. 4), the thin film transistor 10b (see FIG. 5), the thin film transistor 10c (see FIG. 6), or the thin film transistor 10d (see FIG. 7) described in Embodiment 1 can be used. (The same applies to the following embodiments). Further, instead of the thin film transistor 10, a thin film transistor 10e (see FIG. 17) or a thin film transistor 10f (see FIG. 19) can be used (the same applies to the following embodiments).

  First, an active matrix TFT array in which the thin film transistor 10 according to the first embodiment is applied as a switching element of a pixel electrode included in each of a plurality of pixels of an active matrix liquid crystal display will be described with reference to FIGS.

  FIG. 20 is a diagram showing a drive circuit of an active matrix TFT array for an active matrix type liquid crystal display. FIG. 21 is a plan view of an active matrix TFT array for an active matrix liquid crystal display. FIG. 22 is a cross-sectional view of an active matrix TFT array for an active matrix liquid crystal display. 22 is a cross-sectional view taken along line AA in FIG.

  As shown in FIG. 20, the active matrix TFT array 60 for an active matrix liquid crystal display includes a support substrate 11, a gate line 62, a data line 63, a gate line control circuit 64, and a data line control circuit 65. Further, as shown in FIGS. 21 and 22, an active matrix TFT array 60 for an active matrix liquid crystal display includes a thin film transistor 10, a support substrate 11, a gate line 62, source / drain electrodes 13 and 14, and a pixel electrode 66. .

  The support substrate 11 in FIGS. 20 to 22 corresponds to the support substrate 11 (see FIGS. 1 and 2) in the first embodiment.

  As shown in FIG. 21, the gate lines 62 extend in the Y direction intersecting (orthogonal) with the X direction, and a plurality of gate lines 62 are formed so as to be arranged at regular intervals along the X direction. Yes. The data lines 63 extend in the X direction, and a plurality of data lines 63 are formed at regular intervals along the Y direction. Since the pixel electrode 66 is formed at a position where each of the plurality of gate lines 62 and each of the plurality of data lines 63 intersects, the plurality of pixel electrodes 66 are arranged in a matrix array. Each of the plurality of pixels of the active matrix type liquid crystal display is provided corresponding to each of the plurality of pixel electrodes 66. Therefore, a plurality of pixels of the active matrix liquid crystal display are also arranged in a matrix array.

  The pixel electrode 66 is electrically connected to one of the source / drain electrode 13 and the source / drain electrode 14 of the thin film transistor 10, and the data line 63 is connected to the source / drain electrode 13 and the source / drain electrode 14 of the thin film transistor 10. It is electrically connected to the other.

  The data line 63 is made of a metal such as Cu, and is formed by, for example, a screen printing method, an ink jet method, a plating method, or the like. The pixel electrode 66 is made of, for example, an inorganic conductive material such as ITO, and is formed by, for example, a screen printing method, an ink jet method, a CVD method, or a sputtering method.

  The thin film transistor 10 in FIGS. 21 and 22 corresponds to the thin film transistor 10 in Embodiment 1 (see FIGS. 1 and 2). That is, as shown in FIGS. 21 and 22, the gate line 62 is configured by the TFT line member 12 of the thin film transistor 10 in the first embodiment. The TFT line member 12 has a conductor wire 20 as a core wire, and the surface of the conductor wire 20 is sequentially covered with a gate insulating film (insulating film) 21 and a channel layer (semiconductor layer) 22. . On the support substrate 11, source / drain electrodes 13, 14 are formed at positions separated from each other, the source / drain electrode 13 is electrically connected to the channel layer 22, and the source / drain electrode 14 is connected to the channel layer. 22 is electrically connected.

  The source / drain electrode 13 and the source / drain electrode 14 are formed in each of a plurality of regions separated from each other along the direction in which the TFT line member 12 extends. The source / drain electrodes 13 and the source / drain electrodes 14 formed in each region support the TFT line member 12 from both sides in each region.

  Although not shown in FIG. 21, a gate line control circuit 64 (see FIG. 20) and a data line control circuit 65 (see FIG. 20) are formed in the peripheral portion of the support substrate 11.

  In the second embodiment, the gate line 62 and the data line 63 intersect (orthogonal) each other. Therefore, as described later, it can be manufactured by a so-called roll-to-roll manufacturing technique. For example, the support substrate 11 made of a long resin film is prepared, and the data line 63 is formed on the support substrate 11 along the moving direction of the support substrate 11 while moving the support substrate 11 along the long direction. To do. Further, the TFT line member 12 is arranged and connected so as to extend in a direction intersecting (orthogonal) with the moving direction of the support substrate 11 in plan view while moving the support substrate 11 along the longitudinal direction. Thereby, the active matrix TFT array 60 for the active matrix type liquid crystal display can be easily manufactured.

  In addition, as shown in FIG. 21, when the length dimension W1 of the region AR1 is larger than the length dimension W2 of the source / drain electrode 13 and the source / drain electrode 14 along the direction in which the TFT line member 12 extends. The gate width (channel width) of the thin film transistor 10 is equal to the length dimension W2 of the source / drain electrode 13 and the source / drain electrode 14 along the direction in which the TFT line member 12 extends. Therefore, the gate width (channel width) can be controlled by controlling the length dimension W2 of the source / drain electrode 13 and the source / drain electrode 14 along the direction in which the TFT line member 12 extends.

  On the other hand, when the length dimension W1 of the region AR1 is larger than the length dimension W2 of the source / drain electrode 13 and the source / drain electrode 14 along the direction in which the TFT line member 12 extends, the TFT line member 12 is When arranging, it is not necessary to align the position of the TFT line member 12 along the direction in which the TFT line member 12 extends with high accuracy. Therefore, for example, effective alignment accuracy is improved as compared with a case where the thin film transistor is transferred onto the substrate by a transfer technique.

  Further, the thin film transistor 10 of Embodiment 1 can be applied to an organic EL display.

  FIG. 23 is a diagram showing a drive circuit of the organic EL display.

  As shown in FIG. 23, the organic EL display 70 includes a gate line 72, a data line 73, a thin film transistor 74, a buffer capacitor 75, a thin film transistor 76, and an organic EL diode 77. The thin film transistor 74 is for switching, and the thin film transistor 76 is for current driving.

  Also in the organic EL display 70, pixels are formed at positions where each of the plurality of gate lines 72 and each of the plurality of data lines 73 intersect. Therefore, the plurality of pixels of the organic EL display 70 are also arranged in a matrix array.

  The gate electrode of the switching thin film transistor 74 is electrically connected to the gate electrode of another thin film transistor 74 through the gate line 72. Therefore, the TFT line member 12 described in the first embodiment can be arranged and connected as the thin film transistor 74. Thereby, the organic EL display 70 provided with the active matrix TFT array can be easily manufactured.

<Manufacturing process of active matrix TFT array>
Subsequently, a manufacturing process of the active matrix TFT array which is the semiconductor device of the second embodiment will be described.

  In the following, an example of an active matrix TFT array manufacturing process applied to an active matrix type liquid crystal display as described above with reference to FIGS. 21 and 22, in which roll-to-roll manufacturing technology is applied, will be described. explain.

  FIG. 24 is a side view including a partial cross-section for explaining the manufacturing process of the active matrix TFT array. FIG. 25 is a perspective view for explaining a step of disposing the TFT line member.

  First, wiring, an electrode pattern, and the like including the data lines 63 and the pixel electrodes 66 are formed on the support substrate 11 while moving the support substrate 11 made of a long resin film. Part of the process of forming the wiring, electrode pattern, and the like can be performed using the manufacturing apparatus 80a.

  The manufacturing apparatus 80 a includes a chamber 81. The chamber 81 is provided with a transport mechanism 82 that transports the support substrate 11 by roller transport, for example.

  A feed-side roll (bobbin) 82a in which the support substrate 11 is wound in a roll shape is provided outside the introduction port side of the chamber 81, and the support substrate 11 rolls outside the discharge port side of the chamber 81. A take-up roll (bobbin) 82b wound in a shape is provided. The feed side roll (bobbin) 82a and the take-up side roll (bobbin) 82b are rotatably provided in synchronization with the transport mechanism 82 by a rotation drive mechanism (not shown). By such a transport mechanism 82 and a rotation drive mechanism (not shown), the support substrate 11 is sent from the feed side roll (bobbin) 82a, and the sent support substrate 11 is taken up by the take-up side roll (bobbin) 82b. It is done. That is, the long support substrate 11 is transported (moved) by the transport mechanism 82 and the rotation drive mechanism (not shown).

  In the chamber 81, for example, a wiring formation for forming various wirings including the data lines 63 (see FIG. 25) and the pixel electrodes 66 on the support substrate 11 by a coating method such as a screen printing method or an ink jet method or other various methods. A mechanism 83a is provided. When the wiring forming mechanism 83a forms the data line 63 by, for example, a screen printing method, the wiring forming mechanism 83a includes, for example, a screen for applying ink containing raw materials by printing, a moving mechanism for moving the screen, and the like. . Further, when the wiring forming mechanism 83a forms the data line 63 by, for example, an ink jet method, the wiring forming mechanism 83a includes, for example, a nozzle for discharging and applying ink containing a raw material, a moving mechanism for moving the nozzle, and the like. including.

  In the chamber 81, while transporting (moving) the long support substrate 11 by the transport mechanism 82 and the rotation drive mechanism (not shown), the wiring forming mechanism 83a causes the long support substrate 11 to be placed on the long support substrate 11. The process of forming various wirings including the data line 63 (see FIG. 25) and the pixel electrode 66 is repeated. Thereby, the data line 63 (refer FIG. 25) can be continuously formed on the elongate support substrate 11 along the conveyance direction (movement direction) of the support substrate 11. In addition, various wirings such as the pixel electrodes 66 can be repeatedly formed on the long support substrate 11 at a plurality of positions separated from each other along the transport direction (movement direction) of the support substrate 11.

  In addition, a plurality of wiring formation mechanisms 83 a can be provided along the conveyance direction of the support substrate 11. With such a configuration, the data lines 63 can be simultaneously formed at a plurality of positions separated from each other along the transport direction of the support substrate 11, so that the time for the manufacturing process can be shortened.

  Alternatively, as the wiring forming mechanism 83a, a storage container (not shown) for storing the plating solution is installed, and the support substrate 11 to be transported is moved while being immersed in the plating solution in the storage container. 63 can also be formed. Alternatively, as the wiring formation mechanism 83a, a film forming apparatus for performing a vapor phase growth method such as a CVD method or a sputtering method is provided, and is formed on the support substrate 11 by a vapor phase growth method such as a CVD method or a sputtering method. For example, the pixel electrode 66 made of ITO can be formed.

  In addition, the inside of the chamber 81 is further divided into a plurality of regions along the transport direction, and for example, a process of forming the pixel electrode 66 and a process of forming various wirings such as the data lines 63 may be individually performed. it can.

  Next, source / drain electrodes 13 and 14 are formed. Preferably, the process of forming the source / drain electrodes 13 and 14 is repeated while moving the support substrate 11.

  For example, by installing a storage container (not shown) for storing the plating solution and moving the supporting substrate 11 to be transported while being immersed in the plating solution in the storage container, the source / drain electrodes 13 and 14 are moved by plating. Can be formed. Alternatively, the source / drain electrodes 13 and 14 can be formed by, for example, a screen printing method or an ink jet method.

  Next, the TFT line member 12 is arranged and connected. Preferably, the process of disposing and connecting the TFT line member 12 is repeated while moving the support substrate 11. A part of the process of arranging and connecting the TFT line member 12 can be performed by using the manufacturing apparatus 80c.

  As shown in FIG. 25, a feed-side roll (bobbin) 82c around which the support substrate 11 is wound is provided on the outside of the introduction port side of the manufacturing apparatus 80c. Outside, a winding-side roll (bobbin) 82d around which the support substrate 11 is wound is provided. Then, the support substrate 11 is sent from the feed-side roll (bobbin) 82c, and the sent support substrate 11 is taken up by the take-up roll (bobbin) 82d.

  In addition, the manufacturing apparatus 80 c is provided with a line member arrangement mechanism 83 c that arranges the TFT line members 12 on the support substrate 11. The wire member arrangement mechanism 83c includes a feed-side roll (bobbin) 85c in which the TFT line member 12 is wound in a roll shape, and a take-up roll (bobbin) 86c in which the TFT line member 12 is wound in a roll shape. As shown in FIG. 25, a feed-side roll (bobbin) 85c is provided on one of the left and right sides in the conveyance direction of the support substrate 11, and a take-up roll (bobbin) 86c is provided on the other. Yes.

  With such a configuration, on the support substrate 11 on which the data line 63, the pixel electrode 66, and the source / drain electrodes 13 and 14 are formed, it extends in a direction intersecting (orthogonal) with the transport direction of the support substrate 11. The TFT line member 12 is disposed, and the TFT line member 12 is electrically connected to the data line 63 and the pixel electrode 66. Specifically, in plan view, the TFT line member 12 is stretched in a direction intersecting (orthogonal) with the transport direction of the support substrate 11 so as to be sandwiched between the source / drain electrode 13 and the source / drain electrode 14. Further, the TFT line member 12 is disposed, and the thin film transistor 10 formed on the TFT line member 12 is electrically connected to the source / drain electrodes 13 and 14.

  As described above, the source / drain electrodes 13 and 14 have a bump shape, and function as a fastener (supporting member) for fastening (supporting) the TFT line member 12. Therefore, the position where the TFT line member 12 is arranged on the support substrate 11 can be easily aligned along the transport direction of the support substrate 11.

  The line member arrangement mechanism 83c can be provided with a cutting mechanism (not shown) for cutting the arranged TFT line member 12. With such a configuration, the TFT line member 12 is disposed, cut, and connected so as to be sandwiched between the source / drain electrode 13 and the source / drain electrode 14, and then the support substrate 11 is transported (moved). ) It is possible to repeat the process of arranging, cutting and connecting the TFT line member 12 again at a position away from the previous position.

  In addition, a plurality of line member arrangement mechanisms 83c are provided along the transport direction of the support substrate 11. With such a configuration, TFTs can be simultaneously formed at a plurality of positions separated from each other along the transport direction of the support substrate 11. Since the wire member 12 can be arrange | positioned, the time for a manufacturing process can be shortened.

  After the TFT line member 12 is disposed, the support substrate 11 is annealed so that the channel layer 22 and the source / drain electrode 13 are in close contact with each other and the channel layer 22 and the source / drain electrode 14 are in close contact with each other. It can also improve sex.

  Alternatively, for example, a conductive adhesive is applied to the surface of the TFT line member 12 or the surfaces of the source / drain electrodes 13 and 14 in advance, and after the TFT line member 12 is disposed, the applied conductive adhesive is heated. You can also By such a method, the TFT line member 12 can be connected to the source / drain electrodes 13 and 14 firmly and electrically with low resistance.

  FIG. 26 is a side view for explaining the step of disposing the TFT line member. FIG. 27 is a plan view for explaining a state in which the TFT line member is arranged.

  As shown in FIG. 26, for example, a positioning mechanism 87c and a position detection mechanism 88c can be provided in the line member arrangement mechanism 83c.

  The positioning mechanism 87c includes an arm 87d and a guide 87e. The arm 87d is provided by a moving mechanism (not shown) so as to be movable in the plane in the transport direction of the support substrate 11, in the direction intersecting (orthogonal to) the support substrate 11, and in the vertical direction. As a result, the arm 87 d can grip the TFT line member 12 from above, and the gripped TFT line member 12 can be disposed between the source / drain electrode 13 and the source / drain electrode 14.

  The guide 87e is connected to the arm 87d and is a guide member that guides the TFT line member 12 below the arm 87d. As shown in FIG. 26, for example, a member having a ring shape can be used as the guide 87e.

  The position detection mechanism 88c is composed of, for example, a CCD (Charge Coupled Device) camera, and by imaging the TFT line member 12 held by the arm 87d, the position of the TFT line member 12, in particular, the source / drain electrodes 13 and 14 are detected. The position of the TFT line member 12 is detected. By determining whether or not the position of the TFT line member 12 with respect to the source / drain electrodes 13 and 14 detected by the position detection mechanism 88c is within a predetermined range, the position of the TFT line member 12 can be determined with high accuracy. Can be combined.

  The length dimension W1 (see FIG. 21) of the area AR1 can be made larger than the length dimension W2 (see FIG. 21) of the source / drain electrodes 13 and 14 along the direction in which the TFT line member 12 extends. . Further, adjacent thin film transistors 10 are formed at positions separated from each other along the direction in which the TFT line member 12 extends. Therefore, even when the position of the TFT line member 12 is slightly shifted along the direction in which the TFT line member 12 extends, one thin film transistor 10 is adjacent to the source / drain along the direction in which the TFT line member 12 extends. Contact with the electrodes 13 and 14 can be prevented. Further, even when the position of the TFT line member 12 is displaced along the direction in which the TFT line member 12 extends, the length dimension of the portion where the thin film transistor 10 is in contact with the source / drain electrode 13 and the source / drain electrode 14 ( 21 is equal to the length dimension W2 in FIG. 21, and the gate width (channel width) of the thin film transistor 10 can be kept constant.

  Conventionally, when a gate line is formed so as to straddle (overlap) a data line, an insulating film and a conductive film are formed on a support substrate on which the data line is formed, and the formed conductive film and the insulating film are lithography. The gate line is formed by processing with the technology, and the manufacturing process on the support substrate may be complicated.

  On the other hand, according to the second embodiment, the TFT line member 12 in which the thin film transistor is formed is separately manufactured, and the manufactured TFT line member 12 is arranged on the support substrate 11 and connected to the source / drain electrodes 13 and 14. To do. Therefore, the manufacturing process on the support substrate 11 can be significantly reduced.

  With respect to the manufacturing process of the active matrix TFT array using such roll-to-roll manufacturing technology, the effect of reducing the production cost was estimated based on the expected effect of shortening the operation time of the apparatus. As a result, when the manufacturing process of the active matrix TFT array described in the second embodiment is performed, compared to the manufacturing process of the active matrix TFT array using the conventional glass substrate of the eighth generation (2160 mm × 2460 mm), It was found that the production cost can be reduced by about 50 to 80%. The production cost was estimated when a-Si was used as the material of the channel layer 22 of the thin film transistor 10. Therefore, when an oxide semiconductor material such as IGZO or ZTO that can be formed at a process temperature lower than the process temperature for forming a-Si is used as the material of the channel layer 22, the production cost is further increased. Can be reduced.

  Note that after the TFT line member 12 is arranged and connected, a passivation film can be formed on the support substrate 11. Next, an alignment film is formed on the pixel electrode 66. Next, a counter substrate on which a color filter layer and an overcoat layer, for example, a counter electrode made of ITO and an alignment film are sequentially formed, is bonded to the support substrate 11 via a spacer. An active matrix liquid crystal display can be manufactured by enclosing liquid crystal between the support substrate 11 and the counter substrate.

(Embodiment 3)
Next, a semiconductor device according to the third embodiment of the present invention will be described. In the second embodiment described above, an example in which the thin film transistor of the first embodiment is applied to an active matrix TFT array has been described. However, the thin film transistor of the first embodiment can be applied to various circuits other than the active matrix TFT array. In Embodiment 3, an example in which the thin film transistor of Embodiment 1 is applied to a bridge-type rectifier circuit as various circuits other than the active matrix TFT array will be described.

  FIG. 28 is a circuit diagram showing an example in which a thin film transistor is applied to a bridge type rectifier circuit. FIG. 29 is a plan view illustrating an arrangement example of thin film transistors in a bridge-type rectifier circuit. 30 is a cross-sectional view of the bridge-type rectifier circuit shown in FIG. In FIG. 29, the support substrate 11 is not shown for easy understanding. FIG. 30 is a cross-sectional view taken along line AA in FIG.

  As shown in FIG. 28, the bridge-type rectifier circuit 90 is for inputting and rectifying a signal from, for example, a high-frequency power supply (or receiving antenna) 91.

  As shown in FIGS. 28 and 29, the bridge type rectifier circuit 90 includes input terminals 92a and 92b, four thin film transistors 93a, 93b, 93c, and 93d, a ground terminal 94, and an output terminal (load circuit connection terminal) 95. Have. The thin film transistors 93a, 93b, 93c, and 93d in FIG. 28 correspond to the thin film transistor 10 in Embodiment 1 (see FIGS. 1 and 2).

  Further, as shown in FIGS. 29 and 30, the bridge-type rectifier circuit 90 includes a support substrate 11, wirings 96 and 97, and connection terminals 98. The wiring 96 is electrically connected to the input terminal 92a, and the wiring 97 is electrically connected to the input terminal 92b. Support substrate 11 (see FIG. 30) corresponds to support substrate 11 (see FIGS. 1 and 2) in the first embodiment.

  The thin film transistors 93a, 93b, 93c, and 93d are provided on the support substrate 11 (see FIG. 30), and have TFT line members (line members) 12 and source / drain electrodes 13 and 14, respectively.

  As shown in FIG. 29, the source / drain electrode 13 of the thin film transistor 93a is electrically connected to the wiring 96, and the source / drain electrode 14 of the thin film transistor 93a is electrically connected to the source / drain electrode 13 of the thin film transistor 93b. The source / drain electrodes 14 of the thin film transistor 93b are electrically connected to the wiring 97. In each of the thin film transistors 93a and 93b, the TFT line member 12 is supported while being sandwiched between the source / drain electrodes 13 and 14 of the thin film transistors 93a and 93b. One end of the TFT line member 12 of the thin film transistor 93 a is electrically connected to the wiring 97 through the connection terminal 98. One end of the TFT line member 12 of the thin film transistor 93 b is electrically connected to the wiring 96 through the connection terminal 98.

  On the other hand, the source / drain electrode 13 of the thin film transistor 93c is electrically connected to the wiring 96, the source / drain electrode 14 of the thin film transistor 93c is electrically connected to the source / drain electrode 13 of the thin film transistor 93d, and the source of the thin film transistor 93d. The drain electrode 14 is electrically connected to the wiring 97. In each of the thin film transistors 93c and 93d, the TFT line member 12 is supported while being sandwiched between the source / drain electrodes 13 and 14 of the thin film transistors 93c and 93d. One end of the TFT line member 12 of the thin film transistor 93 c is electrically connected to the wiring 96 via the connection terminal 98. One end of the TFT line member 12 of the thin film transistor 93 d is electrically connected to the wiring 97 via the connection terminal 98.

  The source / drain electrodes 14 of the thin film transistor 93 a and the source / drain electrodes 13 of the thin film transistor 93 b are electrically connected to the ground terminal 94. That is, the source / drain electrode 14 of the thin film transistor 93a and the source / drain electrode 13 of the thin film transistor 93b are grounded. The source / drain electrode 14 of the thin film transistor 93 c and the source / drain electrode 13 of the thin film transistor 93 d are electrically connected to the output terminal 95.

  Also in the third embodiment, as in the first embodiment, the thin film transistor 10 is formed on the TFT line member 12, and the gate length (channel length) can be easily controlled by controlling the diameter of the conductor line 20. can do. Therefore, variation in transistor characteristics among a plurality of thin film transistors can be reduced, and the performance of the semiconductor device can be improved even when manufactured by roll-to-roll manufacturing technology.

  Also in the third embodiment, as in the first embodiment, the TFT line member 12 is supported while being sandwiched between the source / drain electrodes 13 and 14 formed on the support substrate 11. Therefore, the position of the TFT line member 12 along the direction intersecting (orthogonal) with the TFT line member 12 in a plan view can be easily adjusted with high accuracy.

  Further, in the third embodiment, as in the first embodiment, by controlling the length dimensions of the source / drain electrodes 13 and the source / drain electrodes 14 along the direction in which the TFT line member 12 extends, The gate width (channel width) can be controlled. Therefore, the position of the TFT line member 12 along the direction in which the TFT line member 12 extends can be easily adjusted with high accuracy.

  In the third embodiment, an example in which the thin film transistor of the first embodiment is applied to a bridge-type rectifier circuit as a relatively simple rectifier circuit as an example has been described. However, a circuit to which the thin film transistor of Embodiment 1 can be applied is not limited to a rectifier circuit. Therefore, the thin film transistor of Embodiment 1 can be applied to various circuits such as a logic circuit including an analog circuit or a digital circuit that is more complicated than a rectifier circuit.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention is effective when applied to a semiconductor device and a manufacturing method thereof.

10, 10a to 10f Thin film transistor 11 Support substrate 12, 12a to 12f TFT line member (line member)
13, 14 Source / drain electrodes 13a, 14a Side surfaces 20, 20a to 20c Conductor lines 21 Gate insulating films 22, 22e Channel layers 23, 24 Electrode members 30, 40, 50 Deposition devices 31, 41, 51 Chambers 32, 42, 52 Inlet 33, 43, 53 Outlet 34, 44, 54 Feeding side roll (bobbin)
35, 45, 55 Winding roll (bobbin)
36, 46, 56 Heater (heating unit)
37, 47, 57 Gas supply unit 38, 48, 58 Gas discharge unit 39, 49, 59 Raw material supply unit 60 Active matrix TFT array 62, 72 Gate line 63, 73 Data line 64 Gate line control circuit 65 Data line control circuit 66 Pixel electrode 70 Organic EL display 74, 76 Thin film transistor 75 Buffer capacity 77 Organic EL diode 80a, 80c Manufacturing apparatus 81 Chamber 82 Transport mechanism 82a, 82c Feeding roll (bobbin)
82b, 82d Winding roll (bobbin)
83a Wiring forming mechanism 83c Wire member arranging mechanism 85c Feeding side roll (bobbin)
86c Winding roll (bobbin)
87c Positioning mechanism 87d Arm 87e Guide 88c Position detection mechanism 90 Bridge type rectifier circuit 91 High frequency power supply 92a, 92b Input terminals 93a to 93d Thin film transistor 94 Ground terminal 95 Output terminal (load circuit connection terminal)
96, 97 Wiring 98 Connection terminal AR1, AR2 Area CC1 Recess D1 Diameter (height dimension)
D2, D3, D4 Height dimension DM Diameter H1-H4 Height dimension L1-L6 Distance MW Mask wire member P1, P2 Position PA1, PA2 Region (position)
SLT1, SLT2 Slit SRC Raw material W1, W2 Length dimension

Claims (13)

And the base plate,
A wire member;
A first source electrode and a first drain electrode which are formed on the substrate and support the wire member in between.
Including
The wire member is
A conductor wire;
A gate insulating film covering the surface of the conductor wire;
A first channel layer covering a surface of the gate insulating film;
With
In the cross section perpendicular to the first direction, which is the direction in which the conductor line extends, the first source electrode and the first drain electrode are respectively separated from each other along the circumferential direction of the cross section of the conductor line. The semiconductor device is electrically connected to the first channel layer. The semiconductor device according to claim 1 ,
The semiconductor device according to claim 1, wherein a height dimension of the first source electrode and a height dimension of the first drain electrode are larger than a diameter of the conductor wire. The semiconductor device according to claim 1 ,
The wire member includes a first electrode member and a second electrode member formed on a surface of the first channel layer,
In the cross section perpendicular to the first direction, each of the first electrode member and the second electrode member is formed at positions separated from each other along the circumferential direction of the cross section of the conductor wire.
The first source electrode is electrically connected to the first electrode member;
The semiconductor device, wherein the first drain electrode is electrically connected to the second electrode member. The semiconductor device according to claim 1 ,
The first channel layer covers a surface of the gate insulating film in a first region;
The length dimension of the first region along the first direction is the length dimension of the first source electrode along the first direction and the length dimension of the first drain electrode along the first direction. A semiconductor device characterized by being larger than the above. The semiconductor device according to claim 1 ,
A second source electrode and a second drain electrode which are formed on the substrate and support the wire member in between.
Including
The wire member is
The first channel layer covering the surface of the gate insulating film in a second region;
A second channel layer covering a surface of the gate insulating film in a third region separated from the second region along the first direction;
With
The first source electrode and the first drain electrode are supported by sandwiching the line member in the second region,
The second source electrode and the second drain electrode are supported by sandwiching the line member in the third region,
In the cross section perpendicular to the first direction, the second source electrode and the second drain electrode are electrically connected to the second channel layer at positions separated from each other along the circumferential direction of the cross section of the conductor line. A semiconductor device characterized by being connected to each other. The semiconductor device according to claim 1,
The semiconductor device, wherein the first channel layer is made of amorphous silicon, polysilicon, or an oxide semiconductor material. (A) a step of covering the surface of the conductor wire with a gate insulating film;
(B) a step of covering the surface of the gate insulating film with a first channel layer and forming a line member including the conductor line, the gate insulating film, and the first channel layer;
(C) forming a first source electrode and a first drain electrode for supporting the wire member on the substrate,
(D) After the step (b) and the step (c), the wire member is disposed so as to be sandwiched between the first source electrode and the first drain electrode, and the conductor wire extends. In a cross section perpendicular to the first direction, the first source electrode and the first drain electrode are electrically connected to the first channel layer at positions separated from each other along the circumferential direction of the cross section of the conductor line. Connecting,
A method of manufacturing a semiconductor device including: The method of manufacturing a semiconductor device according to claim 7 .
The method of manufacturing a semiconductor device, wherein a height dimension of the first source electrode and a height dimension of the first drain electrode are larger than a diameter of the conductor wire. The method of manufacturing a semiconductor device according to claim 7 .
The step (b)
(E) covering the surface of the gate insulating film with the first channel layer;
(F) In the cross section perpendicular to the first direction, each of the first electrode member and the second electrode member on the surface of the first channel layer at positions separated from each other along the circumferential direction of the cross section of the conductor wire. Forming the wire member comprising the conductor line, the gate insulating film, the first channel layer, the first electrode member, and the second electrode member,
Have
In the step (d), the first source electrode is electrically connected to the first electrode member, and the first drain electrode is electrically connected to the second electrode member. Production method. The method of manufacturing a semiconductor device according to claim 7 .
In the step (b), the line including the conductor line, the gate insulating film, and the first channel layer by covering the surface of the gate insulating film with the first channel layer in the first region. Forming a member,
In the step (c), in the first region, the first source electrode and the first drain electrode for supporting the wire member in between are formed.
In the step (d), the line member is arranged so as to be sandwiched between the first source electrode and the first drain electrode in the first region, and in the cross section perpendicular to the first direction, Each of the source electrode and the first drain electrode is electrically connected to the first channel layer at positions separated from each other along the circumferential direction of the conductor wire,
The length dimension of the first region along the first direction is the length dimension of the first source electrode along the first direction and the length dimension of the first drain electrode along the first direction. A method for manufacturing a semiconductor device, wherein The method of manufacturing a semiconductor device according to claim 7 .
In the step (b), the surface of the gate insulating film is covered with the first channel layer in the second region, and the gate is formed in the third region separated from the second region along the first direction. By covering the surface of the insulating film with the second channel layer, the wire member including the conductor line, the gate insulating film, the first channel layer, and the second channel layer is formed,
In the step (c), in the second region, the first source electrode and the first drain electrode for supporting the wire member in between are formed, and on the substrate, in the third region, Forming a second source electrode and a second drain electrode for supporting the wire member in between,
In the step (d), the second region is sandwiched between the first source electrode and the first drain electrode, and the third region is sandwiched between the second source electrode and the second drain electrode. In the cross section perpendicular to the first direction, the wire member is disposed, and the first source electrode and the first drain electrode are separated from each other along the circumferential direction of the cross section of the conductor line. The second channel layer is electrically connected to the first channel layer, and the second source electrode and the second drain electrode are spaced apart from each other along the circumferential direction of the conductor line. A method for manufacturing a semiconductor device, wherein the semiconductor device is electrically connected. The method of manufacturing a semiconductor device according to claim 7 .
The method of manufacturing a semiconductor device, wherein the first channel layer is made of amorphous silicon, polysilicon, or an oxide semiconductor material. The method of manufacturing a semiconductor device according to claim 7 .
While moving the substrate, the step (c) is repeated,
A method of manufacturing a semiconductor device, wherein the step (d) is repeated while moving the substrate.

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