JP5936405B2 - Ranging system - Google Patents

Description

  In the present invention, the time of flight (TOF) method is performed by using the output corresponding to the amount of light received by reflecting the reflected light that is radiated from the light emitting unit and reflected by the object. Thus, the present invention relates to a distance measuring system for obtaining a distance to an object.

  Conventionally, a distance measuring apparatus using the TOF method is generally known as an external sensing technique for realizing non-contact distance measurement (see Patent Documents 1 and 2). In the TOF method, light is emitted from a light emitting unit toward an object, and the light reciprocating time until the light is reflected and returned by the object is sensed by the light receiving unit to obtain the distance to the object. Therefore, the technical premise is that the light emission timing at the light emitting unit is synchronized with the light reception timing at the light receiving unit.

  However, the characteristics of the light-emitting element itself constituting the light-emitting unit, the characteristics of the light-receiving element itself constituting the light-receiving unit, or the characteristics of various elements, wiring, and circuits related to the light-emitting unit and the light-receiving unit are the ambient environment such as temperature and humidity. It is affected and fluctuates. For this reason, even if calibration is performed at the time of product shipment, it is difficult to maintain the distance measurement accuracy of the distance measurement system against environmental changes that change every moment, and the error may increase. Therefore, a method of synchronizing the light emitting unit and the light receiving unit using feedback control has already been proposed (see Patent Document 3).

  In Patent Document 3, the phase comparison circuit detects the difference (phase difference) between the phase of the light emission timing signal output from the light emitting element drive circuit and the phase of the light reception timing signal output from the light receiving element drive circuit, and emits light. A delay time adjusting circuit interposed between the element timing generation circuit and the light emitting element driving circuit adjusts the light emission timing supplied to the light emitting element driving circuit in accordance with the above-described phase difference.

JP 2001-281336 A JP-A-8-313215 JP 2009-236657 A

  By the way, what is important for the synchronization of the timing of light emission and light reception is the phase detection method in the phase comparison circuit. Patent Document 3 does not show a countermeasure for a change in characteristics of the phase comparison circuit itself with respect to environmental fluctuations. Since the characteristic change of the phase comparison circuit itself cannot be corrected by feedback control from the light emission timing or the light reception timing, there is a possibility that the ranging accuracy cannot be ensured. That is, if the output characteristic of the phase comparison circuit (= observer) depends on the surrounding environment, only the characteristic fluctuations of the light emitting element driving circuit and the light receiving element driving circuit, which are originally evaluated, should be corrected. Therefore, the correction is made in consideration of the output characteristic fluctuation of the phase comparison circuit, and the originally intended phase adjustment cannot be performed on the evaluation target.

  Also, in order to achieve high temporal resolution and stability, it is necessary to consider the influence of timing fluctuation (jitter) in a relatively short time included in a feedback signal or the like. How jitter appears depends on the cause. For example, jitter caused by thermal noise is random with respect to time, but jitter generated by being affected by disturbances such as electromagnetic waves may be periodic or sudden.

  In a TOF type ranging system that handles the speed of light, it is necessary to correct the timing with high-accuracy time resolution in consideration of the influence of such jitter. In this case, if feedback control is performed with a small number of samplings, the instability increases, which adversely affects synchronization. On the other hand, although feedback control is performed with a large number of samplings, it is stable. However, even if sampling is performed with higher accuracy than the minimum time resolution of the timing correction circuit, control is impossible and wasteful power is consumed.

  Therefore, a mechanism for performing feedback control with an appropriate number of samplings is required.

  The present invention has been made in consideration of such a problem, and in the correction of the timing difference by feedback control, it is possible to maintain the stable synchronization of the light emission timing and the light reception timing which is not influenced by the surrounding environment, and is appropriate. An object of the present invention is to provide a stable and highly accurate distance measuring system that can perform feedback control with a small number of samplings.

[1] A distance measuring system according to the present invention receives a light emitting unit that emits radiated light toward a distance measuring object, and receives reflected light from the distance measuring object of the radiated light, and according to the amount of received light. A light receiving unit that performs output, a control unit that controls the light emitting unit and the light receiving unit, and a time of flight method to determine a distance to the object to be measured using the output of the light receiving unit. The present invention relates to a distance measuring system having a distance calculating unit for calculating.

  The control unit drives the light emitting unit, a sequencer that defines a light emission timing of the light emitting unit and a light receiving timing of the light receiving unit, a reference clock that generates a reference clock, and outputs the reference clock to the sequencer. A light emission drive unit that drives the light reception unit, and a timing correction unit that is interposed in a preceding stage of the light emission drive unit and corrects the light emission timing.

  The timing correction unit includes a circuit activation sequence generation unit, a delay time control / timing correction phase comparison unit, and a timing correction control logic circuit.

  Then, the circuit activation sequence generation unit outputs an activation trigger signal to the timing correction control logic circuit at the time of system activation, and activates the timing correction control logic circuit. The timing correction control logic circuit sets an initial value in the delay time control / timing correction phase comparison unit based on the activation trigger signal.

  Thereafter, the circuit activation sequence generator outputs an activation signal to the delay time control / timing correction phase comparison unit to activate the delay time control / timing correction phase comparison unit.

[2] In the present invention, the delay time control / timing correction phase comparison unit includes a first delay time control circuit, a second delay time control circuit, and a timing correction phase comparator, and the timing correction The control logic circuit fixes the initial value of the first delay time control circuit based on the input of the start trigger signal, and compares the first delay time control circuit, the second delay time control circuit, and the timing correction phase comparison. You may make it start a container.

[3] In this case, each of the first delay time control circuit, the second delay time control circuit, and the timing correction phase comparator includes a first delay line and a second delay line, respectively. A first delay locked loop circuit body that generates a first delay adjustment bias that adjusts a delay time in each of the first delay lines; and a second delay adjustment that adjusts a delay time in each of the second delay lines. And a second delay locked loop circuit main body for generating a bias, wherein the timing correction control logic circuit activates the first delay time control circuit, the second delay time control circuit, and the timing correction phase comparator. Prior to starting the first delay locked loop circuit body and the second delay locked loop circuit body, the first delay adjusting bias and the second delay adjusting bias are stabilized. It said first delay time control circuit, may be started the second delay time control circuit and the timing correction phase comparator.

[4] Further, the sequencer generates a reference signal synchronized with the reference clock, and inputs the reference signal to the first delay time control circuit and the second delay time control circuit, and the first delay time control circuit Outputs a signal obtained by delaying the reference signal based on the initial value to the light emission driving unit, and the second delay time control circuit uses the reference signal as a reference and an offset signal with a delay time as an offset. The phase comparator for timing correction performs phase comparison between the offset signal and the output signal of the light emission driver, and outputs it as a phase comparison result, and the timing correction control logic circuit outputs the phase comparison An offset adjustment signal may be generated based on the result, and the offset value may be updated in the second delay time control circuit.

[5] The timing correction control logic circuit updates the offset value, and fixes the offset value as the updated offset value when the phase comparison result reaches the median value of the detection range of the timing correction phase comparator. You may make it do.

[6] In this case, the updated offset value may be stored and held in the second delay time control circuit.

[7] Then, the timing correction control logic circuit generates a delay adjustment signal based on the phase comparison result obtained after updating and fixing the offset value, and the first delay time control based on the delay adjustment signal. The circuit may be controlled to delay the reference signal, and the first delay time control circuit may be corrected and controlled so that the offset signal and the output signal of the light emission drive unit have the same phase.

[8] The timing correction control logic circuit may measure a jitter amount for each sampling from the phase comparison result for an arbitrary number of samplings, and adjust at least the sampling interval based on the jitter amount.

[9] In this case, it is preferable that the sampling interval is shortened as the jitter amount is increased, and the sampling interval is increased as the jitter amount is decreased.

[10] When the jitter amount is within an allowable range, the sampling interval may not be adjusted assuming that the sampling interval is appropriate.

[11] Further, the timing correction control logic circuit may adjust an update interval of timing adjustment in the first delay time control circuit based on a variation amount of the phase comparison result in a certain period. .

[12] In this case, it is preferable that the update interval of the timing adjustment is shortened as the amount of change increases.

[13] When the fluctuation amount is within an allowable range, the update interval of the timing adjustment may not be adjusted on the assumption that the update interval of the timing adjustment is appropriate.

  According to the distance measuring system of the present invention, in the correction of the timing difference by the feedback control, it is possible to maintain the stable synchronization of the light emission timing and the light reception timing which is not influenced by the surrounding environment, and to perform the feedback control with an appropriate number of samplings The distance to the object to be measured can be measured with high accuracy.

It is a block diagram which shows the structure of the ranging system which concerns on this Embodiment. It is a block diagram which shows the structure of a timing correction part. 3A is an explanatory diagram illustrating a state in which the light emission timing signal and the offset signal are synchronized, and FIG. 3B is an explanatory diagram illustrating a state in which the light emission timing signal is delayed in phase with respect to the offset signal due to the influence of the surrounding environment. FIG. 3C is an explanatory diagram showing a state in which the phase delay is absorbed by the feedback control in the timing correction unit. FIG. 4A is a block diagram showing an internal configuration of the first delay locked loop circuit main body, and FIG. 4B is a block diagram showing an internal configuration of the second delay locked loop circuit main body. It is a block diagram which shows the internal structure of a 1st delay time control circuit and a 2nd delay time control circuit. It is a block diagram which shows the internal structure of the phase comparator for timing correction. It is a timing chart which shows the signal processing operation of the phase comparator for timing correction. It is a flowchart which shows the processing operation of the 1st operation sequence by a circuit starting sequence production | generation part and a timing correction control logic circuit. It is an operation | movement conceptual diagram which shows the state which started the timing correction control logic circuit. It is an operation | movement conceptual diagram which shows the state which started the delay locked loop circuit part and the phase comparison part for delay time control and timing correction. It is a time chart which shows the starting process of various circuits. It is an operation | movement conceptual diagram which shows the state which is updating the offset value. It is an operation | movement conceptual diagram which shows the state which fixed the offset value. It is an operation | movement conceptual diagram which shows the state which has correct | amending the timing adjustment signal. It is a flowchart which shows the processing operation of the 2nd operation sequence by a circuit starting sequence production | generation part and a timing correction control logic circuit. It is a time chart which shows the case where the frequency | count of sampling in each update space | interval of timing adjustment is 4 times. It is explanatory drawing which shows the difference of the fluctuation | variation of the average value by the influence of the surrounding environment after performing a timing adjustment process when not performing a timing adjustment process, and adjustment of the sampling interval by a jitter amount. It is a block diagram which shows the processing operation in the sampling interval adjustment part and jitter amount measurement part of a timing correction control logic circuit. It is a time chart which shows the case where the frequency | count of sampling in each update space | interval of timing adjustment is 8 times. It is a time chart which shows the case where the frequency | count of sampling in each update space | interval of timing adjustment is 2 times. It is a block diagram which shows the processing operation in the sampling interval adjustment part of a timing correction control logic circuit, a jitter amount measurement part, an update interval adjustment part, and an average value variation | change_quantity measurement part. It is explanatory drawing which shows the preferable example of the period which performs the period which performs sampling, the update interval of a timing adjustment, and the change of a sampling interval.

  Embodiments of a distance measuring system according to the present invention will be described below with reference to FIGS.

  As shown in FIG. 1, the distance measuring system 10 according to the present embodiment includes a light emitting unit 16 that emits radiated light 14 toward the distance measuring object 12, and reflection of the radiated light 14 from the distance measuring object 12. A light receiving unit 20 that receives the light 18 and outputs an output corresponding to the amount of received light, a control unit 22 that controls the light emitting unit 16 and the light receiving unit 20, and an output of the light receiving unit 20 is measured by a time-of-flight method. A distance calculation unit 24 that calculates the distance to the distance object. The output from the light receiving unit 20 is converted into a digital signal by the A / D converter 26 and then output to the distance calculation unit 24.

  The control unit 22 includes a reference clock generation unit 28, a sequencer 30, a light emission drive unit 32, a light reception drive unit 34, and a timing correction unit 36.

  The reference clock generation unit 28 is configured by, for example, a PLL (Phase Locked Loop) circuit using a crystal resonator that is hardly influenced by the surrounding environment such as temperature and humidity as a reference clock frequency signal, and generates a reference clock clk. The reference clock clk is output to the sequencer 30.

  The sequencer 30 defines the light emission timing of the light emitting unit 16 and the light reception timing of the light receiving unit 20. Specifically, a light emission reference signal Pe2 that is a reference of the light emission timing in the light emitting unit 16 and a light reception reference signal Pe2 that is a reference of the light reception timing in the light receiving unit 20 are generated. For example, as shown in FIG. 1, the sequencer 30 includes a first signal generation circuit 38a, a second signal generation circuit 38b, a first clock synchronization circuit 40a, and a second clock synchronization circuit 40b. The first signal generation circuit 38a generates a signal Pe1 that is a basis of light emission timing, and the second signal generation circuit 38b generates a signal Pr1 that is a basis of light reception timing. The first clock synchronization circuit 40a is constituted by, for example, a D-type flip-flop, and supplies the signal Pe1 to the D terminal of the first clock synchronization circuit 40a and supplies the reference clock clk to the CK terminal. At this time, the signal Pe1 synchronized with the reference clock clk, that is, the light emission reference signal Pe2 is output from the Q terminal of the first clock synchronization circuit 40a. Similarly, the signal Pr1 is supplied to the D terminal of the second clock synchronization circuit 40b, and the reference clock clk is supplied to the CK terminal. At this time, the signal Pr1 synchronized with the reference clock clk, that is, the light reception reference signal Pr2 is output from the Q terminal of the second clock synchronization circuit 40b.

  The light emission drive unit 32 drives and controls the light emission unit 16 based on a timing adjustment signal Pe3 from a timing correction unit 36 described later. For example, a light emission timing signal Pe4 for emitting the radiation light 14 is generated and output by the timing adjustment signal Pe3. The light emitting unit 16 radiates, for example, pulsed emitted light 14 in accordance with the light emission timing signal Pe4 from the light emission driving unit 32.

  The light receiving drive unit 34 drives and controls the light receiving unit 20 based on the light receiving reference signal Pr2 from the sequencer 30. For example, a light reception timing signal Pr4 (= electronic shutter timing signal) that defines a period during which the reflected light 18 is received is generated based on the light reception reference signal Pr2, and the light receiving unit 20 is driven and controlled. The light receiving unit 20 receives the amount of the reflected light 18 during the period (electronic shutter period) defined by the light reception timing signal Pr4 and reflects it in the output value of the light receiving unit 20.

  In FIG. 1, the light receiving drive unit 34 is mounted on one solid-state imaging device 42 together with the light receiving unit 20, the A / D converter 26, the reference clock generation unit 28, the sequencer 30, and the timing correction unit 36. Therefore, it is possible to take measures such as mounting a clock synchronization circuit in the light reception drive unit 34 and outputting the light reception timing signal Pr4 synchronized with the clock. Accordingly, it is relatively easy to directly supply the light receiving timing signal Pr4 synchronized with the clock to the light receiving unit 20 in the same manner as the light receiving reference signal Pr2.

  On the other hand, since it is difficult to mount the light emitting unit 16 on the solid-state imaging device 42, the light emission driving unit 32 and the light emitting unit 16 described above are installed outside the solid-state imaging device 42. Therefore, the timing difference (phase difference) between the light emission reference signal Pe2 from the sequencer 30 and the light emission timing signal Pe4 from the light emission drive unit 32 is affected by the surrounding environment such as temperature and humidity, and it is difficult to maintain a stable timing difference. It is.

  Therefore, the timing correction unit 36 is disposed between the sequencer 30 and the light emission drive unit 32 so that the delay difference between the light emission reference signal Pe2 from the sequencer 30 and the light emission timing signal Pe4 from the light emission drive unit 32 is always constant. In addition, a light emission timing signal Pe3 that is delayed with respect to the light emission reference signal Pe2 is generated and supplied to the light emission drive unit 32, whereby the light emission reference signal Pe2 and the light emission timing signal Pe4, and further, the light emission timing signal Pe4 and the light reception timing signal Pr4. Synchronize.

  Here, a configuration example of the timing correction unit 36 will be described with reference to FIG.

  As shown in FIG. 2, the timing correction unit 36 includes a circuit activation sequence generation unit 43, a delay locked loop circuit unit 44, a delay time control / timing correction phase comparison unit 45, and a timing correction control logic circuit 46. Have.

  The circuit activation sequence generation unit 43 has a function of activating various circuits, details of which will be described later.

  The delay locked loop circuit unit 44 includes an initial bias setting circuit 47, a first delay locked loop circuit body 48a having a first delay line, and a second delay locked loop circuit body 48b having a second delay line.

  The phase comparator 45 for delay time control / timing correction includes a first delay time control circuit 50 having a first delay line and a second delay line, and a second delay time control circuit having a first delay line and a second delay line. 52 and a timing correction phase comparator 54 having a first delay line and a second delay line.

  The timing correction control logic circuit 46 includes a sampling interval adjustment unit 55, a jitter amount measurement unit 56, an update interval adjustment unit 57, an average value variation amount measurement unit 58, an offset adjustment signal generation unit 60, and a delay adjustment signal generation. Part 62.

  The first delay locked loop circuit main body 48a generates the first delay adjustment bias Vb1 (voltage) based on the first delay stage number control signal Sprec1 from the time resolution setting unit 53, the first delay time control circuit 50, The delay time per stage of the delay elements of the first delay lines of the two delay time control circuit 52 and the timing correction phase comparator 54 is set.

  The second delay locked loop circuit main body 48b generates the second delay adjustment bias Vb2 (voltage) based on the second delay stage number control signal Sprec2 from the time resolution setting unit 53, the first delay time control circuit 50, The delay time per stage of the delay element of each second delay line of the two delay time control circuit 52 and the timing correction phase comparator 54 is set.

  The initial bias setting circuit 47 has an incorrect delay caused by the fact that the delay adjustment bias is not determined when the circuit power is turned on or when the circuit is activated in the first delay locked loop circuit body 48a and the second delay locked loop circuit body 48b. This is a circuit for preventing a lock (pseudo-lock) phenomenon due to a phase difference, and is activated by a circuit activation sequence generation unit 43, which will be described later, and an initial delay adjustment bias Vb0 (voltage) within a bias range that converges to a normal lock state is applied to the first delay adjustment bias Vb0 (voltage). The first delay locked loop circuit body 48a and the second delay locked loop circuit body 48b are supplied. By inputting the initial delay adjustment bias Vb0 in advance when the circuit power is turned on or immediately before starting the circuit, the correct phase lock state operation is always compensated.

  The first delay time control circuit 50, the second delay time control circuit 52, and the timing correction phase comparator 54 are activated by the circuit activation sequence generator 43 after the first delay adjustment bias Vb1 and the second delay adjustment bias Vb2 are stabilized. .

  The first delay time control circuit 50 receives the light emission reference signal Pe2 from the sequencer 30. The first delay time control circuit 50 adjusts the timing (phase) of the light emission reference signal Pe2 and inputs it to the light emission drive unit 32 as the first timing adjustment signal Pe3.

  The second delay time control circuit 52 receives the light emission reference signal Pe2 from the sequencer 30. The second delay time control circuit 52 sets a delay time (offset time) by an offset adjustment signal S2 from the timing correction control logic circuit 46 when, for example, the ranging system 10 is shipped or after calibration is performed ( (Or reset). That is, as shown in FIG. 3A, for example, when the emission reference signal Pe2 falls (for example, when it rises) and when the emission timing signal Pe4 falls (for example, when it rises), the time constant is constant. There is an offset time Toffset. This offset time Toffset fluctuates due to a change with time of the ranging system 10. Therefore, the offset time Toffset is acquired at the time of shipment of the distance measuring system 10 or at regular or irregular calibration performed thereafter, and information on the acquired offset time Toffset is given to the timing correction control logic circuit 46. The offset adjustment signal S2 corresponding to the new offset time Toffset is output from the timing correction control logic circuit 46 and supplied to the second delay time control circuit 52, whereby the offset time Toffset is set in the second delay time control circuit 52. (Or reset). Therefore, the light emission reference signal Pe2 input to the second delay time control circuit 52 is delayed by the set offset time Toffset and output as the offset signal Pe5.

  The light emission timing signal Pe4 from the light emission drive unit 32 is input to the first input terminal φe4 of the timing correction phase comparator 54, and the offset signal Pe5 from the second delay time control circuit 52 is input to the second input terminal φe5. To do. For example, as shown in FIG. 3B, the timing correction phase comparator 54 detects a time difference (phase difference ΔTchange) between, for example, the falling edge of the offset signal Pe5 and the falling edge of the light emission timing signal Pe4, for example, and the phase comparison result Output as S1. In particular, the timing correction phase comparator 54 converts the offset signal Pe5 and the light emission timing signal Pe4 into a digital signal corresponding to the time difference (phase difference ΔTchange), and outputs the digital signal as the phase comparison result S1 for timing correction. Input to the control logic circuit 46.

  The timing correction control logic circuit 46 generates and outputs a delay adjustment signal S3 based on the phase comparison result S1, and inputs the delay adjustment signal S3 to the first delay time control circuit 50. The first delay time control circuit 50 adjusts the delay time of the light emission reference signal Pe2 based on the delay adjustment signal S3 and outputs it as the timing adjustment signal Pe3. If the delay adjustment signal S3 is an analog signal, examples thereof include a voltage value and a current value. The delay adjustment signal S3 may be a digital signal. Note that the function of the timing correction control logic circuit 46 may be realized by replacing it with hardware such as an embedded computer or FPGA having an external CPU and memory.

  For example, as shown in FIG. 3B, when the light emission timing signal Pe4 is delayed by a certain time (denoted as a variation time) from the offset time Toffset due to the influence of the surrounding environment, the phase difference ΔTchange ( The phase comparison result S1 is output, and the timing correction control logic circuit 46 outputs the delay adjustment signal Pe3 based on the phase comparison result S1. The first delay time control circuit 50 delays the light emission reference signal Pe2 by a time based on the delay adjustment signal S3 and outputs it as a timing adjustment signal Pe3. That is, as shown in FIG. 3C, the first delay time control circuit 50 delays the light emission reference signal Pe2 by the same time (ΔTcontrol) as the phase difference ΔTchange (variation time) described above, and adjusts the timing of the light emission reference signal Pe2. Since the timing adjustment signal Pe3 is output to the light emission driver 32, for example, the falling timing of the emission timing signal Pe4 is synchronized with the falling timing of the offset signal Pe5, and the fluctuation time due to the surrounding environment is reduced. It can be absorbed by feedback control and supplied to the light emitting unit 16 as a light emission timing signal Pe4 that is accurate in terms of timing. As a result, the distance to the distance measuring object 12 can be measured without being affected by the surrounding environment.

  By the way, when a clock signal having a clock frequency of, for example, 250 MHz is assumed as the reference clock clk, the time resolution is about 2 nsec even if the rising and falling edges of the clock are used as the trigger timing of the circuit. Although the radiated light 14 travels about 300 mm in 1 nsec, for example, the distance measuring system 10 measures a round trip optical path, and thus corresponds to 150 mm when converted into a distance value. For this reason, when the timing is adjusted with a time resolution of 2 nsec, the adjustment is made in units of distance measurement values of 300 mm, and the timing adjustment with less than this distance measurement resolution is impossible. For example, in order to obtain distance measurement performance on the order of several mm, a time resolution on the order of several tens of psec is required.

  Therefore, in the present embodiment, the first delay time control circuit 50, the second delay time control circuit 52, and the timing correction phase comparator 54 are each configured by a circuit having a first delay line and a second delay line. Then, the first delay adjustment bias Vb1 (voltage) generated by the first delay locked loop circuit body 48a is applied to each first delay line, and the second delay adjustment bias generated by the second delay locked loop circuit body 48b. By applying Vb2 (voltage) to each second delay line, each delay time τ1 in the plurality of delay elements constituting the first delay line and each delay time in the plurality of delay elements constituting the second delay line Different from τ2. Further, in the first delay time control circuit 50 and the second delay time control circuit 52, the path from the first delay line to the second delay line is made variable so as to obtain a time resolution of | τ1-τ2 | The correction phase comparator 54 uses the Vernier caliper principle (Vernier principle) for the TDC circuit to perform phase comparison with a time resolution of | τ1-τ2 |. As a result, a time resolution on the order of several psec to several tens of psec can be realized, and distance measurement accuracy on the order of several mm can be compensated.

  Here, a specific circuit configuration example of the timing correction unit 36 will be described with reference to FIGS. 4A to 7.

  First, as shown in FIG. 4A, the first delay locked loop circuit main body 48a is configured to delay the first delay line DL1 based on the first delay line DL1 that receives the reference clock clk and the first delay stage number control signal Sprec1. A plurality of first selectors 66a for setting the number of stages, a first clock phase comparator 68a for detecting a phase difference between the output from the first delay line DL1 and the reference clock clk, and the output from the first clock phase comparator 68a A first charge pump 70a that generates an addition or subtraction charge based on the signal, and a first low-pass filter 72a that accumulates the output charge of the first charge pump 70a and outputs it as a first delay adjustment bias Vb1 (voltage). Have. The first delay adjustment bias Vb1 is supplied to the first delay line DL1, forms a feedback loop of the first delay locked loop circuit body 48a, and can output the first delay adjustment bias Vb1 to the outside. .

  The first delay line DL1 is configured by connecting a plurality of first delay elements 74a in series, and a first selector 66a is connected to the preceding stage of each first delay element 74a. Each first delay element 74a is constituted by, for example, an inverter delay element whose delay time is controlled by the first delay adjustment bias Vb1. Each first selector 66a selects a path according to the corresponding binary value (“1” or “0”) of the first delay stage number control signal Sprec1. For example, the first first selector 66a as viewed from the input side selects either the reference clock clk or the ground voltage Vss according to the binary value of, for example, the MSB (most significant bit) of the first delay stage control signal Sprec1. In this example, when the binary value is “1”, the reference clock clk is selected, and when the binary value is “0”, the ground voltage Vss is selected. The second and subsequent first selectors 66a as viewed from the input side select the reference clock clk when the binary value is “1”, and from the first delay element 74a one before when the binary value is “0”. Select the output. That is, the number of delay stages is controlled by the plurality of first selectors 66a.

Therefore, for example, assuming that 16 first delay elements 74a are connected in series with the first selector 66a interposed therebetween, the 14 first delay elements 74a are used as the first delay line DL1. If the first delay stage number control signal Sprec1,
MSB LSB
↓ ↓
"0010000000000000"
Is supplied from the time resolution setting unit 53. As a result, the 14th first selector 66a as viewed from the output side selects the reference clock clk, and the 1st to 13th first selectors 66a as viewed from the output side each of the previous first delay elements 74a. The output is selected, and the first delay line DL1 is formed by 14 continuous first delay elements 74a. In practice, 100 or more first delay elements 74a may be used as the first delay line DL1.

  In the first delay locked loop circuit main body 48a, the first delay line DL1 operates so as to delay the reference clock clk by one cycle, and the rising timing or falling timing of the output of the first delay line DL1 and the reference clock clk is set. The first clock phase comparator 68a compares. Based on the comparison result, the first charge pump 70a and the first low-pass filter 72a operate to always perform feedback control so as to cancel the phase difference between the output of the first delay line DL1 and the reference clock clk. As a result, the first delay adjustment bias Vb1 for generating the delay value (τ1) of the first delay element 74a is obtained. As the number of first delay elements 74a is increased, the delay time (τ1) in each first delay element 74a is shortened. The first delay locked loop circuit main body 48a has an autonomous self-feedback function based on a stable reference clock clk with respect to manufacturing variations of integrated circuits, fluctuations in the surrounding environment, and the like. It is possible to generate the first delay adjustment bias Vb1 corresponding to manufacturing variations and surrounding environment fluctuations.

  The second delay locked loop circuit main body 48b has the same configuration as the first delay locked loop circuit main body 48a described above. As shown in FIG. 4B, the second delay locked loop circuit main body 48b receives the second delay line DL2 that receives the reference clock clk, A plurality of second selectors 66b for setting the number of delay stages of the second delay line DL2 based on the two delay stage number control signal Sprec2, and a second clock for detecting the phase difference between the output from the second delay line DL2 and the reference clock clk Based on the output signal from the phase comparator 68b and the second clock phase comparator 68b, the second charge pump 70b for generating addition or subtraction charges, and the output charge of the second charge pump 70b are accumulated, and the second delay. And a second low-pass filter 72b that outputs the adjustment bias Vb2 (voltage). The second delay adjustment bias Vb2 is supplied to the second delay line DL2, forms a feedback loop of the second delay locked loop circuit body 48b, and can output the second delay adjustment bias Vb2 to the outside. .

  The second delay line DL2 is configured by connecting a plurality of second delay elements 74b in series, and a second selector 66b is connected to the preceding stage of each second delay element 74b. Each second delay element 74b is configured by, for example, an inverter delay element whose delay time is controlled by the second delay adjustment bias Vb2. The configurations of the second delay element 74b, the second selector 66b, and the second delay stage number control signal Sprec2 are the same as the first delay element 74a, the first selector 66a, and the first delay stage number control signal Sprec1 described above. The duplicate description is omitted.

  Also in the second delay locked loop circuit main body 48b, the second delay line DL2 operates so as to delay the reference clock clk by one cycle, and the rising timing or falling timing of the output of the second delay line DL2 and the reference clock clk. Are compared by the second clock phase comparator 68b. Based on the comparison result, the second charge pump 70b and the second low-pass filter 72b operate to always perform feedback control so as to cancel the phase difference between the output of the second delay line DL2 and the reference clock clk. Thus, the second delay adjustment bias Vb2 for generating the delay value (τ2) of the second delay element 74b is obtained. As the number of second delay elements 74b is increased, the delay time (τ2) in each second delay element 74b is shortened.

  By the way, the circuit configurations of the first delay element 74a and the second delay element 74b, the sizes of the transistors constituting the circuit, and the like are the same. Therefore, if the number of first delay elements 74a selected by the first delay line DL1 is the same as the number of second delay elements 74b selected by the second delay line DL2, the delay time of each first delay element 74a ( The first delay time τ1) and the delay time of each second delay element 74b (second delay time τ2) are the same.

  However, in the present embodiment, since the caliper principle is used, the first delay time τ1 and the second delay time τ2 have a difference. Therefore, there is a difference between the number of first delay elements 74a selected by the first delay line DL1 and the number of second delay elements 74b selected by the second delay line DL2. For example, the number of the first delay elements 74a is made larger than the number of the second delay elements 74b, the first delay time τ1 is set to several hundred psec, and the second delay time τ2 is set to (several 100 + several 10) psec. At this time, the delay time difference | τ1−τ2 | is approximately several tens of psec.

  As shown in FIG. 5, the first delay time control circuit 50 has the same configuration as the first delay line DL1 of the first delay locked loop circuit body 48a, and receives the light emission reference signal Pe2 as an input. DL1 has the same configuration as the second delay line DL2 of the second delay locked loop circuit main body 48b, and receives the light emission reference signal Pe2 or a signal of the light emission reference signal Pe2 via the first delay line DL1 as input. The second delay line DL2 and a plurality of second selectors 66b for switching the path from the first delay line DL1 to the second delay line DL2 based on the delay adjustment signal S3.

  The first delay line DL1 is configured by connecting a plurality of first delay elements 74a in series, and a first selector 66a is connected to the preceding stage of each first delay element 74a. Each first selector 66a is a characteristic dummy and is connected to the second delay line DL2 in order to align the load. The first first selector 66a as viewed from the input side selects the light emission reference signal Pe2 fixedly, and the second and subsequent first selectors 66a as viewed from the input side output from the previous first delay element 74a. Is to be fixed and selected. Note that the output side end (termination) of the first delay line DL1 is also connected to a characteristic dummy inverter delay circuit for matching the load characteristic of the final stage of the delay line with the characteristic before the final stage.

  The second delay line DL2 is configured by connecting a plurality of second delay elements 74b in series, and a second selector 66b is connected to the preceding stage of each second delay element 74b. Each second selector 66b selects a path according to the corresponding binary value ("1" or "0") of the delay adjustment signal S3. For example, the first second selector 66b as viewed from the input side selects either the light emission reference signal Pe2 or the ground voltage Vss according to, for example, the binary value of the MSB (most significant bit) of the delay adjustment signal S3. In this example, the light emission reference signal Pe2 is selected when the binary value is “1”, and the ground voltage Vss is selected when the binary value is “0”. The second and subsequent second selectors 66b as viewed from the input side select the output from the previous first delay element 74a when the binary value is "1", and 1 when the binary value is "0". The output from the previous second delay element 74b is selected.

Accordingly, for example, 16 first delay elements 74a are connected in series with the first selector 66a interposed therebetween, and 16 second delay elements 74b are connected in series with the second selector 66b interposed therebetween. Assuming the case, when selecting the two first delay elements 74a as the first delay line DL1 and selecting the 14 second delay elements 74b as the second delay line DL2, as the delay adjustment signal S3,
MSB LSB
↓ ↓
"0010000000000000"
Is supplied from the timing correction control logic circuit 46. As a result, a path from the second first delay element 74a viewed from the input side to the third second delay element 74b viewed from the input side is selected. As a result, the light emission reference signal Pe2 is delayed by the delay time {(2 Is output as a timing adjustment signal Pe3 delayed by xτ1) + (14 × τ2)}. Similarly, when three first delay elements 74a are selected as the first delay line DL1, and thirteen second delay elements 74b are selected as the second delay line DL2, the third first delay element 74a is viewed from the input side. A path from the first delay element 74a to the fourth second delay element 74b as viewed from the input side is selected, and as a result, the light emission reference signal Pe2 is delayed by a delay time {(3 × τ1) + (13 × τ2)}. Is output as the timing adjustment signal Pe3. The difference between the delay time of the former and the latter is | {(2 × τ1) + (14 × τ2)} − {(3 × τ1) + (13 × τ2)} | = | τ2−τ1 | A time resolution of | τ2−τ1 | can be obtained by switching the route by 66b. In the above-described example, the case of 16 first delay elements 74a and 16 second delay elements 74b has been shown. However, actually, 100 or more first delay elements 74a and 100 or more first delay elements 74b are used. A two-delay element 74b may be used.

  Since the second delay time control circuit 52 has the same configuration as the first delay time control circuit 50 (see FIG. 5) described above, the duplicate description thereof will be omitted. However, the second selector 66b receives the offset adjustment signal S2. The route is selected according to the corresponding binary value (“1” or “0”). Also in the second delay time control circuit 52, the time resolution of | τ2−τ1 | can be obtained by switching the path by the second selector 66b.

  As shown in FIG. 6, the timing correction phase comparator 54 includes a first delay line DL1 that receives the light emission timing signal Pe4, a second delay line DL2 that receives the offset signal Pe5, and a delay element. A phase determination circuit 78 having a plurality of arranged flip-flop circuits 76 (here, D-type flip-flops) and a decoder 80 are included.

  The first delay line DL1 is configured by connecting a plurality of first delay elements 74a each having a delay time that can be controlled by the first delay adjustment bias Vb1 in series. The second delay line DL2 is also configured by connecting in series a plurality of second delay elements 74b whose delay times can be controlled by the second delay adjustment bias Vb2. A characteristic dummy delay element is connected to the last stage of the first delay line DL1 and the second delay line DL2 so that the load characteristics of the final stage do not differ from the characteristics before the final stage.

  If the delay time τ2 of the second delay element 74b is set longer than the delay time τ1 of the first delay element 74a by the first delay adjustment bias Vb1 and the second delay adjustment bias Vb2, the light emission timing signal Pe4 is influenced by the surrounding environment. When the light emission timing signal Pe4 is input with a phase delay with respect to the offset signal Pe5, the light emission timing signal Pe4 is gradually delayed in phase with respect to the offset signal Pe5 due to the difference in delay time described above. From the middle of the first delay line DL1 and the second delay line DL2, this time, the light emission timing signal Pe4 advances in phase with respect to the offset signal Pe5, and the phase advance gradually increases.

  The phase determination circuit 78 includes, for example, flip-flop circuits 76 corresponding to the number of first delay elements 74a (or second delay elements 64b) +1. Each flip-flop circuit 76 is constituted by a D-type flip-flop. Among them, flip-flop circuits 76 corresponding to the number of first delay elements 74a (or second delay elements 74b) are arranged corresponding to the first delay elements 74a (or second delay elements 74b), and the D terminal has The output of the corresponding first delay element 74a is input, and the output of the corresponding second delay element 74b is input to the CK terminal. When viewed from the input side, the first flip-flop circuit 76 inputs the light emission timing signal Pe4 to the D terminal and inputs the first offset signal Pe5 to the CK terminal. In this embodiment, since an inverter delay element is used as the first delay element 74a, there is a first delay element 74a that outputs a signal waveform obtained by inverting and delaying the light emission timing signal Pe4. For example, the output waveform of the odd-numbered first delay elements 74a when viewed from the input side is a signal waveform obtained by inverting and delaying the light emission timing signal Pe4, and the output waveform of the even-numbered first delay elements 74a when viewed from the input side is The signal waveform is obtained by delaying the light emission timing signal Pe4 as it is. The same applies to the second delay line DL2, and the output waveform of the odd-numbered second delay element 74b when viewed from the input side is a signal waveform obtained by inverting and delaying the offset signal Pe5, and viewed from the input side. The output waveform of the even-numbered second delay element 74b is a signal waveform obtained by delaying the offset signal Pe5 as it is.

  Therefore, when the light emission timing signal Pe4 is delayed due to the influence of the surrounding environment, for example, in the 2j + 1 (odd number) flip-flop circuit 76 from the input side, the phase of the light emission timing signal Pe4 is delayed from the offset signal Pe5. As shown in FIG. 4, when the input of the CK terminal becomes high of binary logic, the input of the D terminal is low of binary logic, so that a logic value “0” is output from the Q terminal. In the 2j + 2 (even number) flip-flop circuit 76 from the input side, since the input of the D terminal is High when the input of the CK terminal becomes Low, the logic value “1” is output from the Q terminal. That is, the logical value indicating the phase delay is a logical value that is inverted between the odd number and the even number.

  Similarly, in the 2j + 4 (even number) flip-flop circuit 76 from the input side in which the light emission timing signal Pe4 is advanced in phase from the offset signal Pe5 in the middle of the first delay line DL1 and the second delay line DL2, the CK terminal Since the input of the D terminal is Low when the input becomes Low, the logic value “0” is output from the Q terminal. For example, in the 2j + 5 (even) th flip-flop circuit 76 from the input side, CK Since the input of the D terminal is High when the input of the terminal becomes High, the logic value “1” is output from the Q terminal. That is, the logical value indicating the phase advance is a logical value that is inverted between the odd number and the even number.

  Therefore, for example, a NOT gate 82 (see FIG. 6) that inverts (bit inverts) the output from the even-numbered flip-flop circuit 76 is connected, and the light emission timing signal Pe4 has a logical value indicating a phase lag with respect to the offset signal Pe5. The logic value “0” is set for both odd and even numbers, and the logic value indicating phase advance is set to “1” for both odd and even numbers. As a result, the logical value is inverted from “0” to “1” (bit inversion) when the light emission timing signal Pe4 input with a phase delay with respect to the offset signal Pe5 passes the offset signal Pe5 in the middle of the first delay line DL1. ) To obtain the phase determination signal Db. The decoder 80 decodes the phase determination signal Db from the phase determination circuit 78 and passes it to the timing correction control logic circuit 46.

  As a decoding method in the decoder 80, there are the following two methods.

  In the first decoding method, as shown in Table 1 below, the phase determination signal Db from the phase determination circuit 68 is converted into one-to-one (the thermometer code conversion) by the number of 1s arranged from the least significant bit, and the phase difference value Output as S1 (first phase comparison result).

  As shown in Table 2 below, the second decoding method converts the number of bits having a logical value “1” in the phase determination signal Db from the phase determination circuit 78 into a digital value, and outputs it as a phase difference value S1. To do. In this case, since 0 and 1 can be decoded even if they are not continuous due to fluctuations in noise or the like, it is preferable to the first decoding method described above, but the decoder 80 requires a circuit for counting the number of 1s. .

  In the timing correction unit 36, in the first delay time control circuit 50 and the second delay time control circuit 52, a first delay line DL1 and a first delay line in which a plurality of first delay elements 74a (delay time τ1) are arranged in series. A path can be selected with the second delay line DL2 in which a plurality of second delay elements 74b (delay time τ2) are arranged in series corresponding to DL1, and a time resolution of | τ1-τ2 | is obtained. Further, the timing correction phase comparator 54 applies the caliper principle (Vernier principle) using the first delay line DL1, the second delay line DL2, the flip-flop circuit 76, and the phase determination circuit 78. Thus, phase comparison is performed with a time resolution of | τ1-τ2 |. As a result, a time resolution on the order of several tens of psec can be realized, and a distance measurement accuracy of several mm can be compensated.

  Next, two processing operations (first operation sequence and second operation sequence) in the circuit activation sequence generation unit 43 of the timing correction control logic circuit 46 will be described with reference to FIGS.

  First, the first operation sequence will be described with reference to FIGS.

  First, in step S1 of FIG. 8, as shown in FIG. 9, the circuit activation sequence generator 43 outputs the activation trigger signal Stg (see FIG. 11) to the enable terminal of the timing correction control logic circuit 46, and the timing The correction control logic circuit 46 is activated.

  In step S2, the timing correction control logic circuit 46 sets the value of the delay adjustment signal S3 to an initial value and outputs the initial value to the first delay time control circuit 50. For example, the initial value may be a time obtained by adding half the difference between the longest delay time and the shortest delay time that can be set by the first delay time control circuit 50 to the shortest delay time.

  In step S3 of FIG. 8, the circuit activation sequence generation unit 43 activates the delay locked loop circuit unit 44 and the delay time control / timing correction phase comparison unit 45. That is, as illustrated in FIGS. 10 and 11, first, the circuit activation sequence generation unit 43 outputs the first activation signal Sd <b> 1 to the first enable terminal of the delay locked loop circuit unit 44. The delay locked loop circuit unit 44 drives the initial bias setting circuit 47 using the input of the first activation signal Sd1 as a trigger. The initial bias setting circuit 47 sets an initial bias Vb0 within a bias range Zb that converges to a normal lock state, and supplies the initial bias Vb0 to the first delay locked loop circuit body 48a and the second delay locked loop circuit body 48b. In addition, the circuit activation sequence generation unit 43 outputs the second activation signal Sd2 to the second enable terminal of the delay locked loop circuit unit 44 after setting the initial bias Vb0. The delay locked loop circuit unit 44 drives the first delay locked loop circuit body 48a and the second delay locked loop circuit body 48b with the input of the second activation signal Sd2 as a trigger. The first delay locked loop circuit body 48a and the second delay locked loop circuit body 48b generate and output the first delay adjustment bias Vb1 and the second delay adjustment bias Vb2 from the initial bias Vb0. In addition, the circuit activation sequence generation unit 43 uses the third drive signal Sd3 as an enable terminal of the delay time control / timing correction phase comparison unit 45 when the first delay adjustment bias Vb1 and the second delay adjustment bias Vb2 are stabilized. Output. The first delay time control circuit 50, the second delay time control circuit 52, and the timing correction phase comparator 54 of the delay time control / timing correction phase comparison unit 45 are activated using the third drive signal Sd3 as a trigger.

  In step S4 of FIG. 8, the timing correction control logic circuit 46 updates the offset value. As shown in FIG. 12, the timing correction control logic circuit 46 (particularly, the offset adjustment signal generation unit 60) generates an offset value based on the phase comparison result S1 from the timing correction phase comparator 54, and performs offset adjustment. The signal S2 is output to the second delay time control circuit 52. In the initial stage, for example, when the second delay time control circuit 52 sets the shortest delay time, the offset signal Pe5 has a phase advance relative to the light emission timing signal Pe4. The timing correction control logic circuit 46 generates an offset value for canceling the phase delay, outputs the offset value to the second delay time control circuit 52, and updates the offset value in the second delay time control circuit 52.

  In step S5 of FIG. 8, the timing correction control logic circuit 46, as shown in FIG. 13, when the phase comparison result S1 becomes an offset value that becomes the center value of the detection range (phase delay direction and phase advance direction). , Fixed (locked) with an offset value. That is, updating of the offset value is stopped.

  In step S6 of FIG. 8, the timing correction control logic circuit 46, as shown in FIG. 14, the first delay time control circuit 50 so that the phase comparison result S1 is always the same even with environmental changes such as temperature fluctuations. The correction is controlled. That is, the timing adjustment amount (phase delay direction and phase advance direction) in the first delay time control circuit 50 is obtained from the difference between the phase comparison result S1 and the median value, and the delay adjustment signal S3 corresponding to the timing adjustment amount is obtained. Generated and output to the first delay time control circuit 50. The first delay time control circuit 50 adjusts the timing of the light emission reference signal Pe2 based on the supplied delay adjustment signal S3, and outputs it as the timing adjustment signal Pe3.

  Then, in step S7 of FIG. 8, it is determined whether or not there is a distance measurement timing correction end request (power OFF, correction function OFF request). If there is no termination request, the processing in step S6 is repeated. If there is a termination request, the processing operation in this timing correction control logic circuit 46 is terminated. When the power is turned on again or when the distance measurement is started, the processing after step S1 is performed.

  Here, the first delay time control circuit 50, the second delay time control circuit 52, and the timing correction phase comparator 54 are generated by the first delay locked loop circuit body 48a and the second delay locked loop circuit body 48b. Therefore, it is difficult to be affected by the surrounding environment such as temperature. Further, by comparing the phase of the light emission timing signal Pe4 from the light emission drive unit 32 with the offset signal Pe5, the timing deviation of the light emission timing signal Pe4 can be absorbed by the timing adjustment value by feedback control, and the light emission timing is compensated. Can do.

  Next, the second operation sequence will be described with reference to the flowchart of FIG.

  First, in steps S101 to S103 in FIG. 15, the same operations as in steps S1 to S3 described above are performed. That is, in step S101, the timing correction control logic circuit 46 is activated. In step S102, the timing correction control logic circuit 46 sets the value of the delay adjustment signal S3 to an initial value. In step S103, the delay locked loop circuit unit is set. 44 and the delay time control / timing correction phase comparison unit 45 are activated.

  Thereafter, in step S104, the timing correction control logic circuit 46 determines whether the current adjustment operation changes the offset value. This determination includes the case where the offset value needs to be changed, the time of product shipment, the execution of calibration, and the like.

  If the offset value needs to be changed, the process proceeds to the next step S105, and the timing correction control logic circuit 46 performs the offset based on the phase comparison result S1 from the timing correction phase comparator 54 as in step S4 described above. A value is generated and output to the second delay time control circuit 52, and the offset value in the second delay time control circuit 52 is updated.

  In step S106, the timing correction control logic circuit 46 fixes (locks) the phase comparison result S1 with the offset value when the phase comparison result S1 becomes an offset value that becomes the center value of the detection range (phase delay direction and phase advance direction). . That is, updating of the offset value is stopped. The offset value is stored and held in the second delay time control circuit 52.

  When the offset value is not changed in the above-described step S104, or when the processing in step S106 is completed, the process proceeds to the next step S107, and the timing correction control logic circuit 46 is similar to the above-described step S6. The first delay time control circuit 48 is corrected and controlled so that the phase comparison result S1 is always the same.

  In step S108, it is determined whether or not there is a distance measurement timing correction end request (power OFF or correction function OFF request). If there is no termination request, the processing in step S107 is repeated. If there is a termination request, the processing operation in the timing correction control logic circuit 46 is terminated. When the power is turned on again or the distance measurement is started, the processing after step S101 is performed. For example, when the product is not shipped or calibration is not performed, step S105 and step S106 are performed. The process proceeds to step S107 without performing the above process.

  In the second operation sequence, similarly to the first operation sequence described above, the timing shift of the light emission timing signal Pe4 can be absorbed by the timing adjustment value, and the light emission timing can be compensated. In addition, since the offset value is stored and held at the time of product shipment (or at the time of calibration), the same light emission timing as that at the time of product shipment can be compensated even during actual operation after product shipment.

  In the above example, the timing correction unit 36 compares the phase of the light emission timing signal Pe4 from the light emission drive unit 32 and the offset signal Pe5. In addition, the light reception timing signal Pr4 from the light reception drive unit 34 and the offset signal are compared. The light reception timing may be compensated by phase comparison with Pe5. Needless to say, a timing correction unit 36 may be provided at each stage before the light emission drive unit 32 and the light reception drive unit 34 to compensate for the light emission timing and the light reception timing.

  Next, the sampling interval adjustment unit 55 and the jitter amount measurement unit 56 of the timing correction control logic circuit 46 will be described with reference to FIGS.

  The sampling interval adjusting unit 55 adjusts the sampling interval (sampling interval Tsp) of the phase comparison result S1 based on the required number of samplings determined from the jitter amount measured by the jitter amount measuring unit 56.

  First, the operation of the sampling interval adjustment unit 55 will be described. The offset adjustment signal generation unit 60 outputs the offset adjustment signal S2 to the second delay time control circuit 52. The delay time control / timing correction phase comparison unit 45 outputs the phase comparison result S1 at the sampling interval. The sampling interval adjustment unit 55 outputs the phase comparison result S1 captured at each sampling interval Tsp to the update interval adjustment unit 57 as a sampling value. The update interval adjustment unit 57 obtains an average value of a plurality of sampling values in a period between timing adjustment update intervals Ttc, and the delay adjustment signal generation unit 62 generates a delay adjustment signal S3 based on the average value, This is output to the first delay time control circuit 50.

  The phase comparator 54 for timing correction compares the phase from the time when each light emission reference signal Pe2 is delayed by the circuit delay time of the delay control circuit or the phase comparator 45 for timing correction from the falling (or rising) time. Since the result S1 is output, the sampling interval adjustment unit takes in the sampling value from the phase comparison result S1 in consideration of the circuit delay time.

  The sampling interval adjustment unit 55 obtains the required number of samplings based on the jitter amount, and samples the phase comparison result S1 at the update interval Ttc and the timing update interval Ttc derived from the necessary number of samplings. As described above, the update interval adjustment unit 57 obtains the average value of the sampling values in the period between the update intervals Ttc, and the delay adjustment signal generation unit 62 generates the delay adjustment signal S3 based on the average value. , And supplied to the first delay time control circuit 50. The example of FIG. 16 shows a case where the number of samplings at one update interval Ttc is four.

  Normally, as shown in FIG. 17, at the start of distance measurement, since it is a transient state that settles in a steady state, the variation of the average value tends to increase. After that, there is a tendency that the average value gradually decreases with time. Further, the jitter amount increases or decreases depending on the temperature of the surrounding environment. The object of the present embodiment is to stably operate the circuit and reduce the power consumption of the circuit by operating the circuit with the minimum number of samplings / updates corresponding to these fluctuations.

Then, the sampling interval adjusting unit 55 changes the sampling interval Tsp described above according to the jitter amount measured by the jitter amount measuring unit 56 and performs sampling. Similarly, the delay time control / timing correction phase comparison unit 45 performs the circuit operation at the sampling interval Tsp. As shown in FIG. 18, the jitter amount measuring unit 56 measures the jitter amount for every certain number of times of sampling. The amount of jitter is generally expressed by standard deviation σ or Peak to Peak jitter. For example, when the standard deviation σ is used, N is a certain number of times of sampling for obtaining the jitter amount, T _ave is the average phase comparison result at N, and i th (i = 1, 2, 3,... N). When the phase comparison result in sampling is T _i , the following equation (1) can be obtained.

Since the measured value fluctuates by this amount of jitter (standard deviation), the measured value deviates from the true ideal phase comparison result. Therefore, by obtaining the average of the sampling values, the influence of fluctuation (jitter amount) of the measurement values is suppressed. Specifically, when the amount of jitter was Shigumajitter, the average value at a rate of ^{_{√ (σ jitter 2 / N ave}} ) approaches the true phase comparison result. Here, N _ave is the number of samplings for deriving an average value.

  The number of samplings Nk required for averaging is obtained every update interval Ttc so that this ratio is equal to or less than the preset allowable deviation amount. The sampling interval is obtained by calculating Ttc / Nk. Therefore, in an environment where the amount of jitter is large, the number of samplings Nk required for averaging also increases, and the sampling interval decreases accordingly. As a result, as shown in FIG. 17, for example, in the state of “a” where the jitter amount is large, the sampling interval becomes dense. In the example of FIG. 19, an example in which the sampling interval is closer than that of the example of FIG. 16, that is, a case where the number of times of sampling at each update interval Ttc is 8 is shown.

  Conversely, in an environment where the amount of jitter is small, the number of samplings Nk is also reduced, and the sampling interval is increased accordingly. As a result, as shown in FIG. 17, the sampling interval becomes sparse in the state of “b” where the jitter amount is small. In the example of FIG. 20, an example in which the sampling interval is made sparser than the example of FIG. 16, that is, the case where the number of times of sampling at each update interval Ttc is two is shown.

  Therefore, in an environment where the amount of jitter is large, the number of times of sampling at a constant update interval Ttc is increased, and the accuracy of the average value for generating the delay adjustment signal S3 is increased. This makes it possible to ensure the stability of feedback control in an environment where jitter is large. On the other hand, in an environment where the amount of jitter is small, the stability of feedback control is ensured without increasing the accuracy of the average value, so the number of samplings at a constant update interval Ttc is reduced, contributing to low power consumption. Will be.

  Next, the update interval adjusting unit 57 and the average value variation measuring unit 58 of the timing correction control logic circuit 46 will be described with reference to FIG.

  The update interval adjustment unit 57 performs a process of adjusting the update interval Ttc described above according to the average value fluctuation amount measured by the average value fluctuation amount measurement unit 58. Therefore, as shown in FIG. 21, the average value of a certain period is taken at least twice, and the difference between the average value of the latest period and the average value of the past period than the latest period is calculated. The update interval Ttc is adjusted according to the amount.

  Specifically, when the current update interval is Ttc (t) and the difference is ΔH, the new update interval Ttc (t + 1) is, for example,

Ask for. Here, A is a threshold value that shortens the update interval, and B is a threshold value that lengthens the update interval. ΔTtc is an update time addition / subtraction value. ΔTtc may be changeable in magnitude depending on ΔH.

  That is, if the difference is within a certain range (A to B range), the current update interval Ttc is maintained. When the difference ΔH is larger than A, or larger than A and the difference ΔH increases, the update interval Ttc is shortened. By shortening the update interval Ttc, it is possible to obtain faster followability with respect to characteristic fluctuations. However, since the update interval Ttc is shortened every time the average value fluctuates, it is preferable to set the shortest update interval Ttc in advance and control so as not to be shorter than the shortest update interval Ttc. . When the difference ΔH is smaller than B, the update interval Ttc may be gradually increased. However, since the update period Ttc becomes longer when the fluctuation of the average value is small, the longest update interval Ttc is set in advance and control is performed so as not to be longer than the longest update period. It is preferable to be able to respond to the above with a minimum response speed.

  As shown in FIG. 22, the sampling for obtaining the average value of the phase comparison results S1 is performed during the exposure period in the light receiving unit 20, and the change of the update interval Ttc and the change of the sampling interval Tsp (update timing) are received. This is preferably performed during the charge reading period in the unit 20. This is because if these intervals are changed during the exposure period (= during the image determination period), the charge accumulation amount may fluctuate unexpectedly and the distance measurement accuracy may be reduced.

  It should be noted that the distance measuring system according to the present invention is not limited to the above-described embodiment, and can of course adopt various configurations without departing from the gist of the present invention.

DESCRIPTION OF SYMBOLS 10 ... Ranging system 12 ... Ranging object 14 ... Radiation light 16 ... Light emission part 18 ... Reflection light 20 ... Light reception part 22 ... Control part 24 ... Distance calculation part 28 ... Reference clock generation part 30 ... Sequencer 32 ... Light emission drive part 34 ... Light receiving drive unit 36 ... Timing correction unit 43 ... Circuit activation sequence generation unit 44 ... Delay locked loop circuit unit 45 ... Delay time control / timing correction phase comparison unit 46 ... Timing correction control logic circuit 47 ... Initial bias setting circuit 48a ... first delay locked loop circuit main body 48b ... second delay locked loop circuit main body 50 ... first delay time control circuit 52 ... second delay time control circuit 54 ... timing correction phase comparator 55 ... sampling interval adjusting unit 56 ... jitter Quantity measuring unit 57 ... Update interval adjusting unit 58 ... Average value fluctuation amount measuring unit 60 ... Offset adjustment signal generating unit 62 ... Delay adjustment signal Generator DL1 ... first delay line DL2 ... second delay line

Claims (13)

A light emitting unit that emits synchrotron radiation toward the object to be measured;
A light receiving unit that receives reflected light from the distance measurement object of the radiated light and performs output according to the amount of received light;
A control unit for controlling the light emitting unit and the light receiving unit;
In a ranging system having a distance calculation unit that calculates a distance to the ranging object by a time-of-flight method using an output of the light receiving unit,
The controller is
A sequencer that defines the light emission timing of the light emitting unit and the light reception timing of the light receiving unit;
A reference clock generation unit that generates a reference clock and outputs the reference clock to the sequencer;
A light emission drive unit for driving the light emission unit;
A light receiving drive unit for driving the light receiving unit;
A timing correction unit that is interposed in a preceding stage of the light emission driving unit and corrects the light emission timing;
The timing correction unit includes a circuit startup sequence generation unit, a delay time control / timing correction phase comparison unit, and a timing correction control logic circuit,
The circuit startup sequence generation unit outputs a startup trigger signal to the timing correction control logic circuit at the time of system startup, and starts the timing correction control logic circuit,
The timing correction control logic circuit sets an initial value in the phase comparison unit for delay time control and timing correction based on the start trigger signal,
The circuit activation sequence generation unit outputs an activation signal to the delay time control / timing correction phase comparison unit, after the initial value is set in the delay time control / timing correction phase comparison unit, A ranging system characterized by activating a phase comparison unit for time control and timing correction. The ranging system according to claim 1, wherein
The delay time control / timing correction phase comparison unit includes a first delay time control circuit, a second delay time control circuit, and a timing correction phase comparator,
The timing correction control logic circuit fixes an initial value of the first delay time control circuit based on an input of a start trigger signal, the first delay time control circuit, the second delay time control circuit, and the timing correction Ranging system characterized by activating a phase comparator for a vehicle. The ranging system according to claim 2,
Each of the first delay time control circuit, the second delay time control circuit, and the timing correction phase comparator has a first delay line and a second delay line, respectively.
The timing correction unit includes a first delay locked loop circuit body that generates a first delay adjustment bias that adjusts a delay time in each first delay line, and a first delay that adjusts a delay time in each second delay line. A second delay locked loop circuit body for generating a two delay adjustment bias;
The timing correction control logic circuit includes the first delay locked loop circuit main body and the second delay prior to activation of the first delay time control circuit, the second delay time control circuit, and the timing correction phase comparator. When the synchronous loop circuit body is activated and the first delay adjustment bias and the second delay adjustment bias are stabilized, the first delay time control circuit, the second delay time control circuit, and the timing correction phase comparator Ranging system characterized by starting up. The ranging system according to claim 2 or 3,
Generating a reference signal synchronized with the reference clock in the sequencer, and inputting the reference signal to the first delay time control circuit and the second delay time control circuit;
The first delay time control circuit outputs a signal obtained by delaying the reference signal based on the initial value to the light emission driving unit,
The second delay time control circuit outputs an offset signal in which a delay time is offset with reference to the reference signal;
The timing correction phase comparator performs phase comparison between the offset signal and the output signal of the light emission drive unit, and outputs the result as a phase comparison result.
The timing correction control logic circuit generates an offset adjustment signal based on the phase comparison result, and causes the second delay time control circuit to update an offset value. The ranging system according to claim 4, wherein
The timing correction control logic circuit updates an offset value, and fixes the offset value as an updated offset value when the phase comparison result reaches the median value of the detection range of the timing correction phase comparator. Ranging system characterized by The ranging system according to claim 5, wherein
A ranging system characterized in that the updated offset value is stored and held in the second delay time control circuit. The ranging system according to claim 5 or 6,
The timing correction control logic circuit includes:
A delay adjustment signal is generated based on the phase comparison result obtained after updating and fixing the offset value, and the first delay time control circuit is controlled by the delay adjustment signal to delay the reference signal,
The ranging system according to claim 1, wherein the first delay time control circuit is corrected and controlled so that the offset signal and the output signal of the light emission drive unit have the same phase. The ranging system according to claim 7, wherein
The timing correction control logic circuit measures a jitter amount for each sampling from the phase comparison result for an arbitrary number of samplings, and adjusts at least a sampling interval based on the jitter amount. The ranging system according to claim 8, wherein
As the amount of jitter increases, the sampling interval is shortened,
A ranging system characterized in that the sampling interval is lengthened as the jitter amount becomes smaller. The ranging system according to claim 8 or 9,
When the jitter amount is within an allowable range, the sampling interval is not adjusted because the sampling interval is appropriate. The ranging system according to any one of claims 7 to 10,
The distance measuring system, wherein the timing correction control logic circuit adjusts an update interval of timing adjustment in the first delay time control circuit based on a variation amount of the phase comparison result in a certain period. The ranging system according to claim 11, wherein
A ranging system characterized in that the update interval of the timing adjustment is shortened as the fluctuation amount increases. The ranging system according to claim 11 or 12,
When the variation amount is within an allowable range, the timing adjustment update interval is not adjusted, and the timing adjustment update interval is not adjusted.

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