JP2017017671A - Electronic circuit, and method of controlling oscillator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electronic circuit capable of changing an oscillation frequency at high speed so as to follow a power supply noise.SOLUTION: An electronic circuit includes: an oscillator that generates an oscillation signal having a cycle depending on an input signal; a voltage detector that outputs a detection signal depending on a power supply voltage; a frequency divider that performs frequency division of the oscillation signal at a frequency dividing ratio depending on the detection signal to generate a frequency-divided signal; and an adder that calculates a sum of a first signal depending on a phase difference between the frequency-divided signal and a reference signal, and a second signal depending on the detection signal, and supplies a signal depending on the sum to the oscillator as the input signal.SELECTED DRAWING: Figure 1

Description

  The present disclosure relates to an electronic circuit and a method for controlling an oscillator.

  Since digital circuits of LSIs (Large Scale Integrated Circuits) operate in synchronization with the clock signal, if the circuit scale is large, a large current is consumed at the clock transition timing, and power supply noise called IR drop is generated in the power supply voltage. Occur. Due to the IR drop, the power supply voltage shows a voltage change in a frequency band determined by impedances such as a power supply wiring and a stabilization capacitor. In general, this fluctuation has a frequency band of about 50 MHz to 150 MHz.

  When the power supply voltage decreases, the rate of change of the signal propagating in the signal path in the LSI decreases, and data may not be transferred properly in a critical path with a small signal propagation timing margin. In order to avoid such timing errors, some LSIs such as processors adaptively control the operating frequency in response to a voltage drop. Specifically, the voltage is measured, the amount of increase in the delay of the data path due to the voltage drop is estimated, and the clock cycle is lengthened so as to cancel out the amount of delay increase.

  As a method of changing the clock cycle, a method of switching the frequency division ratio of a PLL (Phase Locked Loop) circuit is generally known. In this method, the influence on the timing due to the voltage drop is measured, the frequency division ratio of the PLL circuit is changed based on the measured value, and the adaptive frequency control is realized by lowering the oscillation frequency of the PLL circuit.

  In the adaptive frequency control described above, since the oscillation frequency is changed using the control system of the PLL circuit, it takes a very long time until the oscillation frequency of the PLL circuit reaches the target value after switching the frequency division ratio. Specifically, for example, 200 cycles or more are required in terms of the number of cycles of the reference clock. If the voltage drop is a slow change (a change of about several tens of kHz in frequency), the change in the clock frequency can sufficiently follow the voltage drop even with the above control.

  However, for example, the IR drop that occurs when the operation rate increases in the processor is a high-speed change having a frequency band of about 50 MHz to 150 MHz as described above. Therefore, in the adaptive frequency control in which the frequency division ratio is changed in the PLL circuit, the change in the clock frequency is not in time for the voltage drop rate, and the timing error cannot be avoided.

Japanese Patent Laid-Open No. 11-288325 JP 2002-202829 A

Dong Jiao, Bongjin Kim, and Chris H. Kim, "Design, Modeling, and Test of a Programmable Adaptive Phase-Shifting PLL for Enhancing Clock Data Compensation," The Journal of Solid-state Circuits, VOL. 47, NO. 10, October 2012, pp 2505-2012 MS Floyd, et al., "Runtime power reduction capability of the IBM POWER7 + chip," IBM J. RES. & DEV. VOL. 57, NO. 6, PAPER 2, November / December 2013, pp 2: 1-2: 17

  In view of the above, an electronic circuit capable of changing the oscillation frequency at high speed following power supply noise is desired.

  The electronic circuit divides the oscillation signal by an oscillator that generates an oscillation signal having a period according to an input signal, a voltage detector that outputs a detection signal according to a power supply voltage, and a division ratio according to the detection signal. A frequency divider for generating a frequency-divided signal, a sum of a first signal corresponding to a phase difference between the frequency-divided signal and a reference signal, and a second signal corresponding to the detection signal, And an adder for supplying the signal as an input signal to the oscillator.

  According to at least one embodiment, in an electronic circuit, the oscillation frequency can be changed at high speed following power supply noise.

It is a figure which shows an example of the Example of the electronic circuit which can change an oscillation frequency following a power supply noise. FIG. 2 is a diagram showing an example of the operation of the PLL circuit shown in FIG. 1 in response to a sudden change in power supply voltage VDD. FIG. 2 is a diagram illustrating an example of the operation of the PLL circuit illustrated in FIG. 1 with respect to continuous fluctuations in a power supply voltage VDD. FIG. 2 is a diagram for explaining the operation of the PLL circuit shown in FIG. 1 with respect to continuous fluctuation of a power supply voltage VDD. FIG. 2 is a diagram for explaining the operation of the PLL circuit shown in FIG. 1 with respect to continuous fluctuation of a power supply voltage VDD. It is a figure which shows an example of the Example of the electronic circuit which can change an oscillation frequency following a power supply noise based on a circuit delay measurement. It is a figure which shows the modification of the electronic circuit shown in FIG. It is a figure which shows an example of a structure of a delay monitor circuit. It is a figure which shows an example of a structure of a variable delay line. It is a figure which shows the code conversion part which performs the code conversion for a variable delay line. It is a figure which shows an example of a structure of a mask circuit. It is a flowchart which shows an example of the setting operation | movement by a control circuit. It is a figure which shows another example of the Example of the electronic circuit which can follow a power supply noise and can change an oscillation frequency based on a circuit delay measurement. It is a figure which shows the modification of the electronic circuit shown in FIG. It is a figure which shows an example of a structure of a critical path monitor & delay monitor circuit. It is a figure which shows an example of a structure of a pseudo critical path circuit. It is a figure which shows another example of a structure of a pseudo critical path circuit. It is a figure which shows another example of a structure of a pseudo critical path circuit. It is a figure which shows another example of a structure of a pseudo critical path circuit. It is a flowchart which shows an example of the setting operation | movement by a control circuit. It is a timing diagram which shows an example of the setting operation | movement by a control circuit.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a diagram showing an example of an embodiment of an electronic circuit capable of changing the oscillation frequency following power supply noise. The electronic circuit shown in FIG. 1 includes a PLL circuit 10, an AD converter 11, an averaging unit 12, a code conversion unit 13, and a logic circuit 14. The PLL circuit 10 includes a digitally controlled oscillator (DCO) 20, a frequency divider 21, a phase comparator 22, a loop filter 23, a normalizing unit 24, and an adder 25. The logic circuit 14 includes a data path 30, and the data path 30 includes flip-flops 31 and 32 and a circuit element group 33. An oscillation signal (clock signal) generated by the PLL circuit 10 is applied to clock input terminals of the flip-flops 31 and 32.

  In FIG. 1, the boundary between each circuit or functional block shown in each box and another circuit or functional block basically indicates a functional boundary. It does not necessarily correspond to signal separation, control logic separation, and the like. Each circuit or functional block may be one hardware module physically separated to some extent from another block, or one function in a hardware module physically integrated with another block May be shown.

  The power supply voltage VDD is supplied to the logic circuit 14, and each circuit element in the logic circuit 14 is driven using the power supply voltage VDD as a power supply. The power supply voltage VDD is further applied to the AD converter 11. The AD converter 11 functions as a voltage detector and generates a detection signal Q corresponding to the applied power supply voltage. The detection signal Q may be, for example, a digital code represented by a plurality of bits in which each bit takes a value of 0 or 1. The detection signal Q output from the AD converter 11 is supplied to the averaging unit 12 and is also supplied to the adder 25 of the PLL circuit 10.

The averaging unit 12 takes a time average of the detection signal Q and generates an average value signal Q _avr . When the detection signal Q is a digital code, an average value signal Q _avr is generated by adding the value of the detection signal Q over a predetermined number of clock cycles of 2 or more and dividing the addition result by the predetermined number. It's okay. The average value signal Q _avr generated by the averaging unit 12 is supplied to the code conversion unit 13.

The code conversion unit 13 generates a frequency division ratio setting code corresponding to the average value signal _Qavr . The frequency division ratio setting code generated by the code converter 13 is supplied to the frequency divider 21 of the PLL circuit 10 as a control signal for setting the frequency division ratio.

  The digitally controlled oscillator 20 of the PLL circuit 10 generates an oscillation signal having a period (or frequency) corresponding to an input signal to the digitally controlled oscillator 20. The oscillation signal oscillated by the digitally controlled oscillator 20 is supplied to the frequency divider 21, and the frequency divider 21 oscillates at a frequency dividing rate corresponding to the frequency dividing rate setting code (that is, a frequency dividing rate corresponding to the detection signal Q). The signal is divided to generate a divided signal.

  The phase comparator 22 generates a phase detection signal corresponding to the phase difference between the frequency-divided signal output from the frequency divider 21 and the reference signal REF. When the phase of the divided signal is later than the phase of the reference signal REF, the phase detection signal becomes, for example, a negative value (or a value smaller than a predetermined reference value), and when the phase of the divided signal is earlier than the phase of the reference signal REF. For example, a positive value (or a value larger than a predetermined reference value) may be used. Further, the magnitude of the phase detection signal (or the magnitude of the difference from a predetermined reference value) may correspond to the difference between the phase of the divided signal and the phase of the reference signal REF. The phase detection signal may be, for example, a digital code represented by a plurality of bits in which each bit takes a value of 0 or 1.

  The loop filter 23 is a low-pass filter that passes the low-frequency component of the phase detection signal output from the phase comparator 22 and blocks or suppresses the high-frequency component, and may be realized by a digital filter, for example. The loop filter 23 performs low-pass filter processing on the phase detection signal, thereby generating phase difference information indicating a tendency of the phase difference over a certain period of time without being affected by temporary fine fluctuations. Information is supplied to the normalization unit 24. The phase difference information may be, for example, a digital code represented by a plurality of bits in which each bit takes a value of 0 or 1.

  The normalization unit 24 multiplies the supplied phase difference information by a predetermined coefficient to generate a phase difference code having an appropriate value as an input signal of the digitally controlled oscillator 20. In the digitally controlled oscillator 20, the magnitude (sensitivity) of the change in the oscillation frequency with respect to 1 bit change in the LSB (Least Significant Bit) of the input signal varies depending on the oscillation frequency. The normalization unit 24 multiplies the phase difference information by a coefficient that cancels the sensitivity difference according to the oscillation frequency of the digitally controlled oscillator 20, thereby eliminating the frequency-dependent influence of the sensitivity of the digitally controlled oscillator 20. it can. When the influence of the frequency dependence of the sensitivity of the digitally controlled oscillator 20 can be ignored, the normalizing unit 24 may not be provided. The phase difference code generated by the normalization unit 24 is supplied to the adder 25. The phase difference code may be, for example, a digital code expressed by a plurality of bits in which each bit takes a value of 0 or 1.

  The adder 25 obtains the sum of the phase difference code, which is a signal corresponding to the phase difference between the frequency-divided signal and the reference signal REF, and a signal corresponding to the detection signal Q, which is the output of the AD converter 11, and calculates the sum. Is supplied as an input signal to the digitally controlled oscillator 20. The signal added to the phase difference code by the adder 25 may be the detection signal Q itself that is the output of the AD converter 11, or the detection signal Q is set to an appropriate size as an input to the digital control oscillator 20. It may be a signal normalized by a constant multiplication.

  Alternatively, for example, if the design is such that the value of the detection signal Q increases in response to a decrease in the power supply voltage VDD, the detection signal Q below the predetermined value is rounded down to be equal to the detection signal Q above the predetermined value. You may use the signal adjusted so that a value may become the said predetermined value. By using the signal adjusted in this way, for example, when the power supply voltage VDD becomes larger than a desired value, a control operation that does not execute the frequency adjustment operation by the PLL circuit 10 can be realized. That is, the frequency adjustment may be performed for a decrease in the power supply voltage VDD from a desired level, but the frequency adjustment may not be performed for a rise in the power supply voltage VDD above a desired level.

  In the example illustrated in FIG. 1, the signal added by the adder 25 and the phase difference code that is the output of the normalization unit 24 is the detection signal Q that is the output of the AD converter 11. However, for example, by providing a lower limit value for the output of the AD converter 11 as described above, frequency adjustment is performed for a decrease in the power supply voltage VDD from a desired level as described above. The frequency adjustment may not be performed for the increase of the power supply voltage VDD.

  The input signal of the digitally controlled oscillator 20 may be, for example, a digital code expressed by a plurality of bits each having a value of 0 or 1. The digitally controlled oscillator 20 may be an LC oscillator, for example. A plurality of variable capacitance elements such as varactors may be connected in parallel to form a parallel capacitance, and a corresponding bit of the input signal may be applied to each of the control terminals of the plurality of variable capacitance elements. The magnitude of the parallel capacitance may be controlled by setting each bit of the input signal to 0 or 1, and the digitally controlled oscillator 20 may oscillate with a period (or frequency) corresponding to the controlled parallel capacitance.

  An oscillation signal oscillated by the digitally controlled oscillator 20 of the PLL circuit 10 is supplied to the logic circuit 14 as a clock signal. As described above, the logic circuit 14 is driven by the power supply voltage VDD. The clock signal is applied to the clock terminal of the flip-flop in the logic circuit 14.

  In the electronic circuit shown in FIG. 1, when the value of the input signal of the digitally controlled oscillator 20 increases, the length of the period of the oscillation signal of the digitally controlled oscillator 20 may increase. Conversely, when the value of the input signal of the digitally controlled oscillator 20 decreases, the length of the period of the oscillation signal of the digitally controlled oscillator 20 may decrease. In this case, when the power supply voltage VDD decreases, the value of the detection signal Q that is the output of the AD converter 11 may increase. If the relationship between the increase / decrease in the value of the input signal of the digitally controlled oscillator 20 and the increase / decrease in the period length of the oscillation signal of the digitally controlled oscillator 20 is opposite to the above, AD is responded to the decrease in the power supply voltage VDD. The value of the detection signal Q that is the output of the converter 11 may be small.

When the value of the detection signal Q increases in response to the decrease in the power supply voltage VDD and this state continues for a certain period of time, the value of the average value signal Q _avr that is the output of the averaging unit 12 also increases. The code conversion unit 13 changes the frequency division ratio setting code so that the frequency division ratio decreases as the value of the average value signal Q _avr increases. As a result, the oscillation frequency of the PLL circuit 10 is lowered and the oscillation cycle of the oscillation signal is lengthened. As described above, when the power supply voltage VDD is decreased as judged by the average over a long time, the value of the average value signal Q _avr that is the output of the averaging unit 12 becomes large, and the clock signal that the PLL circuit 10 oscillates. The period of becomes longer.

  In the logic circuit 14 driven by the power supply voltage VDD, when the power supply voltage VDD decreases, the driving power for changing the output signal of each circuit element decreases, and the signal propagation speed between circuit elements, and hence the signal propagation speed between flip-flops. Decreases. For example, in the logic circuit 14 shown in FIG. 1, it is assumed that, for example, the data path 30 among the data paths included in the logic circuit 14 is a critical path with a small timing margin. In the data path 30, the data output from the flip-flop 31 propagates through the circuit element group 33 and is taken into the flip-flop 32. Data fetching by the flip-flop 32 is performed in synchronization with a clock signal (oscillation signal) generated by the PLL circuit 10. If the time required for signal propagation between the flip-flops 31 and 32 in the data path 30 increases due to the drop in the power supply voltage VDD, there is a possibility that data reception in the flip-flop 32 on the receiving side may fail.

  As described above, when the power supply voltage VDD is reduced as judged by an average over a long time, the frequency of the clock signal oscillated by the PLL circuit 10 is lengthened by setting the division ratio to be small. Thereby, data transfer failure can be avoided in the data path such as the data path 30 included in the logic circuit 14.

  When the logic circuit 14 operates in synchronization with the clock signal of the PLL circuit 10, current is consumed at the clock transition timing, and an IR drop may occur in the power supply voltage VDD. Although a significant IR drop does not occur during the operation of the normal logic circuit 14, the IR drop that occurs when the logic circuit 14 is, for example, a processor and a transition occurs in its operation mode, has a size that cannot be ignored. Become. In this case, as described above, the power supply voltage VDD having a frequency band of about 50 MHz to 150 MHz is suddenly changed.

  When such a sudden fluctuation of the power supply voltage VDD occurs, the period of the clock signal oscillated by the digitally controlled oscillator 20 can be obtained simply by changing the frequency dividing ratio of the frequency divider 21 by the code converter 13 as described above. It doesn't change fast enough. In the first place, the instantaneous fluctuation of the power supply voltage VDD is ignored by the averaging operation by the averaging section 12, but the averaging section 12 is not provided, and the frequency of the frequency divider 21 is changed according to the instantaneous fluctuation of the power supply voltage VDD. Even if the division ratio is changed, the cycle of the clock signal does not change at a sufficient speed. This is because, as described above, when the oscillation frequency is changed using the control system of the PLL circuit, it takes a long time until the oscillation frequency of the PLL circuit reaches the target value after switching the division ratio. It is.

  In the electronic circuit shown in FIG. 1, the detection signal Q, which is an output signal of the AD converter 11, is added to the input signal to the digitally controlled oscillator 20 via the adder 25. On the other hand, the oscillation frequency of the PLL circuit 10 can be instantaneously changed. That is, in the PLL circuit 10, the digital code corresponding to the detection signal Q is added to the digital code input to the digitally controlled oscillator 20, so that if the value of the detection signal Q increases due to a decrease in the power supply voltage VDD, The input value to the controlled oscillator 20 increases. The digitally controlled oscillator 20 is designed to oscillate at an oscillation period corresponding to an input value, and the length of the oscillation period increases as the input value increases. Since the control of the oscillation period is realized by directly adjusting the input of the digitally controlled oscillator 20, the oscillation period rapidly changes in response to the fluctuation of the power supply voltage VDD. That is, it is possible to realize a change in the oscillation cycle that follows the fluctuation of the power supply voltage VDD.

  FIG. 2 is a diagram showing an example of the operation of the PLL circuit shown in FIG. 1 in response to a sudden change in the power supply voltage VDD. In FIG. 2, (a) shows the voltage value of the power supply voltage VDD. (B) shows the oscillation period of the PLL circuit 10. (C) shows the average value of the oscillation period of the PLL circuit 10. (D) shows the timing margin of the data path 30 which is a critical path of the logic circuit 14. The horizontal axis in each waveform diagram is time. The voltage V1 is a desired voltage level of the power supply voltage VDD supplied to the electronic circuit shown in FIG. The oscillation period T1 is a desired oscillation period of the PLL circuit 10 corresponding to the power supply voltage VDD.

  First, as shown in FIG. 2A, a fluctuation indicated by a waveform 41 occurs in the power supply voltage VDD due to, for example, an IR drop. This voltage fluctuation is a high-speed change having a frequency band of about 50 MHz to 150 MHz. The power supply voltage VDD decreases from the desired voltage V1 due to the IR drop, and then the voltage is recovered by the current supply through the stabilization capacitor and the power supply wiring, and the voltage overshoot occurs due to the current supply at the time of recovery. The voltage VDD is temporarily higher than the desired voltage V1.

  In response to the voltage drop of the waveform 41, the digital code input to the digitally controlled oscillator 20 increases, and the oscillation period of the digitally controlled oscillator 20 changes as shown by the waveform 42 in FIG. The average value of the oscillation period considering the averaging or integration function of the PLL control loop (phase-locked loop) by the loop filter 23 changes as shown as a waveform 43 in FIG.

  The contribution of the fluctuation of the power supply voltage VDD in the timing margin of the data path 30 changes in the same manner as the waveform 41 of the fluctuation of the power supply voltage VDD shown in FIG. Further, the contribution of the adjustment of the clock cycle to the timing margin of the data path 30 changes in the same manner as the waveform 42 of the clock cycle change shown in FIG. Accordingly, the timing margin in which the fluctuation of the power supply voltage VDD is offset by the adjustment of the clock cycle is the sum of the waveform 41 in FIG. 2A and the waveform 42 in FIG. For example, the waveform 44 shown in FIG. As shown in the waveform 44 of FIG. 2D, a state where the timing margin is equal to or higher than the level where the timing margin is zero (that is, a state where a certain timing margin exists) is maintained. Can work.

  FIG. 3 is a diagram showing an example of the operation of the PLL circuit shown in FIG. 1 with respect to the continuous fluctuation of the power supply voltage VDD. In FIG. 3, (a) shows the voltage value of the power supply voltage VDD. (B) is an oscillation cycle which is a target of the control loop of the PLL, and shows an oscillation cycle corresponding to the frequency division ratio set in the frequency divider 21. (C) shows the oscillation period of the PLL circuit 10. (D) shows the average value of the oscillation period of the PLL circuit 10. (E) shows the timing margin of the data path 30 which is a critical path of the logic circuit 14. The horizontal axis in each waveform diagram is time. The voltage V1 is a desired voltage level of the power supply voltage VDD supplied to the electronic circuit shown in FIG. The oscillation period C1 is a target oscillation period of the PLL circuit 10 corresponding to the power supply voltage VDD. The oscillation period T1 is a desired oscillation period of the PLL circuit 10 corresponding to the power supply voltage VDD.

  In the example shown in FIG. 3A, the periodic fluctuation indicated by the waveform 51 occurs in the power supply voltage VDD due to the IR drop. This voltage fluctuation is a high-speed change having a frequency band of about 50 MHz to 150 MHz. For example, when the operation mode of an LSI such as a processor periodically changes from the standby mode to the operation mode, the power supply voltage VDD varies as shown in FIG. In the waveform 51 of FIG. 3A, the waveform on the upper side of the desired voltage V1 and the waveform on the lower side of the voltage V1 are shown to have substantially the same amplitude. However, in practice, the waveform 51 is formed by the decrease in the power supply voltage VDD due to IR drop and the subsequent increase in the power supply voltage VDD due to overshoot, so the waveform on the upper side of the voltage V1 is higher than the waveform on the lower side of the voltage V1. Also has a small amplitude.

  In the waveform 51 of the power supply voltage VDD shown in FIG. 3A, the state in which the power supply voltage VDD is lower than the desired voltage V1 on average continues, so that the target oscillation period of the PLL control loop, that is, The length of the oscillation period corresponding to the frequency division ratio set in the frequency divider 21 increases. Therefore, as shown by the waveform 52 in FIG. 3B, the oscillation cycle that is the target of the PLL control loop increases.

  In addition, the digital code input to the digitally controlled oscillator 20 increases in response to the voltage drop of the waveform 41 shown in FIG. 3A, and the oscillation period of the digitally controlled oscillator 20 is shown as a waveform 53 in FIG. It changes as shown. Further, the average value of the oscillation period considering the averaging or integration function of the PLL control loop (phase-locked loop) by the loop filter 23 changes as shown as a waveform 54 in FIG.

  Further, the timing margin in which the fluctuation of the power supply voltage VDD is offset by the adjustment of the clock cycle is the sum of the waveform 51 in FIG. 3A and the waveform 53 in FIG. For example, the waveform 55 shown in FIG. As shown by the waveform 55 in FIG. 3E, a state of a level exceeding the level at which the timing margin is zero (that is, a state where a certain timing margin exists) is maintained, and the logic circuit 14 can appropriately operate without a timing error. Can work.

  In the operation examples shown in FIGS. 3A to 3E, the average value of the oscillation period (FIG. 3D) considering the averaging or integration function of the PLL control loop by the loop filter 23 is the PLL control loop. Is substantially the same as the target oscillation period (FIG. 3B). This is because the average value of the oscillation period by the addition of the detection signal Q to the input of the digitally controlled oscillator 20 is rather than the average value of the oscillation period following the target oscillation period due to the operation of the control loop of the PLL. The increase is a result of coincidence with the increase of the target oscillation period. As a result of the increase in the average value of the oscillation period due to the addition of the detection signal Q coincident with the increase in the target oscillation period, a stable state (phase-locked state) of the PLL control loop is realized, and the waveform 52 in FIG. And the waveform 54 in FIG. 3D are kept in agreement.

  FIG. 4 is a diagram for explaining the operation of the PLL circuit shown in FIG. 1 with respect to continuous fluctuation of the power supply voltage VDD. Each waveform shown in FIG. 4 is generated when the addition operation of the adder 25 that adds the detection signal Q of the AD converter 11 to the input signal of the digitally controlled oscillator 20 is stopped in the PLL circuit shown in FIG. It shows how the PLL circuit operates in response to continuous fluctuations in the voltage VDD. The signals shown in FIGS. 4 (a) to 4 (e) are the same as the signals shown in FIGS. 3 (a) to 3 (e).

  In the waveform 61 of the power supply voltage VDD shown in FIG. 4A, the state in which the power supply voltage VDD is averagely lower than the desired voltage V1 continues, so that the target oscillation period of the PLL control loop, that is, The length of the oscillation period corresponding to the frequency division ratio set in the frequency divider 21 increases. Therefore, as shown by the waveform 62 in FIG. 4B, the target oscillation period of the PLL control loop increases.

  As the target oscillation period of the control loop of the PLL increases as shown in FIG. 4B, the oscillation period of the digitally controlled oscillator 20 changes as shown as a waveform 63 in FIG. Further, the average value of the oscillation period in consideration of the averaging or integration function by the loop filter 23 of the PLL control loop (phase-locked loop) changes as shown by a waveform 64 in FIG.

  In this example of operation, the average value of the oscillation period (FIG. 4D) considering the averaging or integration function of the PLL control loop by the loop filter 23 is the target oscillation period of the PLL control loop (FIG. 4B). ) Is gradually increased so as to follow the increase. This is because the oscillation period is changed by the operation of the PLL control loop so that the average value of the oscillation period follows the target oscillation period. As described above, in the operation example shown in FIGS. 4A to 4E, the addition operation of the adder 25 that adds the detection signal Q of the AD converter 11 to the input signal of the digitally controlled oscillator 20 is stopped. This is an example of how the PLL circuit operates in this case. Unlike the oscillation cycle shown in FIG. 3C, the oscillation cycle of the PLL circuit 10 shown in FIG. 4C does not show a high-speed change in response to a sudden change in power supply voltage.

  The timing margin in which the fluctuation of the power supply voltage VDD is offset by the adjustment of the clock cycle is the sum of the waveform 61 in FIG. 4A and the waveform 63 in FIG. It becomes like a waveform 65 shown in FIG. As shown in the waveform 65 of FIG. 4E, for a while after the power supply voltage VDD starts to fluctuate, the oscillation period cannot respond to the fluctuation of the power supply voltage VDD at a high speed, and the timing margin is large. A state of lowering to zero or less occurs. For this reason, the logic circuit 14 of the electronic circuit shown in FIG. 1 may not be able to operate properly due to a timing error. Thereafter, when the oscillation cycle of the PLL circuit 10 is gradually increased by the control operation by the PLL control loop, the timing margin is gradually increased, and the state where the timing margin is zero or higher is maintained.

  As shown in FIGS. 4A to 4E, if the frequency division ratio of the frequency divider 21 is changed only in accordance with the detection signal Q that is the output of the AD converter 11, the power supply voltage VDD is rapidly changed. If there is, the oscillation cycle cannot be changed at high speed according to the fluctuation. As a result, there is no timing margin and a timing error occurs in the data path of the logic circuit 14. Therefore, as in the PLL circuit 10 shown in FIG. 1, the detection signal Q of the AD converter 11 is added to the input signal of the digitally controlled oscillator 20 by the adder 25 in addition to the operation for controlling the frequency division ratio. It is preferable to directly change the oscillation cycle of the digitally controlled oscillator 20.

  FIG. 5 is a diagram for explaining the operation of the PLL circuit shown in FIG. 1 with respect to continuous fluctuation of the power supply voltage VDD. Each waveform shown in FIG. 5 indicates the continuation of the power supply voltage VDD when the operation of adjusting the frequency division ratio of the frequency divider 21 according to the detection signal Q of the AD converter 11 is stopped in the PLL circuit shown in FIG. It shows how the PLL circuit operates in response to typical fluctuations. The signals shown in FIGS. 5 (a) to 5 (e) are the same as the signals shown in FIGS. 3 (a) to 3 (e).

  In the waveform 71 of the power supply voltage VDD shown in FIG. 5A, the state where the power supply voltage VDD is lower than the desired voltage V1 on average continues. However, in the operations shown in FIGS. 5A to 5E, since it is assumed that the operation of adjusting the target oscillation period of the PLL control loop is stopped, the waveform 72 in FIG. As shown, the target oscillation period of the PLL control loop maintains the same value C1.

  Further, in response to the voltage drop of the waveform 71 shown in FIG. 5A, the digital code input to the digitally controlled oscillator 20 is increased by the adding operation of the adder 25, and the oscillation cycle of the digitally controlled oscillator 20 is as shown in FIG. It changes as shown as a waveform 73 in FIG. Furthermore, the average value of the oscillation period considering the averaging or integration function of the PLL control loop (phase-locked loop) by the loop filter 23 changes as shown by a waveform 74 in FIG.

  In this example of operation, the oscillation period increases in response to the power supply fluctuation at high speed as shown by the waveform 73 in FIG. 5C. Therefore, the oscillation in consideration of the averaging or integration function by the loop filter 23 of the PLL control loop. The average value of the period (FIG. 5 (d)) also first shows an increase. However, after that, as shown as a waveform 74 in FIG. 5 (d), the average of the oscillation period so as to approach the period T1 corresponding to the constant value C1 of the target oscillation period (FIG. 5 (b)) of the PLL control loop. The value is gradually decreasing. This is because the oscillation period is changed by the operation of the PLL control loop so that the average value of the oscillation period approaches the target oscillation period.

  The timing margin in which the fluctuation of the power supply voltage VDD is offset by the adjustment of the clock cycle is the sum of the waveform 71 of FIG. 5A and the waveform 73 of FIG. The waveform 75 shown in FIG. As indicated by the waveform 75 in FIG. 5E, for a while after the power supply voltage VDD starts to fluctuate, the oscillation period responds quickly to the fluctuation of the power supply voltage VDD, so the timing margin is zero. The state above the level is maintained. However, if the oscillation period of the PLL circuit 10 is gradually reduced by the control operation by the PLL control loop thereafter, the timing margin is also gradually reduced, and a state below the level where the timing margin is zero occurs. Therefore, the logic circuit 14 of the electronic circuit shown in FIG. 1 may not be able to operate properly due to a timing error.

  As shown in FIGS. 5A to 5E, the target oscillation is obtained simply by adding the signal from the outside of the PLL loop to the input signal of the digitally controlled oscillator 20 and directly changing the oscillation period of the digitally controlled oscillator 20. The period and the average oscillation period are different. As a result, when the fluctuation of the power supply voltage VDD as shown in FIG. 5 (a) occurs, when a long time of a certain time has elapsed since the occurrence of the fluctuation, a timing error may occur due to a decrease in the oscillation period due to the operation of the PLL control loop. May occur. Therefore, as in the PLL circuit 10 shown in FIG. 1, in addition to the operation of directly adding the signal from the outside of the PLL loop to the input signal of the digitally controlled oscillator 20 to directly change the oscillation period of the digitally controlled oscillator 20, It is preferable to execute an operation for controlling the division ratio.

  As described so far, in the electronic circuit shown in FIG. 1, when the value of the digital code of the detection signal Q that is the output of the AD converter 11 increases due to the decrease in the power supply voltage VDD, the oscillation of the digitally controlled oscillator 20 The length of the cycle increases. At this time, it is assumed that the digital code of the detection signal Q, which is the output of the AD converter 11, increases by 1 LSB with respect to the decrease in ΔV of the power supply voltage VDD, and the length of the oscillation period increases by ΔTo. Further, it is assumed that the signal propagation time in the data path 30 of the logic circuit 14 increases by ΔTp due to the decrease in ΔV of the power supply voltage VDD. In this case, it is preferable that the increase ΔTo of the oscillation period in response to the increase of 1 LSB of the detection signal Q is greater than or equal to the increase ΔTp of the signal propagation time of the data path 30. Further, in order to achieve the fastest operation speed while avoiding the timing error, it is preferable that the increase ΔTo of the oscillation period in response to the increase of 1 LSB of the detection signal Q is equal to the increase ΔTp of the signal propagation time of the data path 30. . Therefore, it is preferable to adjust the change of the oscillation period of the digitally controlled oscillator 20 with respect to the 1LSB change of the input digital code (that is, the sensitivity of the oscillation period control) so as to satisfy these conditions.

  In the configuration shown in FIG. 1, the AD converter 11 that functions as a voltage detector outputs a detection signal Q. However, as a voltage detector that generates the detection signal Q, an analog power supply voltage is converted into a digital detection signal Q. It is not limited to the one based on the AD conversion function for converting to. The voltage detector may measure a circuit delay caused by a voltage change of the power supply voltage and output a measurement value indicating the circuit delay as the detection signal Q.

  FIG. 6 is a diagram showing an example of an embodiment of an electronic circuit that can change the oscillation frequency following power supply noise by using a voltage detector that generates a detection signal Q based on circuit delay measurement. In FIG. 6, the same or corresponding elements as those of FIG. 1 are referred to by the same or corresponding numerals, and a description thereof will be omitted as appropriate.

  The electronic circuit shown in FIG. 6 includes a control circuit 80, a delay monitor circuit (DDM) 81, a mask circuit (MASK) 82, and a PLL circuit 83 instead of the AD converter 11 shown in FIG. The control circuit 80, the delay monitor circuit 81, and the mask circuit 82 correspond to a voltage detector.

  The control circuit 80 is a circuit that controls the delay monitor circuit 81 and the mask circuit 82. The control circuit 80 supplies a first control signal C and a second control signal R each having k bits (k is an integer of 2 or more) to the delay monitor circuit 81 and 2n bits (n is an integer of 1 or more). Is supplied to the mask circuit 82. The delay monitor circuit 81 measures a circuit delay difference between two variable delay lines whose delay times are set by the first and second control signals C and R, respectively, based on the clock signal, and the measurement result is obtained. Output as circuit delay measurement value. These two variable delay lines are driven by the power supply voltage VDD and the reference voltage VREF, respectively, and a change in the circuit delay difference between the two variable delay lines indicates a change in the power supply voltage VDD. The mask circuit 82 masks the 2n-bit circuit delay measurement value output from the delay monitor circuit 81 for each bit based on the mask signal M, and outputs the 2n-bit post-masking circuit delay measurement value. The circuit delay measurement value after masking is supplied as a detection signal Q to the PLL circuit 10 and the averaging unit 12.

  The clock signal used by the delay monitor circuit 81 may be supplied from the PLL circuit 83 to the clock input terminal CK of the delay monitor circuit 81. Hereinafter, this clock signal is referred to as a clock signal CK. The delay monitor circuit 81 measures a circuit delay based on a time difference when one clock pulse passes through the two variable delay lines. At this time, only one clock pulse is used to measure the circuit delay once out of a series of a plurality of clock pulses in the clock signal CK. If the circuit delay is measured only once, a single pulse is used. A signal may be supplied to the delay monitor circuit 81. By continuously supplying a plurality of clock pulses to the delay monitor circuit 81, a plurality of circuit delay measurements are continuously performed. Therefore, the circuit delay measurement value itself does not depend on the frequency of the clock signal CK, and the frequency of the clock signal CK may be appropriately set as defining a sampling cycle for measuring the circuit delay.

  FIG. 7 is a modification of the electronic circuit shown in FIG. In the electronic circuit shown in FIG. 7, the clock signal CK used by the delay monitor circuit 81 is supplied from the PLL circuit 10. That is, the clock signal generated by the digitally controlled oscillator 20 of the PLL circuit 10 and supplied to the logic circuit 14 is also applied to the clock input terminal CK of the delay monitor circuit 81. As described above, the circuit delay measurement value output from the delay monitor circuit 81 does not depend on the frequency of the clock signal applied to the clock input terminal CK. Therefore, even when the oscillation frequency of the PLL circuit 10 whose frequency is changed as a control target is applied to the clock input terminal CK, the circuit delay measurement result by the delay monitor circuit 81 changes with the control of the PLL circuit 10. There is no. That is, the delay monitor circuit 81 can detect only the change in the power supply voltage VDD without being affected by the change in the oscillation frequency of the PLL circuit 10. By adopting the configuration of the electronic circuit of FIG. 7, the number of PLL circuits can be reduced as compared with the configuration of the electronic circuit of FIG.

  FIG. 8 is a diagram illustrating an example of the configuration of the delay monitor circuit 81. The delay monitor circuit 81 shown in FIG. 8 includes a first variable delay line 90, a second variable delay line 91, and a time difference measuring circuit 92.

  The first variable delay line 90 is supplied with the power supply voltage VDD and outputs a first delayed oscillation signal obtained by delaying the clock signal CK based on the first control signal C. The second variable delay line 91 is applied with the reference voltage VREF and outputs a second delayed oscillation signal obtained by delaying the clock signal CK based on the second control signal R.

  The time difference measurement circuit 92 includes a plurality of delay circuits 101, a plurality of delay circuits 102, n first flip-flops 103, and n second flip-flops 104. In the first flip-flop 103, the second delayed oscillation signal output from the second variable delay line 91 is supplied to each clock terminal. In addition, the first delayed oscillation signals output from the first variable delay line 90 respectively delayed by the first predetermined delay by the delay circuit 101 from the data input of the first flip-flop 103 in the previous stage are respectively Input to the data input terminal.

  In the second flip-flop 104, the first delayed oscillation signal output from the first variable delay line 90 is input to each data input terminal. Further, the second delayed oscillation signal output from the second variable delay line 91, which is delayed by the second predetermined delay by the delay circuit 102 from the clock input of the second flip-flop 104 in the previous stage, is provided for each clock terminal. To be supplied. Note that each delay time of the delay circuit 101 and each delay time of the delay circuit 102 may be equal. That is, the first predetermined delay and the second predetermined delay may be equal.

  The 2n-bit circuit delay measurement value Q [2n-1: 0] output from the time difference measuring circuit 92 is the n second output data of the n second flip-flops 104, and the n second output bits. The n-bit output data of the flip-flop 104 is the lower n bits. When the delay times of the first variable delay line 90 and the second variable delay line 91 are equal, the circuit delay measurement value Q [2n-1: 0] is all 0's in the upper n bits and the lower n bits are All become 1. The circuit delay measurement value Q [2n−1: 0] having this value is expressed as {n′b00... 00, n′b11. For example, when n is 4, the circuit delay measurement value Q [7: 0] is “00001111”.

  When the circuit delay of the first variable delay line 90 is longer than the circuit delay of the second variable delay line 91, the first delayed oscillation signal output from the first variable delay line 90 is the second variable delay. This is later than the second delayed oscillation signal transmitted from the line 91. In this case, among the n second flip-flops 104, for example, the second flip-flop 104 located on the leftmost side of the drawing has the first delayed oscillation signal before the first delayed oscillation signal becomes HIGH. As a data input. As a result, some of the n-bit output data of the n second flip-flops 104 is 0 instead of 1. When the circuit delay difference between the first variable delay line 90 and the second variable delay line 91 corresponds to, for example, between 3 and 4 of the predetermined delay, the circuit in the case of n = 4 The delay measurement value Q [7: 0] is “00000001”. In addition, when the circuit delay difference between the first variable delay line 90 and the second variable delay line 91 corresponds to, for example, two and three of the predetermined delay, n = 4 The circuit delay measurement value Q [7: 0] is “00000011”.

  When the circuit delay of the first variable delay line 90 is shorter than the circuit delay of the second variable delay line 91, the first delayed oscillation signal output from the first variable delay line 90 is the second variable delay. This is earlier than the second delayed oscillation signal transmitted from the line 91. In this case, among the n first flip-flops 103, for example, the second flip-flop 104 located on the leftmost side of the drawing has the first delayed oscillation signal after the first delayed oscillation signal becomes HIGH. As a data input. As a result, some of the n-bit output data of the n first flip-flops 103 is 1 instead of 0. When the circuit delay difference between the first variable delay line 90 and the second variable delay line 91 corresponds to, for example, between 3 and 4 of the predetermined delay, the circuit in the case of n = 4 The delay measurement value Q [7: 0] is “01111111”. In addition, when the circuit delay difference between the first variable delay line 90 and the second variable delay line 91 corresponds to, for example, two and three of the predetermined delay, n = 4 The measured circuit delay value Q [7: 0] is “00111111”.

  In the circuit configuration shown in FIG. 8, the output of the first variable delay line 90 is applied to the data input terminals of the flip-flops 103 and 104, and the output of the second variable delay line 91 is the clock terminal of the flip-flops 103 and 104. To be applied. Conversely, the output of the first variable delay line 90 is applied to the clock terminals of the flip-flops 103 and 104, and the output of the second variable delay line 91 is applied to the data input terminals of the flip-flops 103 and 104. Good. In this case, the increase / decrease in the circuit delay measurement value Q [2n-1: 0] corresponding to the change in the circuit delay difference between the first variable delay line 90 and the second variable delay line 91 is opposite to the above. Taking this into consideration, the control operation based on the measured circuit delay value Q may be appropriately designed.

  In this way, the delay monitor circuit 81 obtains the circuit delay measurement value Q [2n−1: 0], which is a thermometer code indicating the circuit delay difference between the first variable delay line 90 and the second variable delay line 91. Output. The first variable delay line 90 is driven by the power supply voltage VDD, and the second variable delay line 91 is driven by the reference voltage VREF. Here, the reference voltage VREF is a power supply voltage supplied from the outside separately from the power supply voltage VDD, and is not used in other circuit parts of the electronic circuit shown in FIG. 6 or FIG. It is a voltage that is maintained at a constant voltage with no fluctuation. Therefore, the circuit delay measurement value Q [2n-1: 0] indicating the circuit delay difference between the first variable delay line 90 and the second variable delay line 91 uniquely reflects the value of the power supply voltage VDD. It becomes. When the power supply voltage VDD decreases, the circuit delay of the first variable delay line 90 becomes longer. When the power supply voltage VDD increases, the circuit delay of the first variable delay line 90 becomes shorter. Therefore, when the power supply voltage VDD decreases, the number of bits of the value 0 in the circuit delay measurement value Q [2n-1: 0] increases, and when the power supply voltage VDD increases, the circuit delay measurement value Q [2n-1: 0. ], The number of bits of value 1 increases.

  Even if it is desired to manufacture a circuit so that the circuit delay of the first variable delay line 90 and the circuit delay of the second variable delay line 91 have the same length, the circuit length should be the same due to the effects of process variations and wiring variations. It is difficult. Therefore, it is desirable to set the circuit delay of the first variable delay line 90 and the circuit delay of the second variable delay line 91 to be the same length by the initialization work executed in advance. This initial setting operation will be described later.

FIG. 9 is a diagram illustrating an example of the configuration of the variable delay line. Each of the first variable delay line 90 and the second variable delay line 91 shown in FIG. 8 may include the circuit configuration of the variable delay line shown in FIG. The variable delay line shown in FIG. 9 includes a plurality of inverters 111, ^k switch circuits 112, and a plurality of capacitive elements 113. Inverters 111 are cascaded to form a delay line. Switch control codes T [0] to T [2 ^k −1] are applied to each of the 2 ^k switch circuits 112. Each of the switch circuits 112 is turned on (conducted) when the corresponding bit value of the applied switch control code is 1, and the capacitive element 113 connected in series to the switch circuit 112 is connected to the output of the inverter 111. Is done. Each of the switch circuits 112 is further turned off (cut off) when the corresponding bit value of the applied switch control code is 0, and the capacitive element 113 connected in series to the switch circuit 112 is connected to the output of the inverter 111. To be separated.

As the number of bits of the value 1 of the switch control codes T [0] to T [2 ^k −1] is larger, the number of capacitive elements 113 connected to the delay line shown in FIG. 9 is increased, and the delay time is increased. Further, as the number of bits of the value 0 of the switch control codes T [0] to T [2 ^k −1] is increased, the number of capacitive elements 113 connected to the delay line shown in FIG. 9 is reduced and the delay time is shortened. .

FIG. 10 is a diagram illustrating a code conversion unit that performs code conversion for the variable delay line. Each of the first variable delay line 90 and the second variable delay line 91 shown in FIG. 8 may include a code conversion unit shown in FIG. The code conversion unit 115 illustrated in FIG. 10 is supplied with the k-bit first control signal C [k−1: 0] corresponding to the first variable delay line 90, for example. The code conversion unit 115 is a 2 ^k- bit thermostat whose number is equal to one of 0 to 2 ^k −1 indicated by the first control signal C [k−1: 0]. Generate meter code. That is, for example, when the first control signal C [3: 0] is “1011” and indicates the decimal value 11, the outputs T [0] to T [15] of the code converter 115 are 11 out of all 16 bits. The thermometer code “111111111100000” whose value is 1 in each bit is obtained. For the second variable delay line 91, a similar code conversion unit may similarly convert the second control signal R [k-1: 0] into a 2 ^k- bit thermometer code.

  FIG. 11 is a diagram showing an example of the configuration of the mask circuit 82 shown in FIG. 6 or FIG. The mask circuit 82 shown in FIG. 6 or FIG. 7 receives the 2n−1 bit circuit delay measurement value Q [2n−1: 0] from the delay monitor circuit 81 at the A input and receives 2n−1 bit from the control circuit 80. Is received at the B input. In FIG. 11, 2n-1 bit signals received at the A input are shown as A [0] to A [2n-1], and 2n-1 bit signals received at the B input are B [0] to B [2n- 1].

  The mask circuit shown in FIG. 11 includes 2n−1 OR circuits 120. Outputs X [0] to X [2n-1] of 2n-1 OR circuits 120 are output from the mask circuit as circuit delay measurement values after masking of 2n-1 bits. Each OR circuit 120 performs an OR operation on the corresponding 1 bit of A [0] to A [2n-1] and the corresponding 1 bit of B [0] to B [2n-1]. The result of the OR operation is output as a corresponding 1 bit among X [0] to X [2n-1]. In this way, the bit corresponding to the value 1 bit of the 2n-1 bit mask signal M in the 2n-1 bit circuit delay measurement value Q [2n-1: 0] is masked, and the circuit after masking is performed. Delay measurement is output.

  FIG. 12 is a flowchart illustrating an example of the setting operation by the control circuit. The electronic circuit shown in FIG. 6 or 7 executes the initial setting procedure shown in the flowchart of FIG. 12 before the execution of the routine process intended by the electronic circuit is started. For example, when the electronic circuit is a communication circuit, the initial setting procedure shown in the flowchart of FIG. 12 is executed before the execution of communication processing by the electronic circuit is started. After the initialization is performed, the electronic circuit executes a routine process, and adaptive frequency control for controlling the oscillation frequency of the PLL circuit 10 according to the change of the power supply voltage VDD is executed.

  In step S1, the reference voltage VREF and the power supply voltage VDD are set to the same voltage, and all bits of the mask signal M are set to 1 by the control circuit 80. As for the voltage setting, for example, the control circuit 80 may execute the above voltage setting by transmitting a voltage setting command to an external voltage source. Here, the same set voltage for setting the reference voltage VREF and the power supply voltage VDD is a voltage lower than a rated voltage at which the power supply voltage VDD is set when the electronic circuit executes a routine process, and is a trigger for adaptive frequency control. It may be a voltage. That is, when the power supply voltage VDD decreases from the rated voltage and reaches a predetermined voltage during execution of the routine processing, an operation for lowering the oscillation frequency of the PLL circuit 10 by adaptive frequency control is to be started (trigger is desired). In this case, the set voltage may be equal to the predetermined voltage. Further, since all bits of the mask signal M are set to 1, all bits of the output of the mask circuit 82 are fixed to the value 1, and all bits of the detection signal Q supplied to the PLL circuit 10 and the averaging unit 12 are changed. The value is fixed to 1. Thereby, the adaptive frequency control for controlling the oscillation frequency of the PLL circuit 10 is stopped.

In step S2, the control circuit 80 sets each of the first control signal C and the second control signal R to 2 ^k−1 −1. Thereby, each of the first variable delay line 90 and the second variable delay line 91 of the delay monitor circuit 81 is set to an intermediate delay length between the maximum delay length and the minimum delay length. In step S <b> 3, the control circuit 80 acquires the circuit delay measurement value Q output from the delay monitor circuit 81.

  In step S4, the control circuit 80 determines whether or not the circuit delay measurement value Q acquired in step S3 is smaller than {n′b00... 00, n′b11. That is, it is determined whether or not the circuit delay of the first variable delay line 90 is larger than the circuit delay of the second variable delay line 91. If the determination result is Yes, the processing procedure proceeds to step S5, and if the determination result is No, the processing procedure proceeds to step S7.

  In step S5, the control circuit 80 increases the second control signal R by 1 when the first control signal C is 0, and the first control signal when the first control signal C is not 0. Decrease C by 1. That is, the control circuit 80 first changes the control signal so as to shorten the circuit delay of the first variable delay line 90, and after the circuit delay of the first variable delay line 90 becomes the shortest, the second variable variable The control signal is changed so as to increase the circuit delay of the delay line 91. In step S 6, the control circuit 80 outputs the changed first and second control signals C and R to the delay monitor circuit 81. Thereafter, the processing procedure returns to step S3 and the subsequent processing is repeated.

  In step S7, the control circuit 80 determines whether or not the circuit delay measurement value Q acquired in step S3 is larger than {n′b00... 00, n′b11. That is, it is determined whether or not the circuit delay of the first variable delay line 90 is smaller than the circuit delay of the second variable delay line 91. If the determination result is Yes, the processing procedure proceeds to step S8, and if the determination result is No, the processing procedure proceeds to step S9.

In step S8, the control circuit 80, when the first control signal C is 2 ^k -1 reduces the second control signal R by one, when the first control signal C is not a 2 ^k -1 Increases the first control signal C by one. That is, the control circuit 80 first changes the control signal so as to increase the circuit delay of the first variable delay line 90, and after the circuit delay of the first variable delay line 90 has become the shortest, the second variable variable. The control signal is changed so as to shorten the circuit delay of the delay line 91. Thereafter, in step S 6, the control circuit 80 outputs the changed first and second control signals C and R to the delay monitor circuit 81. Thereafter, the processing procedure returns to step S3 and the subsequent processing is repeated.

  When the processing procedure reaches step S9, the circuit delay measurement value Q is equal to {n′b00... 00, n′b11. That is, the circuit delay of the first variable delay line 90 and the circuit delay of the second variable delay line 91 are equal. In this state, in step S9, the power supply voltage VDD is set to the rated voltage. As for the voltage setting, for example, the control circuit 80 may execute the above voltage setting by transmitting a voltage setting command to an external voltage source.

  In step S10, the control circuit 80 outputs a mask signal M in which all bits are not 1, and starts adaptive frequency control. Here, the value of the mask signal M is a value obtained by shifting {n′b11... 11, n′b00.

  Here, TH is a threshold value set in order to provide a time margin in anticipation of the time taken for the oscillation frequency of the PLL circuit 10 to actually change by adaptive frequency control. If no time margin is considered, TH may be equal to zero. That is, the value of the mask signal M may be equal to {n′b11... 11, n′b00. According to the initial setting operation of FIG. 12 described above, when the power supply voltage VDD is equal to the reference voltage VREF (= trigger voltage), the first variable delay line 90 and the second variable delay line 91 have the same circuit delay. At this time, the circuit delay measurement value Q is equal to {n′b00... 00, n′b11. Therefore, when the power supply voltage VDD set to the rated voltage (> trigger voltage) drops to the reference voltage VREF (= trigger voltage), the measured circuit delay value Q is {n′b00... 00, n′b11 · ..11}. When the value of the mask signal M is {n′b11... 11, n′b00... 00}, the circuit delay measurement value Q is {n′b00... 00, n′b11. When it becomes smaller, the detection signal Q output from the mask circuit 82 changes for the first time. In the electronic circuit shown in FIG. 6 or FIG. 7, when the value of the input signal of the digital control oscillator 20 decreases, the period length of the oscillation signal of the digital control oscillator 20 may increase. Conversely, when the value of the input signal of the digital control oscillator 20 increases, the length of the period of the oscillation signal of the digital control oscillator 20 may decrease. Since the frequency adjustment operation by the PLL circuit 10 is executed according to the change in the value of the detection signal Q generated as described above, when the power supply voltage VDD set to the rated voltage falls below the reference voltage VREF, The frequency adjustment operation by the PLL circuit 10 is started.

  However, it usually takes a certain amount of time for the clock frequency to reach an appropriate frequency after the frequency adjustment operation by the PLL circuit 10 is started. If it takes time for the clock frequency to reach an appropriate frequency, a data transfer error may occur in the critical path of the logic circuit 14. Therefore, in practice, it is preferable to provide a time allowance in consideration of the time required for control. Considering the above, the mask signal M is shifted to the left by TH bits so that the number of upper bits to be masked is reduced and the value of the detection signal Q is changed earlier. If the control delay is Dc [nsec], the slope of the voltage drop is Sn [mV / nsec], and the change of the power supply voltage VDD corresponding to the change of 1LSB of the output of the delay monitor circuit 81 is h [mV], TH is The following equation should be satisfied.

Dc < (h / Sn) · TH
Therefore, TH is a positive integer that satisfies the following expression.

TH > (Dc · Sn) / h
The threshold TH is stored in the memory of the electronic circuit, and may be supplied from the memory to the control circuit 80.

  FIG. 13 is a diagram showing another example of an embodiment of an electronic circuit capable of changing the oscillation frequency following power supply noise based on circuit delay measurement. In FIG. 13, the same or corresponding elements as those in FIG. 6 are referred to by the same or corresponding numerals, and a description thereof will be omitted as appropriate.

  In the electronic circuit shown in FIG. 13, a control circuit 80A is provided instead of the control circuit 80 shown in FIG. 6, and a critical path monitor & delay monitor circuit (CPM / DDM) 81A is used instead of the delay monitor circuit 81 shown in FIG. Is provided. The control circuit 80A includes a register QM and a state machine FSM. The register QM stores the circuit delay measurement value Q of the pseudo critical path circuit measured by the critical path monitor & delay monitor circuit 81A. The state machine FSM controls the operation performed by the control circuit 80A. The critical path monitor & delay monitor circuit 81A is a circuit having both a function of monitoring a pseudo critical path and a function of monitoring a circuit delay, and is hereinafter simply referred to as a delay monitor circuit 81A. The control circuit 80A, the delay monitor circuit 81A, and the mask circuit 82 correspond to a voltage detector.

  The delay monitor circuit 81A measures the circuit delay difference between the variable delay line whose delay time is set by the control signal R and the pseudo critical path based on the clock signal CK, and outputs the measurement result as a circuit delay measurement value. To do. The pseudo critical path and the variable delay line are driven by the power supply voltage VDD and the reference voltage VREF, respectively, and a change in the circuit delay difference between the pseudo critical path and the variable delay line indicates a change in the power supply voltage VDD. The configuration and operation of the delay monitor circuit 81A will be described later. In the delay monitor circuit 81A, as in the case of the delay monitor circuit 81, the circuit delay measurement value itself does not depend on the frequency of the clock signal CK.

  FIG. 14 is a diagram showing a modification of the electronic circuit shown in FIG. In the electronic circuit shown in FIG. 14, the clock signal CK used by the delay monitor circuit 81 </ b> A is supplied from the PLL circuit 10. As described above, the circuit delay measurement value output from the delay monitor circuit 81A does not depend on the frequency of the clock signal applied to the clock input terminal CK. Therefore, even when the oscillation frequency of the PLL circuit 10 whose frequency is changed as a control target is applied to the clock input terminal CK, the circuit delay measurement result by the delay monitor circuit 81A changes with the control of the PLL circuit 10. There is no. That is, the delay monitor circuit 81A can detect only the change in the power supply voltage VDD without being affected by the change in the oscillation frequency of the PLL circuit 10. With the configuration of the electronic circuit in FIG. 14, the number of PLL circuits can be reduced as compared with the configuration of the electronic circuit in FIG.

  FIG. 15 is a diagram illustrating an example of the configuration of the delay monitor circuit 81A. The delay monitor circuit 81A shown in FIG. 15 includes a pseudo critical path circuit 131, a delay control circuit 132, and a time difference measurement circuit 92. The delay control circuit 132 includes a variable delay line 141 and a selection circuit 142.

  The pseudo critical path circuit 131 is supplied with the power supply voltage VDD and outputs a first delayed oscillation signal obtained by delaying the clock signal CK. The variable delay line 141 is applied with the reference voltage VREF and outputs a second delayed oscillation signal obtained by delaying the clock signal CK based on the control signal R. The selection circuit 142 selects and outputs a third delayed oscillation signal that is either the clock signal CK or the second delayed oscillation signal based on the input selection signal S.

  In the first flip-flop 103 included in the time difference measurement circuit 92, the third delayed oscillation signal output from the selection circuit 142 is supplied to each first input terminal (clock terminal in this example). Also, the first output which is the output of the pseudo critical path circuit 131 delayed from the second input terminal (data input terminal in this example) of the first flip-flop 103 in the previous stage by the delay circuit 101 by a first predetermined delay. Delayed oscillation signals are input to the respective second input terminals.

  In the second flip-flop 104, the first delayed oscillation signal output from the pseudo critical path circuit 131 is input to each second input terminal (in this example, the data input terminal). The third delay oscillation output from the selection circuit 142 is delayed from the first input terminal (in this example, the clock input terminal) of the second flip-flop 104 in the previous stage by the delay circuit 102 by a second predetermined delay. A signal is supplied to each first input terminal. Note that each delay time of the delay circuit 101 and each delay time of the delay circuit 102 may be equal. That is, the first predetermined delay and the second predetermined delay may be equal.

  In the routine processing for activating adaptive frequency control, the selection circuit 142 selects and outputs the output of the variable delay line 141. In this state, when the delay times of the pseudo critical path circuit 131 and the variable delay line 141 are equal, the circuit delay measurement value Q [2n-1: 0] is all 0 in the upper n bits and all the lower n bits. 1 That is, the circuit delay measurement value Q [2n−1: 0] is {n′b00... 00, n′b11.

  When the circuit delay of the pseudo critical path circuit 131 is longer than the circuit delay of the variable delay line 141, some of the n-bit output data of the n second flip-flops 104 is not 1 but 0. become. That is, the circuit delay measurement value Q [2n−1: 0] is smaller than {n′b00... 00, n′b11.

  When the circuit delay of the pseudo critical path circuit 131 is shorter than the circuit delay of the variable delay line 141, some of the n-bit output data of the n first flip-flops 103 is 1 instead of 0. become. That is, the circuit delay measurement value Q [2n−1: 0] is larger than {n′b00... 00, n′b11.

  In this way, the delay monitor circuit 81A outputs a circuit delay measurement value Q [2n-1: 0] which is a thermometer code indicating a circuit delay difference between the pseudo critical path circuit 131 and the variable delay line 141. The pseudo critical path circuit 131 is driven by the power supply voltage VDD, and the variable delay line 141 is driven by the reference voltage VREF. Here, the reference voltage VREF is a power supply voltage supplied from the outside separately from the power supply voltage VDD, and is not used in other circuit parts of the electronic circuit shown in FIG. 6 or FIG. It is a voltage that is maintained at a constant voltage with no fluctuation.

  The variable delay line 141 is designed so as to have a delay time equivalent to one clock cycle of the operation clock signal at the time of routine processing of the electronic circuit so as to have a delay time length equivalent to the critical path in the logic circuit 14. The pseudo critical path circuit 131 is designed. If designed in this way, if the circuit delay of the pseudo critical path circuit 131 is shorter than one clock cycle, the circuit delay measurement value Q is {n′b00... 00, n′b11. It is a state larger than. On the other hand, when the circuit delay of the pseudo critical path circuit 131 becomes longer than one clock cycle, the circuit delay measurement value Q becomes smaller than {n′b00... 00, n′b11. Therefore, if the value of the mask signal M is set to {n′b11... 11, n′b00... 00}, when the circuit delay of the pseudo critical path circuit 131 becomes longer than one clock cycle, The detection signal Q output from the mask circuit 82 changes (decreases) for the first time. In response to this change, the frequency adjustment operation of the PLL circuit 10 is executed. In practice, it is preferable to provide a time margin in anticipation of the time required for control. Therefore, by shifting the mask signal M to the left by TH bits, the number of upper bits to be masked is reduced, so that the value of the detection signal Q changes earlier.

  Even if it is desired to manufacture a circuit so that the circuit delay of the variable delay line 141 is equal to one clock cycle, it is difficult to realize a circuit delay equal to one clock cycle due to the influence of process variations and wiring variations. Therefore, it is desirable to set the circuit delay of the variable delay line 141 to be equal to one clock cycle by the initialization work executed in advance. This initial setting operation will be described later.

  FIG. 16 is a diagram illustrating an example of the configuration of the pseudo critical path circuit. The pseudo critical path circuit shown in FIG. 16 realizes a desired delay time by connecting a plurality of even-numbered inverters 151 in cascade. In this circuit configuration, a pseudo critical path circuit in which the gate delay is dominant can be realized by a relatively simple circuit.

  FIG. 17 is a diagram illustrating another example of the configuration of the pseudo critical path circuit. The pseudo critical path circuit shown in FIG. 17 includes an inverter 152, a plurality of NOR circuits 153, a plurality of AND circuits 154, and a plurality of NAND circuits 155. Here, the logic circuit formed by one NOR circuit 153 and two AND circuits 154 is a composite logic circuit of 2AND-2OR inverter output. These logic gates are appropriately combined and cascaded to achieve a desired delay time. In this circuit configuration, a pseudo-critical path circuit in which the gate delay is dominant is realized by combining various logic gates as in the case of the actual critical path, and a circuit delay that exhibits behavior closer to that of the actual critical path is realized. can do.

  FIG. 18 is a diagram illustrating another example of the configuration of the pseudo critical path circuit. The pseudo critical path circuit shown in FIG. 18 realizes a desired delay time by alternately cascading a plurality of even number of inverters 156 and a plurality of resistance elements 157. In this circuit configuration, a pseudo critical path circuit in which wiring delay is dominant can be realized by a relatively simple circuit.

  FIG. 19 is a diagram illustrating another example of the configuration of the pseudo critical path circuit. The pseudo critical path circuit shown in FIG. 19 includes an inverter 158, a plurality of NOR circuits 159, a plurality of AND circuits 160, a NAND circuit 161, and a plurality of resistance elements 162. Here, the logic circuit formed by one NOR circuit 159 and two AND circuits 160 is a composite logic circuit of 2AND-2OR inverter output. These logic gates and resistance elements are appropriately combined and cascaded to realize a desired delay time. In this circuit configuration, a pseudo-critical path circuit in which wiring delay is dominant is realized by combining various logic gates in the same way as an actual critical path, and a circuit delay that exhibits behavior closer to that of the actual critical path is realized. can do.

  FIG. 20 is a flowchart illustrating an example of the setting operation by the control circuit. The electronic circuit shown in FIG. 13 or FIG. 14 executes the initial setting procedure shown in the flowchart of FIG. For example, when the electronic circuit is a communication circuit, the initial setting procedure shown in the flowchart of FIG. 12 is executed before the execution of communication processing by the electronic circuit is started. After the initialization is performed, the electronic circuit executes a routine process, and adaptive frequency control for controlling the oscillation frequency of the PLL circuit 10 according to the change of the power supply voltage VDD is executed.

  In step S21, all bits of the mask signal M are set to 1 by the control circuit 80A, and the selection signal S and the control signal R are set to 0. By setting all bits of the mask signal M to 1, all bits of the output of the mask circuit 82 are fixed to the value 1, and all bits of the detection signal Q supplied to the PLL circuit 10 and the averaging unit 12 are values. 1 is fixed. Thereby, the adaptive frequency control for controlling the oscillation frequency of the PLL circuit 10 is stopped.

  In step S22, the control circuit 80A acquires the circuit delay measurement value Q output from the delay monitor circuit 81A. At this time, since the selection signal S is 0, the selection circuit 142 shown in FIG. 15 selects and outputs the clock signal CK that is directly input without passing through the variable delay line 141. Therefore, the circuit delay measurement value Q output from the delay monitor circuit 81A is a value indicating the time difference between the clock signal CK without delay and the clock signal CK delayed by the pseudo critical path circuit 131, and the circuit of the pseudo critical path circuit 131. A value representing the delay itself. When the delay time length of the pseudo critical path circuit 131 is set to be substantially equal to the delay time length of the critical path of the logic circuit 14, the clock signal CK is an operation at the time of executing the routine processing of the electronic circuit. The frequency is preferably the same as that of the clock signal. The delay time length of the pseudo critical path circuit 131 is normally designed to be slightly shorter than one clock cycle of the clock signal. The circuit delay measurement value Q is a time difference between a pulse in which a pulse of the clock signal CK is delayed by the pseudo critical path circuit 131 and a pulse in which the next pulse of the clock signal CK is output from the selection circuit 142 as it is. Is the measured value. When the delay time length of the pseudo critical path circuit 131 is set to, for example, N times the delay time length of the critical path of the logic circuit 14, the clock signal CK is an operation clock when the routine processing of the electronic circuit is executed. The frequency is preferably N times that of the signal.

  In step S23, the control circuit 80A stores the circuit delay measurement value Q in the register QM. In step S24, the control circuit 80A sets the selection signal S to 1 and sets the control signal R to 0. Since the control signal R is 0, the variable delay line 141 of the delay monitor circuit 81A is in the state with the shortest delay time.

  In step S25, the control circuit 80A acquires the circuit delay measurement value Q output from the delay monitor circuit 81A. At this time, since the selection signal 1 is 0, the selection circuit 142 shown in FIG. 15 selects and outputs the clock signal CK delayed by the variable delay line 141. Therefore, the circuit delay measurement value Q output from the delay monitor circuit 81A is a value indicating the time difference between the clock signal CK delayed by the variable delay line 141 and the clock signal CK delayed by the pseudo critical path circuit 131. That is, the circuit delay measurement value Q is a time difference between a pulse in which a pulse of the clock signal CK is delayed by the pseudo critical path circuit 131 and a pulse in which the pulse of the clock signal CK is delayed by the variable delay line 141. Is the measured value.

  In step S26, the control circuit 80A determines whether or not the circuit delay measurement value Q acquired in step S3 is smaller than the circuit delay measurement value Q (that is, the circuit delay measurement value acquired in step S22) that is the stored value of the register QM. Determine. If the determination result is Yes, the processing procedure proceeds to step S27, and if the determination result is No, the processing procedure proceeds to step S28.

  In step S27, the control circuit 80A increases the control signal R by 1, and outputs the increased control signal R to the delay monitor circuit 81A. That is, the control circuit 80A increases the delay time length of the variable delay line 141 of the delay monitor circuit 81A by the minimum change amount. Thereafter, the processing procedure returns to step S25 and the subsequent processing is repeated.

  When the processing procedure reaches step S28, the circuit delay measurement value Q corresponding to the current control signal R is equal to the circuit delay measurement value Q that is the stored value of the register QM. That is, the time difference between the clock pulse delayed by the pseudo critical path circuit 131 and the clock pulse of the next cycle without delay is equal to the difference between the delay time of the pseudo critical path circuit 131 and the delay time of the variable delay line 141. It has become. This means that the delay time length of the variable delay line 141 in this state is equal to one clock cycle of the clock signal CK. In this state, in step S28, the control circuit 80A determines the control signal R and outputs the determined control signal R to the delay monitor circuit 81A.

  In step S29, the control circuit 80A outputs a mask signal M in which all bits are not 1, and starts adaptive frequency control. Here, the value of the mask signal M is a value obtained by shifting {n′b11... 11, n′b00.

  As described above, the variable delay line 141 can be set to have a delay time length equal to one clock cycle of the operation clock signal during the routine processing of the electronic circuit by the initial setting operation shown in FIG. With this setting, when the circuit delay of the pseudo critical path circuit 131 becomes longer than one clock cycle, the circuit delay measurement value Q becomes smaller than {n′b00... 00, n′b11. Therefore, if the value of the mask signal M is set to {n′b11... 11, n′b00... 00}, when the circuit delay of the pseudo critical path circuit 131 becomes longer than one clock cycle, The detection signal Q output from the mask circuit 82 changes (decreases) for the first time. However, in anticipation of the time required for control, the mask signal M is shifted to the left by TH bits, so that the number of upper bits to be masked is reduced and the value of the detection signal Q is changed earlier.

  In the case where the electronic circuit shown in FIG. 6 or FIG. 7 is initialized by the initialization operation shown in FIG. 12, the operation for changing the power supply voltage VDD is executed. On the other hand, when the initial setting is performed on the electronic circuit shown in FIG. 13 or 14 by the initialization operation shown in FIG. 20, the operation of changing the power supply voltage is not included. These initialization operations are usually executed at the time of the startup operation immediately after the electronic circuit is turned on. However, there are cases where it is desired to avoid the operation of changing the power supply voltage as described above at the startup operation. In the electronic circuit shown in FIG. 13 or FIG. 14, it is not necessary to change the power supply voltage during the initialization operation.

  FIG. 21 is a timing chart showing an example of the setting operation by the control circuit. For example, for n = 4, FIG. 21 shows an example of changes in signal values when the initial setting operation shown in FIG. 20 is executed. In this example, TH = 2 is fixed. In the initial state, by executing step S21 shown in FIG. 20, the selection signal S is set to 0, all bits of the mask signal M are set to the value 1, and the control signal R is set to 0. Yes.

  At the timing T1 shown in FIG. 21, the operations of steps S22 and S23 shown in FIG. 20 are executed, and the circuit delay measurement value Q output from the delay monitor circuit 81A in the state where the selection signal S = 0 is stored in the register QM. The In this example, the circuit delay measurement value Q stored in the register QM is 8b'0111_1111. That is, the circuit delay measurement value Q is 8-bit data, and its value is “01111111”.

  Thereafter, at timing T2, the operations of steps S24 and S25 shown in FIG. 20 are executed. As a result, the circuit delay measurement value Q indicating the time difference between the clock signal CK delayed by the variable delay line 141 and the clock signal CK delayed by the pseudo critical path circuit 131 in the state of the selection signal S = 1 is obtained. In this example, the circuit delay measurement value Q obtained first is 8b′0000 — 0111, which is smaller than the stored value 8b′0111 — 1111 of the register QM. Therefore, the control signal R is increased by the operation of step S27 shown in FIG. As the control signal R increases sequentially, the circuit delay measurement value Q output from the delay monitor circuit 81A also gradually increases.

  Thereafter, in response to the circuit delay measurement value Q being equal to the value stored in the register QM, the operation of step S28 shown in FIG. 28 is executed at the timing T3, and the value of the control signal R is determined to be 15. . Further, at timing T4, a value 8b'1100_0000 obtained by shifting 8b'1111_0000 to the left by TH bits (that is, 2 bits) is output as a mask signal M, and adaptive frequency control is started.

  As mentioned above, although this invention was demonstrated based on the Example, this invention is not limited to the said Example, A various deformation | transformation is possible within the range as described in a claim.

10 PLL circuit 11 AD converter 12 Averaging unit 13 Code conversion unit 14 Logic circuit 20 Digitally controlled oscillator (DCO)
21 Frequency Divider 22 Phase Comparator 23 Loop Filter 24 Normalization Unit 25 Adder 30 Data Path 31, 32 Flip-Flop 33 Circuit Element Group

Claims (12)

An oscillator that generates an oscillation signal having a period according to an input signal;
A voltage detector that outputs a detection signal according to the power supply voltage;
A frequency divider that generates a divided signal by dividing the oscillation signal by a division ratio according to the detection signal;
A sum of a first signal corresponding to the phase difference between the divided signal and the reference signal and a second signal corresponding to the detection signal is obtained, and a signal corresponding to the sum is supplied to the oscillator as the input signal. An electronic circuit including an adder.   2. The electronic circuit according to claim 1, wherein the detection signal and the input signal are digital codes expressed by a plurality of bits, and the oscillator is a digitally controlled oscillator.   The electronic circuit according to claim 1, wherein the frequency divider divides the oscillation signal by a frequency division ratio according to a signal obtained by averaging the detection signals with time.   The electronic circuit according to claim 1, further comprising a logic circuit driven by the power supply voltage, wherein the oscillation signal is applied to a clock input terminal of a flip-flop in the logic circuit. The voltage detector is
A first variable delay line that outputs a first delayed oscillation signal obtained by applying a first voltage and delaying the oscillation signal based on a first control signal, and a second voltage being applied A second variable delay line that outputs a second delayed oscillation signal obtained by delaying the oscillation signal based on a second control signal; the second delayed oscillation signal is supplied to each clock terminal; N first flip-flops that receive the first delayed oscillation signals delayed from the data inputs of the first flip-flops by a first predetermined delay, respectively, and the second flip-flops in the previous stage. Second delayed oscillation signals delayed by a second predetermined delay from the respective clock inputs are supplied to the respective clock terminals, and the first delayed oscillation signals are respectively supplied. A delay monitor circuit comprising n number of the second flip-flop input to the data input,
A mask circuit that outputs 2n post-mask output signals obtained by masking 2n output signals output from the delay monitor circuit based on 2n mask signals input as the detection signals;
5. The electronic circuit according to claim 1, further comprising a control circuit that outputs the first control signal and the second control signal based on the detection signal and outputs the 2n mask signals. 6. . The voltage detector is
A pseudo critical path circuit that outputs a first delayed oscillation signal obtained by applying the power supply voltage and delaying the oscillation signal, and a reference voltage is applied and the oscillation signal is delayed based on a control signal. A variable delay line that outputs two delayed oscillation signals, and a selection unit that selects and outputs a third delayed oscillation signal that is either the oscillation signal or the second delayed oscillation signal based on an input selection signal And the third delayed oscillation signal is supplied to each first input terminal, and a first delayed oscillation signal delayed by a first predetermined delay from the second input terminal of the first flip-flop in the previous stage is provided. Each of the n first flip-flops input to the second input terminal and the first input terminal of the second flip-flop in the previous stage are respectively delayed by a second predetermined delay. A delay monitor circuit delays the oscillation signal of 3 and an n-number of the second flip-flop in which the first delay oscillation signal is input to the second input terminal respectively is supplied to the first input terminal, respectively,
A mask circuit that outputs 2n post-mask output signals obtained by masking 2n output signals output from the delay monitor circuit based on 2n mask signals input as the detection signals;
5. The electronic circuit according to claim 1, further comprising a control circuit that outputs the control signal based on the detection signal and outputs the 2n mask signals. 6.   The electronic circuit according to claim 6, wherein the pseudo critical path circuit has a delay corresponding to a maximum operating frequency of the electronic circuit. An oscillation signal having a period corresponding to an input signal to the oscillator is generated by the oscillator,
Generates a detection signal according to the power supply voltage,
Performing a frequency-divided signal generation process for generating a frequency-divided signal by dividing the oscillation signal by a frequency-dividing ratio according to the detection signal;
A sum of a first signal corresponding to the phase difference between the divided signal and the reference signal and a second signal corresponding to the detection signal is obtained, and a signal corresponding to the sum is supplied to the oscillator as the input signal. Execute input signal supply processing
An oscillator control method including each stage. A first drive voltage applied to the first variable delay line and a second drive voltage applied to the second variable delay line are set to an equal voltage;
The circuit delay difference between the circuit delay of the first variable delay line and the circuit delay of the second variable delay line is zero when the first drive voltage and the second drive voltage are equal. Execute the process to adjust to
The method further includes the steps of applying the power supply voltage to the first variable delay line after performing the adjusting process, wherein the first variable delay line is driven by the power supply voltage and the second variable delay line is 9. The oscillator according to claim 8, wherein a signal corresponding to the circuit delay difference is generated as the detection signal while being driven by the second drive voltage, and the divided signal generation process and the input signal supply process are executed. Control method. Applying the power supply voltage and a predetermined drive voltage to the pseudo critical path circuit and the variable delay line,
Executing a process of adjusting the delay time length of the variable delay line to a length equal to one cycle of the clock signal;
The method further includes measuring each circuit delay difference between the circuit delay of the pseudo critical path circuit and the circuit delay of the variable delay line after executing the adjustment process, and a signal corresponding to the circuit delay difference is used as the detection signal. 9. The method of controlling an oscillator according to claim 8, wherein the frequency division signal generation process and the input signal supply process are executed. The adjustment process is
Input the clock signal to the pseudo-critical path;
Measuring a time difference between a first pulse of the clock signal delayed by the pseudo-critical path and a second pulse immediately after the first pulse of the clock signal;
11. The oscillator according to claim 10, further comprising: adjusting a delay time length of the variable delay line so that a circuit delay difference between the circuit delay of the pseudo critical path and the circuit delay of the variable delay line is equal to the time difference. Control method.   12. The method of controlling an oscillator according to claim 10, wherein the clock signal is the oscillation signal.

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