JP5928128B2 - Simulation method for digital circuit - Google Patents

Description

  The present invention relates to a digital circuit simulation method, and more particularly to instruction expansion of a simulation CPU.

  In developing digital circuits, hardware / software co-verification is performed for the purpose of verifying and solving problems that can be predicted before making a prototype. As a collaborative verification method, a method such as a non-patent document is known.

  FIG. 6 shows an outline of a simulation apparatus for performing cooperative verification, and includes virtual hardware (virtual HW) having functions 1 to 5 and an execution object 6. Reference numeral 1 denotes a logic circuit under test (ASIC) such as a custom LSI created by a user, ROM model 2 and RAM model 3 are memory models for software operation, and 4 is a CPU model equivalent to a real machine that is a software execution part. It has a function as shown in. The CPU model 4 is constructed in a hardware language so as to operate on the simulator shown in FIG. These 1 to 4 are connected by a bus model 5.

The execution object 6 is an object that operates on the actual printed board.
A command generated by a computer (hereinafter referred to as CPU) instruction is output from the execution object 6 to the virtual hardware and initialized, and the embedded software in which the instruction set is described is read and the operation is executed. The CPU model 4 equivalent to the actual machine can simulate a software operation in consideration of the time axis of the actual machine by reading the execution object.

  Official number 2011-502130

  When the simulation is performed using the apparatus as shown in FIG. 6, the CPU model 4 equivalent to the actual CPU can accurately simulate the actual software. For this reason, when a virtual hardware environment using an equivalent CPU model 4 is used, it is possible to simulate a test of the entire hardware using actual machine software.

  However, actual software having the same instruction set as the actual CPU is not always effective for testing the logic circuit under test. For example, an instruction that handles immediate data is limited to the bit length of the instruction word, and in the case of immediate data having a bit width exceeding the limit, a plurality of lines of instructions are required, and readability is poor. In addition, the test of the logic circuit under test may require adjustment of the access start time from the CPU to the ROM model and the RAM model, but it is difficult to achieve with only the instruction set of the actual CPU. In some cases, a screen display is required in the test, but a display controller for display is required for the screen display, and software for controlling the display controller itself is also required.

  An object of the present invention is to provide an efficient test execution object for performing an original test.

In a method for executing a test of a logic circuit under test on a virtual hardware having a CPU model and a logic circuit under test for a digital circuit through a CPU model by a program constituted by CPU instructions,
The virtual hardware has a function capable of processing a virtual instruction group that handles immediate data having a wider bit width than the actual CPU ,
An execution instruction for virtual hardware is added to the program as an extension instruction and input to the CPU model,
The virtual hardware includes a 2-port memory and two sets of CPUs each having a logic circuit under test and connected to the 2-port memory,
The extension instruction by the program is a WAIT extension instruction for generating an execution waiting time, and the contention timing for the 2-port memory is adjusted at the time of the WAIT extension instruction .

Furthermore, the present invention is characterized in that an extended instruction for displaying a screen is added to an extended instruction by a program, and the screen is displayed on a console window of a simulator for a digital circuit.

As described above, according to the present invention, the execution instruction for the virtual hardware is an extension instruction, and the extension instruction is added to the execution instruction for the virtual hardware by the execution object. Hardware debugging can be performed with a small number of man-hours without requiring an execution object. In addition, since the immediate data extension instruction is not limited by the bit length of the instruction word, programming with good readability is possible.
In addition, since the extended instruction generates an execution waiting time, the test of the competitive operation of the two-port memory enables a test with a higher coverage than the test with the actual machine.
Furthermore, even when a test is performed while displaying the screen on the console window, the screen can be displayed without the need for software for controlling the display controller as in the past by using an extended instruction for displaying the screen. Is

The block diagram which shows embodiment of this invention. The block diagram which shows embodiment of this invention. CPU instruction → extension instruction conversion diagram. The output timing diagram of the extension command by the execution object. Digital circuit simulator diagram. The block diagram of the conventional virtual hardware. FIG. 3 is a configuration diagram of a CPU model equivalent to a conventional real machine.

FIG. 1 is a configuration diagram of virtual hardware showing an embodiment of the present invention. Execution object 10 in the present invention, in addition to the function of the execution object 6 shown in FIG. 6, a function to supply the extended instruction. Further, the CPU model 20 is not operated by a CPU command by an execution object as in the prior art, but is configured as a CPU model that operates based on an extended command that generates an execution waiting time.

  The CPU model used on the virtual hardware must be compatible with the actual CPU and software, and the CPU model 20 of the present invention also has compatibility with the actual CPU and software. Therefore, the CPU model 20 is equipped with a function capable of processing an extended instruction group not found in the actual CPU in addition to an instruction group that can be executed by the actual CPU. Further, unlike the actual CPU, the CPU model 20 has the initial setting contents of the CPU, so that an execution object including the initial setting contents of the CPU is not required. Thus, only software created for debugging partial hardware can be executed. This will be specifically described below with reference to the drawings.

The execution object 10 in FIG. 1 executes an execution object including an extended instruction group that is not included in the actual CPU. The objects executed by the CPU model 20 are also different from those stored in the actual ROM. The virtual CPU 20 of the present invention processes the character string of the assembler instruction word, so that the number of bits of the instruction word is not limited. For this reason, by using the immediate address method as an instruction for handling immediate data , the instruction can be expanded without restriction and contribute to programming with good readability.

  FIG. 2 is a block diagram of the virtual hardware, and is composed of a CPU model 20 comprising a two-port memory 30 and two CPUs (CPU-A, CPU-B), 20A, 20B. Although not shown in the virtual hardware CPU 20A (CPU-A) and CPU 20B (CPU-B) shown in FIG. 2, the logic circuit under test (ASIC), ROM model 2 and RAM shown in FIG. Model 3 is provided. The 2-port memory 30 has a program (execution programs 10A and 10B) having a function accessible from both the CPU-A and the CPU-B and a simulation function for executing cooperative verification.

  FIG. 3 shows a case where 0x12345678 of 32-bit immediate data is set in the execution objects 10A and 10B as an example. FIG. 3A shows an example of the CPU instruction of the execution object for the original actual machine, but the execution object 10 according to the present invention further shows the CPU instruction of FIG. Such an extended instruction can be realized in one line.

The execution object 10 stores instructions for causing CPU-A and CPU-B to generate the competition timing as shown in FIG. 4, and the CPU-A and CPU-B at the read timing are as shown in FIG. The operation based on the same program is executed. In addition, at the time of a WAIT extension instruction that generates an execution waiting time, hardware debugging is performed while adjusting the contention timing of the 2-port memory 30.
In other words, the WAIT extension instruction for generating the execution waiting time is tested while adjusting the timing of CPU-A and CPU-B with a difference in the waiting time WAIT. As a result, competing timings can be comprehensively created, so that a test with a higher coverage ratio can be performed than a test with an actual machine.

FIG. 5 shows an embodiment of the digital circuit simulator. This embodiment is an extension instruction for displaying a screen and is used for checking the progress status during debugging. In order to display the screen on the actual machine, conventionally, software for controlling the display controller included in the actual machine hardware is required. However, the display controller is controlled by using a PRINT instruction as shown in the program example of FIG. The screen can be displayed without using software, and the screen can be displayed on the console window of the digital circuit simulator. The PRINT command that displays the screen can be implemented using HDL description display commands (eg $ display, report).
The virtual hardware shown in FIG. 1 is used.

  As described above, according to the present invention, the extension instruction is added to the CPU instruction in the execution object. A simulation can be performed while adjusting the timing by setting a difference in the waiting time WAIT for virtual hardware composed of two CPUs and a two-port memory. Therefore, it is possible to debug the hardware with a small number of man-hours without requiring an execution object including the initial setting contents of the CPU as in the prior art.

In addition, since the execution object is an immediate data extension instruction that is not limited by the bit length of the instruction word, programming with good readability is possible.
In addition, since the extended instruction generates an execution waiting time, it is possible to perform a test with a higher coverage ratio than a test with an actual machine.
Furthermore, even when a test is performed while displaying the screen on the console window, the screen can be displayed without the need for software for controlling the display controller as in the past by using an extended instruction for displaying the screen. It is.

1 ... Logic circuit under test (ASIC)
2 ... ROM model 3 ... RAM model 4 ... CPU model equivalent to actual machine 5 ... Bus model 6 ... Execution object 10 (10A, 10B) ... Execution object 20 (20A, 20B) ... CPU model 30 ... 2-port memory

Claims (2)

In a method for executing a test of a logic circuit under test on a virtual hardware having a CPU model and a logic circuit under test for a digital circuit through a CPU model by a program constituted by CPU instructions,
The virtual hardware has a function capable of processing a virtual instruction group that handles immediate data having a wider bit width than the actual CPU ,
An execution instruction for virtual hardware is added to the program as an extension instruction and input to the CPU model,
The virtual hardware includes a 2-port memory and two sets of CPUs each having a logic circuit under test and connected to the 2-port memory,
The extended instruction by the program, a WAIT extension instructions to generate execution waiting time, the digital circuit simulation method characterized by adjusting the contention timing of two sets of the CPU definitive in the 2-port memory during WAIT extended instruction. 2. The digital circuit simulation method according to claim 1, wherein an extended instruction for displaying a screen is added to the extended instruction by the program, and the screen is displayed on a console window of the simulator for the digital circuit.

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