JP5919653B2 - Semiconductor device - Google Patents

Description

  The present technology relates to a semiconductor device in which two or more semiconductor members are bonded and stacked.

Conventionally, for example, when a semiconductor member is bonded to produce a three-dimensional integrated circuit or the like, a method of directly bonding Cu electrodes provided on a bonding surface of the semiconductor member may be used (for example, patents). Reference 1).
For example, Patent Document 1 below discloses that a first substrate on which a light receiving element is formed and a second substrate on which a peripheral circuit is formed are bonded by a Cu electrode (bonding pad).
In such a method, Cu electrodes and interlayer insulating films provided on the respective semiconductor members are flattened and bonded to the same surface, thereby bonding the opposing Cu electrodes and the interlayer insulating films together.

However, in the electrical connection between the semiconductor members, it is difficult to ensure that the Cu electrodes provided on the respective semiconductor members are in direct contact with each other and that the flatness of the joint surface is as high as possible.
For example, when the bonding surface of the semiconductor member is planarized by CMP (chemical mechanical polishing), it is necessary to strictly set the polishing conditions in order to suppress the occurrence of dishing on the bonding surface. Moreover, it is difficult to carry out the set conditions stably and continuously.

  Therefore, the Cu electrode and the interlayer insulating film are not completely flattened, and only the interlayer insulating film is partially removed by, for example, wet etching or dry etching, so that the Cu electrode protrudes from the interlayer insulating film. Has been proposed (see, for example, Patent Document 2 and Non-Patent Document 1).

On the other hand, in general semiconductor members that are not joined, dishing is also suppressed by providing a dummy pattern so that the wiring density is constant (see, for example, Patent Document 3 below).
Moreover, when measuring the joining strength of the semiconductor members bonded in this way, a so-called razor test as described in Non-Patent Document 2, for example, has been conventionally known.

JP 2006-191081 A JP-T-2006-522461 JP-A-11-265866 JJMcMahon, J.-Q.Lu and RJ Gutmann, IEEE 55th ECTC, 2005 [Non-Patent Document 2] WPMaszara, G. Goetz, A. Caviglia and JBMcKitterick, J. Appl. Phys. 64 (10) 1988, pp.4943 "

As described above, various methods have been proposed in order to join the semiconductor members more firmly. However, a reliable method has not yet been found, and a more reliable joining method is currently available. A semiconductor device having a surface is desired.
In view of the above points, an object of the present technology is to provide a semiconductor device in which semiconductor members are firmly bonded to each other.

In order to solve this problem, in the semiconductor device according to the present technology, the first wiring layer of one semiconductor member and the second wiring layer of the other semiconductor member are joined by a dummy electrode.
For this purpose, the first wiring layer includes a first interlayer insulating film and a first electrode pad embedded in the first interlayer insulating film and having one surface located on the same plane as the surface of the first interlayer insulating film. Including. The first wiring layer is further embedded in the first interlayer insulating film, one surface of which is located on the same plane as the surface of the first interlayer insulating film, and is disposed around the first electrode pad. A first dummy electrode is included.
The second wiring layer is embedded in the second interlayer insulating film located on the surface side of the first electrode pad of the first interlayer insulating film and the second interlayer insulating film, and one surface is the second interlayer insulating film And a second electrode pad located on the same surface as the surface on the first interlayer insulating film side and joined to the first electrode pad. The second wiring layer further has one surface located on the same plane as the surface of the second interlayer insulating film on the first interlayer insulating film side, and is disposed around the second electrode pad. A second dummy electrode joined to the electrode. Furthermore, the first dummy electrode is disposed between the first electrode pads, and the second dummy electrode is disposed between the second electrode pads. In addition, a first region in which two first electrode pads are bonded to one second electrode pad, and a second region in which two first dummy electrodes are bonded to one second dummy electrode including.

  According to the present technology, the dummy electrodes are bonded to each other by arranging the dummy electrodes on the bonding surface between the first wiring layer and the second wiring layer. For this reason, the area where metal joining is performed can be increased.

  According to the above-described present technology, the area where metal bonding is performed can be increased on the bonding surface between the first wiring layer and the second wiring layer. For this reason, it is possible to improve the joint strength between the first wiring layer and the second wiring layer.

1A, 1B, and 1C are diagrams illustrating a semiconductor device according to a first embodiment of the present technology. 2A, 2B, and 2C are diagrams illustrating a semiconductor device according to a second embodiment of the present technology. 3A and 3B are diagrams illustrating a semiconductor device according to a third embodiment of the present technology. 4A and 4B are diagrams illustrating a semiconductor device according to the fourth embodiment of the present technology. 5A and 5B are diagrams illustrating a semiconductor device according to the fifth embodiment of the present technology. It is a figure showing a semiconductor image receiving device concerning a 6th embodiment of this art. It is a figure showing electronic equipment concerning a 7th embodiment of this art. 8A, 8B, and 8C are diagrams illustrating a semiconductor device according to a comparative example.

Hereinafter, modes for carrying out the present technology (hereinafter referred to as embodiments) will be described.
The description will be given in the following order.
1. First Embodiment <Example of Disposing Dummy Electrodes around Electrode Pad>
2. Second Embodiment <Example in which electrode pads and dummy electrodes to be joined are not plane-symmetric>
3. Third Embodiment <Example in which electrode pads and dummy electrodes have the same shape, and both are arranged in the same pattern>
4). Fourth Embodiment <Example in which dummy electrodes are arranged only around electrode pads>
5. Fifth Embodiment <Example of Connecting Dummy Electrode to Ground>
6). Sixth Embodiment <Example of Semiconductor Image Receiver>
7). Seventh Embodiment <Example of Electronic Device>
8). Example

1. First Embodiment <Example of Disposing Dummy Electrodes around Electrode Pad>
FIG. 1A is a schematic cross-sectional view of the semiconductor device 100 according to the first embodiment. The semiconductor device 100 of the present embodiment includes a first semiconductor member 10 and a second semiconductor member 20 joined to the first semiconductor member 10.
Moreover, FIG. 1B is a figure which shows the joint surface of the 1st semiconductor member 10, and FIG. 1A is sectional drawing in the line L1 in FIG. 1B. 1C is a cross-sectional view taken along line L2 in FIG. 1B.

As shown in FIGS. 1A and 1C, the first semiconductor member 10 includes, for example, a substrate 1 and a first wiring layer 2 formed on the substrate 1. Although not shown, a semiconductor element such as a transistor or a diode is formed on the substrate 1. On the semiconductor element, for example, a planarizing film made of SiO ₂ , NSG (non-doped silicate glass), PSG (phosphosilicate glass), TEOS (tetraethoxysilane), or the like is provided, and a first wiring is formed on the planarizing film. Layer 2 is formed.
Further, the first semiconductor member 10 may have a multilayer wiring structure in which a plurality of wiring layers are stacked. However, in this case, the first wiring layer 2 is disposed closest to the second semiconductor member 20 among the wiring layers.

The first wiring layer 2 is provided with a first electrode pad 4 made of, for example, Cu and a dummy electrode 5 made of, for example, Cu. The first electrode pad 4 and the dummy electrode 5 are embedded in an interlayer insulating film 3 made of a low dielectric constant material such as organic silica glass or SiO ₂ .
The surfaces of the first electrode pad 4, the dummy electrode 5, and the interlayer insulating film 3 on the side opposite to the substrate 1 side are located in the same plane, and the first wiring layer 2 and a second wiring layer 9 described later. The joint surface Pj is formed.

  Each first electrode pad 4 is connected to a via 12, and each first electrode pad 4 is connected to a wiring (not shown) via the via 12. The number of connections of the first electrode pads 4 to one wiring is determined such that the total resistance value of the pads 4 and vias 12 connected to the wiring is equal to the resistance value required for the wiring. By connecting a plurality of first electrode pads 4 to one wiring, the same effect as in the case of arranging a large area pad can be obtained.

For example, the second semiconductor member 20 includes a substrate 11 and a second wiring layer 9 formed on the substrate 11. Further, a semiconductor element (not shown) such as a transistor or a diode may be formed on the substrate 11.
The second semiconductor member 20 may have a multilayer wiring structure in which a plurality of wiring layers are stacked. However, the second wiring layer 9 is located farthest from the substrate 11 (uppermost layer) among the wiring layers. Arranged.

The second wiring layer 9 includes a second electrode pad 7 made of, for example, Cu, a dummy electrode 8 made of, for example, Cu, and an interlayer insulating film 6. The second electrode pad 7 and the dummy electrode 8 are embedded in the interlayer insulating film 6. The material of the interlayer insulating film 6 may be the same as that of the interlayer insulating film 3.
The respective surfaces of the second electrode pad 7, the dummy electrode 8, and the interlayer insulating film 6 on the side opposite to the substrate 11 side are located in the same plane, and the first wiring layer 2 and the second wiring layer 9 A joint surface Pj is formed.
Each second electrode pad 7 is connected to a via 13, and each second electrode pad 7 is connected to a wiring (not shown) via the via 13.

  Further, the first electrode pad 4 and the second electrode pad 7, and the dummy electrode 5 and the dummy electrode 8 are arranged symmetrically with respect to the bonding surface Pj. In the bonding surface Pj, the first electrode pad 4, the dummy electrode 5, and the interlayer insulating film 3 are bonded to the second electrode pad 7, the dummy electrode 8, and the interlayer insulating film 6, respectively. For this bonding, various methods such as plasma bonding can be used.

  By joining the first electrode pad 4 and the second electrode pad 7, the first semiconductor member 10 and the second semiconductor member 20 are electrically connected. On the other hand, the dummy electrode 5 and the dummy electrode 8 do not electrically connect the first semiconductor member 10 and the second semiconductor member 20, but are disposed independently of the surroundings. .

  Here, as shown in FIG. 1B, the dummy electrode 5 (dummy electrode 8) is disposed between the first electrode pads 4 (second electrode pads 7). Thus, by providing the dummy electrode 5 (dummy electrode 8) and bonding the dummy electrode 5 and the dummy electrode 8, the bonding area between the metals can be increased. For this reason, it is possible to increase the bonding strength between the first semiconductor member 10 and the second semiconductor member 20.

When the dummy electrode is not disposed as in the prior art, for example, if the alignment of the first semiconductor member 10 and the second semiconductor member 20 is shifted, the bonding between the Cu electrode pad and the interlayer insulating film such as the SiO ₂ film is performed. There can also be places to be done. The bonding between Cu and SiO ₂ film is significantly weaker than the bonding between Cu. For this reason, variation in bonding strength is likely to occur within the bonding surface.

On the other hand, in the semiconductor device 100 of the present embodiment, by arranging the dummy electrode 5 (dummy electrode 8), the bonding area between the metals increases, so that a high bonding strength can be obtained even with a slight misalignment. Can be maintained.
The effect of increasing the bonding area between the metals does not depend on whether the arrangement pattern of the dummy electrodes 5 (dummy electrodes 8) is uniform, for example. Therefore, when the purpose is only to improve the bonding strength, it is not necessary to bond all the dummy electrodes, and it is only necessary to bond at least the dummy electrodes for an area where the target bonding strength can be obtained.

  Further, by arranging the dummy electrode 5 (dummy electrode 8) between the first electrode pads 4 (second electrode pads 7), the metal wiring density on the bonding surface Pj can be made uniform. For this reason, for example, when the bonding surface Pj is formed by a CMP method or the like, it is possible to suppress the occurrence of dishing or erosion of the bonding surface Pj. This effect also does not depend on the arrangement pattern of the dummy electrodes 5 (dummy electrodes 8), and the area density of the dummy electrodes 5 satisfies even a predetermined value that does not cause dishing or erosion under predetermined CMP conditions. If so, the arrangement pattern can be changed as appropriate.

  For example, the dummy electrode 5 (dummy electrode 8) may be disposed only around the first electrode pad 4 (second electrode pad 7) where dishing is likely to occur. That is, it is also possible to arrange the dummy electrode 5 (dummy electrode 8) whose area density satisfies a predetermined value only at a location where it is desired to suppress dishing or erosion.

2. Second Embodiment <Example in which electrode pads and dummy electrodes to be joined are not plane-symmetric>
In the first embodiment, the first electrode pad 4 and the second electrode pad 7, and the dummy electrode 5 and the dummy electrode 8 are arranged symmetrically with respect to the bonding surface Pj. However, as described above, they are not necessarily arranged symmetrically with respect to each other.

2A is a diagram illustrating a bonding surface of the first semiconductor member 10 of the semiconductor device 200 according to the second embodiment, and FIG. 2B is a diagram illustrating a bonding surface of the second semiconductor member 20. 2C is a cross-sectional view of the semiconductor device 200 taken along line L3 in FIGS. 2A and 2B.
In addition, the same code | symbol is attached | subjected to the site | part corresponding to 1st Embodiment, and the overlapping description is avoided. In the present embodiment, the configuration other than the first wiring layer 2 and the second wiring layer 9 is the same as that of the first embodiment (see FIG. 1C). Therefore, in FIG. Only the two wiring layers 9 are shown.

  The semiconductor device 200 according to this embodiment includes a first semiconductor member 10 and a second semiconductor member 20 joined to the first semiconductor member 10. The first semiconductor member 10 includes a first wiring layer 2, and the second semiconductor member 20 includes a second wiring layer 9. In the first wiring layer 2 and the second wiring layer 9, the arrangement pattern of the first electrode pad 4, the second electrode pad 7, the dummy electrode 5 and the dummy electrode 8 is different from that of the first embodiment.

For example, in the region T1 of FIG. 2C, two first electrode pads 4 and one dummy electrode 5 are bonded to one second electrode pad 7. In the region T <b> 2, two dummy electrodes 5 are bonded to one dummy electrode 8.
Thus, in this embodiment, the 1st electrode pad 4, the 2nd electrode pad 7, the dummy electrode 5, and the dummy electrode 8 are not made into plane symmetry with respect to the joint surface Pj. However, since the plurality of dummy electrodes 5 are bonded to the second electrode pad 7 and the dummy electrode 8, the bonding strength can be improved as in the first embodiment.

  Also in this embodiment, since the dummy electrode 5 (dummy electrode 8) is disposed between the first electrode pads 4 (second electrode pads 7), the metal wiring density on the bonding surface Pj can be made uniform. It is possible to suppress dishing, erosion, and the like that occur when the bonding surface Pj is formed by the CMP method. In addition, the operations and effects of the other configurations are the same as in the first embodiment.

3. Third Embodiment <Example in which electrode pads and dummy electrodes have the same shape, and both are arranged in the same pattern>
FIG. 3A is a diagram illustrating a bonding surface of the first semiconductor member 10 of the semiconductor device 300 according to the third embodiment, and FIG. 3B is a cross-sectional view of the semiconductor device 300 along a line L4 illustrated in FIG. 3A.
In this embodiment, the configuration is the same as that of the first embodiment (see FIG. 1C) except for the configuration of the first wiring layer 2, the second wiring layer 9, the third wiring layer 18, and the fourth wiring layer 19. FIG. 3B shows only these wiring layers.

The semiconductor device 300 of this embodiment includes a first semiconductor member 10 and a second semiconductor member 20. The first semiconductor member 10 includes a first wiring layer 2 and a third wiring layer 18.
As shown in FIG. 3A, in the present embodiment, in the first wiring layer 2, the first electrode pad 4 and the dummy electrode 5 have the same joint surface shape and are all arranged at equal intervals.

  Further, as shown in FIG. 3B, the first electrode pad 4 is connected to the wiring 21 in the third wiring layer 18 by the via 12. A diffusion prevention film 14 made of, for example, SiN is formed between the first wiring layer 2 and the third wiring layer 18.

The second semiconductor member 20 includes a second wiring layer 9 and a fourth wiring layer 19. The second electrode pad 7 and the dummy electrode 8 in the second wiring layer 9 are arranged in plane symmetry with the first electrode pad 4 and the dummy electrode 5 with respect to the bonding surface Pj, respectively.
The second electrode pad 7 is connected to the wiring 22 in the fourth wiring layer 19 by the via 13. Further, a diffusion prevention film 15 such as SiN is disposed between the second wiring layer 9 and the fourth wiring layer 19.

Thus, also in this embodiment, since the dummy electrodes 5 and 8 are provided and bonded to each other, the bonding strength between the first semiconductor member 10 and the second semiconductor member 20 can be improved.
In particular, in the present embodiment, the first electrode pad 4 (second electrode pad 3) and the dummy electrode 5 (dummy electrode 8) have the same joint surface shape and are all arranged at equal intervals. It is possible to make the area density of the electrode pads and the dummy electrodes more uniform.
Accordingly, dishing, erosion, and the like that occur when the bonding surface is polished and formed can be suppressed, and the bonding surface can be further planarized. For this reason, at the time of joining the first semiconductor member 10 and the second semiconductor member 20, it is possible to prevent a void from being generated on the joining surface Pj.

In the present embodiment, for example, even when the layouts of the wirings 21 and 22 are different, the layout of the first electrode pad 4 (second electrode pad 7) and the dummy electrode 5 (dummy electrode 8) is not changed. Can be used in common as they are.
In this case, the 1st electrode pad 4, the 2nd electrode pad 7, the dummy electrode 5, and the dummy electrode 8 are comprised by the same Cu electrode, for example. That is, from among Cu electrodes arranged at the same interval, one used as the first electrode pad 4 or the second electrode pad 7 is selected, and the via 12 or the via 13 is connected to the Cu electrode, respectively. By using other Cu electrodes as dummy electrodes, it is easy to change the layout of the Cu electrodes in the first wiring layer 2 and the second wiring layer 9 with respect to an arbitrary pattern of the wirings 21 and 22. It is possible to establish conduction.
For this reason, since it is not necessary to change the layout of the electrodes to be joined each time the wiring pattern is changed, the design cost can be reduced.
The operation and effect of the other configurations are the same as those in the first embodiment.

4). Fourth Embodiment <Example in which dummy electrodes are arranged only around electrode pads>
FIG. 4A is a diagram illustrating a bonding surface of the first semiconductor member 10 included in the semiconductor device 400 according to the fourth embodiment. In addition, the same code | symbol is attached | subjected to the site | part corresponding to 1st Embodiment, and the overlapping description is avoided. In the present embodiment, only the layout of the first electrode pad 4 (second electrode pad 7) and the dummy electrode 5 (dummy electrode 8) is different from that of the first embodiment. To do.

As shown in FIG. 4A, in the first semiconductor member 10 of the present embodiment, the dummy electrode 5 is disposed only around the first electrode pad 4. By performing such an arrangement, for example, after polishing of the bonding surface by CMP or the like, a substantially uniform flatness is ensured in the peripheral region where the first electrode pad 4 and the dummy electrode 5 are arranged. Is possible.
In the second semiconductor member 20 (not shown), the second electrode pad 7 and the dummy electrode 8 are arranged in plane symmetry with the first electrode pad 4 and the dummy electrode 5 with respect to the bonding surface, respectively. Accordingly, substantially uniform flatness is ensured in the peripheral region where the second electrode pad 7 and the dummy electrode 8 are similarly arranged.
For this reason, also in this embodiment, the second electrode pad 7 and the dummy electrode 8 can be bonded to the first electrode pad 4 and the dummy electrode 5 without generating any voids.

4B, the dummy electrode 5 may be disposed not only around the first electrode pad 4 but also in the entire region other than the first electrode pad 4 as in the semiconductor device 410 shown in FIG. 4B. 4B shows only the first semiconductor member 10, the second electrode pad 7 and the dummy electrode 8 of the second semiconductor member are respectively the same as the first electrode pad 4 and the dummy electrode 5 of the first semiconductor member 10. Arranged plane-symmetrically.
In this case, the dummy electrodes 5 do not need to be arranged at regular intervals, for example. For example, when the first semiconductor member 10 and the second semiconductor member 20 are joined, a layout having a wiring density such that one or more of the plurality of dummy electrodes 5 and the plurality of dummy electrodes 8 are joined to each other. The effect of improving the bonding strength can be obtained.

5. Fifth Embodiment <Example of Connecting Dummy Electrode to Ground>
FIG. 5A is a diagram illustrating a bonding surface of the first semiconductor member 10 included in the semiconductor device 500 according to the fifth embodiment. FIG. 5B is a cross-sectional view of the semiconductor device 500 taken along line L5 in FIG. 5A.
In addition, the same code | symbol is attached | subjected to the site | part corresponding to 2nd Embodiment, and the overlapping description is avoided. Further, the present embodiment is different from the second embodiment only in that the vias 23 and 24 are provided. Therefore, in FIG. 5B, illustration of structures other than the 1st wiring layer 2 and the 2nd wiring layer 9 is abbreviate | omitted.

In the semiconductor device 500 of this embodiment, the via 23 is connected to the dummy electrode 5 of the first semiconductor member 10. The via 23 is connected to the ground.
A via 24 is connected to the dummy electrode 8 of the second semiconductor member 20, and the via 24 is connected to the ground.

Thus, by connecting all the dummy electrodes 5 and 8 to the ground, the ground levels of the first semiconductor member 10 and the second semiconductor member 20 can be made uniform.
Further, when the dummy electrodes 5 and 8 are connected to the power supply voltage, the power supply can be shared.
The operation and effect of the other configurations are the same as those in the second embodiment.

6). Sixth Embodiment <Example of Semiconductor Image Receiver>
Here, a semiconductor image receiving device will be described as a more specific example of the semiconductor device according to the present technology.
FIG. 6 is a diagram showing a configuration of a semiconductor image receiving device 600 according to the sixth embodiment. In addition, the same code | symbol is attached | subjected to the site | part corresponding to 2nd Embodiment (refer FIG. 2C), and the duplicate description is abbreviate | omitted.

The semiconductor image receiving device 600 of the present embodiment includes a first semiconductor member 30 and a second semiconductor member 40 joined to the first semiconductor member 30.
The first semiconductor member 30 includes, for example, a Si substrate 33 and a transistor 34 made of a complementary metal oxide semiconductor formed on the Si substrate 33. A plurality of wiring layers are stacked on the transistor 34, and a first wiring layer 31 is formed at a position farthest from the substrate 33 (uppermost layer). Further, a diffusion prevention film 41 made of, for example, SiCN or SiN is provided between the wiring layers.

The first wiring layer 31 is provided with a first electrode pad 4 made of Cu, for example, and a dummy electrode 5 made of Cu, for example. The first electrode pad 4 and the dummy electrode 5 are embedded in a low dielectric constant material such as organic silica glass or an interlayer insulating film 39 such as SiO _2. The surface of the interlayer insulating film 39 opposite to the Si substrate 33 is located in the same plane.
The first electrode pad 4 is connected to the wiring in the wiring layer on the Si substrate 33 side by a via.

On the other hand, the second semiconductor member 40 is disposed on the photoelectric conversion layer 35 that outputs an electrical signal (charge) corresponding to the amount of received light, the color filter 36 disposed on the photoelectric conversion layer 35, and the color filter 36. A microlens 37. An insulating film 38 is formed on the photoelectric conversion layer 35 in a region other than the color filter 36.
One pixel is formed for each set of one photoelectric conversion layer 35, color filter 36, and microlens 37.

A wiring layer is laminated on the surface of the photoelectric conversion layer 35 opposite to the color filter 36, and the second wiring layer 32 is formed at a position farthest from the photoelectric conversion layer 35. A diffusion prevention film 42 made of, for example, SiCN or SiN is formed between the wiring layers.
The second wiring layer 32 includes a low dielectric constant material such as organic silica glass, an interlayer insulating film 43 made of SiO ₂ , the second electrode pad 7, and the dummy electrode 8. The second electrode pad 7 and the dummy electrode 8 are embedded in the interlayer insulating film 43, and the surface of the second electrode pad 7, the dummy electrode 8 and the interlayer insulating film 43 opposite to the photoelectric conversion layer 35 side is Located in the same plane.
As the layout of the first electrode pad 4, the dummy electrode 5, the second electrode pad 7, and the dummy electrode 8, any layout of the layouts shown in the first to fifth embodiments may be adopted. .

  The photoelectric conversion layer 35 is configured by, for example, a photodiode. In addition, the transistor 34 provided in the second semiconductor member is a so-called transfer transistor, reset transistor, amplification transistor, or the like, and is used for calculating the charge output from the photoelectric conversion layer 35.

In addition, although not shown, the semiconductor image receiving apparatus 600 includes other circuits such as a vertical drive circuit, a column signal processing circuit, and a horizontal drive circuit, for example.
The vertical drive circuit selectively scans each pixel in the vertical direction in units of rows, and supplies a pixel signal based on the charge generated in the photoelectric conversion layer 35 to the column signal processing circuit.
The column signal processing circuit is arranged for each column of pixels, for example, and performs signal processing such as noise removal for each pixel column on a signal output from one row of pixels.
Further, the horizontal drive circuit sequentially outputs the horizontal scanning pulses, thereby selecting each of the column signal processing circuits in order and outputting a pixel signal from each of the column signal processing circuits to the horizontal signal line.

Also in the semiconductor image receiving device 600 of this embodiment, since the first semiconductor member 30 and the second semiconductor member 40 are joined by the dummy electrodes 5 and 8, the joining strength can be improved.
Further, since the layout of the first electrode pad 4, the dummy electrode 5, the second electrode pad 7, and the dummy electrode 8 is the same as that of any one of the first to fifth embodiments, the bonding surface Pj Can be formed in a more uniform plane. Therefore, dishing and erosion can be suppressed, and generation of voids at the joint surface Pj can be prevented.
In addition, the operations and effects of the other configurations are also the same as those in the first to fifth embodiments.

7). Example of Electronic Device Next, an example in which the semiconductor device described so far is applied to an electronic device such as a camera will be described below with reference to FIGS.
FIG. 7 is a schematic configuration diagram illustrating a configuration of the electronic apparatus 700 according to the present embodiment. The electronic apparatus 700 according to this embodiment includes a light collecting unit 70 that collects light from an imaging target, and a semiconductor image receiving device 71 that receives the light collected by the light collecting unit 70.
In addition, a shutter unit 75 that determines the exposure time for the semiconductor image receiving device, a drive circuit that drives the shutter unit 75, a control circuit 73 that controls charges output from the semiconductor image receiving device 71, and an output from the semiconductor image receiving device 71. And a signal processing circuit 74 for processing the signal.

  The condensing part 70 will not be specifically limited if it condenses the light from an imaging target and makes it image-form. One lens may be included, and two or more lenses may be included.

The light from the imaging target collected by the condenser 70 is received by the semiconductor image receiving device 71, and an image of the imaging target is acquired. The semiconductor image receiving device 71 is constituted by the semiconductor image receiving device 600 shown in the sixth embodiment (see FIG. 6), for example.
The semiconductor image receiving device 71 is provided with a charge / voltage conversion circuit, a noise correction circuit, and an analog / digital conversion circuit as necessary.

The drive circuit 72 adjusts the exposure time for the semiconductor image receiving device 71 by, for example, driving the shutter unit 75. The shutter unit 75 may be a mechanism that blocks incident light. For example, a mechanically moving shutter mechanism may be used, and a configuration in which an opening for irradiating a part of pixels with light can be arbitrarily set, such as a liquid crystal shutter.
The control circuit 73 includes a timing generator such as a start pulse and a clock pulse, for example, and controls accumulation, discharge, and the like of charges generated by light irradiation to the semiconductor image receiving device 71.

  Further, the signal processing circuit 74 performs signal processing such as correlated double sampling on the output signal from the semiconductor image receiving device 71 and records it on a recording medium such as a memory or outputs it to a monitor such as a liquid crystal display. To do.

  As described above, by using the semiconductor device (semiconductor image receiving device 600) according to the present technology in which a plurality of semiconductor members are firmly bonded, an electronic device having excellent impact resistance can be provided. In addition, since the reliability of stacking a plurality of semiconductor members can be improved, it is possible to further promote downsizing of the electronic device.

8). Examples Hereinafter, examples of the first to sixth embodiments described above and comparative examples will be described.
<Example 1>
The semiconductor device 100 shown in the first embodiment (see FIGS. 1A to 1C) was manufactured, and the void inspection by ultrasonic waves was performed on the bonding surface between the first semiconductor member 10 and the second semiconductor member 20.
In the first semiconductor member 10 and the second semiconductor member 20, the first electrode pad 4 and the second electrode pad 7 embedded in the interlayer insulating films 3 and 6, respectively, were formed by a general damascene process. Further, the surface of the first semiconductor member 10 and the second semiconductor member 20 is polished using a general CMP pad in which a soft layer and a hard layer are laminated and a general slurry for manufacturing a semiconductor device. went.
Next, the surfaces of the first semiconductor member 10 and the second semiconductor member 20 after polishing were brought into contact with each other. And the temporary joining was performed by pressing down the center of the 2nd semiconductor member 20 with the load 12N using the pin. Thereafter, heat treatment was performed at 350 ° C., and the first semiconductor member 10 and the second semiconductor member 20 were joined.
As a result of ultrasonic void inspection, no void was found, and it was confirmed that the entire bonded surface was securely bonded. In addition, when it was going to measure the joint strength of the 1st semiconductor member 10 and the 2nd semiconductor member 20 by the razor test described in the above-mentioned nonpatent literature 2, the joint surface of electrode pads and dummy electrodes Did not peel off and accurate measurement was impossible. That is, it has been confirmed that the first semiconductor member 10 and the second semiconductor member 20 are strongly bonded so that the bonding strength cannot be measured by the conventional measurement method.

<Example 2>
The semiconductor device 200 (see FIGS. 2A to 2C) shown in the second embodiment was manufactured by the same method as in Example 1, and a void inspection was performed using ultrasonic waves.
In the bonding surface of the first semiconductor member 10, the ratio of the surface area of the first electrode pad 4 and the dummy electrode 5 to the surface area of the interlayer insulating film 3 was in the range of 50% to 60%.
As a result of performing a void inspection with ultrasonic waves on the semiconductor device 200, no void was found, and it was confirmed that the semiconductor device 200 was reliably bonded over the entire bonding surface .

<Example 3>
When the semiconductor device 300 shown in the third embodiment (see FIG. 3) was manufactured by the same method as in Example 1 and a void inspection was performed using ultrasonic waves, no void was generated on the bonding surface. It was confirmed that it was able to be joined .

<Example 4>
When the semiconductor device 400 shown in the fourth embodiment (see FIG. 4A) was manufactured by the same method as in Example 1 and the void inspection was performed using ultrasonic waves, no void was generated on the bonding surface, and it was ensured. It was confirmed that it was able to be joined .
In addition, the semiconductor device 410 illustrated in FIG. 4B was manufactured in the same manner, and a void inspection was performed using ultrasonic waves. Note that the ratio of the surface area of the first electrode pad 4 and the dummy electrode 5 to the surface area of the interlayer insulating film 3 on the bonding surface of the first semiconductor member 10 was in the range of 50% to 60%. Also in this semiconductor device 410, it was confirmed that no void was generated on the bonding surface, and bonding could be performed reliably.

<Example 5>
The semiconductor image receiving device shown in the sixth embodiment was manufactured, and void inspection was performed using ultrasonic waves. For the production of the first semiconductor member 10 and the second semiconductor member 20, the surfaces to be joined to each other were polished by a CMP method using a general semiconductor process.
Next, the first semiconductor member 10 and the second semiconductor member 20 were temporarily joined in the same manner as in Example 1, and then heat treatment was performed at 350 ° C. to complete the joining.
Even in this case, no void is generated on the joint surface between the first semiconductor member 10 and the second semiconductor member 20, and the joint surface is not peeled off, and the reliability deterioration due to the fragility of the joint portion does not occur. It was confirmed.

<Comparative Example 1>
As a comparative example, a semiconductor device 100a having a configuration in which no dummy electrode is disposed was manufactured. FIG. 8A is a diagram illustrating a bonding surface of the first semiconductor member 10a of the semiconductor device 100a according to the comparative example. 8B is a cross-sectional view of the semiconductor device 100a taken along line L6 in FIG. 2A. 8C is a cross-sectional view of the semiconductor device 100a taken along line L7 in FIG. 8A.
The semiconductor device 100a is the same as the semiconductor device 100 of the present embodiment except that the dummy electrodes 5 and 8 are not provided as compared with the semiconductor device 100 of the present embodiment.

In the first semiconductor member 10a and the second semiconductor member 20a, the first electrode pad 4a and the second electrode pad 7a embedded in the interlayer insulating films 3a and 6a, respectively, were formed by a general damascene process. Also, the bonding surface Pj of the first semiconductor member 10a and the second semiconductor member 20a is polished using a general CMP pad in which a soft layer and a hard layer are laminated and a general slurry for manufacturing a semiconductor device. Went.
The joining of the first semiconductor member 10a and the second semiconductor member 20a was performed in the same manner as in Example 1.

As shown in FIG. 8B, no void was formed on the joint surface between the first semiconductor member 10a and the second semiconductor member 20a at the location indicated by line L6 in FIG. 8A.
However, at the location indicated by line L7 in FIG. 8A, as shown in FIG. 8C, a void was formed between the first electrode pad 4a and the second electrode pad 7a. This is because dishing occurred on the bonding surfaces of the first electrode pads 4a and the second electrode pads 7a when the bonding surfaces of the semiconductor members were formed.

  As described above, in Examples 1 to 5 in which the dummy electrodes are provided according to the present technology, since no void is formed on the bonding surface, it is possible to provide a semiconductor device in which two semiconductor members are firmly bonded. is there. Further, since the dummy electrodes 5 and 8 can be formed simultaneously with the formation of the first electrode pad 4 and the second electrode pad 7, respectively, the bonding strength can be improved without increasing the number of manufacturing steps.

The present technology is not limited to the above-described embodiments and experimental examples, and various other configurations can be taken without departing from the gist of the present technology.
Moreover, this technique can also take the following structures.
(1)
A first interlayer insulating film; a first electrode pad embedded in the first interlayer insulating film and having one surface located on the same plane as the one surface of the first interlayer insulating film; and the first interlayer insulating film A first dummy electrode embedded in the film and having one surface located on the same plane as the one surface of the first interlayer insulating film and disposed around the first electrode pad. 1 wiring layer,
A second interlayer insulating film located on the one surface side of the first electrode pad of the first interlayer insulating film, and embedded in the second interlayer insulating film, and one surface of the second interlayer insulating film A second electrode pad located on the same surface as the surface on the first interlayer insulating film side and joined to the first electrode pad; and the first interlayer insulating film of which the first surface is the second interlayer insulating film A second wiring layer including a second dummy electrode located on the same plane as the side surface and disposed around the second electrode pad and joined to the first dummy electrode;
Including a semiconductor device.
(2)
The first electrode pad and the first dummy electrode are disposed in plane symmetry with the second electrode pad and the second dummy electrode with respect to a bonding surface between the first wiring layer and the second wiring layer. The semiconductor device according to claim 1.
(3)
In the bonding surface between the first wiring layer and the second wiring layer, the ratio of the surface area of the first electrode pad and the dummy electrode to the surface area of the first interlayer insulating film is 50% or more and 60% or less. Or the semiconductor device according to (2).
(4)
The semiconductor device according to any one of (1) to (3), wherein the first and second dummy electrodes are all connected to a ground.
(5)
The semiconductor device according to any one of (1) to (4), wherein the first electrode pad and the first dummy electrode have the same outer shape and are all arranged at equal intervals.
(6)
The semiconductor device according to any one of (1) to (4), wherein the first dummy electrode is disposed only around the first electrode pad at a joint surface between the first wiring layer and the second wiring layer.

DESCRIPTION OF SYMBOLS 1 ... Board | substrate, 2,31 ... 1st wiring layer, 3 ... Interlayer insulation film, 3a ... Interlayer insulation film, 4, 4a ... 1st electrode pad, 5 ... Dummy electrode , 6 ... interlayer insulating film, 7, 7a ... second electrode pad, 8 ... dummy electrode, 9, 32 ... second wiring layer, 10, 10a, 30 ... first semiconductor member , 11 ... substrate, 12, 13, 23, 24 ... via, 14, 15 ... diffusion prevention film, 15, 42 ... diffusion prevention film, 18 ... third wiring layer, 19. ..4th wiring layer, 20, 20a, 40 ... second semiconductor member, 21,22 ... wiring, 33 ... Si substrate, 34 ... transistor, 35 ... photoelectric conversion layer, 36 ... Color filter, 37 ... Microlens, 39,43 ... Interlayer insulating film, 70 ... Condenser, 71 ... Semiconductor image receiver 72 ... Drive circuit 73 ... Control circuit 74 ... Signal processing circuit 75 ... Shutter unit 100,100a, 200,300,400,410,500 ... Semiconductor device 600 ... Semiconductor image receiving device, 700 ... electronic equipment

Claims (1)

A first interlayer insulating film; a first electrode pad embedded in the first interlayer insulating film and having one surface located on the same plane as the one surface of the first interlayer insulating film; and the first interlayer insulating film A first dummy electrode embedded in the film and having one surface located on the same plane as the one surface of the first interlayer insulating film and disposed around the first electrode pad. 1 wiring layer,
A second interlayer insulating film located on the one surface side of the first electrode pad of the first interlayer insulating film, and embedded in the second interlayer insulating film, and one surface of the second interlayer insulating film A second electrode pad located on the same surface as the surface on the first interlayer insulating film side and joined to the first electrode pad; and the first interlayer insulating film of which the first surface is the second interlayer insulating film A second wiring layer including a second dummy electrode located on the same plane as the side surface and disposed around the second electrode pad and joined to the first dummy electrode;
Including
The first dummy electrode is disposed between the first electrode pads, the second dummy electrode is disposed between the second electrode pads ,
A first region where two first electrode pads are bonded to one second electrode pad, and a second area where two first dummy electrodes are bonded to one second dummy electrode. A semiconductor device including the region .

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