JP5915740B2 - Programmable controller and power-off countermeasure method - Google Patents

Description

  The present invention relates to a programmable controller capable of programming control processing for a controlled device, and a method for dealing with power-off when power is turned off.

  In the programmable control system, one or more programmable controllers are connected to a higher-level management device, and each programmable controller controls a plurality of controlled devices. Therefore, the programmable controller must receive a control command from a higher-level management device, analyze the control command, control a lower-level controlled device, and hold parameters and status information required for control.

  In addition, since the lower-level controlled devices often have power, the programmable control system as a whole must perform various control operations safely and reliably by appropriately controlling the controlled devices in the programmable controller. . For example, even if the power is turned off during the operation of the programmable control system, the programmable controller must reliably back up data indicating the operating state at the time of the disconnection and stop the controlled device safely. Also, when the power is turned on again, the programmable controller should relocate the backed up data and quickly return to the original operating state.

  Therefore, a technique is known in which when a power-off is detected, a processor (CPU) backs up some data stored in an SRAM to a flash memory (for example, Patent Document 1). Also disclosed is a technique for detecting such a power cut based on a power supply voltage and ensuring a sufficient processable period for backup processing (for example, Patent Document 2).

JP 2000-305610 A JP 2009-193371 A

  However, in the techniques of Patent Documents 1 and 2 described above, the processor executes all processes related to backup through its own program. Therefore, the processor once reads the information from the backup target memory storing the information to be backed up, and writes the information in the backup destination backup memory at different timings.

  Then, a large amount of power and time that can be used for backup is consumed by a processor with high power consumption for reading and writing data. Therefore, in order to reliably back up data that needs to be backed up, the capacity of the capacitor, which is a power source for backup, must be increased, which causes problems in terms of occupied area and cost.

  Therefore, in view of such a problem, an object of the present invention is to devise a backup processing procedure and provide a programmable controller and a power-off countermeasure method that can avoid an unnecessary increase in the capacitance of a capacitor.

In order to solve the above problems, a programmable controller according to the present invention includes a backed up memory that can be controlled through a common bus, a backup memory that can be controlled through a common bus, and a processor that is connected to the common bus and operates based on a control program. And a dedicated memory accessible only by the processor, an access element connected to the backup target memory and the backup memory through a common bus, and power detection for detecting that the power supply voltage is less than a predetermined first threshold value. comprising a part, an access device, Ri is the power supply voltage Do less than the first threshold value, the processor, after saving the data in the dedicated memory in the backup memory, the processor operating mode, less power consumption than the normal mode is shifted to the power saving mode, the data of the backup memory Tsu Ru is retracted to click up memory.

  The power consumption of the access element is less than the power consumption of the processor.

The power supply line further includes a capacitor for accumulating power connected to the power supply line from the power source via a backflow prevention diode and a switch, and the power detection unit includes the first power supply voltage being less than the first threshold value. The switch detects that the second threshold value is less than the second threshold value, and the switch maintains the capacitor and the main circuit including the processor and the access element in a disconnected state while the power supply voltage is equal to or higher than the second threshold value. When the voltage is less than the second threshold, the capacitor and the main circuit may be connected.

The power storage unit further includes a capacitor for storing electric power connected to a power supply line from the power source via a switch, and the power detection unit has a second lower than the first threshold in addition to the power source voltage being lower than the first threshold. The switch detects that the threshold value has become less than the threshold value, and the switch maintains the capacitor and the main circuit including the processor and the access element in a disconnected state while the power supply voltage is less than the first threshold value and greater than or equal to the second threshold value. May be connected to the main circuit while is equal to or higher than the first threshold value or lower than the second threshold value.

The access element may read data from the backup target memory and write the data to the backup memory while the data is being output to the common bus.

In order to solve the above-described problem, a power-off countermeasure method according to the present invention is connected to a backup memory that can be controlled through a common bus, a backup memory that can be controlled through a common bus, and operates based on a control program. , A dedicated memory accessible only by the processor, an access element connected to the backed up memory and the backup memory through a common bus, and detecting that the power supply voltage is less than a predetermined first threshold value in the programmable controller and a power detector, the processor, when the power supply voltage becomes less than the first threshold value, is saved in the backup memory data-only memory, access device, Ri is the power supply voltage Do less than the first threshold value, the processor However, save the data in the dedicated memory to the backup memory After the operation mode of the processor to transition to the normal low power saving mode power consumption than the mode, it reads data from the backup memory, and writes the data in the backup memory.

  The access element may read data from the backup target memory and write the data to the backup memory while the data is being output to the common bus.

  According to the present invention, it is possible to devise a backup processing procedure and avoid an unnecessary increase in the capacitance of the capacitor.

It is explanatory drawing which showed the schematic relationship of each apparatus which comprises a programmable control system. It is the block diagram which showed the schematic structure of the programmable controller. It is explanatory drawing which showed transition of the electric power at the time of the cutting | disconnection of a power supply. It is a block diagram which shows the schematic structure of the main circuit of a programmable controller. It is the flowchart which showed the flow of the process of the power-off countermeasure method. 5 is a timing chart showing detailed timing of data transfer.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The dimensions, materials, and other specific numerical values shown in the embodiment are merely examples for facilitating understanding of the invention, and do not limit the present invention unless otherwise specified. In the present specification and drawings, elements having substantially the same function and configuration are denoted by the same reference numerals, and redundant description is omitted, and elements not directly related to the present invention are not illustrated. To do.

(Programmable control system 100)
FIG. 1 is an explanatory diagram showing a schematic relationship between devices constituting the programmable control system 100. The programmable control system 100 includes a management device 110, one or more programmable controllers 120, and one or more controlled devices 130. Further, the management device 110 and the one or more programmable controllers 120 are connected by a network wiring 140 based on Ethernet (registered trademark) such as a Giga (G) base, for example. The programmable controller 120 and the one or more controlled devices 130 are connected through, for example, a dedicated connection wiring 142.

  The management device 110 reads status information from the one or more programmable controllers 120 and outputs various control commands to the one or more programmable controllers 120 so as to follow the process flow in the entire programmable control system 100.

  The programmable controller 120 includes a plurality of modules such as a power supply module, a CPU module, an input / output module, and a communication module, and is also called a PLC (Programmable Logic Controller). For example, the CPU module has a control program for sequence control generated through a ladder diagram or the like, and is based on a control command from the management apparatus 110 and a sensor detection result of the controlled device 130 input through the input / output module. To control the controlled device 130.

  The controlled device 130 includes a sensor that detects various states in FA (Factory Automation), and an electric device such as an electric motor and an encoder that operate according to the detection result of the sensor.

  Such a programmable control system 100 can be applied to various control objects. For example, when the programmable control system 100 is applied to a production execution system (MES), it is programmable to a production device such as a center sealer unit or a film unit as a controlled device 130. The controller 120 is connected.

  The programmable controller 120 reads the operation state of the production device from the input / output module and the like, and controls the rotation of the electric motor in the production device through a motor driver or the like. The management device 110 collects information for each programmable controller 120 and transmits a control command. In this way, the production control management such as process management, quality management, and production amount management can be comprehensively performed as the entire programmable control system 100.

  Hereinafter, specific operations of the programmable controller 120 will be described separately for power supply when the power is turned off and backup processing.

(Power supply when the power is cut off)
The programmable controller 120 is connected to the higher-level management device 110 and the lower-level controlled device 130, respectively, and controls parameters and status information regarding control commands from the higher-level management device 110, and controls the lower-level controlled device 130. Parameters and status information are stored in each memory.

  Such a memory needs to be rewritten according to the operating state. That is, a read-only memory (simple ROM) cannot be applied. In addition, the controlled device 130 may have power, and in order to increase the reactivity of the drive control, it is necessary to read / write data to / from the memory quickly. Therefore, a relatively high-speed and volatile SRAM is often used as the memory.

  However, in a volatile RAM such as SRAM, when the power is turned off, the stored contents are erased, and parameters and status information may become unintended values when the power is turned on again. Then, there is a possibility that the safe and reliable control operation of the controlled device 130 may be hindered. Therefore, when the programmable controller 120 detects power-off, a part of the parameter or status information is displayed in a backup memory that can maintain data even when the power is off from the backup memory such as SRAM. Transfer data. In this way, parameters and status information are maintained. When the power is turned on again, the programmable controller 120 rearranges the backed up data and quickly returns to the original operating state.

  FIG. 2 is a block diagram illustrating a schematic configuration of the programmable controller 120. The programmable controller 120 includes a first diode 150, a voltage conversion unit 152, a main circuit 154, a capacitor unit 156, and a power detection unit 158.

In the first diode 150, the anode 150 a is connected to the power source 148, and the cathode 150 b is connected to the voltage conversion unit 152, thereby preventing the backflow of power from the capacitor unit 156. The voltage converter 152 is configured by a regulator or the like that stabilizes the output voltage to a constant level, and converts the power supply voltage V _S (for example, 24 V) into a voltage V _R (for example, 3.3 V) that can be used by the main circuit 154. The main circuit 154 is connected to the management device 110 and the controlled device 130, and the main control of the programmable controller 120 is executed. A specific configuration of the main circuit 154 will be described in detail later.

The capacitor unit 156 receives power from the power source 148 to store power during normal operation of the main circuit 154, and supplies power to the main circuit 154 instead of the power source 148 when the power source 148 is disconnected. The power detection unit 158 detects that the power supply 148 has been cut off, for example, through a decrease in the power supply voltage V _S , and outputs an interrupt signal serving as a backup trigger to the main circuit 154. In the main circuit 154, when the power detection unit 158 detects the disconnection of the power source 148, the data in the memory to be backed up is transferred to the backup memory accordingly, and backup processing is performed to prevent the power supply from being interrupted.

Thus, in the programmable controller 120, when the supply of power from the power source 148 is likely to be interrupted, it is necessary to detect the disconnection of the power source 148 at an early stage and transfer data in a state where the power can still be used. Therefore, the power detection unit 158 is less than the first threshold V ₁ before the main circuit 154 becomes inoperable, that is, the power supply voltage V _S is lower than the rated value but higher than the power supply voltage at which the main circuit 154 becomes inoperable. Therefore, it is detected that the power source 148 is cut off, and this is transmitted to the main circuit 154.

  On the other hand, the above-described capacitor unit 156 is provided in order to reliably supply power during data transfer even when the power source 148 is cut off. As the capacitor unit 156, a capacitor 156a having a relatively large capacity is used. Conventionally, one end of the capacitor 156a is directly connected to the power supply line 160 extending from the first diode 150 to the voltage converter 152. However, if the capacitor 156a is simply connected directly to the power supply line 160, the effective use of the power may not be achieved as described below.

FIG. 3 is an explanatory diagram showing the transition of power when the power source 148 is turned off. If the capacitor 156a is directly connected to the power supply line 160 as in the conventional case, the voltage changes as shown in FIG. That is, the power supply 148 is disconnected, the power supply when the voltage _{V S} starts to drop, the power based on the charge stored in the capacitor 156a begins to be supplied to the main circuit 154, the main circuit 154 from the power source 148 voltage is lower than the capacitor 156a Will not be supplied with power. Therefore, the voltage V _C of the capacitor 156a decreases with the consumption of power based on the charge of the capacitor 156a, and the main circuit 154 operates after the elapse of time t ₁ after the power supply voltage V _S becomes less than the first threshold value V _1. inability to become so that the voltage reaches the higher second threshold value V _2.

In FIG. 3A, since the voltage V _{C of the} capacitor 156a continues to be higher than the power supply voltage V _S after the power supply 148 is cut off, the main circuit 154 starts after the power supply voltage V _S starts to drop. Is not supplied with power from the power source 148. That is, the energy from the time of the voltage drop related to the power supply voltage V _S to the second threshold V ₂ shown by hatching in FIG. 3A is wasted. The main circuit 154, up to the second threshold value _{V 2,} receives supply of power only from the capacitor 156a.

  Therefore, when the data that needs to be backed up increases, the time required for saving to the backup memory becomes longer, and accordingly, the capacity of the capacitor 156a for securing the power at the time of backup must be increased. It was.

  Therefore, in this embodiment, the configuration of the capacitor unit 156 is devised to improve the power supply mode. As shown in FIG. 2, the capacitor unit 156 includes a second diode 156b for preventing backflow (backflow preventing diode) 156b and an ON / OFF switch 156c. The capacitor 156a is connected to the second diode 156b and the switch 156c. Connected to the power supply line 160. Since the second diode 156b allows a power flow from the power supply line 160 to the capacitor 156a, power is normally stored in the capacitor 156a.

Then, the power detection unit 158 indicates that the power supply voltage V _S is less than the first threshold value V ₁ (for example, 19 V) and less than the second threshold value V ₂ (for example, 3.5 V) that is smaller than the first threshold value V ₁ . Are detected, and an interrupt signal is output for each. Here, two different voltages are detected by one power detection unit 158, but two power detection units 158 having different detection voltages may be provided to output interrupt signals, respectively. Thus, the drop in the power supply voltage V _S can be detected in two stages.

When the power supply voltage V _S becomes less than the first threshold V ₁ , the power detection unit 158 outputs an interrupt signal to an access element (described later) provided in the main circuit 154, and changes the operation mode of the processor in the main circuit 154 to normal. Transition to the power saving mode, which consumes less power than the mode. Here, the normal mode is a mode in which the programmable controller 120 is executing an assumed operation. The power saving mode is a mode (resume mode, standby mode) in which the programmable controller 120 stops its original operation but performs at least a minimum function such as accepting an interrupt signal.

Further, when the power supply voltage V _S becomes less than the first threshold V ₁ , the main circuit 154 performs data backup processing. The backup process will be described in detail later. Immediately after the power supply voltage V _S becomes less than the first threshold value V _1, the switch 156c of the capacitor unit 156 is set to disconnect the capacitor 156a and the power supply line 160, and the power supply voltage V _S is set to the second threshold value. to below V ₂ to maintain the state of the disconnected.

Therefore, capacitor 156a and the main circuit 154 is not connected by a switch 156c, also, since the higher voltage _{V C} of the capacitor 156a than the supply voltage _{V S,} the second diode 156b, to the power supply line 160 from the capacitor 156a Does not flow power. Then, power from the power source 148 is supplied to the main circuit 154, and energy until the power source voltage V _S becomes less than the second threshold value V ₂ shown by hatching in FIG. It will be.

Then, when the power supply voltage V _S becomes less than the second threshold V ₂ , the power detection unit 158 inverts the state signal (interrupt signal) output to the switch 156c (for example, inversion from Low to High). The switch 156c switches the disconnected state between the capacitor 156a and the main circuit 154 to the connected state in accordance with the inversion of the state signal. When the power supply voltage V _S becomes less than the second threshold value V ₂ , power can no longer be received from the power supply 148. However, by connecting the capacitor 156a and the power supply line 160 at that timing, the main circuit 154 can receive power based on the charge of the capacitor 156a after receiving power from the power source 148. It becomes.

Thus, the main circuit 154, after the power supply voltage _{V S} is until the second less than the threshold _{V 2,} supplied with electric power from a power source 148, the power supply voltage _{V S} becomes smaller than the second threshold value _{V 2,} the first capacitor 156a It is supplied with power based on the electric charge. Thus, energy from the power source 148 can be effectively used until the power source voltage V _S becomes less than the second threshold value V ₂ . As a result, a time obtained by adding a time t ₂ for 148 minutes in addition to the time t ₁ shown in FIG. 3A until it becomes impossible to receive power supply from either the power source 148 or the capacitor 156a. This is the maximum time allowed for backup.

After the power supply voltage V _S becomes less than the second threshold V ₂ , the voltage V _{C of the} capacitor 156a is higher than the power supply voltage V _S. However, since the first diode 150 prevents the backflow of power from the capacitor 156a to the power source 148, the power stored in the capacitor 156a is consumed only by the main circuit 154. During this time, the main circuit 154 completes the backup process, and the processor completes the transition to the power saving mode.

  As described above, the capacitor unit 156 of this embodiment can extend the maximum time allowed for backup. Therefore, even when the data that needs to be backed up increases, the backup can be performed stably and reliably without increasing the capacity of the capacitor 156a. On the other hand, when there is no increase in data that needs to be backed up, the capacity of the capacitor 156a can be changed to be small, and the occupied area and cost can be reduced.

(Modification)
In the above description, the capacitor 156a is described as being connected to the power supply line 160 via the second diode 156b and the switch 156c. However, the capacitor 156a is connected to the power supply line 160 only via the switch 156c. You can also

In this case, the switch 156c keeps the capacitor 156a and the power supply line 160 disconnected while the power supply voltage V _S is less than the first threshold V ₁ and greater than or equal to the second threshold V ₂ . The switch 156c connects the capacitor 156a and the power supply line 160 while the power supply voltage V _S is equal to or higher than the first threshold V ₁ or lower than the second threshold V ₂ .

  Even in the configuration including only the switch 156c, the voltage transition as shown in FIG. 3B can be obtained as in the configuration including the second diode 156b. In this configuration, not only the second diode 156b is unnecessary, but also a voltage drop due to the second diode 156b can be ignored.

(Backup process)
FIG. 4 is a block diagram showing a schematic configuration of the main circuit 154 of the programmable controller 120. The main circuit 154 includes a processor 170, a first communication element 172, a first memory (dedicated memory) 174, a common bus 176, an access element 178, a second communication element 180, and a second memory (backed up memory). ) 182 and a third memory (backup memory) 184.

  The processor (microcomputer) 170 is composed of a semiconductor integrated circuit including a central processing unit (CPU), a ROM storing programs, and the like, and has a bus master function. The processor 170 controls the entire main circuit 154 and controls one or more controlled devices 130 based on a control program for sequence control stored in the ROM.

  The first communication element 172 communicates with the management device 110 and the other programmable controller 120 through the network wiring 140 by Ethernet (registered trademark) such as Giga (G) base. The first memory 174 is a volatile SDRAM that is directly connected to the processor 170 (not connected through the common bus 176), and functions as a work area of the processor 170. The first memory 174 stores at least RAS (Reliability, Availability, Serviceability) information such as a communication state and an abnormality history in communication with the management device 110 and other programmable controllers 120.

  The access element 178 is configured by an integrated circuit such as a PGA (Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit) connected to the common bus 176, and performs logical calculation in the main circuit 154. The access element 178 has a bus master function and can access the second memory 182 and the third memory 184 through the common bus 176.

  The second communication element 180 communicates with the controlled device 130 through the dedicated connection wiring 142. The second memory 182 is a volatile and relatively high speed SRAM connected to the common bus 176. The second memory 182 stores at least information indicating the operation state of the controlled device 130 acquired through the input / output module, such as RAS information such as a communication state and abnormality history in communication with the controlled device 130.

  The third memory 184 is a nonvolatile RAM connected to the common bus 176. The third memory 184 is used to back up part of the data stored in the first memory 174 and the second memory 182 when the power source 148 is cut off. Therefore, it has a function of holding data at least while the power source 148 is disconnected. Here, a non-volatile RAM is cited, but a volatile RAM that can hold the stored contents of the memory for an assumed time using a built-in or external capacitor or the like can also be used. Hereinafter, the flow of the power-off countermeasure method for performing backup by the functional unit of the main circuit 154 will be described.

(Power-off countermeasures)
FIG. 5 is a flowchart showing a process flow of the power-off countermeasure method. The power detection unit 158 monitors whether or not the power supply voltage V _S is less than the first threshold V ₁ (S1), and performs the monitoring process while the power supply voltage V _S is equal to or higher than the first threshold V ₁ (NO in S1). repeat. Here, when the power supply voltage V _S becomes less than the first threshold value V ₁ (YES in S1), the power detection unit 158 transmits an interrupt signal to the access element 178 (S2).

When the access element 178 receives the fact that the power supply voltage V _S is less than the first threshold value V ₁ from the power detection unit 158, the access element 178 transmits the fact to the processor 170, and the processor 170, the access element 178, and the first memory 174. Then, the elements other than the second memory 182 and the third memory 184 are stopped (S3).

Based on its own control program, the processor 170 transfers the data that needs to be backed up stored in the first memory 174 to the third memory 184 to back up the information in the first memory 174, and when the transfer is completed. A completion signal is transmitted to the access element 178 (S4). Start trigger the backup process is a first threshold value V _1, the main circuit 154 need not be aware of the second threshold value V _2.

  Further, the processor 170 transmits the address and size of data to be backed up in the second memory 182 and the address to be stored in the third memory 184 to the access element 178, and the access element 178 Information is held (S5).

  When the transfer of data from the first memory 174 to the third memory 184 is completed (when a completion signal is received), the access element 178 outputs an operation mode change signal to change the operation mode of the processor 170 from the normal mode. The mode is shifted to the power saving mode (S6). Further, when a separate monitoring device capable of starting and stopping the processor 170 is provided, the access element 178 can also stop the processor 170. Then, the access element 178 transfers the data that needs to be backed up stored in the second memory 182 to the third memory 184 (S7).

  At this time, the access element 178 is connected to the second memory 182 and the third memory 184 through the common bus 176, and transfers data from the second memory 182 to the third memory 184 independently of the processor 170. The transfer independently of the processor 170 is to transfer data based on the judgment of only the access element 178 without receiving a control command from the processor 170 or leaving the processing to the processor 170.

The access element (PGA or ASIC) 178 can arbitrarily set a logic circuit and its operation timing. Therefore, the logic circuit is validated based on the interrupt signal indicating that it is less than the first threshold value V ₁ and the completion signal from the processor 170, and the control signal to the second memory 182 and the third memory 184 is appropriately set. It can be generated at the timing. Control signals to the second memory 182 and the third memory 184 will be described in detail later.

  In this way, following the first memory 174, the data in the second memory 182 is also transferred to the third memory 184. At this time, the data transfer from the second memory 182 to the third memory 184 is realized by only the access element 178 (hardware) that does not involve the processor 170 and consumes less power than the processor 170. The processor 170 can be quickly shifted to the power saving mode. Therefore, as compared with the conventional case where the processor 170 is involved in the backup processing of all the memories, it is possible to reduce the power consumption required for the backup processing.

  In this embodiment, the access element 178 reads data from the second memory 182 and transfers the data to the common bus 176 when transferring data from the second memory 182 to the third memory 184. Then, the data is written into the third memory 184.

  FIG. 6 is a timing chart showing the detailed timing of data transfer. For example, an example in which data B stored at an arbitrary address A in the second memory 182 is transferred to the third memory 184 will be described. Here, the storage capacity of the third memory 184 is set to be equal to or greater than the storage capacity of the second memory 182, and the address spaces (memory maps) of the second memory 182 and the third memory 184 are made equal.

  The access element 178 specifies an arbitrary address A in the second memory 182 and the third memory 184 by outputting the address A to the address line of the common bus 176, and directly controls only the / RD signal of the second memory 182. As a result, the data B of the second memory 182 is read to the data line of the common bus 176. However, other permission signals such as CS (Chip Select) are omitted here.

  While the address A is output to the address line of the common bus 176 and the data B is output to the data line of the common bus 176, the access element 178 directly receives only the / WR signal of the third memory 184. By controlling, the data B output to the data line of the common bus 176 can be written in the third memory 184.

  Conventionally, data reading and writing have been performed at different timings. In the present embodiment, since data can be performed at the same timings, data transfer can be speeded up and backup processing can be shortened. be able to. Also, the time required for shortening can be used for other backup processing. Furthermore, since the data transfer load can be reduced, the power consumed for backup processing can be greatly reduced. Therefore, the capacity of the capacitor 156a can be reduced, which is advantageous in terms of exclusive area and cost.

  As described above, according to the programmable controller 120 described above, it is possible to devise a backup processing procedure and avoid an unnecessary increase in the capacity of the capacitor 156a.

  Specifically, the maximum time allowed for backup can be extended by delaying the timing of receiving power supply from the capacitor 156a for power supply when the power source 148 is cut off. Further, even when data that needs to be backed up increases, the backup can be performed stably and reliably without increasing the capacitance of the capacitor 156a. On the other hand, when there is no increase in data that needs to be backed up, the capacity of the capacitor 156a can be changed to be small, and the occupied area and cost can be reduced.

  Also in the backup process, the access element 178 performs a data transfer process independently of the processor 170, whereby the processor 170 can be shifted to the power saving mode and power consumption can be reduced. In the backup process, it is possible to further reduce time and reduce power consumption by matching the timing of reading and writing.

  As mentioned above, although preferred embodiment of this invention was described referring an accompanying drawing, it cannot be overemphasized that this invention is not limited to this embodiment. It will be apparent to those skilled in the art that various changes and modifications can be made within the scope of the claims, and these are naturally within the technical scope of the present invention. Is done.

  Note that each step of the power-off countermeasure method of the present specification does not necessarily have to be processed in time series in the order described in the flowchart, and may include parallel or subroutine processing.

  INDUSTRIAL APPLICABILITY The present invention can be used for a programmable controller that can program control processing for a controlled device, and a power-off countermeasure method when power is turned off.

DESCRIPTION OF SYMBOLS 100 ... Programmable control system 110 ... Management apparatus 120 ... Programmable controller 130 ... Controlled device 148 ... Power supply 156a ... Capacitor 156b ... 2nd diode (diode for backflow prevention)
156c ... switch 158 ... power detection unit 160 ... power supply line 170 ... processor 176 ... common bus 178 ... access element 182 ... second memory (backed up memory)
184 ... Third memory (backup memory)

Claims (7)

Backed up memory that can be controlled through a common bus;
A backup memory controllable through the common bus;
A processor connected to the common bus and operating based on a control program;
Dedicated memory accessible only by the processor;
An access element connected to the backup memory and the backup memory through the common bus;
A power detection unit for detecting that the power supply voltage is less than a predetermined first threshold;
With
It said access element, Ri supply voltage Do and less than the first threshold value, the processor, after saving the data of the dedicated memory to the backup memory, the operation mode of the processor, consumes less power than the normal mode It is shifted to the power saving mode, the programmable controller, wherein Rukoto retracts the data of the object to be backed up memory to the backup memory. The programmable controller of claim 1 power consumption of the access device, characterized in that less than the power consumption of the processor. The power supply line from the power supply further includes a capacitor for storing power, connected via a backflow prevention diode and a switch,
The power detection unit detects that the power supply voltage is less than the first threshold, and in addition, is less than the second threshold smaller than the first threshold,
The switch maintains the capacitor and the main circuit including the processor and the access element in a disconnected state while a power supply voltage is equal to or higher than the second threshold, and when the power supply voltage becomes lower than the second threshold, the programmable controller of claim 1 or 2, characterized in that a capacitor and said main circuit. A power storage capacitor connected to a power supply line from the power supply via a switch;
The power detection unit detects that the power supply voltage is less than the first threshold, and in addition, is less than the second threshold smaller than the first threshold,
The switch maintains the capacitor and the main circuit including the processor and the access element in a disconnected state while the power supply voltage is less than the first threshold and greater than or equal to the second threshold, and the power supply voltage is the first threshold. above or while the is less than the second threshold value, the programmable controller according to claim 1 or 2, characterized in that for connecting the capacitor and the main circuit. Said access device, reads the data of the object to be backed up memory, while the data is being output to the common bus, any of claims 1 to 4, characterized in that writing the data into the backup memory The programmable controller of Claim 1 . A backed up memory that can be controlled through a common bus, a backup memory that can be controlled through the common bus, a processor connected to the common bus and operating based on a control program, and a dedicated memory accessible only by the processor , In a programmable controller comprising: the memory to be backed up; an access element connected to the backup memory through the common bus; and a power detection unit that detects that a power supply voltage is less than a predetermined first threshold value.
When the power supply voltage is less than the first threshold, the processor saves the data in the dedicated memory to the backup memory,
The access element is
Supply voltage Ri is Do less than the first threshold value, the processor, after said data-only memory has been saved in the backup memory, shifts the operation mode of the processor, the less the power saving mode power consumption than the normal mode Let
Read data from the backed up memory,
A method for coping with power-off, wherein the data is written to the backup memory. 7. The power supply according to claim 6 , wherein the access element reads data from the memory to be backed up and writes the data to the backup memory while the data is being output to the common bus. How to deal with disconnection.

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