JP5877814B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

A semiconductor device (also referred to as a non-contact signal processing device, a semiconductor integrated circuit substrate chip, or an IC chip) that transmits and receives data by wireless communication via an antenna is made smaller and thinner.

However, such a reduction in size and thickness has a problem of reducing the strength of the semiconductor device, and a countermeasure for this has been reported (for example, see Patent Document 1).

Patent Document 1 is an example in which the size of a semiconductor chip is limited to 0.5 mm or less as a countermeasure against bending and concentrated load.

Japanese Patent Laid-Open No. 2004-78991

As the market for the semiconductor device expands, the demands on its shape and required characteristics vary. Therefore, there is a need for a semiconductor device that has higher resistance to external stress and has the required characteristics.

Accordingly, an object is to provide a highly reliable semiconductor device that is resistant to external stress while achieving thinning and miniaturization. Another object is to prevent a defect in shape and characteristics due to external stress in a manufacturing process and to manufacture a semiconductor device with high yield. Another object is to manufacture a semiconductor device at low cost and high productivity.

In the semiconductor device of the present invention, a semiconductor integrated circuit substrate formed using a single crystal semiconductor substrate is sealed between a pair of impact resistant layers. The semiconductor integrated circuit substrate is disposed at the center between the pair of impact resistant layers, and the opposing impact resistant layers are directly bonded to each other at the peripheral end of the impact resistant layer.

Further, an impact diffusion layer may be provided outside the impact resistant layer (opposite side of the semiconductor integrated circuit substrate).

By providing an impact resistant layer against an external force applied to the semiconductor device (also referred to as external stress) and an impact diffusion layer that diffuses the force, the force applied locally can be reduced. It becomes possible to prevent a characteristic defect.

As the impact resistant layer, a structure in which a fibrous body is impregnated with an organic resin can be used. The impact resistant layer preferably has an elastic modulus of 13 GPa or more and a fracture modulus of less than 300 MPa.

As the impact diffusion layer, it is preferable to use a material having a low elastic modulus and a high breaking strength,
A film having rubber elasticity may be used. The impact diffusion layer preferably has an elastic modulus of 5 GPa or more and 12 GPa or less and a fracture modulus of 300 MPa or more.

The impact diffusion layer is preferably formed of a high strength material. Typical examples of high-strength materials include polyvinyl alcohol resins, polyester resins, polyamide resins, polyethylene resins, aramid resins, polyparaphenylene benzobisoxazole resins, glass resins, and the like. When an impact diffusion layer formed of a high-strength material having elasticity is provided, a load such as local pressing is diffused and absorbed throughout the layer, so that damage to the semiconductor device can be prevented.

More specifically, as the impact diffusion layer, aramid resin, polyethylene naphthalate (PEN)
) Resin, polyethersulfone (PES) resin, polyphenylene sulfide (PPS)
) Resin, polyimide (PI) resin, or the like.

Further, a conductive shield may be provided in the semiconductor device of the present invention. Since the conductive shield can be provided on the outermost surface of the semiconductor device, the conductive shield may be provided on the outer surface (opposite side of the semiconductor integrated circuit substrate) of the pair of impact resistant layers. When an impact diffusion layer is provided further outside the impact resistant layer, a conductive shield can be provided on the outer surface of the impact diffusion layer.

The conductive shield diffuses and releases the static electricity applied by electrostatic discharge, or prevents local existence (localization) of electric charges (to prevent local potential difference from occurring). It can prevent electrostatic breakdown. The conductive shield is formed so as to cover (overlap) both surfaces of the semiconductor integrated circuit via an impact-resistant layer that is an insulator.

By using the present invention, a non-contact signal processing device having a function of transmitting / receiving a signal to / from an external device by wireless communication can be manufactured. In this case, the conductive shield transmits an electromagnetic wave to be transmitted and received by the antenna included in the semiconductor device, and blocks external static electricity from being applied to the semiconductor integrated circuit inside the semiconductor device. Therefore, it is possible to provide a highly reliable semiconductor device that is resistant to electrostatic breakdown and that can transmit and receive data by wireless communication via an antenna.

Note that the conductive shield is not electrically connected to the antenna and the semiconductor integrated circuit.

One embodiment of a semiconductor device according to the present invention includes a structure in which a first fibrous body provided so as to face each other is impregnated with an organic resin, and a structure in which a second fibrous body is impregnated with an organic resin, First to
And a semiconductor integrated circuit substrate provided between the structure in which the fibrous body is impregnated with the organic resin and the structure in which the second fibrous body is impregnated with the organic resin. A structure including a semiconductor substrate, in which a first fibrous body is impregnated with an organic resin and a second fibrous body impregnated with an organic resin, a semiconductor integrated circuit substrate is disposed at the center, and at the end The semiconductor integrated circuit substrates are sealed by bonding to each other.

One embodiment of a semiconductor device according to the present invention includes a structure in which a first fibrous body provided so as to face each other is impregnated with an organic resin, and a structure in which a second fibrous body is impregnated with an organic resin, First to
And a semiconductor integrated circuit substrate provided between the structure body in which the fibrous body is impregnated with the organic resin and the structure body in which the second fiber body is impregnated with the organic resin, and the first fiber body is organic The first impact diffusion layer and the second impact diffusion layer provided on the surface opposite to the semiconductor integrated circuit substrate of the structure impregnated with resin and the structure impregnated with organic resin in the second fibrous body, respectively The semiconductor integrated circuit board includes a single crystal semiconductor substrate, and the structure body in which the first fiber body is impregnated with the organic resin and the structure body in which the second fiber body is impregnated with the organic resin are the central portion. The semiconductor integrated circuit substrate is disposed on the substrate and bonded to each other at the end portion to seal the semiconductor integrated circuit substrate.

In the above structure, an antenna that receives or transmits a signal to the outside may be provided in the semiconductor device. For example, an antenna may be provided between the semiconductor integrated circuit substrate and the first impact resistant layer. Further, a protective layer may be provided over the semiconductor integrated circuit substrate. For example, an inorganic insulating layer may be formed as a protective layer so as to cover the antenna provided over the integrated circuit substrate.

Note that in the present invention, a semiconductor device refers to a device that can function by utilizing semiconductor characteristics. By using the present invention, a device having a circuit including a semiconductor element (a transistor, a memory element, a diode, or the like) or a semiconductor device such as a chip having a processor circuit can be manufactured.

A pair of impact-resistant layers sandwiching the semiconductor integrated circuit can provide a highly reliable semiconductor device having durability while achieving a reduction in thickness and size. Further, also in the manufacturing process, a defect in shape and characteristics due to external stress can be prevented, and a semiconductor device can be manufactured with high yield.

6A and 6B illustrate a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A and 8B illustrate an application example of a semiconductor device of the invention. 6A and 6B illustrate a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. FIG. 11 is a block diagram illustrating a structure of a microprocessor obtained by the semiconductor device of the invention. FIG. 6 is a block diagram illustrating a configuration of an RFCPU obtained by the semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention.

Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in structures of the present invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated.

(Embodiment 1)
In this embodiment, a highly reliable semiconductor device and a method for manufacturing a semiconductor device with high yield will be described in detail with reference to FIGS.

In the semiconductor device in this embodiment, the semiconductor integrated circuit substrate is sandwiched between flexible impact-resistant layers.

1A and 1B show a semiconductor device of this embodiment mode. In FIG. 1, a semiconductor integrated circuit substrate 100 is sealed with a first impact resistant layer 112 and a second impact resistant layer 102.

FIG. 1B illustrates an antenna 10 that receives or transmits signals to and from the outside of the semiconductor device illustrated in FIG.
1 is an example. An antenna 101 that is electrically connected to the semiconductor integrated circuit substrate 100 is provided between the semiconductor integrated circuit substrate 100 and the first impact-resistant layer 112. The semiconductor device in FIG. 1B can function as a non-contact signal processing device having a function of transmitting and receiving signals to and from an external device through wireless communication.

As in this embodiment, by providing an impact-resistant layer against a force (also referred to as external stress) applied from the outside to the semiconductor device, the force applied locally can be reduced.
It is possible to increase the strength of the semiconductor device and prevent damage or defective characteristics.

As the impact resistant layer, a structure in which a fibrous body is impregnated with an organic resin can be used. A structure in which a fibrous body is impregnated with an organic resin is used for the first impact resistant layer 112 and the second impact resistant layer 102.

The first impact-resistant layer 112 and the second impact-resistant layer 102 use a structure in which a fibrous body is impregnated with an organic resin, and the first impact-resistant layer 112 has a fibrous body 160 in which an organic resin 161 is impregnated. The second impact-resistant layer 102 is a structure in which a fibrous body 150 is impregnated with an organic resin 151.

FIG. 1C shows a plan view of a woven fabric in which the fibrous body 160 is woven using a fiber yarn bundle as warps and wefts.

As shown in FIG. 1 (C), the fibrous body 160 is woven with warps spaced at regular intervals and wefts spaced at regular intervals. A fiber body woven using such warps and wefts has a region where no warp and wefts exist. In such a fibrous body 160, the ratio of impregnation with the organic resin 161 is increased, and adhesion between the fibrous body 160 and the semiconductor integrated circuit can be improved.

The fibrous body 160 may have a high density of warps and wefts and a low ratio of regions where there are no warps and wefts.

A structure body in which the fibrous body 160 is impregnated with the organic resin 161 is also called a prepreg. Specifically, the prepreg is obtained by impregnating a fiber body with a varnish obtained by diluting a matrix resin with an organic solvent, and drying to volatilize the organic solvent and semi-curing the matrix resin. The thickness of the structure is preferably 10 μm or more and 100 μm or less, and more preferably 10 μm or more and 30 μm. By using a structure with such a thickness, a thin semiconductor device that can be bent can be manufactured. For example, a prepreg having an elastic modulus of 13 GPa or more and 15 GPa or less and a breaking coefficient of 140 MPa can be used as the impact resistant layer.

Note that a structure body in which a fibrous body is impregnated with an organic resin may have a plurality of layers. In this case, a structure may be formed by laminating a plurality of structures in which a single-layer fiber body is impregnated with an organic resin, or a structure in which a plurality of laminated fiber bodies are impregnated with an organic resin. It may be used. In addition, when a plurality of structures in which a single-layer fiber body is impregnated with an organic resin are stacked, another layer may be sandwiched between the structures.

Further, as the organic resin 161, an epoxy resin, an unsaturated polyester resin, a polyimide resin,
A thermosetting resin such as a bismaleimide triazine resin or a cyanate resin can be used. Alternatively, as the organic resin 161, a thermoplastic resin such as a polyphenylene oxide resin, a polyetherimide resin, or a fluororesin can be used. Organic resin 161
As the above, a plurality of the thermoplastic resin and the thermosetting resin may be used. By using the organic resin, the fiber body can be fixed to the semiconductor integrated circuit by heat treatment. Note that the higher the glass transition temperature of the organic resin 161 is, the more difficult it is to break against local pressing.

A high thermal conductive filler may be dispersed in the organic resin 161 or in a fiber bundle. Examples of the high thermal conductive filler include aluminum nitride, boron nitride, silicon nitride, and alumina. Moreover, metal particles, such as silver and copper, are mentioned as a highly heat conductive filler. The inclusion of the conductive filler in the organic resin or fiber yarn bundle makes it easier to release the heat generated in the semiconductor integrated circuit to the outside, so it is possible to suppress the heat storage of the semiconductor device and reduce the destruction of the semiconductor device. can do.

The fibrous body 160 is a woven or non-woven fabric using high-strength fibers of an organic compound or an inorganic compound, and is arranged so as to partially overlap. Specifically, the high-strength fiber is a fiber having a high tensile elastic modulus or Young's modulus. Typical examples of high-strength fibers include polyvinyl alcohol fibers, polyester fibers, polyamide fibers, polyethylene fibers, aramid fibers, polyparaphenylene benzobisoxazole fibers, glass fibers, or carbon fibers. Examples of the glass fiber include glass fibers using E glass, S glass, D glass, Q glass, and the like. The fiber body 160 may be formed of one type of the above high-strength fibers.
Moreover, you may form with the said some high strength fiber.

The fibrous body 160 is a woven fabric obtained by weaving a bundle of fibers (single yarn) (hereinafter referred to as a yarn bundle) for warp and weft, or a yarn bundle of a plurality of types of fibers is randomly or unidirectionally deposited. It may be a non-woven fabric. In the case of a woven fabric, a plain weave, twill weave, a weave can be used as appropriate.

The cross section of the yarn bundle may be circular or elliptical. As the fiber yarn bundle, a fiber yarn bundle that has been opened by high pressure water flow, high-frequency vibration using a liquid medium, continuous ultrasonic vibration, pressing with a roll, or the like may be used. The fiber yarn bundle subjected to the fiber opening process has a wide yarn bundle width and can reduce the number of single yarns in the thickness direction, and the cross section of the yarn bundle is elliptical or flat. Further, by using a low twist yarn as the fiber yarn bundle, the yarn bundle is easily flattened, and the cross-sectional shape of the yarn bundle becomes an elliptical shape or a flat plate shape. Thus, the fiber body 16 can be obtained by using an elliptical or flat thread bundle.
It is possible to make 0 thinner. Therefore, the structure can be thinned and a thin semiconductor device can be manufactured.

In the drawings of the present embodiment, the fibrous body 160 is shown as a woven fabric that is plain-woven with a bundle of threads having an elliptical cross section.

Further, in order to increase the penetration rate of the organic resin into the fiber yarn bundle, the fiber may be subjected to a surface treatment. For example, there are corona discharge treatment and plasma discharge treatment for activating the fiber surface. Moreover, there exists surface treatment using a silane coupling agent and a titanate coupling agent.

Further, a protective layer may be formed on the semiconductor integrated circuit. For example, the semiconductor integrated circuit board 100
The antenna 101 may be formed over and an inorganic insulating layer may be formed over the antenna 101 as a protective layer. By covering the antenna 101 with the inorganic insulating layer, oxidation of the conductive layer functioning as the antenna can be prevented.

The inorganic insulating layer is formed as a single layer or a stacked layer using an inorganic compound by a sputtering method, a plasma CVD method, a coating method, a printing method, or the like. As a typical example of the inorganic compound, silicon oxide or silicon nitride can be given. Typical examples of silicon oxide and silicon nitride include silicon oxide, silicon oxynitride, silicon nitride, and silicon nitride oxide. Note that in this specification, the silicon oxynitride film has a higher oxygen content than nitrogen in the composition, and the concentration ranges of oxygen are 55 to 65 atomic%, nitrogen is 1 to 20 atomic%, Si is 25 to 35 atomic%, hydrogen is 0.1
The thing contained in the range of -10 atomic%. In addition, the silicon nitride oxide film has a composition containing more nitrogen than oxygen, and the concentration range of oxygen is 15 to 30 atomic%.
, Nitrogen is included in the range of 20 to 35 atomic%, Si is included in the range of 25 to 35 atomic%, and hydrogen is included in the range of 15 to 25 atomic%.

Furthermore, the inorganic insulating layer may have a laminated structure. For example, the layers may be stacked using an inorganic compound, and typically, silicon oxide, silicon nitride oxide, and silicon oxynitride may be stacked.

A method for manufacturing a semiconductor device of the present invention will be described with reference to FIGS. A semiconductor integrated circuit substrate 111 is formed (see FIG. 2A). The semiconductor integrated circuit substrate 111 is formed using a semiconductor substrate (semiconductor wafer). As the semiconductor substrate, a single crystal semiconductor substrate or a polycrystalline semiconductor substrate can be used, and a semiconductor wafer such as a silicon wafer or a germanium wafer, or a compound semiconductor wafer such as gallium arsenide or indium phosphide is used. In this embodiment mode, a single crystal silicon substrate is used. A silicon nitride film may be formed on the semiconductor integrated circuit substrate 111 as an antenna and an inorganic insulating layer.

Since the structure body in which the fibrous body 160 is impregnated with the organic resin 161 is used as the first impact resistant layer 112, the structure body can be heated and pressed to plasticize or cure the organic resin of the structure body. When the organic resin is a plastic organic resin, the plasticized organic resin is cured by cooling to room temperature. The organic resin is uniformly spread and cured by heating and pressure bonding so as to be in close contact with the semiconductor integrated circuit. The step of pressure-bonding the structure is performed under atmospheric pressure or reduced pressure. The first impact-resistant layer 112 is heated and pressure-bonded to the semiconductor integrated circuit substrate 111, and the semiconductor integrated circuit substrate 111 is bonded to the first impact-resistant layer 112 (see FIG. 2B).

Next, the exposed surface of the semiconductor integrated circuit substrate 111 is ground and polished to reduce the thickness of the semiconductor integrated circuit substrate 111 to obtain a thinner semiconductor integrated circuit substrate 100 (see FIG. 2C).
).

The step of polishing the semiconductor integrated circuit substrate to reduce the thickness (thinning step) can be performed by suitably combining a polishing machine, a grinding machine, and the like. Further, chemical mechanical polishing may be performed as the polishing treatment. The thickness of the semiconductor integrated circuit substrate 100 is preferably reduced to about 50 nm to 5 μm.

Since the second impact-resistant layer 102 also uses a structure body in which the fibrous body 150 is impregnated with the organic resin 151, the structure body can be heated and pressed to plasticize or cure the organic resin of the structure body. The second impact-resistant layer 102 is heated and pressure-bonded to the semiconductor integrated circuit substrate 100, so that the second impact-resistant layer 102 is bonded to the semiconductor integrated circuit substrate 100 (see FIG. 2D).

As shown in FIG. 2D, the first impact-resistant layer 112 and the second impact-resistant layer 102 have the semiconductor integrated circuit substrate 100 disposed at the center, and the end portions where the semiconductor integrated circuit substrate 100 does not exist are mutually connected. The semiconductor integrated circuit substrate 100 is sealed in contact therewith.

As shown in FIG. 2, the thinning process may be performed after the semiconductor substrate is divided into chips for each semiconductor integrated circuit substrate 100, or the thinning process is performed on the semiconductor substrate on which a plurality of semiconductor integrated circuit substrates are manufactured. It may be divided into chips. FIGS. 3A to 3F show an example in which the thinning process is performed on a semiconductor substrate on which a plurality of semiconductor integrated circuit substrates are manufactured.

A semiconductor substrate 172 over which a plurality of semiconductor integrated circuit substrates are formed is formed (see FIG. 3A).
). Next, the semiconductor substrate 172 is fixed to the fixing tape 176 that fixes the semiconductor substrate 172 at the time of the thinning process with the semiconductor integrated circuit side facing, and the semiconductor substrate 172 is processed into a thin semiconductor substrate 173 ( (See FIG. 3B).

The semiconductor substrate 173 is divided into individual semiconductor integrated circuit substrates 100 (see FIG. 3C).
The dividing means is not particularly limited as long as it can be physically divided (cut), and a cutting device such as a dicer or a wire saw, laser cutting, plasma cutting, electron beam cutting, or any other dividing (cutting) means may be used. it can.

The divided semiconductor integrated circuit substrate 100 is bonded to the first impact-resistant layer 112 by heating and pressing,
A stacked body 174 is formed (see FIG. 3D). The stacked body 174 is divided into individual semiconductor integrated circuit substrates 100, and a semiconductor device including the semiconductor integrated circuit substrate chips 175a, 175b, and 175c can be manufactured (see FIG. 3F). By dividing, the semiconductor integrated circuit substrate 100 is sealed by the first impact resistant layer 112 and the second impact resistant layer 102. Therefore, the semiconductor integrated circuit substrate chips 175a, 175b, and 175c chips are divided (divided). Therefore, the semiconductor integrated circuit substrate 100 is not exposed.

In addition, when a pair of impact-resistant layers are provided symmetrically with respect to the semiconductor integrated circuit substrate as in the present embodiment, the force applied to the semiconductor device can be more uniformly diffused, so that the semiconductor integrated circuit caused by bending or warping Damage to the substrate can be further prevented. In this effect, when a pair of impact-resistant layers are made of the same material and the same film thickness, since the same characteristics can be imparted, the force diffusion effect is further enhanced.

As described above, a pair of impact-resistant layers sandwiching the semiconductor integrated circuit can provide a highly reliable semiconductor device having durability while achieving thinning and downsizing. Further, also in the manufacturing process, a defect in shape and characteristics due to external stress can be prevented, and a semiconductor device can be manufactured with high yield.

(Embodiment 2)
In this embodiment mode, a semiconductor device intended to provide high reliability using the present invention,
Another example of a method for manufacturing a semiconductor device will be described with reference to FIGS. In the structure of this embodiment described below, the same portions as those in Embodiment 1 or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated.

In the present embodiment, an example in which an impact diffusion layer is further provided outside the impact resistant layer for sealing the semiconductor integrated circuit substrate (on the side opposite to the semiconductor integrated circuit substrate) will be described.

In FIG. 4, the antenna 101 and the semiconductor integrated circuit substrate 100 connected to the antenna 101.
Is sealed by the first impact resistant layer 112 and the second impact resistant layer 102, and the first impact resistant layer 1 is sealed.
A first impact diffusion layer 113 and a second impact diffusion layer 103 are provided on the outer side of 12 and the second impact resistant layer 102 (on the side opposite to the semiconductor integrated circuit substrate 100).

The impact diffusion layer has an effect of diffusing and reducing the force applied to the semiconductor integrated circuit substrate from the outside. Therefore, as in this embodiment, by providing an impact resistant layer against an external force applied to the semiconductor device (also referred to as external stress) and an impact diffusion layer that diffuses the force, the force applied locally can be further increased. Since it can be reduced, it is possible to increase the strength of the semiconductor device and to prevent damage or defective characteristics.

As shown in FIG. 4, as the first impact resistant layer 112 and the second impact resistant layer 102, a structure body in which a fibrous body is impregnated with an organic resin is used. The first impact resistant layer 112 and the second impact resistant layer 102 preferably have an elastic modulus of 13 GPa or more and a fracture modulus of less than 300 MPa. In this embodiment mode, an epoxy resin is used as the organic resin for the first impact resistant layer 112 and the second impact resistant layer 102.

The first impact diffusion layer 113 and the second impact diffusion layer 103 are composed of the first impact resistant layer 112 and the second impact diffusion layer 103, respectively.
It is preferable that the elastic modulus is lower than that of the impact resistant layer 102 and the breaking strength is higher. In this embodiment, an aramid film using an aramid resin is used as the first impact diffusion layer 113 and the second impact diffusion layer 103.

As the first impact diffusion layer 113 and the second impact diffusion layer 103, it is preferable to use a material having a low elastic modulus and a high breaking strength. For example, as the first impact diffusion layer 113 and the second impact diffusion layer 103, a film having rubber elasticity having an elastic modulus of 5 GPa or more and 12 GPa or less and a fracture coefficient of 300 MPa or more can be used.

The first impact diffusion layer 113 and the second impact diffusion layer 103 are preferably made of a high-strength material. Typical examples of high-strength materials include polyvinyl alcohol resins, polyester resins, polyamide resins, polyethylene resins, aramid resins, polyparaphenylene benzobisoxazole resins, glass resins, and the like. If the first impact diffusion layer 113 and the second impact diffusion layer 103 formed of a high-strength material having elasticity are provided, a load such as local pressing is diffused and absorbed throughout the layer, so that the semiconductor device is damaged. Can be prevented.

More specifically, as the first impact diffusion layer 113 and the second impact diffusion layer 103, an aramid resin, a polyethylene naphthalate (PEN) resin, a polyethersulfone (PES) resin, a polyphenylene sulfide (PPS) resin, Polyimide (PI) resin or the like can be used. In the present embodiment, an aramid resin film (elastic modulus 10 GPa, breaking strength 480 MPa) is used as the second impact diffusion layer 103.

The first impact resistant layer 112, the first impact diffusion layer 113, the second impact resistant layer 102, and the second impact diffusion layer 103 are bonded together by the first impact resistant layer 112 and the second impact resistant layer. In order to use a prepreg which is a structure in which a fibrous body is impregnated with an organic resin, it can be bonded directly by heating and pressing without using an adhesive layer.

A method for manufacturing the semiconductor device of this embodiment will be described with reference to FIGS. An antenna 101 and a semiconductor integrated circuit substrate 111 are formed (see FIG. 4A). Antenna 10
A silicon nitride film may be formed on 1 as an inorganic insulating layer.

Since the structure body in which the fibrous body 160 is impregnated with the organic resin 161 is used as the first impact resistant layer 112, the structure body can be heated and pressed to plasticize or cure the organic resin of the structure body. The first impact diffusion layer 113 and the first impact resistant layer 112 are heated and pressed against the antenna 101 and the semiconductor integrated circuit substrate 111, so that the first impact diffusion layer 113 and the first impact resistant layer 112 are
The antenna 101 and the semiconductor integrated circuit substrate 111 are attached (see FIG. 4B).

Next, the exposed surface of the semiconductor integrated circuit substrate 111 is ground and polished to reduce the thickness of the semiconductor integrated circuit substrate 111, so that the semiconductor integrated circuit substrate 100 is thinner (see FIG. 4C).
). As in this embodiment, the semiconductor substrate may be divided into chips in each semiconductor integrated circuit substrate 100, and the thinning process may be performed, or the semiconductor substrate in which a plurality of semiconductor integrated circuit substrates are manufactured may be subjected to the thinning process. And then cut into chips.

Since the second impact-resistant layer 102 also uses a structure body in which the fibrous body 150 is impregnated with the organic resin 151, the structure body can be heated and pressed to plasticize or cure the organic resin of the structure body. The second impact diffusion layer 103 and the second impact resistant layer 102 are heated and pressure-bonded to the semiconductor integrated circuit substrate 100, and the second impact diffusion layer 103 and the second impact resistant layer 102 are applied to the semiconductor integrated circuit substrate 100. Are bonded (see FIG. 4D).

As shown in FIG. 4D, the first impact-resistant layer 112 and the second impact-resistant layer 102 have the semiconductor integrated circuit substrate 100 arranged at the center, and the end portions where the semiconductor integrated circuit substrate 100 does not exist are mutually connected. The semiconductor integrated circuit substrate 100 is sealed in contact therewith.

In addition to the effect of increasing the strength against external stress of the semiconductor device, the impact diffusion layer diffuses force even in the pressure treatment in the manufacturing process, so that the semiconductor integrated circuit substrate 100 is damaged or has poor characteristics. Does not adversely affect. Accordingly, a semiconductor device can be manufactured with high yield.

Further, when a pair of impact resistant layers and a pair of impact diffusion layers are provided symmetrically with respect to the semiconductor integrated circuit substrate 100 as in the present embodiment, the force applied to the semiconductor device can be more uniformly diffused, so that bending and warping are performed. It is possible to further prevent damage to the semiconductor integrated circuit substrate caused by the above. In this effect, when a pair of impact-resistant layers and impact diffusion layers are produced with the same material and the same film thickness, the same characteristics can be imparted, so that the force diffusion effect is further enhanced.

This embodiment can be combined with any of the other embodiments as appropriate.

In this embodiment, a pair of impact resistant layers and impact diffusion layers for sealing a semiconductor integrated circuit substrate can provide a highly reliable semiconductor device having durability while achieving thinning and downsizing. Further, also in the manufacturing process, a defect in shape and characteristics due to external stress can be prevented, and a semiconductor device can be manufactured with high yield.

(Embodiment 3)
In this embodiment mode, a semiconductor device intended to provide high reliability using the present invention,
Another example of a method for manufacturing a semiconductor device will be described with reference to FIGS. In the structure of this embodiment described below, the same portions as those in Embodiment 1 or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated.

In this embodiment, an example in which a conductive shield is provided in a semiconductor device is described. Since the conductive shield can be provided on the outermost surface of the semiconductor device, the conductive shield may be provided on the outer surface (opposite side of the semiconductor integrated circuit substrate) of the pair of impact resistant layers. In the case where the impact diffusion layer is provided further outside the impact resistant layer as shown in Embodiment 2, a conductive shield can be provided on the outer surface of the impact diffusion layer.

The conductive shield diffuses and releases the static electricity applied by electrostatic discharge, or prevents the local existence (localization) of electric charges (so as not to cause a local potential difference). Can prevent electrostatic breakdown. The conductive shield is formed so as to cover (overlap) both surfaces of the semiconductor integrated circuit substrate via the impact resistant layer.

As the semiconductor device of the present invention, a non-contact signal processing device having a function of transmitting / receiving a signal to / from an external device by wireless communication can be manufactured. In this case, the conductive shield transmits electromagnetic waves to be transmitted / received by the antenna included in the semiconductor device, and blocks external static electricity from being applied to the semiconductor integrated circuit substrate inside the semiconductor device.

Note that the conductive shield is not electrically connected to the antenna and the semiconductor integrated circuit board.

Such a conductive shield is formed of a material having a film thickness and a material that transmits an electromagnetic wave to be transmitted and received by the sandwiched antenna and the semiconductor integrated circuit substrate and blocks static electricity. Therefore, it is possible to provide a highly reliable semiconductor device that is resistant to electrostatic breakdown and that can transmit and receive data by wireless communication via an antenna.

The conductive shield is provided over the entire region overlapping the semiconductor integrated circuit so as to cover at least the semiconductor integrated circuit.

The conductive shield may be provided on the surfaces of both the first impact resistant layer and the second impact resistant layer in the semiconductor device, or may be provided only on one of the surfaces.

FIG. 5A shows an example in which the conductive shield 140 is provided outside the second impact-resistant layer 102 (on the side opposite to the semiconductor integrated circuit substrate 100 side). FIG. 5B shows an example in which conductive shields 140a and 140b are provided outside the first impact resistant layer 112 and the second impact resistant layer 102, respectively. Note that in FIG. 5B, the conductive shields 140a and 140b are not electrically connected.

When a conductive shield is provided on each of the first impact resistant layer side and the second impact resistant layer side, the conductive shields may be formed so as to be electrically connected to each other.

The conductive shield may be formed so as to cover the entire periphery (upper surface, lower surface, and side surfaces) of the semiconductor device (so as to enclose the semiconductor device), or a pair of conductive shields provided on the outer sides of the respective impact resistant layers. A conductive region which is electrically connected may be formed. The conductive region may be a part of the side surface of the semiconductor device, or may be an electrode layer that penetrates the inside of the semiconductor device. In the semiconductor device, the side surface is a cut surface (divided cross section) generated when a plurality of semiconductor integrated circuit substrate chips provided on the same impact-resistant layer are cut (divided) into individual chips. The cut surface may be entirely covered or partially covered by the conductive shield.

FIG. 6A illustrates an example in which the conductive shield 140 is formed so as to cover the entire periphery (upper surface (front surface), lower surface (back surface), and side surfaces) of the semiconductor device. FIG. 6B illustrates a structure in which the conductive shield 140 covers at least one side surface. FIG. 6C shows the conductive shield 1 formed on the surface.
40a and 140b are electrode layers 141a penetrating the inside of the semiconductor device. In FIG.
This is an example of electrical connection at 41a and 141b. The through-hole forming the electrode layer may be processed by a physical process such as a needle or a cone, or may be processed by a chemical process such as etching. Moreover, you may process using a laser beam.

In FIG. 6, since the semiconductor integrated circuit board 100 is provided with a conductive shield electrically connected to both the front surface and the back surface, the semiconductor integrated circuit substrate 100 is protected over a wide area against static electricity from the outside. A high effect of preventing electrostatic breakdown can be obtained.

FIG. 21 shows a specific example of the semiconductor device provided with the impact diffusion layer and the conductive shield according to the second embodiment.

In FIG. 21, a semiconductor integrated circuit substrate 100 is sealed with a first impact resistant layer 112 and a second impact resistant layer, and further, a first impact diffusion layer 113 is formed outside the first impact resistant layer 112. The second impact diffusion layer 103 is provided outside the second impact resistant layer 102. The conductive shield 140a is provided outside the first impact diffusion layer, and the conductive shield 1 is provided outside the second impact diffusion layer 103.
40b is provided. At least a part of the conductive shield 140a and the conductive shield 140b is electrically connected, and the conductive shield 140a and the conductive shield 1
40b is set to an equipotential.

By making the conductive shield 140a and the conductive shield 140b equipotential, an effect of protecting against static electricity can be obtained. Before the semiconductor integrated circuit substrate is destroyed by static charge, the upper and lower surfaces of the semiconductor device are equipotential to protect the semiconductor integrated circuit substrate.

In the semiconductor device of FIG. 21, the first impact resistant layer 112 and the second impact resistant layer 102 are a structure in which a fibrous body is impregnated with an organic resin, the first impact diffusion layer 113, and the second impact diffusion layer 103. Is an example using an aramid film and a titanium film for the conductive shields 140a and 140b. The thickness of the first impact resistant layer 112 and the second impact resistant layer 102 is 10 μm or more and 30 μm, the thickness of the first impact diffusion layer 113 and the second impact diffusion layer 103 is 3 μm or more and 15 μm or less, a semiconductor integrated circuit When the thickness of the substrate 100 is 50 nm or more and 5 μm or less, the first impact resistant layer 112, the second impact resistant layer 102, the first impact diffusion layer 113, and the second impact resistant layer 112 are compared with the thickness of the semiconductor integrated circuit substrate 100. Since the impact diffusion layer 103 is thick, the semiconductor integrated circuit substrate 100 is disposed almost at the center, thereby providing a semiconductor device that is resistant to bending stress.

The surface opposite to the antenna 101 with respect to the semiconductor integrated circuit substrate 100 is electrostatic discharge (ESD).
Therefore, the thickness of the conductive shield on the second impact resistant layer 102 side may be larger than that of the conductive shield on the first impact resistant layer 112 side.

The conductive shield may be formed by sputtering or the like on the surface of the impact resistant layer after sealing the semiconductor integrated circuit substrate between the impact resistant layers. When producing a conductive shield on both of the pair of impact resistant layers, it may be produced by a plurality of steps.

Further, as shown in the second embodiment, when an impact diffusion layer is further provided outside the impact resistant layer (on the side opposite to the semiconductor integrated circuit substrate), the impact diffusion layer is bonded before the impact diffusion layer is bonded to the impact resistant layer. A conductive shield may be formed thereon.

As the conductive shield, any conductive layer may be used as long as it has conductivity, and a conductive layer formed using a conductive material can be used.

As the conductive shield, a film of metal, metal nitride, metal oxide, or the like, and a stacked layer thereof can be used.

Examples of conductive shields include titanium, molybdenum, tungsten, aluminum, copper, silver,
An element selected from gold, nickel, platinum, palladium, iridium, rhodium, tantalum, cadmium, zinc, iron, silicon, germanium, zirconium, barium, or an alloy material, compound material, or nitride material containing the element as a main component The oxide material may be used.

As the nitride material, tantalum nitride, titanium nitride, or the like can be used.

As the oxide material, indium tin oxide (ITO), indium tin oxide containing silicon oxide (ITSO), organic indium, organic tin, zinc oxide, or the like can be used. Also,
Indium zinc oxide containing zinc oxide (ZnO) (IZO (Indium Zinc O
xide)), zinc oxide (ZnO), zinc oxide containing gallium (Ga), tin oxide (Sn)
O ₂ ), indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, or the like may be used.

Alternatively, a semiconductor film or the like in which an impurity element or the like is added to a semiconductor to impart conductivity can be used. For example, a polycrystalline silicon film doped with an impurity element such as phosphorus can be used.

Further, a conductive high molecule (also referred to as a conductive polymer) may be used as the conductive shield. As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. Examples thereof include polyaniline and / or a derivative thereof, polypyrrole and / or a derivative thereof, polythiophene and / or a derivative thereof, and a copolymer of two or more of these.

The conductive shield can be formed by various dry methods such as sputtering, plasma CVD, and vapor deposition, various wet methods such as coating, printing, and droplet discharge (inkjet). Various plating methods such as electrolytic plating and electroless plating may be used.

Further, a protective layer on the conductive shield may be laminated. For example, a titanium film may be formed as a conductive shield, and a titanium oxide film may be stacked as a protective layer on the titanium film. Even when the conductive shield is provided on the surface of the semiconductor device by the protective layer, the protective layer becomes the outermost surface, and deterioration of the conductive shield can be prevented.

In addition, the semiconductor device described in this embodiment operates by generating an induced electromotive force with an electromagnetic wave from the outside (having a wireless function). For this reason, it is necessary to form the conductive shield using a conductive material that prevents the semiconductor integrated circuit substrate from being destroyed by static electricity and transmits electromagnetic waves.

In general, it is known that electromagnetic waves are attenuated in a substance, and this attenuation is particularly remarkable in a conductive material. For this reason, in this Embodiment, a film thickness is made thin enough so that electromagnetic waves can permeate | transmit an electroconductive shield.

The film thickness of the conductive shield may be determined based on the frequency of electromagnetic waves used for communication and the resistivity and permeability of the conductive material used as the conductive shield.

For example, when the frequency of electromagnetic waves is 13.56 MHz and titanium (resistivity ρ: 5.5 × 10 ⁻⁷ (Ω · m)) is used as the conductive shield, the film thickness is at least about 500 nm or less. . This suppresses the destruction of the semiconductor device due to electrostatic discharge,
Good external communication can be performed.

Of course, the material used for the conductive shield is not limited to titanium. For example, in the case of using indium tin oxide containing silicon oxide having a higher resistivity than titanium (also referred to as ITSO), the film thickness may be at least about 700 nm.

Moreover, it is preferable to determine the lower limit of the film thickness of the conductive shield based on the resistivity. For example,
When the resistivity of the conductive material used as the conductive shield is high, it is preferable to form the conductive shield thick in order to effectively diffuse static electricity. If the conductive shield is made too thin using a conductive material with high resistivity, the sheet resistance will increase, and if electrostatic discharge occurs, static electricity cannot be effectively diffused, causing a large current to flow through the semiconductor integrated circuit board. This is because it may flow and be destroyed.

Therefore, in order to effectively prevent the destruction of the semiconductor device due to static electricity, the sheet resistance of the conductive shield is 1.0 × 10 ⁷ Ω / □ or less, preferably 1.0 × 10 ⁴ Ω / □ or less, More preferably, the film thickness is determined to be 1.0 × 10 ² Ω / □ or less. Also,
From the viewpoint of electromagnetic wave transmission, it is preferable to make the film thickness as small as possible while satisfying the sheet resistance. For example, when titanium is used, the thickness may be 1 nm or more, preferably about 10 nm to 30 nm. In the case of using indium tin oxide containing silicon oxide (also referred to as ITSO), the thickness can be 10 nm or more, and preferably 50 nm.
The thickness may be about nm to 200 nm.

By forming the conductive shield as described above, it is possible to obtain a semiconductor device that can effectively suppress the destruction of the semiconductor device due to electrostatic discharge and can satisfactorily communicate with the outside.

This embodiment can be combined with any of the other embodiments as appropriate.

The conductive shield covering the semiconductor integrated circuit board prevents electrostatic breakdown (malfunction of the circuit or damage of the semiconductor element) due to electrostatic discharge of the semiconductor integrated circuit board. In addition, a pair of impact-resistant layers that seal the semiconductor integrated circuit substrate can provide a highly reliable semiconductor device having durability while achieving thinning and downsizing. Further, also in the manufacturing process, defects in shape and characteristics due to external stress or electrostatic discharge can be prevented, and a semiconductor device can be manufactured with high yield.

(Embodiment 4)
In this embodiment mode, a semiconductor device intended to provide high reliability using the present invention,
Another example of a method for manufacturing a semiconductor device will be described with reference to FIGS. In the structure of this embodiment described below, the same portions or portions having the same functions as those in Embodiments 1 and 2 are denoted by the same reference numerals in different drawings, and description thereof is repeated. Is omitted.

In this embodiment, an example of another method for manufacturing a semiconductor device in which conductive shields that are electrically connected to both surfaces (an upper surface and a back surface) of the semiconductor device in Embodiment 3 are provided is illustrated in FIG. A
2) Shown in (B1) and (B2). 7, FIGS. 7A2 and 7B are plan views, and FIGS. 7A1 and 7B1 are cross-sectional views taken along line EF in FIGS. 7A2 and 7B2, respectively.

7A1 and 7A2 illustrate the semiconductor device of this embodiment in the manufacturing process. First impact diffusion layer 113, second impact diffusion layer 103, first impact resistant layer 112, and second impact resistant layer 102
Encapsulates a plurality of semiconductor integrated circuit substrates 100 and antennas 101 to form a laminate 144. The stacked body 144 is before being divided into individual chips and includes a plurality of semiconductor integrated circuit substrates 100. Sealed regions where the first impact resistant layer 112 and the second impact resistant layer 102 are in contact are provided between the plurality of semiconductor integrated circuit substrates 100, and the semiconductor integrated circuit substrates 100 are individually sealed.

On the outer surface of the first impact diffusion layer 113, which is the outermost surface of the laminate 144, the conductive shield 140 is provided.
a, Conductive shields 140b are formed on the outer surface of the second impact diffusion layer 103, respectively.

The stacked body 144 in which the conductive shield 140a and the conductive shield 140b are formed is divided into individual semiconductor integrated circuit substrate chips 145a, 145b, 145c, 145d, 145e, and 145f (see FIGS. 7B1 and 7B2). .) Semiconductor integrated circuit board chips 145a, 145b
145c, 145d, 145e, and 145f each have a stacked body 143 in which the stacked body 144 is divided.

In the present embodiment, the process of electrically connecting the conductive shield 140a and the conductive shield 140b is performed by a semiconductor device dividing process (dividing into individual semiconductor integrated circuit substrate chips). As the dividing means, means in which the first impact diffusion layer 113, the second impact diffusion layer 103, the first impact resistant layer 112, and the second impact resistant layer 102 are melted at the time of the division is used. Preferably (the conductive shields 140a and 140b are more preferably means for melting). In this embodiment mode, division by laser light irradiation is applied.

There are no particular limitations on the conditions such as the wavelength, intensity, and beam size of the laser light used in the dividing step. It is sufficient that the semiconductor device is separated at least. Examples of laser light oscillators include Ar laser, Kr laser, CO ₂ laser, YAG laser, YVO ₄ laser, YLF laser, YAlO ₃ laser, GdVO ₄ laser, Y ₂ O ₃ laser, ruby laser, alexandrite laser, Ti : Continuous wave laser such as sapphire laser, helium cadmium laser, Ar laser, Kr laser, excimer (ArF, KrF, XeCl)
Laser, CO ₂ laser, YAG laser, YVO ₄ laser, YLF laser, YAlO ₃ laser, GdVO ₄ laser, Y ₂ O ₃ laser, ruby laser, alexandrite laser, T
i: A pulsed laser such as a sapphire laser, a copper vapor laser, or a gold vapor laser can be used.

As shown in the present embodiment, each semiconductor integrated circuit substrate chip 1 is irradiated with laser light.
By dividing into 45a, 145b, 145c, 145d, 145e, and 145f, the resistance value between the conductive shield 140a and the conductive shield 140b decreases, and the conductive shield 140a.
And the conductive shield 140b are electrically connected to be equipotential. For this reason, the process of dividing into the semiconductor integrated circuit substrate chip and the process of electrically connecting the conductive shields 140a and 140b can be performed at a time.

The resistance value between the conductive shield 140a and the conductive shield 140b may be, for example, 1 GΩ or less, preferably about 5 MΩ to 500 MΩ, and more preferably 10 MΩ to 20
It is about 0 MΩ. Therefore, division by laser light irradiation processing or the like may be performed so as to satisfy such a condition.

Through the above process, the semiconductor integrated circuit substrate chip 145a, 1 as the semiconductor device of the present embodiment.
45b, 145c, 145d, 145e, and 145f can be manufactured.

This embodiment can be combined with any of the other embodiments as appropriate.

In this embodiment, the conductive shield covering the semiconductor integrated circuit substrate prevents electrostatic breakdown (malfunction of the circuit or damage of the semiconductor element) due to electrostatic discharge of the semiconductor integrated circuit. In addition, with the pair of impact resistant layers and impact diffusion layers that seal the semiconductor integrated circuit substrate, it is possible to provide a highly reliable semiconductor device having durability while achieving a reduction in thickness and size. Further, also in the manufacturing process, defects in shape and characteristics due to external stress or electrostatic discharge can be prevented, and a semiconductor device can be manufactured with high yield.

(Embodiment 5)
In this embodiment mode, a semiconductor device intended to provide high reliability using the present invention,
Another example of a method for manufacturing a semiconductor device will be described with reference to FIGS. In the structure of this embodiment described below, the same portions as those in Embodiment 1 or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated.

In the present embodiment, the contact region (sealing region) between the first impact resistant layer and the second impact resistant layer at the end portion of the semiconductor device is configured to further improve adhesion.

FIG. 8A corresponds to FIG. 2C of Embodiment 1, and the fibrous body 160 has the organic resin 16.
A semiconductor integrated circuit substrate 100 is bonded to a first impact resistant layer 112 which is a structure impregnated with 1.

The semiconductor integrated circuit substrate 100 is disposed in the center of the first impact resistant layer 112, and the end portion of the first impact resistant layer 112, which is a sealing region in the semiconductor device, is exposed. Next, a part of end portion of the first impact resistant layer 112 is removed and processed. The processing means may be physically performed by excision or the like, or may be chemically performed by an etching method (dry etching method or wet etching method). In this embodiment mode, processing is performed with laser beams 170a and 170b as shown in FIG. By the laser beams 170a and 170b, concave portions 171a and 171a
171b is formed.

Processing of the first impact resistant layer 112 in the sealing region of the present embodiment is performed in the second region in the sealing region.
This is because the contact area with the impact resistant layer 102 is increased to further improve the adhesion. Therefore, the shape of processing is not limited to this embodiment mode, and a plurality of recesses may be formed.

As shown in FIG. 8C, the second impact resistant layer 102 which is a structure in which the fibrous body 150 is impregnated with the organic resin 151 is heated in the first impact resistant layer 112 in which the concave portions 171a and 171b are formed. Bonding is performed by processing and pressure treatment. The second impact-resistant layer 102 which is a structure in which the fibrous body 150 is impregnated with the organic resin 151 has a fluidity because it is in a semi-cured state at the time of bonding, and the concave portions 171a and 171b of the first impact-resistant layer 112 are provided. Adhere to fill and harden.

In the semiconductor device of the present invention, the first impact resistant layer 112 and the second impact resistant layer 102 are in contact with each other in the sealing region at the end, thereby sealing the semiconductor integrated circuit substrate 100 inside (center). To do. Therefore, as in the present embodiment, a recess is formed in the sealing region, and the first impact resistant layer 112 is formed.
By increasing the contact area with the second impact resistant layer 102, the adhesion between the first impact resistant layer 112 and the second impact resistant layer 102 can be enhanced. A semiconductor device that has been tightly sealed in this manner can be a stronger and more reliable semiconductor device.

This embodiment can be combined with any of the other embodiments as appropriate.

In the present embodiment, by a pair of impact resistant layers that firmly seal the semiconductor integrated circuit substrate,
A highly reliable semiconductor device having durability while achieving thinning and downsizing can be provided. Further, also in the manufacturing process, a defect in shape and characteristics due to external stress can be prevented, and a semiconductor device can be manufactured with high yield.

(Embodiment 6)
In this embodiment mode, as an example of a semiconductor integrated circuit substrate applicable to the present invention, a CMOS (Complementary Metal Oxide Semiconductor: Complementary Metal Oxide Semiconductor) is used.
(Conductor) will be described.

In this embodiment mode, a substrate having an SOI structure (an SOI structure in which a single crystal semiconductor layer is provided over an insulating surface)
An example using a substrate) is shown. The SOI substrate is SIMOX (Separation by I).
It can be formed using the Mplanted Oxygen) method or the Smart-Cut method. In the SIMOX method, oxygen ions are implanted into a single crystal silicon substrate, an oxygen-containing layer is formed at a predetermined depth, and then heat treatment is performed to form a buried insulating layer at a certain depth from the surface. In this method, a single crystal silicon layer is formed on the layer. In the Smart-Cut method, hydrogen ions are implanted into an oxidized single crystal silicon substrate, a hydrogen-containing layer is formed at a position corresponding to a desired depth, and another semiconductor substrate (an oxide for bonding to the surface) is formed. A single crystal silicon substrate having a silicon film) or the like, and by performing a heat treatment, the single crystal silicon substrate is divided by a hydrogen-containing layer, and a silicon oxide film and a single crystal silicon layer are stacked over the semiconductor substrate It is a method of forming.

In FIG. 15A, an insulating layer 201 and a single crystal semiconductor layer 202 are formed over a semiconductor substrate 200. A selectively formed mask 250 is formed over the single crystal semiconductor layer 202. Note that although an example in which the SOI substrate having the structure illustrated in FIG. 15A is applied is shown here, an SOI substrate having another structure can also be applied.

In the single crystal semiconductor layer 202, a p-type impurity element such as boron, aluminum, or gallium or an n-type impurity element such as phosphorus or arsenic is formed in accordance with the formation region of the n-channel field effect transistor and the p-channel field effect transistor. It may be configured to have an impurity region (channel doped region) to which is added.

Etching is performed using the mask 250 to remove the exposed single crystal semiconductor layer 202 and part of the insulating layer 201 below the single crystal semiconductor layer 202. Next, a silicon oxide film is deposited by chemical vapor deposition using organosilane. This silicon oxide film is deposited thick so that the single crystal semiconductor layer 202 is embedded. Next, after removing the silicon oxide film overlying the single crystal semiconductor layer 202 by polishing, the mask 250 is removed, and the element isolation insulating layer 203 is left. The single crystal semiconductor layer 202 is separated into an element region 205 and an element region 206 by the element isolation insulating layer 203 (see FIG. 15B).

The element region 205 and the element region 206 can be controlled to be a region containing an impurity element imparting one conductivity type, which is formed according to channel doping conditions corresponding to required electrical characteristics of a transistor to be manufactured.

Next, a first insulating film is formed, gate electrode layers 208a and 208b having a polysilicon film containing a conductive material are formed over the first insulating film, and the first electrode is formed using the gate electrode layers 208a and 208b as a mask. The insulating film is etched to form gate insulating layers 207a and 207b.

The gate insulating layers 207a and 207b may be formed using a silicon oxide film or a stacked structure of a silicon oxide film and a silicon nitride film. A silicon oxynitride film, a silicon nitride oxide film, or the like can also be used as the gate insulating layer. The gate insulating layers 207a and 207b are formed of plasma C
It may be formed by depositing an insulating film by a VD method or a low pressure CVD method, or by solid phase oxidation or solid phase nitridation by plasma treatment. This is because a gate insulating layer formed by oxidizing or nitriding a semiconductor layer by plasma treatment is dense, has high withstand voltage, and is excellent in reliability. For example, nitrous oxide (N ₂ O) is diluted 1 to 3 times (flow rate ratio) with Ar, and 3 to 5 kW microwave (2.45 GHz) power is applied at a pressure of 10 to 30 Pa. The surface of the crystalline semiconductor layer 202 (element regions 205 and 206) is oxidized or nitrided. By this treatment, an insulating film having a thickness of 1 nm to 10 nm (preferably 2 nm to 6 nm) is formed. Further, nitrous oxide (N ₂ O) and silane (SiH ₄ ) were introduced, and 3 to 3 at a pressure of 10 to 30 Pa.
A gate insulating layer is formed by applying a 5 kW microwave (2.45 GHz) power and forming a silicon oxynitride film by vapor deposition. A gate insulating layer having a low interface state density and an excellent withstand voltage can be formed by combining a solid phase reaction and a reaction by a vapor deposition method.

Further, as the gate insulating layers 207a and 207b, zirconium dioxide, hafnium oxide,
High dielectric constant materials such as titanium dioxide and tantalum pentoxide may be used. Gate insulating layer 207
By using a high dielectric constant material, gate leakage current can be reduced.

The gate electrode layers 208a and 208b can be formed by a technique such as sputtering, vapor deposition, or CVD. The gate electrode layers 208 and 209 include tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu),
An element selected from chromium (Cr) and neodymium (Nd), or an alloy material or compound material containing the element as a main component may be used. In addition, as the gate electrode layers 208a and 208b, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus, Ag,
A PdCu alloy may be used.

Next, a second insulating film 210 is formed to cover the gate electrode layers 208a and 208b, and sidewall insulating layers 216a, 216b, 217a, and 217b having a sidewall structure are formed. p
Side wall insulating layers 216a, 216 in a region to be a channel type field effect transistor (pFET)
b denotes a sidewall insulating layer 217a in a region to be an n-channel field effect transistor (nFET).
Width is wider than 217b. Next, arsenic (As) or the like is added to a region to be an n-channel field effect transistor to form first impurity regions 220a and 220b having a shallow junction depth, and boron ( B) or the like is added to form second impurity regions 215a and 215b having a shallow junction depth (see FIG. 15C).

Next, the second insulating film 210 is partially etched to form gate electrode layers 208a and 208b.
And the first impurity regions 220a and 220b and the second impurity regions 215a and 215.
b. Next, As or the like is doped in a region to be an n-channel field effect transistor to form third impurity regions 219a and 219b having a deep junction depth, and B or the like is doped in a region to be a p-channel field effect transistor. The fourth impurity regions 224a and 224b having a deep junction depth are formed. Next, heat treatment for activation (800 ° C. to 1 °
100 ° C.). Next, a cobalt film is formed as a metal film for forming silicide. Next, heat treatment (500 ° C., 1 minute) such as RTA is performed to silicide the silicon in contact with the cobalt film, thereby forming silicides 222a, 222b, 223a, and 223b. Thereafter, the cobalt film is selectively removed. Next, heat treatment is performed at a temperature higher than the heat treatment for silicidation to reduce the resistance of the silicide portion (see FIG. 15D). A channel formation region 226 is formed in the element region 206, and a channel formation region 22 is formed in the element region 205.
1 is formed.

Next, an interlayer insulating layer 227 is formed, and the interlayer insulating layer 227 is formed using a resist mask.
Then, contact holes (openings) reaching the third impurity regions 219a and 219b having a deep junction depth and the fourth impurity regions 224a and 224b having a deep junction depth are formed. Etching may be performed once or a plurality of times depending on the selection ratio of the material to be used.

The etching method and conditions may be set as appropriate depending on the material of the interlayer insulating layer 227 for forming the contact hole. Wet etching, dry etching, or both can be used as appropriate. In this embodiment mode, dry etching is used. As an etching gas, a chlorine-based gas typified by Cl ₂ , BCl ₃ , SiCl ₄ or CCl ₄ ,
A fluorine-based gas such as CF ₄ , SF ₆ or NF ₃ or O ₂ can be appropriately used. Further, an inert gas may be added to the etching gas used. As the inert element to be added, one or more elements selected from He, Ne, Ar, Kr, and Xe can be used. As an etchant for wet etching, a hydrofluoric acid-based solution such as a mixed solution containing ammonium hydrogen fluoride and ammonium fluoride is preferably used.

A conductive film is formed so as to cover the contact hole, and the conductive layer is etched to form wiring layers 242a and 242b that also function as a source electrode layer or a drain electrode layer that is electrically connected to a part of each source region or drain region. 242c is formed. Wiring layer is PVD method, C
A conductive film can be formed by VD, vapor deposition, or the like, and then etched into a desired shape. Further, the conductive layer can be selectively formed at a predetermined place by a droplet discharge method, a printing method, an electrolytic plating method, or the like. Furthermore, a reflow method or a damascene method may be used. The wiring layer materials are Ag, Au, Cu, Ni, Pt, Pd, Ir, Rh, W, Al, Ta, Mo, C
It is formed using a metal such as d, Zn, Fe, Ti, Zr, or Ba, and Si, Ge, an alloy thereof, or a nitride thereof. Moreover, it is good also as these laminated structures.

In this embodiment, wiring layers 240a, 240b, 240c, and 240d are formed as embedded wiring layers so as to fill contact holes formed in the interlayer insulating layer 227. The buried wiring layers 240a, 240b, 240c, and 240d are formed by forming a conductive film having a sufficient thickness to fill the contact hole, and leaving the conductive film only in the contact hole portion by polishing treatment such as a CMP method. It is formed by removing the conductive film portion.

An insulating layer 228 and wiring layers 241a, 241b, and 241c are formed as buried wiring layers on the buried wiring layers 240a, 240b, 240c, and 240d, and the wiring layers 242a and 242b are formed.
242c is formed.

Through the above process, the single crystal semiconductor layer 202 bonded to the semiconductor substrate 200 with the insulating layer 201 interposed therebetween.
The n-channel field effect transistor 232 is formed using the element region 206 of the element region 205.
Can be used to manufacture a p-channel field effect transistor 231 (see FIG. 15E).
. Note that in this embodiment, the n-channel field effect transistor 232 and the p-channel field effect transistor 231 are electrically connected to each other through the wiring layer 242b.

As described above, the n-channel field effect transistor 232 and the p-channel field effect transistor 231 can be complementarily combined to manufacture the semiconductor integrated circuit substrate 270 having a CMOS structure.

A semiconductor device having various functions can be manufactured by further stacking wirings and semiconductor elements on the CMOS structure.

15 shows an example in which the element region 205 and the element region 206 are separated by the element isolation insulating layer 203, the element region 205 is shown in FIGS. And the element region 206 may be processed into an island-shaped semiconductor layer. In this case, FIG.
As shown in FIG. 0B, the element isolation insulating layer 203 is provided between the element region 205 and the element region 206.
Therefore, the second insulating film 260 is formed as shown in FIG. FIG.
At 0 (D), the second insulating film 260 is etched, and the insulating films 261a, 261b,
261c. Therefore, as illustrated in FIG. 20E, the element region 205 and the element region 206 which are island-shaped semiconductor layers of the n-channel field effect transistor 232 and the p-channel field effect transistor 231 included in the semiconductor integrated substrate 280 are insulated. Membranes 261a, 261b,
The end portion is surrounded by 261c.

The semiconductor integrated circuit substrates 270 and 280 shown in FIGS. 15E and 20E are divided for each semiconductor integrated circuit, and the semiconductor substrate 200 is subjected to a thinning process. The order of performing the dividing step and the thinning step may be reversed. The semiconductor integrated circuit substrates 270 and 280 shown in FIGS. 15E and 20E can also be applied as appropriate as the semiconductor integrated circuit substrate of the present invention.

The semiconductor device of the present invention can be applied to not only a field effect transistor but also a memory (memory) element using a semiconductor layer as a semiconductor element, and a semiconductor device satisfying a function required for various purposes is manufactured. Can be offered.

Without being limited to this embodiment mode, the thin film transistor may have a single gate structure in which one channel formation region is formed, a double gate structure in which two channel formation regions are formed, or a triple gate structure in which three channel formation regions are formed.

The semiconductor integrated circuit substrates 270 and 280 shown in FIGS. 15E and 20E are formed by the first impact resistant layer 112 and the second impact resistant layer 102 as shown in FIG. 1 of the first embodiment. The semiconductor device can be formed as a semiconductor integrated circuit substrate chip by being sealed.

This embodiment can be combined with any of the other embodiments as appropriate, and can be appropriately applied as the semiconductor integrated circuit substrate 100 in another embodiment.

The semiconductor device manufactured in this embodiment can be a flexible semiconductor device by using a flexible impact-resistant layer (or an impact diffusion layer).

A pair of impact-resistant layers sandwiching the semiconductor integrated circuit can provide a highly reliable semiconductor device having durability while achieving a reduction in thickness and size. Further, also in the manufacturing process, a defect in shape and characteristics due to external stress can be prevented, and a semiconductor device can be manufactured with high yield.

(Embodiment 7)
In this embodiment, another example of a semiconductor integrated circuit substrate that can be applied to the present invention will be described with reference to FIGS.

FIG. 14A illustrates an example of a semiconductor integrated circuit substrate 350 having a CMOS structure according to the present invention. The conductive layer 306 which is electrically connected to the semiconductor integrated circuit substrate 350 and functions as an antenna is illustrated.
An inorganic insulating layer 307 is formed as a protective layer.

In the semiconductor integrated circuit substrate 350, a transistor 301a which is an n-channel transistor and a transistor 301b which is a p-channel transistor are formed on a semiconductor substrate 300 with element regions separated by an element isolation insulating layer 302, and covers the transistors 301a and 301b. An insulating layer 303, an insulating layer 304, and an insulating layer 305 are stacked.

The transistor 301a includes a gate insulating layer 310a, a gate electrode layer 311a, and a sidewall insulating layer 3
12a, a shallow junction depth impurity region 314a, a deep junction depth impurity region 313a, and a wiring layer 315a. The transistor 301b includes a gate insulating layer 310b and a gate electrode layer 31.
1b, a sidewall insulating layer 312b, a shallow junction depth impurity region 314b, a deep junction depth impurity region 313b, and a wiring layer 315b.

In this embodiment, since a single crystal silicon substrate having p-type conductivity is used as the semiconductor substrate 300, an impurity element imparting n-type conductivity is added to the transistor 301b which is a p-channel transistor, and the n-well region 316 is added. Is forming.

Further, the semiconductor integrated circuit substrate 350 may include a memory element, a memory cell array, and a drive circuit unit that drives the memory cell array.

The conductive layer 306 functioning as an antenna is formed using a conductive material by a CVD method, a sputtering method, a printing method such as screen printing or gravure printing, a droplet discharge method, a dispenser method, a plating method, or the like. Conductive materials are aluminum (Al), titanium (Ti), silver (Ag), copper (Cu), gold (Au), platinum (Pt) nickel (Ni), palladium (Pd), tantalum (Ta), molybdenum A metal element such as (Mo) or an alloy material or compound material containing the metal element is used to form a single layer structure or a stacked structure.

For example, when the conductive layer 306 functioning as an antenna is formed using a screen printing method, a conductive paste in which conductive particles having a particle size of several nanometers to several tens of micrometers are dissolved or dispersed in an organic resin is selected. Can be provided by printing. In forming the conductive layer, it is preferable to fire after extruding the conductive paste.

The first impact-resistant layer 321 is heated and pressure-bonded to the inorganic insulating layer 307, the conductive layer 306, and the semiconductor integrated circuit substrate 350, and the first impact-resistant layer 321 is bonded to the inorganic insulating layer 307, the conductive layer 306, and the semiconductor integrated circuit. The circuit board 350 is adhered. Since the structure body in which the fibrous body 322 is impregnated with the organic resin 323 is used as the first impact-resistant layer 321, the structure body can be heated and pressed to plasticize or cure the organic resin of the structure body.

Next, the exposed surface of the semiconductor integrated circuit substrate 350 is ground and polished to reduce the thickness of the semiconductor integrated circuit substrate 350, whereby a semiconductor integrated circuit substrate 360 having a thinner thickness is obtained. As in this embodiment, the semiconductor substrate may be divided into chips in each semiconductor integrated circuit substrate 350, and the thinning process may be performed, or the semiconductor substrate in which a plurality of semiconductor integrated circuit substrates are manufactured may be subjected to the thinning process. Done
Thereafter, it may be divided into chips.

Since the second impact-resistant layer 324 also uses a structure body in which the fibrous body 325 is impregnated with the organic resin 326, the structure body can be heated and pressed to plasticize or cure the organic resin of the structure body. The second impact-resistant layer 324 is heated and pressure-bonded to the semiconductor integrated circuit substrate 360, and the second impact-resistant layer 324 is bonded to the semiconductor integrated circuit substrate 360 (see FIG. 14B).

The first impact-resistant layer 321 and the second impact-resistant layer 324 have the semiconductor integrated circuit substrate 360 disposed in the center, and are in contact with each other at the end where the semiconductor integrated circuit substrate 360 does not exist, thereby sealing the semiconductor integrated circuit substrate 360. To do.

This embodiment can be combined with any of the other embodiments as appropriate.

As described above, a pair of impact-resistant layers sandwiching the semiconductor integrated circuit can provide a highly reliable semiconductor device having durability while achieving thinning and downsizing. Further, also in the manufacturing process, a defect in shape and characteristics due to external stress can be prevented, and a semiconductor device can be manufactured with high yield.

(Embodiment 8)
In this embodiment, an example of a semiconductor device for the purpose of imparting higher reliability will be described. Specifically, as an example of a semiconductor device, an example of a semiconductor device provided with a microprocessor and an arithmetic function capable of transmitting and receiving data without contact will be described.

FIG. 12 illustrates an example of a microprocessor 500 as an example of a semiconductor device. The microprocessor 500 is manufactured by the semiconductor device according to the above embodiment.
The microprocessor 500 includes an arithmetic circuit 501 (Arthematic logic).
unit. Also called ALU. ), Arithmetic circuit control unit 502 (ALU Control)
r), instruction analysis unit 503 (Instruction Decoder), interrupt control unit 504 (Interrupt Controller), timing control unit 505 (Ti
mining Controller), register 506 (Register), register control unit 507 (Register Controller), bus interface 508
(Bus I / F), read-only memory 509, and memory interface 510 (
ROM I / F).

An instruction input to the microprocessor 500 via the bus interface 508 is input to the instruction analysis unit 503 and decoded, and then to the arithmetic circuit control unit 502, the interrupt control unit 504, the register control unit 507, and the timing control unit 505. Entered. The arithmetic circuit control unit 502, the interrupt control unit 504, the register control unit 507, and the timing control unit 505 perform various controls based on the decoded instruction. Specifically, the arithmetic circuit control unit 502 generates a signal for controlling the operation of the arithmetic circuit 501. The interrupt control unit 504 processes an interrupt request from an external input / output device or a peripheral circuit based on its priority or mask state while the microprocessor 500 executes a program. The register control unit 507 generates an address of the register 506, and registers 50 according to the state of the microprocessor 500.
6 is read and written. The timing control unit 505 generates a signal for controlling the operation timing of the arithmetic circuit 501, the arithmetic circuit control unit 502, the instruction analysis unit 503, the interrupt control unit 504, and the register control unit 507. For example, the timing control unit 505 includes an internal clock generation unit that generates an internal clock signal CLK2 based on the reference clock signal CLK1, and supplies the clock signal CLK2 to the various circuits. Note that the microprocessor 500 illustrated in FIG. 12 is only an example in which the configuration is simplified, and actually, the microprocessor 500 may have various configurations depending on the application.

Next, an example of a semiconductor device having an arithmetic function capable of transmitting and receiving data without contact will be described with reference to FIGS. FIG. 13 shows an example of a computer (hereinafter referred to as “RFCPU”) that operates by transmitting and receiving signals to and from an external device by wireless communication. RFCPU5
11 has an analog circuit portion 512 and a digital circuit portion 513. Analog circuit 5
12, a resonance circuit 514 having a resonance capacitance, a rectification circuit 515, a constant voltage circuit 516, a reset circuit 517, an oscillation circuit 518, a demodulation circuit 519, and a modulation circuit 520 are included.
The digital circuit unit 513 includes an RF interface 521, a control register 522, a clock controller 523, an interface 524, a central processing unit 525, a random access memory 526, and a read only memory 527.

The operation of the RFCPU 511 having such a configuration is roughly as follows. A signal received by the antenna 528 generates an induced electromotive force by the resonance circuit 514. The induced electromotive force is generated by the rectifier circuit 515.
The capacitor 529 is charged via the above. Capacitance portion 529 is preferably formed of a capacitor such as a ceramic capacitor or an electric double layer capacitor. Capacitor 529 is R
The FCPU 511 does not need to be integrally formed, and may be attached to a substrate having an insulating surface constituting the RFCPU 511 as a separate component.

The reset circuit 517 generates a signal that resets and initializes the digital circuit portion 513.
For example, a signal that rises after a rise in the power supply voltage is generated as a reset signal. The oscillation circuit 518 changes the frequency and duty ratio of the clock signal in accordance with the control signal generated by the constant voltage circuit 516. A demodulation circuit 519 formed by a low-pass filter binarizes fluctuations in the amplitude of an amplitude modulation (ASK) received signal, for example. The modulation circuit 520
Transmission data is transmitted by varying the amplitude of an amplitude modulation (ASK) transmission signal. The modulation circuit 520 changes the amplitude of the communication signal by changing the resonance point of the resonance circuit 514. The clock controller 523 generates a control signal for changing the frequency and duty ratio of the clock signal in accordance with the power supply voltage or the current consumption in the central processing unit 525. The power supply management circuit 530 monitors the power supply voltage.

A signal input from the antenna 528 to the RFCPU 511 is demodulated by the demodulation circuit 519 and then decomposed into a control command and data by the RF interface 521. The control command is stored in the control register 522. For the control command, reading of data stored in the read-only memory 527, writing of data to the random access memory 526,
Calculation instructions to the central processing unit 525 are included. The central processing unit 525 is
Read-only memory 527 and random access memory 5 via interface 524
26, the control register 522 is accessed. The interface 524 has a function of generating an access signal for any of the read-only memory 527, the random access memory 526, and the control register 522 from the address requested by the central processing unit 525.

As a calculation method of the central processing unit 525, a method in which an OS (operating system) is stored in the read-only memory 527 and a program is read and executed together with activation can be employed. Further, it is also possible to adopt a method in which an arithmetic circuit is configured by a dedicated circuit and arithmetic processing is processed in hardware. In the method using both hardware and software, a method in which a part of processing is performed by a dedicated arithmetic circuit and the central processing unit 525 executes the remaining operations using a program can be applied.

Also in the microprocessor according to this embodiment, a pair of impact-resistant layers that seal the semiconductor integrated circuit substrate can provide a highly reliable semiconductor device having durability while achieving thinning and downsizing. Further, also in the manufacturing process, a defect in shape and characteristics due to external stress can be prevented, and a semiconductor device can be manufactured with high yield.

(Embodiment 9)
In this embodiment, an example of usage of the semiconductor device described in the above embodiment is described. Specifically, application examples of a semiconductor device capable of inputting and outputting data without contact will be described below with reference to the drawings. A semiconductor device in which data can be input / output without contact is also referred to as an RFID tag, an ID tag, an IC tag, an RF tag, a wireless tag, an electronic tag, or a wireless chip depending on a usage pattern.

An example of a top structure of the semiconductor device described in this embodiment will be described with reference to FIG. The semiconductor device illustrated in FIG. 19A includes a semiconductor integrated circuit substrate chip 400 provided with an antenna (also referred to as an on-chip antenna) and a support substrate 406 provided with an antenna 405 (also referred to as a booster antenna). Yes. The semiconductor integrated circuit substrate chip 400 is provided on an insulating layer 410 formed on the support substrate 406 and the antenna 405.
The semiconductor integrated circuit substrate chip 4 is formed on the support substrate 406 and the antenna 405 by the insulating layer 410.
00 can be fixed. Note that in the case where the conductive shield is provided on the surface of the semiconductor integrated circuit substrate chip 400 as a countermeasure against electrostatic breakdown shown in the third embodiment, the resistance of the conductive shield is high and the pattern of the antenna 405 is not conductive. The antenna 405 and the conductive shield provided on the surface of the semiconductor integrated circuit substrate chip 400 may be provided in contact with each other.

A semiconductor integrated circuit provided in the semiconductor integrated circuit substrate chip 400 is provided with elements such as a plurality of transistors constituting a memory unit and a logic unit. The semiconductor device according to this embodiment can be applied to not only a field effect transistor as a semiconductor element but also a memory element using a semiconductor layer, and a semiconductor device that satisfies functions required for various purposes is manufactured. Can be provided.

FIG. 18A shows an enlarged view of the antenna and the semiconductor integrated circuit included in the semiconductor integrated circuit substrate chip 400 shown in FIG. In FIG. 18A, the antenna 101 is a rectangular loop antenna having one winding, but the present invention is not limited to this structure. The shape of the loop antenna is not limited to having a rectangular shape, and may have a curved shape, for example, a circular shape. The number of turns is not limited to 1 and may be plural. However, antenna 10
When the number of turns of 1 is 1, the parasitic capacitance generated between the semiconductor integrated circuit substrate 100 and the antenna 101 can be reduced.

In FIGS. 19A and 18A, the antenna 101 is the semiconductor integrated circuit substrate 1.
The antenna 101 is arranged in a region different from the semiconductor integrated circuit substrate 100 except for a portion corresponding to the feeding point 408 indicated by a broken line. However, the present invention is not limited to this configuration, and as shown in FIG.
Except for the portion corresponding to 8, the antenna 101 may be disposed so as to at least partially overlap the semiconductor integrated circuit substrate 100. However, as shown in FIGS. 19A and 18A, the antenna 101 is arranged in a region different from the semiconductor integrated circuit substrate 100, and thus is generated between the semiconductor integrated circuit substrate 100 and the antenna 101. Parasitic capacitance can be reduced.

In FIG. 19A, the antenna 405 can transmit and receive signals or supply power by electromagnetic induction with the antenna 101 mainly in a loop-shaped portion surrounded by a broken line 407. The antenna 405 can exchange signals with an interrogator or supply power by radio waves mainly in a region other than a portion surrounded by a broken line 407. The frequency of the radio wave used as a carrier between the interrogator and the semiconductor device is 30 MHz or more and 5
For example, a frequency band such as 950 MHz and 2.45 GHz may be used.

Further, the antenna 405 has a rectangular loop shape with a winding number of 1 in a portion surrounded by a broken line 407, but the present invention is not limited to this configuration. The loop-shaped portion is not limited to having a rectangular shape, and may have a curved shape, for example, a circular shape. The number of turns is not limited to 1 and may be plural.

An electromagnetic induction method, an electromagnetic coupling method, and a microwave method can be applied to the semiconductor device of the present invention. In the case of a microwave method, the shapes of the antenna 101 and the antenna 405 may be determined as appropriate depending on the wavelength of the electromagnetic wave to be used.

For example, when a microwave method (for example, UHF band (860 MHz band to 960 MHz band), 2.45 GHz band, etc.) is applied as a signal transmission method in a semiconductor device, the wavelength of an electromagnetic wave used for signal transmission is considered. Thus, the length and shape of the antenna may be set as appropriate. For example, the antenna can be formed in a linear shape (for example, a dipole antenna), a flat shape (for example, a patch antenna or a ribbon shape), or the like. Further, the shape of the antenna is not limited to a linear shape, and may be provided in a curved shape, a meandering shape, or a combination thereof in consideration of the wavelength of electromagnetic waves.

FIG. 10 illustrates an example in which the antenna 101 and the antenna 405 are provided in a coil shape and an electromagnetic induction method or an electromagnetic coupling method is applied.

In FIG. 10, the semiconductor integrated circuit substrate chip 4 in which the coiled antenna 101 is provided on the support substrate 406 in which the coiled antenna 405 is provided as a booster antenna.
00 is provided. The antenna 405 which is a booster antenna is a support substrate 40.
A capacitor 411 is formed across 6.

Next, the structure and arrangement of the semiconductor integrated circuit substrate chip 400 and the booster antenna will be described. FIG. 19B corresponds to a perspective view of the semiconductor device in which the semiconductor integrated circuit substrate chip 400 illustrated in FIG. 19A and the antenna 405 formed over the supporting substrate 406 are stacked. FIG. 19C corresponds to a cross-sectional view taken along dashed line XY in FIG.

As the semiconductor integrated circuit substrate chip 400 shown in FIG. 19C, the semiconductor device described in any of Embodiments 1 to 7 can be used. Here, a semiconductor integrated circuit substrate chip divided into individual chips is used. That's it. Note that the semiconductor integrated circuit substrate chip illustrated in FIG. 19C is an example using Embodiment Mode 1, but this embodiment mode can also be applied to other embodiment modes.
It is not limited to this structure.

A semiconductor integrated circuit substrate 100 shown in FIG. 19C is sandwiched between a first impact resistant layer 112 and a second impact resistant layer 102, and the side surfaces thereof are also sealed. In this embodiment, after sandwiching a plurality of semiconductor integrated circuit substrates and bonding the first impact resistant layer and the second impact resistant layer together, the semiconductor integrated circuit substrate is divided into individual laminates for each semiconductor integrated circuit substrate. The semiconductor integrated circuit substrate is sealed. The dividing means is not particularly limited as long as it can be physically divided. In this embodiment, the dividing means is divided by irradiation with laser light.

In FIG. 19C, the semiconductor integrated circuit substrate 100 is disposed closer to the antenna 405 than the antenna 101; however, the present invention is not limited to this structure. Antenna 10
1 may be disposed closer to the antenna 405 than the semiconductor integrated circuit substrate 100. Further, the antenna 101 may be provided outside the impact resistant layer. In this case, a through hole is formed in the impact resistant layer so that the connection terminals of the semiconductor integrated circuit substrate sealed in the pair of impact resistant layers are exposed, and the antenna 101 is electrically connected through the through holes. That's fine. This electrical connection may be performed by forming an electrode layer in the through hole, or may be configured to be electrically connected via conductive particles contained in an adhesive resin.

Next, the operation of the semiconductor device according to the present embodiment will be described. FIG. 17 is an example of a block diagram illustrating a configuration of the semiconductor device according to this embodiment. The semiconductor device 420 shown in FIG.
Has an antenna 422 as a booster antenna, a semiconductor integrated circuit 423, and an antenna 424 as an on-chip antenna. When an electromagnetic wave is transmitted from the interrogator 421, the antenna 422 receives the electromagnetic wave, thereby generating an alternating current in the antenna 422.
A magnetic field is generated around the antenna 422. The loop portion of the antenna 422 and the antenna 424 having the loop shape are electromagnetically coupled, so that the antenna 424
An induced electromotive force is generated in The semiconductor integrated circuit 423 receives a signal or power from the interrogator 421 by using the induced electromotive force. On the contrary, according to the signal generated in the semiconductor integrated circuit 423, current is passed through the antenna 424 to generate an induced electromotive force in the antenna 422, so that the reflected wave of the radio wave transmitted from the interrogator 421 is put on the interrogator. A signal can be transmitted to 421.

Note that the antenna 422 is mainly divided into a loop-shaped portion that is electromagnetically coupled to the antenna 424 and a portion that mainly receives radio waves from the interrogator 421. The shape of the antenna 422 in the portion that mainly receives radio waves from the interrogator 421 may be any shape that can receive radio waves. For example, a shape such as a dipole antenna, a folded dipole antenna, a slot antenna, a meander line antenna, or a microstrip antenna may be used.

In addition, although FIG. 17 illustrates the structure of a semiconductor integrated circuit having only one antenna, the present invention is not limited to this structure. You may have two antennas, the antenna for receiving electric power, and the antenna for receiving a signal. If there are two antennas, the frequency of the radio wave for supplying power and the frequency of the radio wave for sending signals can be used properly.

In the semiconductor device according to this embodiment, an on-chip antenna is used, and a signal or power can be exchanged between the booster antenna and the on-chip antenna in a contactless manner. Unlike the case of connecting to an integrated circuit, the connection between the semiconductor integrated circuit and the antenna is not easily broken by an external force, and the occurrence of an initial failure in the connection can be suppressed. In addition, since a booster antenna is used in this embodiment mode, unlike the case of using only an on-chip antenna, the size or shape of the on-chip antenna is not easily restricted by the area of the semiconductor integrated circuit, and the frequency band of receivable radio waves However, it is not limited, and the merit of the external antenna that the communication distance can be extended can be enjoyed.

A semiconductor device to which the present invention is applied can provide a highly reliable semiconductor device having durability while achieving a reduction in thickness and size by a pair of impact-resistant layers that seal a semiconductor integrated circuit substrate. In addition, in the manufacturing process, we prevent defects in shape and characteristics due to external stress,
A semiconductor device can be manufactured with high yield. Therefore, it is effective in the case of a small semiconductor device capable of inputting / outputting data without contact as shown in this embodiment mode. Since the semiconductor device of this embodiment has high reliability with respect to external force, it is possible to widen the conditions of the environment in which the semiconductor device can be used, and thus to broaden the range of uses of the semiconductor device.

(Embodiment 10)
In this embodiment, application examples of a semiconductor device which is formed using the above-described invention and can input / output data without contact will be described below with reference to the drawings. A semiconductor device in which data can be input / output without contact is also referred to as an RFID tag, an ID tag, an IC tag, an IC chip, an RF tag, a wireless tag, an electronic tag, or a wireless chip depending on the application.

The semiconductor device 800 has a function of exchanging data without contact, and controls a high frequency circuit 810, a power supply circuit 820, a reset circuit 830, a clock generation circuit 840, a data demodulation circuit 850, a data modulation circuit 860, and other circuits. A control circuit 870, a memory circuit 880, and an antenna 890 are provided (see FIG. 11A). The high-frequency circuit 810 is a circuit that receives a signal from the antenna 890 and outputs the signal received from the data modulation circuit 860 from the antenna 890, and the power supply circuit 820 is a circuit that generates a power supply potential from the received signal, and a reset circuit 830 Is a circuit that generates a reset signal, and the clock generation circuit 840 includes an antenna 89.
The data demodulating circuit 850 is a circuit that demodulates the received signal and outputs it to the control circuit 870. The data modulating circuit 8
Reference numeral 60 denotes a circuit that modulates a signal received from the control circuit 870. As the control circuit 870, for example, a code extraction circuit 910, a code determination circuit 920, a CRC determination circuit 930, and an output unit circuit 940 are provided. The code extraction circuit 910 is a circuit that extracts a plurality of codes included in the instruction sent to the control circuit 870, and the code determination circuit 920 compares the extracted code with a code corresponding to a reference. The CRC determination circuit 930 is a circuit that detects the presence or absence of a transmission error or the like based on the determined code.

Next, an example of operation of the above-described semiconductor device will be described. First, a radio signal is received by the antenna 890. The radio signal is sent to the power supply circuit 820 via the high frequency circuit 810,
A high power supply potential (hereinafter referred to as VDD) is generated. VDD is supplied to each circuit included in the semiconductor device 800. The signal sent to the data demodulation circuit 850 via the high frequency circuit 810 is demodulated (hereinafter, demodulated signal). Further, the reset circuit 8 is connected via the high frequency circuit 810.
30 and the clock signal passing through the clock generation circuit 840 and the demodulated signal are sent to the control circuit 870. The signal sent to the control circuit 870 is analyzed by the code extraction circuit 910, the code determination circuit 920, the CRC determination circuit 930, and the like. Then, information on the semiconductor device stored in the memory circuit 880 is output in accordance with the analyzed signal. The output semiconductor device information is encoded through the output unit circuit 940. Further, the encoded information of the semiconductor device 800 passes through the data modulation circuit 860 and is transmitted on the radio signal by the antenna 890. Note that a low power supply potential (hereinafter referred to as VSS) is common in the plurality of circuits included in the semiconductor device 800, and VSS can be GND.

As described above, by transmitting a signal from the communication device to the semiconductor device 800 and receiving the signal transmitted from the semiconductor device 800 by the communication device, data of the semiconductor device can be read.

Further, the semiconductor device 800 may be of a type in which supply of power supply voltage to each circuit is performed by electromagnetic waves without mounting a power supply (battery), or a power supply (battery) is mounted and electromagnetic waves and power supply (
The power supply voltage may be supplied to each circuit by a battery.

Next, an example of a usage pattern of a semiconductor device capable of inputting and outputting data without contact will be described.
A communication device 3200 is provided on a side surface of the mobile terminal including the display unit 3210, and an article 3220 is provided.
A semiconductor device 3230 is provided on the side surface (FIG. 11B). When the communication device 3200 is held over the semiconductor device 3230 included in the product 3220, information about the product such as the description of the product, such as the raw material and origin of the product, the inspection result for each production process, the history of the distribution process, etc. is displayed on the display unit 3210 The Further, when the product 3260 is conveyed by the belt conveyor, the communication device 324 is used.
0 and the semiconductor device 3250 provided in the product 3260 can be used to inspect the product 3260 (FIG. 11C). In this manner, by using a semiconductor device in the system, information can be easily acquired, and high functionality and high added value are realized.

As described above, the applicable range of the highly reliable semiconductor device of the present invention is so wide that the semiconductor device can be used for a wide range of electronic devices.

(Embodiment 11)
According to the present invention, a semiconductor device that functions as a chip having a processor circuit (hereinafter also referred to as a processor chip, a wireless chip, a wireless processor, a wireless memory, or a wireless tag) can be formed. The application of the semiconductor device of the present invention is wide-ranging, and can be applied to any product that can be used for production and management by clarifying information such as the history of an object without contact. For example, banknotes, coins, securities, certificate documents, bearer bonds, packaging containers, books, recording media, personal belongings, vehicles, foods, clothing, health supplies, daily necessities, chemicals, etc. It can be provided and used in an electronic device or the like. These examples will be described with reference to FIG.

Banknotes and coins are money that circulates in the market, and include those that are used in the same way as money in a specific area (cash vouchers), commemorative coins, and the like. Securities refers to checks, securities, promissory notes,
A chip 190 having a processor circuit can be provided (see FIG. 9A). The certificate refers to a driver's license, a resident's card, and the like, and can be provided with a chip 191 having a processor circuit (see FIG. 9B). Personal belongings refer to bags, glasses, and the like, and can be provided with a chip 197 including a processor circuit (see FIG. 9C). Anonymous bonds are stamps,
Refers to gift cards and various gift certificates. Packaging containers refer to wrapping paper such as lunch boxes, plastic bottles, and the like, and can be provided with a chip 193 including a processor circuit (see FIG. 9D). Books refer to books, books, and the like, and can be provided with a chip 194 including a processor circuit (see FIG. 9E). A recording medium refers to DVD software, a video tape, or the like, and can be provided with a chip 195 including a processor circuit (see FIG. 9F). The vehicles refer to vehicles such as bicycles, ships, and the like, and can be provided with a chip 196 including a processor circuit (see FIG. 9G). Foods refer to food products, beverages, and the like. Clothing refers to clothing, footwear, and the like. Health supplies refer to medical equipment, health equipment, and the like. Livingware refers to furniture, lighting equipment, and the like. Chemicals refer to pharmaceuticals, agricultural chemicals, and the like. Electronic devices include liquid crystal display devices and EL
It refers to a display device, a television device (a television receiver, a thin television receiver), a mobile phone, and the like.

Such a semiconductor device is provided by being attached to the surface of an article or embedded in an article. For example, a book may be embedded in paper, and a package made of an organic resin may be embedded in an organic resin.

In this way, by providing semiconductor devices in packaging containers, recording media, personal items, foods, clothing, daily necessities, electronic devices, etc., it is possible to improve the efficiency of inspection systems and rental store systems. it can. Further, forgery or theft can be prevented by providing a semiconductor device in the vehicles. Moreover, by embedding it in creatures such as animals, it is possible to easily identify individual creatures. For example, by embedding or attaching a semiconductor device equipped with a sensor to a living creature such as livestock, it is possible to easily manage the health state such as body temperature as well as the year of birth, gender or type.

Note that this embodiment can be implemented in combination with any of Embodiments 1 to 10 as appropriate.

(Embodiment 12)
In this embodiment mode, a mounting example of the semiconductor device of the present invention will be described with reference to FIGS.

The semiconductor device of the present invention can be variously mounted on an article as shown in Embodiment Mode 11. In this embodiment, an example in which a flexible semiconductor device is manufactured by mounting over a flexible substrate (also referred to as a flexible substrate) is described.

FIGS. 16A to 16C show examples in which a semiconductor integrated circuit substrate chip is embedded in a flexible substrate. The semiconductor device described in any of Embodiments 1 to 7 can be used as the semiconductor integrated circuit substrate chip. Here, the semiconductor device divided into chips is referred to as a semiconductor integrated circuit substrate chip. FIG. 16D shows details of the semiconductor integrated circuit substrate chip 600. FIG. 16 (D)
The semiconductor integrated circuit substrate chip is an example using the first embodiment, but this embodiment can be applied to other embodiments and is not limited to this structure.

In FIG. 16D, the antenna 101 and the semiconductor integrated circuit substrate 100 are formed of the first impact resistant layer 11.
2. It is sandwiched between the second impact resistant layers 102 and the side surfaces thereof are also sealed. In this embodiment,
The first impact resistant layer 112 and the second impact resistant layer 102 sandwich a plurality of semiconductor integrated circuits, and are divided into individual antennas 101 and semiconductor integrated circuit substrates 100 to produce semiconductor integrated circuit substrate chips. . The dividing means is not particularly limited as long as it can be physically divided. In this embodiment, the dividing means is divided by irradiation with laser light.

By dividing, the antenna 101 and the semiconductor integrated circuit substrate 100 are sealed by the first impact resistant layer 112 and the second impact resistant layer 102.

A pair of impact-resistant layers for sealing a semiconductor integrated circuit substrate can provide a highly reliable semiconductor device having durability while achieving reduction in thickness and size. Further, also in the manufacturing process, a defect in shape and characteristics due to external stress can be prevented, and a semiconductor device can be manufactured with high yield.

FIG. 16A shows a flexible substrate 601 and a semiconductor integrated circuit substrate chip 600 sandwiched between the flexible substrates 602, and the semiconductor integrated circuit substrate chip 600 is disposed in a recess provided in the flexible substrate 601. Has been.

The recess in which the semiconductor integrated circuit substrate chip 600 is disposed may be provided on one flexible substrate, or may be provided on both. FIG. 16B shows an example in which the semiconductor integrated circuit substrate chip 600 is disposed in the recesses provided in both the flexible substrate 601 and the flexible substrate 602.

Further, the flexible substrate has a three-layer structure, and the semiconductor integrated circuit substrate chip 60 is formed on the central flexible substrate.
An opening for arranging 0 may be provided. In FIG. 16C, an opening is provided in the flexible substrate 603, the semiconductor integrated circuit substrate chip 600 is disposed in the opening, and the flexible substrate 601 and the flexible substrate 60 are arranged.
2 is an example in which the flexible substrate 603 and the semiconductor integrated circuit substrate chip 600 are sandwiched.

16A to 16C, a flexible substrate may be stacked on the outside of the flexible substrate 601 and the flexible substrate 602.

As the flexible substrates 601, 602, and 603, a woven fabric obtained by weaving a bundle of fibers (single yarn) (hereinafter referred to as a yarn bundle) for warp and weft, or a yarn bundle of a plurality of types of fibers is randomly or Nonwoven fabric, paper, etc. deposited in one direction can be used. Specifically, from PET (polyethylene terephthalate), PEN (polyethylene naphthalate), PES (polyethersulfone), polypropylene, polypropylene sulfide, polycarbonate, polyetherimide, polyphenylene sulfide, polyphenylene oxide, polysulfone, polyphthalamide, etc. A substrate made of polypropylene, polyester, vinyl, polyvinyl fluoride, vinyl chloride, polyester, polyamide or the like, a film, paper made of a fibrous material, or the like can be used. A laminated film with an adhesive synthetic resin film (acrylic synthetic resin, epoxy synthetic resin, or the like) can be used. When the substrate or film adheres to the object to be processed, an adhesive layer may be used. The conditions can be selected depending on the type of the substrate or film, and can be bonded by heat treatment or pressure. The adhesive layer corresponds to a layer containing an adhesive such as a thermosetting resin, an ultraviolet curable resin, an epoxy resin adhesive, or a resin additive.

When the semiconductor integrated circuit substrate chip 600 is arranged to be embedded by providing a recess or an opening in the flexible substrate to be mounted as in this embodiment, a convex portion is formed by providing the semiconductor integrated circuit substrate chip 600. Therefore, the surface of the flexible substrate is flat and the film thickness can be made uniform. Therefore, even when a pressure treatment is performed by a roller or the like for bonding when mounting the semiconductor integrated circuit board chip on the flexible substrate, pressure is locally applied to the semiconductor integrated circuit board chip (pressure is concentrated). This can be prevented. Therefore, damage to the semiconductor integrated circuit substrate chip can be reduced in the mounting process, and the yield of the semiconductor device is improved. Further, even after mounting, a highly reliable semiconductor device that is resistant to external stress can be obtained.

Moreover, since it can be set as a flat and smooth surface, it is excellent in storage, the stackability on a machine, and a conveyance property. Furthermore, since the semiconductor integrated circuit board chip is not visually recognized from the outside (there is no convex portion reflecting the shape of the semiconductor integrated circuit board chip on the surface), the semiconductor device can have high security.

Claims (1)

A first structure body in which a first fibrous body is impregnated with a first organic resin;
A second structure in which a second fibrous body is impregnated with a second organic resin;
A circuit including a transistor provided between the first structure and the second structure;
A third conductive layer electrically connected to the circuit;
A first conductive layer provided on the outer surface of the first structure;
A second conductive layer provided on the outer surface of the second structure;
Have
The first conductive layer has a region overlapping the circuit;
The second conductive layer has a region overlapping the circuit;
The third conductive layer has a region functioning as an antenna,
The first conductive layer and the second conductive layer are electrically connected via an electrode penetrating the inside of the first structure and the second structure,
The first conductive layer, the second conductive layer, and the electrode are not electrically connected to the circuit,
Said second conductive layer, have a thickness greater than the first conductive layer,
The semiconductor device, wherein the second conductive layer is provided on the opposite side of the circuit from the side on which the third conductive layer is provided .

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